SIMD-based fingerprint comparison method, apparatus and device, and medium

Abstract

The invention discloses a SIMD-based fingerprint comparison method, device and equipment and a medium, and relates to the technical field of fingerprint identification, and the method comprises the steps: generating a first fixed-length feature vector and a second fixed-length feature vector according to a to-be-compared fingerprint and a minutiae topological structure of a pre-stored fingerprint template; carrying out binarization processing on the two feature vectors to obtain corresponding binarization feature vectors; calling an SIMD (Single Instruction Multiple Data) instruction set of the embedded processor, carrying out parallel operation on the binarized feature vectors, and calculating a similarity distance value of the binarized feature vectors; and judging whether the fingerprints are matched based on the distance value. According to the method, feature regularization is achieved through the fixed-length vector, data is compressed through binarization, calculation is simplified into bit operation, then hardware-level parallel processing is conducted through the SIMD instruction set, and the operation throughput rate of fingerprint comparison is remarkably improved. The method effectively adapts to the architecture of the embedded processor, greatly improves the operation efficiency and meets the real-time requirement on the premise of not increasing the cost and power consumption of special hardware.

Description

Technical Field

[0001] This invention relates to the field of fingerprint recognition technology, and in particular to a fingerprint comparison method, apparatus, device, and medium based on SIMD. Background Technology

[0002] In the field of embedded biometrics, fingerprint recognition technology has been widely used in terminal devices such as smart door locks and identity authentication modules due to its uniqueness and security.

[0003] Embedded devices are typically implemented using low- to mid-range microcontrollers or microprocessors with limited computing power, resulting in generally low general-purpose computing performance. The core of fingerprint comparison lies in calculating the similarity of high-dimensional feature vectors between the acquired fingerprint and a pre-stored template, such as calculating Euclidean distance or Hamming distance. This process involves a large amount of numerical computation and logical comparison, placing high demands on the processor's parallel data processing capabilities.

[0004] However, embedded devices, limited by their hardware architecture, mostly employ traditional serial scalar computation methods to handle these vector operations, resulting in insufficient effective computational capacity per unit time. Meanwhile, these applications have stringent requirements for real-time response, demanding comparisons be completed within an extremely short timeframe to ensure a positive user experience. Furthermore, devices typically face strict power consumption constraints, needing to complete computational tasks within a limited energy budget.

[0005] Therefore, under the existing embedded general-purpose computing architecture, how to significantly improve the computational efficiency of fingerprint feature comparison to meet real-time requirements without significantly increasing hardware costs and power consumption has become an urgent technical problem to be solved. Summary of the Invention

[0006] This invention provides a SIMD-based fingerprint comparison method, apparatus, device, and medium, aiming to solve the technical problem of how to significantly improve the computational efficiency of fingerprint feature comparison to meet real-time requirements without significantly increasing hardware costs and power consumption.

[0007] In a first aspect, embodiments of the present invention provide a fingerprint comparison method based on SIMD, comprising: A first fixed-length feature vector is generated based on the topological structure of the minutiae of the fingerprint to be compared, and a second fixed-length feature vector is generated based on the topological structure of the minutiae of the pre-stored fingerprint template. The first fixed-length feature vector and the second fixed-length feature vector are binarized respectively to obtain the first binarized feature vector and the second binarized feature vector; The embedded processor's SIMD instruction set is invoked to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing the similarity between the two. Based on the distance value, it is determined whether the fingerprint to be compared matches the pre-stored fingerprint template.

[0008] A further technical solution is that generating a first fixed-length feature vector based on the topological structure of the minutiae of the fingerprint to be compared includes: From the topological structure of the minutiae of the fingerprint to be compared, information of N minutiae is extracted, where the information of each minutiae includes the horizontal coordinate value, the vertical coordinate value and the orientation angle value, and N is a preset positive integer; The extracted N detail points are sorted in ascending order of their x-coordinate values; The x-coordinate, y-coordinate, and orientation angle values ​​of each of the sorted N detail points are extracted as feature elements. The extracted 3N feature elements are combined sequentially in a first predetermined order to form a first fixed-length feature vector with a dimension of 3N. The step of generating a second fixed-length feature vector based on the minutiae topology of the pre-stored fingerprint template includes: From the minutiae topology of the pre-stored fingerprint template, extract information of M minutiae, where the information of each minutiae includes the x-coordinate value, y-coordinate value and orientation angle value, and M is a preset positive integer; The extracted M detail points are sorted in ascending order of their x-coordinate values; Sequentially extract the x-coordinate, y-coordinate, and orientation angle values ​​of each of the sorted M detail points as feature elements; The extracted 3M feature elements are combined sequentially in a second predetermined order to form a second fixed-length feature vector with a dimension of 3M. Wherein, the first predetermined order is consistent with the second predetermined order, and N is equal to M.

[0009] A further technical solution is that the first fixed-length feature vector and the second fixed-length feature vector are respectively binarized to obtain a first binarized feature vector and a second binarized feature vector, including: Each feature element in the first fixed-length feature vector is compared with a first preset threshold. If the feature element is greater than the first preset threshold, it is quantized as 1; otherwise, it is quantized as 0, thereby obtaining the first binary feature vector. Each feature element in the second fixed-length feature vector is compared with a second preset threshold. If the feature element is greater than the second preset threshold, it is quantized to 1; otherwise, it is quantized to 0, thereby obtaining the second binarized feature vector. Wherein, the first preset threshold is equal to the second preset threshold.

[0010] A further technical solution is that the distance value is the Hamming distance, and the step of calling the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing the similarity between the two includes: The vector loading instructions in the SIMD instruction set are used to load the corresponding data blocks of the first binarized feature vector and the second binarized feature vector into the vector register in parallel. The corresponding data block in the vector register is subjected to a parallel bitwise XOR operation using the bitwise XOR instruction in the SIMD instruction set to obtain an intermediate result vector representing the bit difference. The Hamming distance is obtained by using the population counting or bit extraction and accumulation instructions provided by the SIMD instruction set to perform parallel statistics and accumulation on the number of bits set for each element in the intermediate result vector.

[0011] A further technical solution is that the distance value is Euclidean distance, and the step of calling the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing the similarity between the two includes: The vector loading instructions in the SIMD instruction set are used to load the corresponding data blocks of the first binarized feature vector and the second binarized feature vector into the vector register in parallel. The difference between each pair of elements in the corresponding data block is calculated in parallel using the vector subtraction instruction in the SIMD instruction set. The square of each difference is calculated in parallel using vector multiplication instructions in the SIMD instruction set; The sum of squares of the Euclidean distance is obtained by accumulating multiple squared results in parallel using the vector reduction addition instruction in the SIMD instruction set.

[0012] A further technical solution is that, before calling the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity, the method further includes: The memory alignment length is determined based on the vector register bit width of the SIMD instruction set; Addresses are allocated in memory for the first fixed-length feature vector, the second fixed-length feature vector, the first binarized feature vector, and the second binarized feature vector that participate in the parallel operation, and the starting position of the address is aligned with the memory alignment length.

[0013] A further technical solution is that when the dimensions of the first binarized feature vector and the second binarized feature vector exceed a preset block processing threshold, the embedded processor's SIMD instruction set is invoked to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate a distance value characterizing their similarity, including: The size of the target block for a single processing step is determined based on the cache size of the embedded processor and the bit width of the vector register of the SIMD instruction set. The first binarized feature vector and the second binarized feature vector are divided into multiple data blocks with dimensions matching the target block size; The parallel operation is performed sequentially on each pair of corresponding data blocks in the first and second binarized feature vectors, and the calculation results of all data blocks are accumulated to obtain the distance value.

[0014] Secondly, embodiments of the present invention also provide a SIMD-based fingerprint comparison device, which includes a unit for performing the above-described method.

[0015] Thirdly, embodiments of the present invention also provide a computer device, which includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described method.

[0016] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the above-described method.

[0017] This invention provides a SIMD-based fingerprint comparison method, apparatus, device, and medium. The method includes: generating a first fixed-length feature vector based on the minutiae topology of the fingerprint to be compared, and generating a second fixed-length feature vector based on the minutiae topology of a pre-stored fingerprint template; binarizing the first and second fixed-length feature vectors to obtain a first binarized feature vector and a second binarized feature vector; invoking the SIMD instruction set of an embedded processor to perform parallel operations on the first and second binarized feature vectors to calculate a distance value representing their similarity; and determining whether the fingerprint to be compared matches the pre-stored fingerprint template based on the distance value. Generating fixed-length feature vectors achieves feature data normalization, providing a data foundation with a unified structure and efficient memory access for subsequent processing. Furthermore, binarizing the fixed-length vectors compresses the data into a binary sequence, significantly reducing storage usage and simplifying similarity calculation to bitwise logical operations. Finally, invoking the SIMD instruction set built into the embedded processor performs parallel bitwise operations and statistics on the binarized vectors, transforming the core distance calculation into a hardware-level data parallel task, significantly improving computational throughput. This method systematically adapts the fingerprint comparison process to the embedded processor architecture, thereby substantially improving computational efficiency to meet real-time requirements without increasing the cost and power consumption of dedicated hardware. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic flowchart of a SIMD-based fingerprint comparison method provided in an embodiment of the present invention; Figure 2 This is a schematic block diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0022] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0023] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0025] Please see Figure 1 This invention provides a SIMD-based fingerprint comparison method. By constructing a complete technical process encompassing feature structuring, data compression, and parallel computing optimization, it systematically solves multiple challenges faced by fingerprint comparison in embedded devices, such as computational bottlenecks, real-time constraints, and power consumption limitations. This substantially improves the overall computational efficiency of fingerprint feature comparison without significantly increasing dedicated hardware costs and power consumption, reliably meeting stringent real-time response requirements. Specifically, the method includes the following steps: S1, generate a first fixed-length feature vector based on the minutiae topology of the fingerprint to be compared, and generate a second fixed-length feature vector based on the minutiae topology of the pre-stored fingerprint template.

[0026] In practice, a first fixed-length feature vector and a second fixed-length feature vector are generated based on the topological structure of the minutiae of the fingerprint to be compared and the pre-stored fingerprint template, respectively. This lays the data foundation for the efficient operation of the entire algorithm and realizes the normalization and structuring of feature data. By forcibly transforming and encapsulating the multidimensional minutiae feature information, which may originally have a variable number and irregular structure, into feature vectors with a preset fixed dimension, the complexity of memory management and control flow logic branches caused by the dynamic changes in the number of feature points in traditional methods are fundamentally eliminated. This unified-dimensional data structure standardizes the input format of all subsequent processing steps, which not only simplifies algorithm design and implementation, but more importantly, provides the processor, especially its SIMD unit, with a predictable, continuous, and regular memory access pattern.

[0027] In some preferred embodiments, the above step "generating a first fixed-length feature vector based on the minutiae topology of the fingerprint to be compared" specifically includes the following steps: extracting information of N minutiae from the minutiae topology of the fingerprint to be compared, wherein the information of each minutiae includes an abscissa value, a ordinate value, and an orientation angle value, and N is a preset positive integer; sorting the extracted N minutiae in ascending order of their abscissa values; sequentially extracting the abscissa value, ordinate value, and orientation angle value of each minutiae as feature elements from the sorted information of the N minutiae; and combining the extracted 3N feature elements in a first predetermined order to form a first fixed-length feature vector with a dimension of 3N.

[0028] In practice, a set of standardized feature extraction and vector construction rules is implemented to provide a stable and uniform input data foundation for the entire fingerprint comparison process.

[0029] First, this embodiment explicitly specifies the extraction of a fixed number of N minutiae from the fingerprint to be compared, and standardizes the information of each minutiae into three basic feature elements: x-coordinate, y-coordinate, and orientation angle. This mandatory rule ensures that regardless of the number and distribution of minutiae in the original fingerprint image, the final generated first fixed-length feature vector has a completely definite and consistent dimension, namely 3N. This absolute fixation of data dimension fundamentally eliminates dynamic memory allocation, irregular data storage, and complex control flow logic caused by dynamic changes in the number of feature points. This allows the algorithm to have a predictable execution path and resource consumption when processing any input, greatly enhancing the stability and reliability of the system.

[0030] Furthermore, this step sorts the extracted N minutiae according to their x-coordinate values. This spatial sorting operation is not arbitrary; it introduces a stable spatial order to the feature vectors based on the physical structure of the fingerprint. This order ensures that the corresponding feature elements in the vector sequence remain highly consistent across different acquisitions of the same fingerprint, provided that the minutiae are successfully extracted. Conversely, for different fingerprints, due to the inherent differences in the spatial distribution of their minutiae, the sorted sequences will exhibit significant differences. This improves the repeatability and robustness of the same fingerprint feature representation while also enhancing the discriminative power between different fingerprint features, thus laying the foundation for high-precision matching at the data representation level.

[0031] Furthermore, the sorted feature elements are combined into a fixed-dimensional vector according to a first predetermined order. This operation creates ideal data conditions for subsequent efficient parallel computing. This step establishes a definite mapping relationship from the original fingerprint features to a continuous, linear address space in memory. The resulting first fixed-length feature vector exists in memory in an aligned, continuous block form, with its element arrangement strictly determined. This highly regular and deterministic data layout is a prerequisite for subsequent parallel computing using the SIMD (Single Instruction Multiple Data) instruction set. Because SIMD instructions need to efficiently and continuously load data blocks from memory into their wide registers, a feature vector with a fixed dimension, continuous memory layout, and predictable characteristics allows compilers or programmers to generate highly optimized data loading instruction sequences. This ensures that each SIMD load operation obtains a complete and useful data block, maximizing the use of the processor's memory bandwidth and avoiding performance penalties caused by non-contiguous or unaligned data access.

[0032] Further, in some preferred embodiments, the above step "extracting information of N minutiae from the minutiae topology of the fingerprint to be compared" specifically includes: obtaining a set of minutiae of the fingerprint to be compared, wherein each minutiae in the set has at least a type attribute, a coordinate attribute, and an orientation angle attribute; scoring and sorting the minutiae in the set according to a preset filtering rule, wherein the filtering rule is determined based on at least one of the following factors: the type weight of the minutiae, the distance weight from the fingerprint center point, and the density of minutiae in the local area; selecting K minutiae with scores higher than a preset scoring threshold from the sorted minutiae sequence, where K is a positive integer; if K is greater than N, selecting N minutiae from the first K minutiae based on their coordinate attributes using spatial uniformity sampling; if K is less than or equal to N, selecting N minutiae from the minutiae sequence in descending order of scores; and recording the x-coordinate, y-coordinate, and orientation angle values ​​of the finally selected N minutiae as the extracted information.

[0033] In practice, firstly, through fingerprint image preprocessing and feature extraction algorithms (such as gradient method or neural network model), all valid minutiae are detected from the fingerprint images to be compared, forming an initial set of minutiae. The data structure of each minutiae object in the set contains at least the following attribute fields: type attribute (e.g., classified as ridge endpoint or bifurcation point), coordinate attribute (x-coordinate and y-coordinate in pixels), and orientation angle attribute (the tangent angle θ of the ridge at that point).

[0034] Further, a detailed point screening, scoring, and ranking process based on multi-factor fusion is executed. For each detailed point i in the detailed point set, its comprehensive score Score_i is calculated. The comprehensive score is obtained by weighted summation of at least the following three components: Type weighting: Based on the type attribute of detail point i, a preset type weight value W_type is assigned to it. For example, the type weight of a bifurcation point can be set higher than that of a ridge endpoint to reflect their difference in feature stability.

[0035] Distance weighting component: Calculate the Euclidean distance Dist_i from the coordinates of the minutiae i to a preset fingerprint center point (usually the grayscale centroid or geometric center of the fingerprint image). Map Dist_i to a distance weight value W_dist according to a preset distance decay function (e.g., linear decay or Gaussian decay). This function is usually set to give higher weights to minutiae closer to the fingerprint center, as they typically have better image quality and stability.

[0036] Local density weighting: A square region with fixed side length or a circular region with fixed radius is defined as the local neighborhood, centered on the coordinates of the minutiae i. The number of other minutiae falling within this neighborhood is counted to obtain the local density Density_i. Density_i is then mapped to a density weight value W_density according to a preset density weighting function (e.g., an inverse ratio function or a threshold function). This function is typically used to appropriately reduce the weight of minutiae in overly dense regions to promote the uniformity of spatial distribution in subsequent selections.

[0037] Furthermore, the overall score is calculated as Score_i = α * W_type + β * W_dist + γ * W_density, where α, β, and γ are preset weighting coefficients used to balance the influence of each sub-item. After calculating the scores for all detail points, the entire set of detail points is sorted from highest to lowest according to Score_i, forming a sorted sequence of detail points.

[0038] Further, detail points are selected based on the sorting results. A preset scoring threshold T_score is set. Starting from the top of the sorted sequence, detail points with scores Score_i higher than the threshold T_score are selected sequentially until the number of selected detail points reaches K, or the sequence is traversed to the end. Here, K is the number of all detail points that meet the threshold condition, and is a positive integer.

[0039] Furthermore, based on the relationship between the quantity K and the target quantity N, the final N selected detail points are determined: If K > N: For the K minutiae with scores higher than the threshold, spatial uniformity sampling is performed based on their coordinate attributes. Specifically, a grid-based method can be used, dividing the fingerprint image region into several uniformly sized grids. Then, the minutiae with the highest score within each grid are selected first, until the total number reaches N. If the number of grids is greater than N, some grids can be merged or a second random selection can be performed; if the number after selection is less than N, the remaining unselected minutiae are supplemented according to their scores. This step aims to ensure that the selected minutiae are relatively evenly distributed in space, avoiding over-concentration in a certain local area.

[0040] Furthermore, if K ≤ N: Since the number of high-scoring detail points is limited, the top N detail points are selected directly from the entire detail point sequence in descending order of scores. If the total number of detail points is less than N, all detail points are selected.

[0041] Furthermore, the x-coordinate, y-coordinate, and orientation angle values ​​of the N detail points finally determined by the above process are recorded as the output of the step "extracting information from N detail points".

[0042] This embodiment significantly improves the quality of feature extraction and the overall performance of subsequent comparisons by introducing a minutiae selection mechanism based on multi-factor fusion scoring and spatial uniformity sampling. First, by comprehensively weighting the minutiae by type, distance from the fingerprint center, and local region minutiae density, a quantitative assessment of the stability and discriminative power of the minutiae is achieved. This results in a set of selected minutiae with higher feature representativeness and intrinsic reliability, laying a better data foundation for generating high-quality feature vectors.

[0043] Furthermore, when there are enough high-resolution detail points, the spatial uniformity sampling forces the selected detail points to be more evenly distributed in space, thereby capturing the overall topological structure of the fingerprint more comprehensively. This enhances the robustness to interference from real-world scenarios such as local deformation and poor imaging in some areas, and improves the discriminative power and generalization of the feature vector.

[0044] Furthermore, while ensuring a fixed number of detail points in the output, this mechanism not only guarantees the regularity of subsequent fixed-length feature vector generation, but also provides input data with higher information content and less noise for binarization processing and SIMD parallel distance calculation. Thus, while maintaining the efficient operation of the algorithm, it potentially improves the accuracy of fingerprint comparison and achieves synergistic optimization of efficiency and accuracy.

[0045] Furthermore, the above step "generating a second fixed-length feature vector based on the minutiae topology of the pre-stored fingerprint template" specifically includes the following steps: extracting information from M minutiae from the minutiae topology of the pre-stored fingerprint template, wherein the information of each minutiae includes an abscissa value, a ordinate value, and an orientation angle value, and M is a preset positive integer; sorting the extracted M minutiae in ascending order of their abscissa values; sequentially extracting the abscissa value, ordinate value, and orientation angle value of each minutiae as feature elements from the sorted M minutiae information; and combining the extracted 3M feature elements in a second predetermined order to form a second fixed-length feature vector with a dimension of 3M; wherein the first predetermined order is consistent with the second predetermined order, and N is equal to M.

[0046] In specific implementation, the generation method of the second fixed-length feature vector is the same as that of the first fixed-length feature vector, and will not be described again in this invention.

[0047] S2, the first fixed-length feature vector and the second fixed-length feature vector are binarized respectively to obtain the first binarized feature vector and the second binarized feature vector.

[0048] In specific implementation, the step of binarizing the fixed-length feature vector to obtain a binary feature vector produces a significant dual effect of data compression and computational simplification. This process quantizes each feature element in the original feature vector, which contains rich numerical information, into a simple binary value (0 or 1) according to a preset threshold. This transformation first leads to a sharp reduction in storage space requirements. The binary representation requires only one bit for each feature element, achieving a significant reduction in data volume compared to the original multi-bit integer or floating-point representation. For embedded environments with limited storage resources, this means that the number of fingerprint templates that can be accommodated can be multiplied, directly improving the practical capacity of the device.

[0049] Furthermore, binarization transforms the problem of measuring feature similarity into the problem of comparing binary sequences. Calculating the distance between two binary vectors, such as the Hamming distance, simplifies the core operations to bitwise XOR and bit counting operations. This computational model fundamentally eliminates complex arithmetic operations, and its operational logic is highly compatible with the bit manipulation instruction set of general-purpose processors. This paves the way for subsequent extreme parallel acceleration using SIMD technology and is a key transformation step in reducing the computational complexity of algorithms to a level that can be efficiently parallelized by hardware.

[0050] In some preferred embodiments, the above step of "binarizing the first fixed-length feature vector and the second fixed-length feature vector to obtain a first binarized feature vector and a second binarized feature vector" specifically includes the following steps: comparing each feature element in the first fixed-length feature vector with a first preset threshold; if the feature element is greater than the first preset threshold, it is quantized as 1, otherwise it is quantized as 0, thereby obtaining the first binarized feature vector; comparing each feature element in the second fixed-length feature vector with a second preset threshold; if the feature element is greater than the second preset threshold, it is quantized as 1, otherwise it is quantized as 0, thereby obtaining the second binarized feature vector; wherein, the first preset threshold and the second preset threshold are equal.

[0051] In practice, the specific rules for binarization are clearly defined: each feature element is compared with a corresponding preset threshold, and the result is quantized into a binary value of 1 or 0. Firstly, this process achieves extremely strong data compression. The original minutiae coordinates and orientation values ​​typically require 16-bit or 32-bit integers or even floating-point numbers for storage, while after binarization, each feature element can be represented using only one binary bit. This means that the memory space occupied by the feature vector is compressed to a fraction of its original size, or even less. For embedded devices with limited storage resources, this effect directly translates into a significant increase in the fingerprint template library capacity, allowing the device to register more user fingerprints.

[0052] Furthermore, binarization greatly simplifies the subsequent similarity calculation model. For binarized feature vectors, a core and efficient metric for measuring their similarity is the Hamming distance, which is the number of different corresponding bits in two equal-length binary strings. Calculating the Hamming distance essentially only requires bitwise XOR and bit-counting operations, which is much simpler than calculating the Euclidean distance between the original numerical vectors (which involves subtraction, multiplication, and square root). This reduction in computational complexity itself makes rapid comparison possible.

[0053] Furthermore, this simplified binary arithmetic model perfectly matches the bit manipulation instructions at the bottom layer of general-purpose processors and the bit-parallel processing capabilities of the SIMD instruction set. The bitwise XOR and bit counting operations for calculating Hamming distance can be mapped to extremely efficient SIMD bit instructions (such as bitwise XOR instructions) and bit counting instructions (such as population counting instructions). These instructions can perform parallel processing on all bits (such as 128 bits or 256 bits) in a vector register in one cycle, compressing the bit comparison and counting operations that require tens or hundreds of iterations in scalar algorithms into a very few vector instructions.

[0054] Therefore, the explicit binarization rule defined in this embodiment is not only a data-level compression, but also a transformation of the complex fingerprint feature matching problem into a highly parallelized bit logic operation problem that can be accelerated to the maximum extent by modern processor hardware. This is one of the core links to achieve ultra-high-speed comparison.

[0055] It should be noted that in the binarization process, the first preset threshold and the second preset threshold are the criteria used to quantize the numerical feature elements in the fixed-length feature vector into binary values. By comparing each feature element with its corresponding preset threshold, elements greater than the threshold are quantized into a first binary value (e.g., 1), and elements less than or equal to the threshold are quantized into a second binary value (e.g., 0), thereby generating a binarized feature vector. This process achieves data compression and transforms similarity calculation into bitwise logical operations. To ensure that the two binarized feature vectors are in a comparable binary space, the first preset threshold and the second preset threshold must have equal values ​​in a single comparison.

[0056] The specific value of the preset threshold can be determined based on the statistical characteristics of the feature data or prior knowledge. In some embodiments, it can be determined using one of the following methods: Fixed thresholds based on global statistical distribution: During the system training phase, by analyzing the statistical distribution of a large number of sample feature elements, their statistical median, mean, or specific quantiles are set as globally fixed preset thresholds.

[0057] Sample-based adaptive threshold: For a single fingerprint sample, calculate the statistical median or mean of all feature elements in its fixed-length feature vector, and use this value as the adaptive preset threshold for processing the sample.

[0058] Furthermore, in this embodiment, based on the different numerical distribution characteristics of the three feature elements—horizontal coordinate, vertical coordinate, and direction angle—independent preset thresholds are set for each.

[0059] By setting the preset thresholds as described above, we can effectively preserve the identification information of features while achieving data compression and simplified calculation, enhance the robustness of the algorithm to noise and minor deformations, and thus ensure the accuracy of fingerprint comparison.

[0060] S3, invoke the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing the similarity between the two.

[0061] In practice, the core of this method's performance leap lies in the step of using the embedded processor's built-in SIMD instruction set to perform parallel operations on the binarized feature vector to calculate the distance value. SIMD (Single Instruction Multiple Data) technology allows the processor to use its wide bit vector register and corresponding instructions to perform the same operation on multiple data elements packed in the register within one clock cycle. When applied to the binarized feature vector generated in the aforementioned steps, the bitwise comparison (XOR) and difference bit statistics (population counting) operations required to calculate the Hamming distance can be efficiently mapped to a single SIMD bit operation instruction and bit statistics instruction. This means that the bitwise processing that requires dozens or even hundreds of iterations in traditional scalar computation can now be compressed into a very few vector instructions. For example, a 128-bit SIMD bitwise XOR instruction can simultaneously compare 128 pairs of binary bits, while a dedicated bit counting instruction can quickly count the number of "1"s in the result. This hardware-level data parallelism allows the amount of data processed per unit time to increase several times, boosting the throughput of core distance calculation to a new order of magnitude, directly resulting in a significant reduction in the overall comparison time.

[0062] In some preferred embodiments, before invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value characterizing their similarity, the method further includes: determining the memory alignment length based on the bit width of the vector register of the SIMD instruction set; allocating addresses in memory for the first fixed-length feature vector, the second fixed-length feature vector, the first binarized feature vector, and the second binarized feature vector participating in the parallel operation, and ensuring that the starting position of the address is aligned with the memory alignment length.

[0063] In specific implementation, a preprocessing step for data memory address alignment is introduced. By actively managing the memory layout of data, the significant performance penalty caused by misaligned data access is eliminated, thereby ensuring that SIMD parallel computing instructions can execute at their designed optimal performance. This allows the theoretical effectiveness of the aforementioned computational acceleration methods to be stably and fully realized in the actual system. Modern processors, especially those with SIMD units, typically have requirements or a strong preference for memory access alignment. When a SIMD instruction attempts to load data from an address that is not aligned with a natural boundary (such as a 16-byte or 32-byte boundary), two situations may occur: first, a processor exception is triggered, forcing the software to perform slow exception handling; second, the hardware can still execute, but additional memory bus cycles are required to assemble the required data block, which is called "unaligned access overhead." This overhead significantly increases memory access latency, severely offsetting the speed advantage brought by SIMD computation itself. The technical means defined in this embodiment directly solves this problem. It first determines the explicit memory alignment length based on the hardware specifications of the SIMD instruction set used (e.g., a 128-bit vector register width corresponds to a 16-byte natural boundary). Subsequently, when allocating addresses in memory for the feature vectors involved in the computation, the processor actively ensures that their starting addresses meet the alignment requirement. This measure guarantees that all SIMD vector loading instructions in subsequent step S3 access aligned memory addresses. Aligned memory access allows the processor to acquire the complete data block at once with the fewest and fastest bus transactions and load it directly into the vector register, thus optimizing the data supply pipeline. This not only reduces the execution time of each load instruction but also reduces congestion in the memory subsystem and improves overall data throughput.

[0064] In some preferred embodiments, the distance value is the Hamming distance. The above step "calling the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity" specifically includes the following steps: using the vector loading instruction in the SIMD instruction set, the corresponding data blocks of the first and second binarized feature vectors are loaded in parallel into the vector register; using the bitwise XOR instruction in the SIMD instruction set, the corresponding data blocks in the vector register are subjected to a parallel bitwise XOR operation to obtain an intermediate result vector representing bit differences; using the population counting or bit extraction and accumulation instructions provided by the SIMD instruction set, the number of bits set in each element of the intermediate result vector is counted and accumulated in parallel to obtain the Hamming distance.

[0065] In practice, the calculation of Hamming distance is decomposed into three sub-steps that can be efficiently mapped by SIMD instructions: parallel loading, parallel bitwise XOR, and parallel bit statistics and accumulation. First, the corresponding data blocks of the binary feature vectors are loaded in parallel into the vector registers using vector loading instructions. This fully utilizes the bandwidth of the processor's wide-bit data bus, allowing a single memory transaction to acquire a large amount of data (e.g., 16 bytes, 32 bytes) required for the calculation. Compared to byte-by-byte loading in scalar processing, this significantly reduces the number of memory access instructions and the probability of cache misses, improving data supply efficiency. Further, a parallel bitwise XOR operation is performed on the two data blocks loaded into the registers using bitwise XOR instructions. This is the core of the Hamming distance calculation. This instruction can complete the logical XOR operation of all corresponding bits in the two vector registers within a single clock cycle. For example, for two 128-bit registers, it simultaneously compares 128 pairs of binary bits (determining if they are the same) and directly outputs an intermediate result vector representing the bit difference. This step achieves the comparison work that would require hundreds of cycles in a scalar loop within one clock cycle, which is key to the speed improvement. Finally, the XOR result vector is subjected to parallel bit counting using a population counting instruction. This instruction can directly calculate the number of "1" bits (i.e., the number of set bits) in a register value, efficiently completing the counting of difference bits. In some instruction set architectures, bit extraction and accumulation instructions may be combined to achieve the same purpose. This step avoids the inefficient loop of checking bit by bit through shift and mask operations. The entire process forms a highly efficient "load-compute-reduce" pipeline, with all operations completed at the vector register level, minimizing the back-and-forth movement of scalar control logic and intermediate data between registers and memory.

[0066] Therefore, this embodiment can ensure that the processor's parallel computing resources can be fully utilized when calculating the Hamming distance of the binarized fingerprint features, thereby directly and losslessly converting the hardware parallel capability of SIMD into a multiple increase in algorithm execution speed, and realizing the compression of comparison time from millisecond level to sub-millisecond level.

[0067] In one embodiment, the specific implementation is as follows: First, ensure that the first and second binarized feature vectors involved in the computation are stored in memory aligned to the width of the SIMD register (e.g., 128 bits) to guarantee the efficiency of subsequent loading operations.

[0068] The specific calculation process is executed cyclically in units of data blocks. In each iteration, SIMD vector loading instructions (such as vld1q_u8 or vle8.v) are first used to load consecutive data blocks with matching bit widths from the corresponding memory addresses of the two feature vectors into two independent vector registers (denoted as V1 and V2) in parallel, thus realizing a one-time batch reading of data.

[0069] Furthermore, a SIMD bitwise XOR instruction (such as veorq_u8 or vxor.vv) is invoked to perform a parallel logical XOR operation on all corresponding bits in registers V1 and V2. This instruction outputs the result to another vector register (denoted as V3) within one clock cycle, where each bit being 1 indicates a difference in the original vector at that position, thus obtaining an intermediate result vector representing the bit difference.

[0070] Furthermore, parallel bit statistics are performed on the intermediate result vector V3 to accumulate the difference count. Based on instruction set support, there are two main optimization paths: First, a vectorized population counting instruction (such as vcntq_u8) is used to calculate the number of "1" bits in each byte (or other data unit) of V3 in parallel, the result is stored in the vector register V4, and then all elements of V4 are summed using a vector reduction addition instruction (such as vaddvq_u8) to obtain the partial Hamming distance of the current data block. Second, a more specialized bit statistics instruction (such as vcpop.m in RVV) is used to directly calculate the total number of set bits in V3 and directly output the partial sum. All data blocks are processed iteratively, and the partial sums are accumulated to obtain the complete Hamming distance between the two feature vectors.

[0071] This embodiment compresses the comparison and statistical operations of multiple bits into a single instruction using SIMD instructions, realizing the transformation from serial bit looping to hardware-level parallel computing, which is the key to improving the core computing efficiency of fingerprint comparison.

[0072] In some preferred embodiments, the distance value is the Euclidean distance. The above step "calling the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity" specifically includes the following steps: loading the corresponding data blocks of the first and second binarized feature vectors into the vector register in parallel using the vector loading instruction in the SIMD instruction set; calculating the difference between each pair of elements in the corresponding data block in parallel using the vector subtraction instruction in the SIMD instruction set; calculating the square of each difference in parallel using the vector multiplication instruction in the SIMD instruction set; and accumulating the multiple squared results in parallel using the vector reduction addition instruction in the SIMD instruction set to obtain the sum of squares of the Euclidean distance.

[0073] In practice, calculating the Euclidean distance involves the sum of squared differences between corresponding vector elements. Traditional scalar implementations require iterative subtraction, multiplication, and addition. This embodiment breaks down this process and maps it into four consecutive SIMD vector operations: parallel loading, parallel subtraction, parallel multiplication, and parallel reduction accumulation.

[0074] First, the original binary feature vector data blocks are loaded into registers in parallel using vector loading instructions, providing a high-speed data source for subsequent calculations. Further, vector subtraction instructions simultaneously calculate the difference between all corresponding element pairs in the data block. For example, for a 128-bit SIMD unit that can hold four 32-bit floating-point numbers, a single subtraction instruction can perform four floating-point subtraction operations simultaneously, which is four times more efficient than scalar processing. Further, vector multiplication instructions perform parallel squaring (i.e., multiplying by itself) on each element in the difference vector obtained in the previous step, also in a data-parallel manner. Further, vector reduction addition instructions sum all elements in the squared result vector to obtain a scalar partial sum of squares. Although reduction operations usually involve some internal sequential stacking, the implementation efficiency of its dedicated instructions is far higher than manually accumulating the elements in the vector register using scalar loops. For feature vectors with large dimensions, the entire vector is divided into multiple blocks, each of which independently executes the above four-step pipeline. The sums of squares from each block are then summed to obtain the final sum of squares of the Euclidean distance. This "block vectorization" strategy allows core arithmetic operations with high computational intensity and good data independence to be fully executed in the SIMD pipeline, effectively hiding instruction latency and achieving dual optimization of instruction-level parallelism and data-level parallelism.

[0075] In one embodiment, the specific implementation is as follows: First, ensure that the first and second binarized feature vectors involved in the computation are stored in memory aligned to the width of the SIMD register (e.g., 128 bits) to guarantee the efficiency of subsequent loading operations.

[0076] This implementation performs iterative calculations in units of data blocks, the size of which is determined by the number of elements that the SIMD vector register can hold at one time. Assuming the vector register has a bit width of L bits and the data type bit width of each element in the feature vector is B bits (e.g., a 32-bit single-precision floating-point number or a 16-bit integer), then the number of elements that can be processed in parallel at one time is P = L / B.

[0077] In each iteration, a vector loading operation is performed first. Using the vector loading instructions provided by the SIMD instruction set (for example, for single-precision floating-point numbers, the ARM NEON architecture can use the vld1q_f32 instruction, and the RISC-V RVV architecture can use the vle32.v instruction), a complete data block containing P consecutive elements is loaded in parallel into two independent vector registers, denoted as vector register VA and vector register VB, respectively, from the memory starting address corresponding to the current iteration of the first and second binarized feature vectors.

[0078] After loading, parallel difference calculation is performed. A vector subtraction instruction from the SIMD instruction set (e.g., NEON's vsubq_f32 or RVV's vfsub.vv) is invoked, using vector registers VA and VB as input operands. This instruction performs a subtraction operation on each pair of corresponding elements in VA and VB within a single clock cycle, i.e., parallel calculation of VA[i] - VB[i] (i ranging from 0 to P-1). The output of this instruction is stored in a new vector register VC, where each element represents the difference between a pair of characteristic elements at the corresponding position.

[0079] Further, parallel squaring is performed. A vector multiplication instruction from the SIMD instruction set (e.g., NEON's vmulq_f32 or RVV's vfmul.vv) is invoked, with the vector register VC serving as both the first and second operands, to perform element-wise multiplication. This operation computes the square of each difference in parallel, i.e., VC[i] * VC[i]. The result is stored in the vector register VD, where each element is the square of the difference at the corresponding position.

[0080] Furthermore, parallel accumulation and reduction are performed. Vector reduction addition instructions from the SIMD instruction set are invoked (for example, NEON typically implements reduction through a series of vector addition and fetch instructions, while RVV can use the vfredsum.vs instruction) to perform parallel reduction and summation on all P squared elements in the vector register VD. This operation accumulates P scalar values ​​into a single scalar partial sum, which is the sum of the squares of the differences between P pairs of elements within the current data block.

[0081] Furthermore, the loading, subtraction, multiplication, and reduction steps described above are repeated iteratively until all elements of the two feature vectors have been processed. The scalar sums generated from all iterations are then accumulated; the final sum is the sum of squares of the Euclidean distance between the first and second binarized feature vectors. To obtain the standard Euclidean distance, a scalar square root operation can be performed on the sum of squares after all calculations are completed. This implementation fully utilizes data-level parallelism by mapping computationally intensive operations to SIMD vector pipeline operations, significantly improving the computational efficiency of Euclidean distance.

[0082] In some preferred embodiments, when the dimensions of the first binarized feature vector and the second binarized feature vector exceed a preset block processing threshold, the above step "calling the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate a distance value representing their similarity" specifically includes the following steps: determining the size of the target block for a single processing based on the cache size of the embedded processor and the bit width of the vector register of the SIMD instruction set; dividing the first binarized feature vector and the second binarized feature vector into multiple data blocks whose dimensions match the size of the target block; sequentially performing the parallel operation on each pair of corresponding data blocks in the first binarized feature vector and the second binarized feature vector, and accumulating the calculation results of all data blocks to obtain the distance value.

[0083] In practical implementation, for scenarios involving the processing of large-scale feature vectors, a parallel computing method based on a block-based strategy is introduced. By decomposing large-scale computing tasks into appropriately sized sub-task blocks that match hardware resources, the performance bottleneck caused by the limited cache capacity and register resources of embedded systems is effectively overcome. This achieves efficient and scalable parallel processing of high-dimensional fingerprint feature vectors, maintaining the processing speed of the algorithm under high-precision (high-dimensional) requirements. When the feature vector dimension is very high, its total data volume may exceed the cache capacity of each level of the processor. The block-based processing strategy provided in this embodiment is precisely to solve this problem.

[0084] First, the size of the "target block" for a single processing iteration is scientifically determined based on two key hardware constraints: processor cache size and SIMD register bit width. This size ensures that a data block and its intermediate results can be well accommodated in the cache, while its data width facilitates efficient loading by the SIMD register. Further, the high-dimensional feature vector is divided into a series of data blocks that conform to this target size. During computation, the algorithm sequentially performs complete SIMD parallel operations (such as calculating the local distance contribution of the block) on each corresponding pair of data blocks, and immediately accumulates the local results into the global variable.

[0085] This approach offers several advantages: First, it significantly improves cache hit rate. Since only a small block of data is processed in each loop, this block can be retained in the cache for extended periods for repeated computation, avoiding conflicts with subsequent data and ensuring the data supply rate remains close to the cache speed. Furthermore, it keeps register pressure manageable. Processing smaller data blocks requires fewer intermediate vector registers, reducing the risk of register overflow onto the stack. Finally, it provides excellent scalability and flexibility. Regardless of the overall dimension of the feature vectors, the algorithm processes them through stable block iterations, preventing performance from suddenly degrading when the dimension exceeds a certain threshold; simultaneously, the block size can be fine-tuned according to the specific hardware configuration of different embedded devices to achieve optimal cross-platform performance.

[0086] In one embodiment, the specific implementation is as follows: First, based on the capacity C (in bytes) of the L1 Data Cache of the embedded processor and the bit width L (in bits) of the vector register of the SIMD instruction set, combined with the data type bit width B of the feature vector elements (e.g., B=4 bytes for 32-bit floating-point numbers), the size of the target block for a single processing is determined by calculation.

[0087] Specifically, under the principles of ensuring data reusability and caching efficiency, the size of the target block is set such that the total memory footprint of all data involved in a single computation (including but not limited to a pair of data blocks from the first and second binarized feature vectors, as well as intermediate vectors during the computation process) is significantly less than the cache capacity C, thus avoiding cache thrashing. A typical strategy is to set the number of elements P_block contained in each feature vector of the target block such that the value of 2 * P_block * B * N_vectors is less than C * R. Here, N_vectors is the total number of vectors residing in registers or requiring caching in a single core parallel operation, and R is a utilization factor less than 1 (e.g., 0.5) used to reserve cache space for the system. Simultaneously, the value of P_block should be as close as possible to an integer multiple of (L / B), matching the number of elements that can be processed by a complete load of the SIMD vector register, to eliminate the performance loss caused by partial vector loading. The P_block value determined accordingly is the size of the target block (in terms of the number of elements).

[0088] After determining the target block size, the first and second binarized feature vectors are partitioned. Both feature vectors have the same total dimension D (total number of elements). The partitioning process starts from the beginning of the vector and sequentially extracts P_block consecutive elements to form a data block. For each feature vector, if its last data block contains fewer than P_block elements (when D is not divisible by P_block), this data block is considered a smaller tail block. Ultimately, the first binarized feature vector is partitioned into M sequentially arranged data blocks, denoted as Block_A1, Block_A2, ..., Block_AM; the second binarized feature vector is correspondingly partitioned into the same number M data blocks, denoted as Block_B1, Block_B2, ..., Block_BM, where any index i corresponds to Block_Ai and Block_Bi with the same starting position and number of elements in their respective vectors, forming a corresponding pair of data blocks.

[0089] Furthermore, during the computation phase, each pair of corresponding data blocks is processed sequentially using a loop-based iterative approach. For each pair of data blocks (Block_Ai, Block_Bi) with indices from 1 to M, the SIMD parallel computation process described above (e.g., loading, subtraction, multiplication, reduction and accumulation) is executed to calculate the partial distance value (or partial sum of squares) contributed by that pair of data blocks, Partial_Result_i. After each iteration calculates a Partial_Result_i, it is immediately accumulated into an accumulator register or memory variable, which is used to accumulate the computation results of all data blocks.

[0090] Furthermore, after the loop ends, the final value stored in the accumulator is the complete distance value for the entire feature vector pair (e.g., the total number of bits in the Hamming distance) or the sum of squares of the Euclidean distance. For the processing of the tail block, mask loading or partial storage operations provided in the SIMD instruction set ensure that only valid elements are computed, avoiding out-of-bounds access. This block-based strategy decomposes large-scale computation into a series of independent tasks matched with small-size cache and register resources. By improving data locality and maximizing cache hit rate and SIMD unit utilization, it achieves stable and efficient distance computation for high-dimensional feature vectors.

[0091] In some preferred embodiments, the SIMD instruction set is the NEON instruction set in an ARM architecture processor or a vector instruction extension in a RISC-V architecture processor.

[0092] In specific implementation, the SIMD instruction set will be an extension of two instruction sets widely supported by mainstream embedded processor architectures: ARM NEON or RISC-V Vector Instruction Extension (RVV). This invention does not specifically limit this.

[0093] In some preferred embodiments, step S1 uses a 16-bit signed integer data type to generate the fixed-length feature vector; in step S3, the parallel operation of calling the SIMD instruction set is achieved by calling a mathematical function library pre-compiled and optimized for the target embedded processor architecture, wherein the mathematical function library provides vector dot product, vector distance calculation or bit operation functions optimized based on the SIMD instruction set.

[0094] In this specific implementation, two key implementation details are further specified: first, a 16-bit signed integer data type is used when generating fixed-length feature vectors; second, SIMD parallel computation is achieved by calling a mathematical function library pre-compiled and optimized for the target processor architecture.

[0095] First, using 16-bit signed integers (int16) to represent minutiae coordinates and orientation information offers significant advantages over commonly used 32-bit integers (int32) or single-precision floating-point numbers (float32). At the storage level, the data footprint is halved, reducing memory bandwidth pressure and storage requirements. At the computation level, this choice has a positive impact on the parallelism of SIMD operations. For example, a 128-bit SIMD register can hold eight int16 data points simultaneously, but only four int32 or four float32 data points. This means that, with the same hardware resources, SIMD operations on int16 (such as loading, subtraction, and multiplication) have twice the data parallelism of the latter two, theoretically resulting in a significant increase in throughput. As long as the dynamic range and precision requirements of fingerprint features can be met by 16-bit integers, this data type downgrade is an effective way to achieve high performance at a very low cost.

[0096] Furthermore, implementing core SIMD operations by calling pre-compiled and optimized mathematical function libraries brings a dual improvement in development and runtime efficiency. These function libraries (such as ARM's CMSIS-DSP and RISC-V's vector math library) are meticulously developed by chip manufacturers or community experts. Their functions (such as vector dot product and distance calculation) are typically implemented directly using assembly language or compiler intrinsics, and are optimized for the specific processor's pipeline, cache, instruction latency, and other characteristics. Directly calling these functions avoids developers manually writing complex, error-prone, and difficult-to-portable SIMD inline code, lowering the technical threshold and development cycle. It also ensures that the computing kernel obtained on the target platform is a verified one that approaches the theoretical peak performance of the hardware. The stable and efficient "computational black box" provided by the library functions allows application-layer algorithms to focus on process logic, while delegating the most time-consuming computational parts to the optimized underlying implementation.

[0097] S4, determine whether the fingerprint to be compared matches the pre-stored fingerprint template based on the distance value.

[0098] In practice, the step of matching based on the efficiently calculated distance value is the logical endpoint of the entire process. Since the preceding steps have ensured the speed and accuracy of the distance value calculation, this step can make a quick decision based on the reliable calculation results, completing the entire comparison process.

[0099] Specifically, a preset matching threshold is set. The calculated distance value is compared with the matching threshold. If the distance value is less than or equal to the matching threshold, it is determined that the fingerprint to be compared matches the pre-stored fingerprint template; if the distance value is greater than the matching threshold, it is determined that the fingerprint to be compared does not match the pre-stored fingerprint template.

[0100] This invention proposes a SIMD-based fingerprint comparison method, comprising: generating a first fixed-length feature vector based on the minutiae topology of the fingerprint to be compared, and generating a second fixed-length feature vector based on the minutiae topology of a pre-stored fingerprint template; binarizing the first and second fixed-length feature vectors to obtain a first binarized feature vector and a second binarized feature vector; invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first and second binarized feature vectors to calculate a distance value representing their similarity; and determining whether the fingerprint to be compared matches the pre-stored fingerprint template based on the distance value. Generating fixed-length feature vectors achieves feature data normalization, providing a data foundation with a unified structure and efficient memory access for subsequent processing. Furthermore, binarizing the fixed-length vectors compresses the data into a binary sequence, significantly reducing storage usage and simplifying similarity calculation to bitwise logical operations. Finally, invoking the SIMD instruction set built into the embedded processor performs parallel bitwise operations and statistics on the binarized vectors, transforming the core distance calculation into a hardware-level data parallel task, significantly improving computational throughput. This method systematically adapts the fingerprint comparison process to the embedded processor architecture, thereby substantially improving computational efficiency to meet real-time requirements without increasing the cost and power consumption of dedicated hardware.

[0101] Corresponding to the above-described SIMD-based fingerprint comparison method, the present invention also provides a SIMD-based fingerprint comparison device. This SIMD-based fingerprint comparison device includes a unit for executing the aforementioned SIMD-based fingerprint comparison method, and can be configured in a terminal or a server. Specifically, the SIMD-based fingerprint comparison device includes: The generation unit is used to generate a first fixed-length feature vector based on the topological structure of the minutiae of the fingerprint to be compared, and to generate a second fixed-length feature vector based on the topological structure of the minutiae of the pre-stored fingerprint template. The binarization unit is used to binarize the first fixed-length feature vector and the second fixed-length feature vector respectively to obtain the first binarized feature vector and the second binarized feature vector; The arithmetic unit is used to call the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing the similarity between the two. The judgment unit is used to determine whether the fingerprint to be compared matches the pre-stored fingerprint template based on the distance value.

[0102] In some preferred embodiments, generating a first fixed-length feature vector based on the topological structure of the minutiae of the fingerprint to be compared includes: From the topological structure of the minutiae of the fingerprint to be compared, information of N minutiae is extracted, where the information of each minutiae includes the horizontal coordinate value, the vertical coordinate value and the orientation angle value, and N is a preset positive integer; The extracted N detail points are sorted in ascending order of their x-coordinate values; The x-coordinate, y-coordinate, and orientation angle values ​​of each of the sorted N detail points are extracted as feature elements. The extracted 3N feature elements are combined sequentially in a first predetermined order to form a first fixed-length feature vector with a dimension of 3N. The step of generating a second fixed-length feature vector based on the minutiae topology of the pre-stored fingerprint template includes: From the minutiae topology of the pre-stored fingerprint template, extract information of M minutiae, where the information of each minutiae includes the x-coordinate value, y-coordinate value and orientation angle value, and M is a preset positive integer; The extracted M detail points are sorted in ascending order of their x-coordinate values; Sequentially extract the x-coordinate, y-coordinate, and orientation angle values ​​of each of the sorted M detail points as feature elements; The extracted 3M feature elements are combined sequentially in a second predetermined order to form a second fixed-length feature vector with a dimension of 3M. Wherein, the first predetermined order is consistent with the second predetermined order, and N is equal to M.

[0103] In some preferred embodiments, the step of binarizing the first fixed-length feature vector and the second fixed-length feature vector to obtain a first binarized feature vector and a second binarized feature vector includes: Each feature element in the first fixed-length feature vector is compared with a first preset threshold. If the feature element is greater than the first preset threshold, it is quantized as 1; otherwise, it is quantized as 0, thereby obtaining the first binary feature vector. Each feature element in the second fixed-length feature vector is compared with a second preset threshold. If the feature element is greater than the second preset threshold, it is quantized to 1; otherwise, it is quantized to 0, thereby obtaining the second binarized feature vector. Wherein, the first preset threshold is equal to the second preset threshold.

[0104] In some preferred embodiments, the distance value is the Hamming distance, and the step of invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity includes: The vector loading instructions in the SIMD instruction set are used to load the corresponding data blocks of the first binarized feature vector and the second binarized feature vector into the vector register in parallel. The corresponding data block in the vector register is subjected to a parallel bitwise XOR operation using the bitwise XOR instruction in the SIMD instruction set to obtain an intermediate result vector representing the bit difference. The Hamming distance is obtained by using the population counting or bit extraction and accumulation instructions provided by the SIMD instruction set to perform parallel statistics and accumulation on the number of bits set for each element in the intermediate result vector.

[0105] In some preferred embodiments, the distance value is Euclidean distance, and the step of invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity includes: The vector loading instructions in the SIMD instruction set are used to load the corresponding data blocks of the first binarized feature vector and the second binarized feature vector into the vector register in parallel. The difference between each pair of elements in the corresponding data block is calculated in parallel using the vector subtraction instruction in the SIMD instruction set. The square of each difference is calculated in parallel using vector multiplication instructions in the SIMD instruction set; The sum of squares of the Euclidean distance is obtained by accumulating multiple squared results in parallel using the vector reduction addition instruction in the SIMD instruction set.

[0106] In some preferred embodiments, before invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity, the method further includes: The memory alignment length is determined based on the vector register bit width of the SIMD instruction set; Addresses are allocated in memory for the first fixed-length feature vector, the second fixed-length feature vector, the first binarized feature vector, and the second binarized feature vector that participate in the parallel operation, and the starting position of the address is aligned with the memory alignment length.

[0107] In some preferred embodiments, when the dimensions of the first binarized feature vector and the second binarized feature vector exceed a preset block processing threshold, the step of invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate a distance value characterizing their similarity includes: The size of the target block for a single processing step is determined based on the cache size of the embedded processor and the bit width of the vector register of the SIMD instruction set. The first binarized feature vector and the second binarized feature vector are divided into multiple data blocks with dimensions matching the target block size; The parallel operation is performed sequentially on each pair of corresponding data blocks in the first and second binarized feature vectors, and the calculation results of all data blocks are accumulated to obtain the distance value.

[0108] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned SIMD-based fingerprint comparison device and its various units can be referred to the corresponding descriptions in the foregoing method embodiments. For the sake of convenience and brevity, these details will not be repeated here.

[0109] The aforementioned SIMD-based fingerprint comparison device can be implemented as a computer program, which can be used in, for example... Figure 2 It runs on the computer device shown.

[0110] Please see Figure 2 , Figure 2 This is a schematic block diagram of a computer device provided in an embodiment of this application. The computer device 500 can be a terminal or a server, wherein the server can be a standalone server or a server cluster composed of multiple servers.

[0111] The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a system bus 501. The memory may include a non-volatile storage medium 503 and internal memory 504.

[0112] The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. When the computer program 5032 is executed, it causes the processor 502 to execute a SIMD-based fingerprint comparison method.

[0113] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.

[0114] The internal memory 504 provides an environment for the execution of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a SIMD-based fingerprint comparison method.

[0115] The network interface 505 is used for network communication with other devices. Those skilled in the art will understand that the above structure is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 500 to which the present application is applied. A specific computer device 500 may include more or fewer components than shown in the figures, or combine certain components, or have different component arrangements.

[0116] The processor 502 is used to run a computer program 5032 stored in the memory to perform the following steps: A first fixed-length feature vector is generated based on the topological structure of the minutiae of the fingerprint to be compared, and a second fixed-length feature vector is generated based on the topological structure of the minutiae of the pre-stored fingerprint template. The first fixed-length feature vector and the second fixed-length feature vector are binarized respectively to obtain the first binarized feature vector and the second binarized feature vector; The embedded processor's SIMD instruction set is invoked to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing the similarity between the two. Based on the distance value, it is determined whether the fingerprint to be compared matches the pre-stored fingerprint template.

[0117] In some preferred embodiments, generating a first fixed-length feature vector based on the topological structure of the minutiae of the fingerprint to be compared includes: From the topological structure of the minutiae of the fingerprint to be compared, information of N minutiae is extracted, where the information of each minutiae includes the horizontal coordinate value, the vertical coordinate value and the orientation angle value, and N is a preset positive integer; The extracted N detail points are sorted in ascending order of their x-coordinate values; The x-coordinate, y-coordinate, and orientation angle values ​​of each of the sorted N detail points are extracted as feature elements. The extracted 3N feature elements are combined sequentially in a first predetermined order to form a first fixed-length feature vector with a dimension of 3N. The step of generating a second fixed-length feature vector based on the minutiae topology of the pre-stored fingerprint template includes: From the minutiae topology of the pre-stored fingerprint template, extract information of M minutiae, where the information of each minutiae includes the x-coordinate value, y-coordinate value and orientation angle value, and M is a preset positive integer; The extracted M detail points are sorted in ascending order of their x-coordinate values; Sequentially extract the x-coordinate, y-coordinate, and orientation angle values ​​of each of the sorted M detail points as feature elements; The extracted 3M feature elements are combined sequentially in a second predetermined order to form a second fixed-length feature vector with a dimension of 3M. Wherein, the first predetermined order is consistent with the second predetermined order, and N is equal to M.

[0118] In some preferred embodiments, the step of binarizing the first fixed-length feature vector and the second fixed-length feature vector to obtain a first binarized feature vector and a second binarized feature vector includes: Each feature element in the first fixed-length feature vector is compared with a first preset threshold. If the feature element is greater than the first preset threshold, it is quantized as 1; otherwise, it is quantized as 0, thereby obtaining the first binary feature vector. Each feature element in the second fixed-length feature vector is compared with a second preset threshold. If the feature element is greater than the second preset threshold, it is quantized to 1; otherwise, it is quantized to 0, thereby obtaining the second binarized feature vector. Wherein, the first preset threshold is equal to the second preset threshold.

[0119] In some preferred embodiments, the distance value is the Hamming distance, and the step of invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity includes: The vector loading instructions in the SIMD instruction set are used to load the corresponding data blocks of the first binarized feature vector and the second binarized feature vector into the vector register in parallel. The corresponding data block in the vector register is subjected to a parallel bitwise XOR operation using the bitwise XOR instruction in the SIMD instruction set to obtain an intermediate result vector representing the bit difference. The Hamming distance is obtained by using the population counting or bit extraction and accumulation instructions provided by the SIMD instruction set to perform parallel statistics and accumulation on the number of bits set for each element in the intermediate result vector.

[0120] In some preferred embodiments, the distance value is Euclidean distance, and the step of invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity includes: The vector loading instructions in the SIMD instruction set are used to load the corresponding data blocks of the first binarized feature vector and the second binarized feature vector into the vector register in parallel. The difference between each pair of elements in the corresponding data block is calculated in parallel using the vector subtraction instruction in the SIMD instruction set. The square of each difference is calculated in parallel using vector multiplication instructions in the SIMD instruction set; The sum of squares of the Euclidean distance is obtained by accumulating multiple squared results in parallel using the vector reduction addition instruction in the SIMD instruction set.

[0121] In some preferred embodiments, before invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity, the method further includes: The memory alignment length is determined based on the vector register bit width of the SIMD instruction set; Addresses are allocated in memory for the first fixed-length feature vector, the second fixed-length feature vector, the first binarized feature vector, and the second binarized feature vector that participate in the parallel operation, and the starting position of the address is aligned with the memory alignment length.

[0122] In some preferred embodiments, when the dimensions of the first binarized feature vector and the second binarized feature vector exceed a preset block processing threshold, the step of invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate a distance value characterizing their similarity includes: The size of the target block for a single processing step is determined based on the cache size of the embedded processor and the bit width of the vector register of the SIMD instruction set. The first binarized feature vector and the second binarized feature vector are divided into multiple data blocks with dimensions matching the target block size; The parallel operation is performed sequentially on each pair of corresponding data blocks in the first and second binarized feature vectors, and the calculation results of all data blocks are accumulated to obtain the distance value.

[0123] It should be understood that in the embodiments of this application, the processor 502 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0124] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program may be stored in a storage medium, which is a computer-readable storage medium. The computer program is executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0125] Therefore, the present invention also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program. When executed by a processor, the computer program causes the processor to perform the following steps: A first fixed-length feature vector is generated based on the topological structure of the minutiae of the fingerprint to be compared, and a second fixed-length feature vector is generated based on the topological structure of the minutiae of the pre-stored fingerprint template. The first fixed-length feature vector and the second fixed-length feature vector are binarized respectively to obtain the first binarized feature vector and the second binarized feature vector; The embedded processor's SIMD instruction set is invoked to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing the similarity between the two. Based on the distance value, it is determined whether the fingerprint to be compared matches the pre-stored fingerprint template.

[0126] In some preferred embodiments, generating a first fixed-length feature vector based on the topological structure of the minutiae of the fingerprint to be compared includes: From the topological structure of the minutiae of the fingerprint to be compared, information of N minutiae is extracted, where the information of each minutiae includes the horizontal coordinate value, the vertical coordinate value and the orientation angle value, and N is a preset positive integer; The extracted N detail points are sorted in ascending order of their x-coordinate values; The x-coordinate, y-coordinate, and orientation angle values ​​of each of the sorted N detail points are extracted as feature elements. The extracted 3N feature elements are combined sequentially in a first predetermined order to form a first fixed-length feature vector with a dimension of 3N. The step of generating a second fixed-length feature vector based on the minutiae topology of the pre-stored fingerprint template includes: From the minutiae topology of the pre-stored fingerprint template, extract information of M minutiae, where the information of each minutiae includes the x-coordinate value, y-coordinate value and orientation angle value, and M is a preset positive integer; The extracted M detail points are sorted in ascending order of their x-coordinate values; Sequentially extract the x-coordinate, y-coordinate, and orientation angle values ​​of each of the sorted M detail points as feature elements; The extracted 3M feature elements are combined sequentially in a second predetermined order to form a second fixed-length feature vector with a dimension of 3M. Wherein, the first predetermined order is consistent with the second predetermined order, and N is equal to M.

[0127] In some preferred embodiments, the step of binarizing the first fixed-length feature vector and the second fixed-length feature vector to obtain a first binarized feature vector and a second binarized feature vector includes: Each feature element in the first fixed-length feature vector is compared with a first preset threshold. If the feature element is greater than the first preset threshold, it is quantized as 1; otherwise, it is quantized as 0, thereby obtaining the first binary feature vector. Each feature element in the second fixed-length feature vector is compared with a second preset threshold. If the feature element is greater than the second preset threshold, it is quantized to 1; otherwise, it is quantized to 0, thereby obtaining the second binarized feature vector. Wherein, the first preset threshold is equal to the second preset threshold.

[0128] In some preferred embodiments, the distance value is the Hamming distance, and the step of invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity includes: The vector loading instructions in the SIMD instruction set are used to load the corresponding data blocks of the first binarized feature vector and the second binarized feature vector into the vector register in parallel. The corresponding data block in the vector register is subjected to a parallel bitwise XOR operation using the bitwise XOR instruction in the SIMD instruction set to obtain an intermediate result vector representing the bit difference. The Hamming distance is obtained by using the population counting or bit extraction and accumulation instructions provided by the SIMD instruction set to perform parallel statistics and accumulation on the number of bits set for each element in the intermediate result vector.

[0129] In some preferred embodiments, the distance value is Euclidean distance, and the step of invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity includes: The vector loading instructions in the SIMD instruction set are used to load the corresponding data blocks of the first binarized feature vector and the second binarized feature vector into the vector register in parallel. The difference between each pair of elements in the corresponding data block is calculated in parallel using the vector subtraction instruction in the SIMD instruction set. The square of each difference is calculated in parallel using vector multiplication instructions in the SIMD instruction set; The sum of squares of the Euclidean distance is obtained by accumulating multiple squared results in parallel using the vector reduction addition instruction in the SIMD instruction set.

[0130] In some preferred embodiments, before invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity, the method further includes: The memory alignment length is determined based on the vector register bit width of the SIMD instruction set; Addresses are allocated in memory for the first fixed-length feature vector, the second fixed-length feature vector, the first binarized feature vector, and the second binarized feature vector that participate in the parallel operation, and the starting position of the address is aligned with the memory alignment length.

[0131] In some preferred embodiments, when the dimensions of the first binarized feature vector and the second binarized feature vector exceed a preset block processing threshold, the step of invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate a distance value characterizing their similarity includes: The size of the target block for a single processing step is determined based on the cache size of the embedded processor and the bit width of the vector register of the SIMD instruction set. The first binarized feature vector and the second binarized feature vector are divided into multiple data blocks with dimensions matching the target block size; The parallel operation is performed sequentially on each pair of corresponding data blocks in the first and second binarized feature vectors, and the calculation results of all data blocks are accumulated to obtain the distance value.

[0132] The storage medium is a physical, non-transient storage medium, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk, or any other physical storage medium capable of storing program code. The computer-readable storage medium can be non-volatile or volatile.

[0133] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0134] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0135] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0136] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0137] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0138] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0139] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A fingerprint comparison method based on SIMD, characterized in that, include: A first fixed-length feature vector is generated based on the topological structure of the minutiae of the fingerprint to be compared, and a second fixed-length feature vector is generated based on the topological structure of the minutiae of the pre-stored fingerprint template. The first fixed-length feature vector and the second fixed-length feature vector are binarized respectively to obtain the first binarized feature vector and the second binarized feature vector; The embedded processor's SIMD instruction set is invoked to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing the similarity between the two. Based on the distance value, it is determined whether the fingerprint to be compared matches the pre-stored fingerprint template.

2. The fingerprint comparison method based on SIMD according to claim 1, characterized in that, The step of generating a first fixed-length feature vector based on the topological structure of the minutiae of the fingerprint to be compared includes: From the topological structure of the minutiae of the fingerprint to be compared, information of N minutiae is extracted, where the information of each minutiae includes the horizontal coordinate value, the vertical coordinate value and the orientation angle value, and N is a preset positive integer; The extracted N detail points are sorted in ascending order of their x-coordinate values; The x-coordinate, y-coordinate, and orientation angle values ​​of each of the sorted N detail points are extracted as feature elements. The extracted 3N feature elements are combined sequentially in a first predetermined order to form the first fixed-length feature vector with a dimension of 3N. The step of generating a second fixed-length feature vector based on the minutiae topology of a pre-stored fingerprint template includes: From the minutiae topology of the pre-stored fingerprint template, extract information of M minutiae, where the information of each minutiae includes the x-coordinate value, y-coordinate value and orientation angle value, and M is a preset positive integer; The extracted M detail points are sorted in ascending order of their x-coordinate values; Sequentially extract the x-coordinate, y-coordinate, and orientation angle values ​​of each of the sorted M detail points as feature elements; The extracted 3M feature elements are combined sequentially in a second predetermined order to form a second fixed-length feature vector with a dimension of 3M. Wherein, the first predetermined order is consistent with the second predetermined order, and N is equal to M.

3. The fingerprint comparison method based on SIMD according to claim 1, characterized in that, The step of binarizing the first fixed-length feature vector and the second fixed-length feature vector to obtain a first binarized feature vector and a second binarized feature vector includes: Each feature element in the first fixed-length feature vector is compared with a first preset threshold. If the feature element is greater than the first preset threshold, it is quantized as 1; otherwise, it is quantized as 0, thereby obtaining the first binary feature vector. Each feature element in the second fixed-length feature vector is compared with a second preset threshold. If the feature element is greater than the second preset threshold, it is quantized to 1; otherwise, it is quantized to 0, thereby obtaining the second binarized feature vector. Wherein, the first preset threshold is equal to the second preset threshold.

4. The fingerprint comparison method based on SIMD according to claim 1, characterized in that, The distance value is the Hamming distance. The step of calling the embedded processor's SIMD instruction set to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity includes: The vector loading instructions in the SIMD instruction set are used to load the corresponding data blocks of the first binarized feature vector and the second binarized feature vector into the vector register in parallel. The corresponding data block in the vector register is subjected to a parallel bitwise XOR operation using the bitwise XOR instruction in the SIMD instruction set to obtain an intermediate result vector representing the bit difference. The Hamming distance is obtained by performing parallel counting and accumulation of the number of bits set for each element in the intermediate result vector using the population counting or bit extraction and accumulation instructions provided by the SIMD instruction set.

5. The fingerprint comparison method based on SIMD according to claim 1, characterized in that, The distance value is the Euclidean distance. The step of calling the embedded processor's SIMD instruction set to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity includes: The vector loading instructions in the SIMD instruction set are used to load the corresponding data blocks of the first binarized feature vector and the second binarized feature vector into the vector register in parallel. The difference between each pair of elements in the corresponding data block is calculated in parallel using the vector subtraction instruction in the SIMD instruction set. The square of each difference is calculated in parallel using vector multiplication instructions in the SIMD instruction set; The sum of squares of the Euclidean distance is obtained by accumulating multiple squared results in parallel using the vector reduction addition instruction in the SIMD instruction set.

6. The fingerprint comparison method based on SIMD according to claim 1, characterized in that, Before invoking the SIMD instruction set of the embedded processor to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate the distance value representing their similarity, the method further includes: The memory alignment length is determined based on the vector register bit width of the SIMD instruction set; Addresses are allocated in memory for the first fixed-length feature vector, the second fixed-length feature vector, the first binarized feature vector, and the second binarized feature vector that participate in the parallel operation, and the starting position of the address is aligned with the memory alignment length.

7. The SIMD-based fingerprint comparison method according to claim 1, characterized in that, When the dimensions of the first binarized feature vector and the second binarized feature vector exceed a preset block processing threshold, the embedded processor's SIMD instruction set is invoked to perform parallel operations on the first binarized feature vector and the second binarized feature vector to calculate a distance value representing their similarity, including: The size of the target block for a single processing step is determined based on the cache size of the embedded processor and the bit width of the vector register of the SIMD instruction set. The first binarized feature vector and the second binarized feature vector are divided into multiple data blocks with dimensions matching the target block size; The parallel operation is performed sequentially on each pair of corresponding data blocks in the first and second binarized feature vectors, and the calculation results of all data blocks are accumulated to obtain the distance value.

8. A fingerprint comparison device based on SIMD, characterized in that, Includes a unit for performing the method as described in any one of claims 1-7.

9. A computer device, characterized in that, The computer device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, can implement the method as described in any one of claims 1-7.

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