Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a charge multiplexing module. The charge multiplexing module has at least one first connection end and at least one second connection end. The first connection end is used for connecting a first clock wire, and the second connection end is used for connecting a second clock wire. The first clock wire is used for transmitting a first clock signal, and the second clock wire is used for transmitting a second clock signal. The first clock wire corresponds to the second clock wire one by one. The charge multiplexing module is provided with a charge transfer path for connecting the second clock wire and the corresponding first clock wire. The charge multiplexing module is used for supplying power to the corresponding second clock wire by using the electric energy on the first clock wire through the charge transfer path under the condition of meeting a first condition. The charge multiplexing module can use the potential difference in the clock signal edge switching to complete the energy transfer between the clock wires, significantly reduce the power consumption, and improve the driving efficiency.

Description

Technical Field

[0001] This application belongs to the field of display device technology, and in particular relates to gate driving circuits and display panels. Background Technology

[0002] As display technology evolves towards higher resolution, higher refresh rates, and larger sizes, panel power consumption has become increasingly prominent, especially in mobile display products such as laptops, where low power consumption has become a core requirement.

[0003] Gate Driver on Array (GOA) technology achieves narrow bezels and low cost by integrating the gate driver circuitry onto the array substrate. In traditional GOA schemes, during signal level switching (from high to low), the charge stored in the parasitic capacitance on the signal lines is directly released through the pull-down transistor, resulting in energy waste. Summary of the Invention

[0004] The purpose of this application is to provide a gate driving circuit and a display panel, which aims to solve the problem of energy waste in traditional gate driving circuits.

[0005] A first aspect of this application provides a gate driving circuit, including: a charge multiplexing module, the charge multiplexing module having at least one first connection terminal and at least one second connection terminal, the first connection terminal being used to connect to a first clock trace, the second connection terminal being used to connect to a second clock trace, the first clock trace being used to transmit a first clock signal, and the second clock trace being used to transmit a second clock signal; the first clock trace and the second clock trace correspond one-to-one, the charge multiplexing module having a charge transfer path connecting the second clock trace and the corresponding first clock trace; the charge multiplexing module being used, under the condition of satisfying a first condition, to supply power to the corresponding second clock trace using the electrical energy on the first clock trace through the charge transfer path, the first condition including: the first clock signal is a falling edge, and the corresponding second clock signal is a rising edge.

[0006] In one embodiment, the first clock signal includes a plurality of falling edges, and the second clock signal includes a plurality of rising edges, wherein each falling edge of the first clock signal is aligned with each rising edge of the second clock signal.

[0007] In one embodiment, the first condition further includes: the voltage of the first clock signal is greater than the voltage of the second clock signal.

[0008] In one embodiment, the charge multiplexing module is further configured to supply power to the corresponding first clock line via the charge transfer path using the electrical energy on the second clock line when a second condition is met. The second condition includes: the second clock signal is a falling edge, and the corresponding first clock signal is a rising edge.

[0009] In one embodiment, each rising edge of the first clock signal is aligned with each falling edge of the second clock signal.

[0010] In one embodiment, the second condition further includes that the voltage of the second clock signal is greater than the voltage of the first clock signal.

[0011] In one embodiment, the charge multiplexing module includes: at least one shorting switch device, the shorting switch device being connected to the first clock trace and the corresponding second clock trace respectively; the shorting switch device is configured to be in an on state when the first clock signal is a falling edge and the second clock signal is a rising edge, and / or to be in an on state when the first clock signal is a rising edge and the second clock signal is a falling edge.

[0012] In one embodiment, the charge multiplexing module includes a common node and at least two shorting switches. Each of the at least two shorting switches corresponds to one of at least two clock traces, including at least one first clock trace and at least one second clock trace. A first terminal of each shorting switch is connected to the corresponding clock trace, and a second terminal of each shorting switch is connected to the common node. The shorting switch connected to the first clock trace is turned on when the first clock signal is a falling edge, and the shorting switch connected to the second clock trace is turned on when the second clock signal is a rising edge. Alternatively, the shorting switch connected to the first clock trace is turned on when the first clock signal is a falling edge, and the shorting switch connected to the second clock trace is turned on when the second clock signal is a rising edge.

[0013] In one embodiment, the charge reuse module further includes a grounding switch, the first end of which is connected to the common node, and the second end of which is grounded.

[0014] A second aspect of this application provides a display panel including a pixel array and a gate driving circuit as described above, wherein the pixel array is connected to the gate driving circuit.

[0015] The beneficial effects of this application embodiment compared with the prior art are as follows: when the charge multiplexing module is connected to multiple clock traces, multiple sets of charge transfer paths can be formed between each first clock trace and second clock trace. Through precise edge matching of the clock signal by the charge multiplexing module, energy transfer between clock traces can be completed, significantly reducing power consumption and improving driving efficiency. Attached Figure Description

[0016] Figure 1 A schematic diagram of a gate driving circuit provided in an embodiment of this application; Figure 2 A circuit diagram of a charge multiplexing module provided in an embodiment of this application; Figure 3 for Figure 2 Waveforms of each clock signal and shorting pulse signal corresponding to the circuit diagram; Figure 4 Another circuit diagram of a charge multiplexing module provided in one embodiment of this application; Figure 5 for Figure 4 Waveforms of each clock signal and shorting pulse signal corresponding to the circuit diagram; Figure 6 for Figure 4 Another waveform diagram of each clock signal and shorting pulse signal corresponding to the circuit diagram; Figure 7 for Figure 4 Another waveform diagram of the various clock signals and shorting pulse signals corresponding to the circuit diagram; Figure 8 This is a schematic diagram of a display panel provided in one embodiment of this application.

[0017] Figure descriptions: 10, gate driving circuit; 20, display panel; 30, pixel array; 100, charge multiplexing module; 200, gate driving unit. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0019] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0020] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0022] Figure 1 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows: A gate drive circuit 10 includes: multiple clock traces (exemplary, Figure 1 The clock signals CLK1 to CLK8 and the charge multiplexing module 100 are shown. Clock traces are used to transmit clock signals. Specifically, the gate driving circuit 10 also includes a plurality of gate driving units 200, which are connected to corresponding clock traces. The gate driving units 200 are used to generate and output scan signals according to the received clock signals. The scan signals are used to drive the corresponding row pixels in the pixel array to write data.

[0023] The charge multiplexing module 100 has at least one first connection terminal and at least one second connection terminal. The first connection terminal is used to connect to a first clock trace, and the second connection terminal is used to connect to a second clock trace. The first clock trace is used to transmit a first clock signal, and the second clock trace is used to transmit a second clock signal. The first clock trace and the second clock trace correspond one-to-one. The charge multiplexing module 100 is provided with a charge transfer path connecting the second clock trace and the corresponding first clock trace.

[0024] The charge multiplexing module 100 is used to supply power to the corresponding second clock line through the charge transfer path using the electrical energy on the first clock line when a first condition is met. The first condition includes: the first clock signal is a falling edge, and the corresponding second clock signal is a rising edge.

[0025] In one embodiment, multiple gate driving units 200 are cascaded sequentially. The output terminal of the last-stage gate driving unit 200 is connected to the reset terminal of the first-stage gate driving unit 200. Each gate driving unit 200 outputs a scan signal, and its reset terminal resets the voltage of each potential in the circuit upon receiving a pulse signal or a high-level signal. It is understood that when the last-stage gate driving unit 200 outputs a corresponding pulse signal, it signifies the end of the scan cycle. The pulse signal output by the last-stage gate driving unit 200 can trigger the first-stage gate driving unit 200 to perform a reset operation. Therefore, by cascading multiple gate driving units 200, the reset functions of each gate driving unit 200 can be triggered sequentially, completing the potential reset of the gate driving circuit 10.

[0026] For example, in Figure 2 The diagram shows eight clock traces (CLK1 to CLK8), and the clock signals transmitted by each trace are as follows: Figure 3 As shown in the diagram, clock traces CLK1 and CLK5 form the first group of charge transfer paths, clock traces CLK2 and CLK6 form the second group, and so on, up to clock traces CLK4 and CLK8 forming the fourth group. In each group, the former can be the first clock trace, and the latter can be the second clock trace. This grouping method is only an example; based on the actual phase relationship of the clock signals, other clock traces with complementary edges can also be paired. The specific configuration can be based on the actual driving timing requirements.

[0027] Any set of charge transfer paths is configured to form a current path between the first clock trace and the second clock trace to transmit the voltage difference between the two clock signals, thereby realizing the multiplexing and transfer of charge between different clock signals.

[0028] Any set of charge transfer paths can be configured to be on or off. When any set of charge transfer paths is configured to be on, a current path is formed between the first clock trace and the second clock trace to transmit the voltage difference between the two clock signals, thereby realizing the multiplexing and transfer of charge between different clock signals.

[0029] If any set of charge transfer paths is configured to be off, the current path between the first clock trace and the second clock trace is broken, and the voltage difference between the two clock signals cannot be transferred.

[0030] This application does not limit the implementation method of the charge transfer path being on or off. As an example, the charge transfer path can be provided with a short-circuit switching device as described in the following embodiments. When the short-circuit switching device is on, any set of charge transfer paths can be configured to be on. When the short-circuit switching device is off / open, any set of charge transfer paths can be configured to be off.

[0031] In this embodiment, the charge multiplexing module 100 can utilize the potential difference when the clock signal edge switches to realize the transfer and reuse of charge between different clock lines.

[0032] Understandably, when a clock signal transitions from high to low, the parasitic capacitance on its trace stores a large amount of positive charge. In traditional solutions, this charge is directly discharged to ground, resulting in waste. However, in this embodiment, this charge from the first clock signal is guided to the second clock trace, which is currently on its rising edge and needs to be charged to a high level. This provides some of the necessary power to the second clock trace, reducing the amount of charge drawn from an external power source, achieving charge reuse, and lowering dynamic power consumption.

[0033] When the charge multiplexing module 100 is connected to multiple clock traces, each clock trace connected to the charge multiplexing module 100 may include multiple first clock traces and multiple second clock traces. The number of first clock traces and second clock traces are the same and they correspond one-to-one. Multiple sets of charge transfer paths can be formed between each first clock trace and second clock trace.

[0034] By precisely matching the edge of the clock signal with the charge multiplexing module 100, energy transfer between clock traces can be completed, significantly reducing power consumption and improving drive efficiency.

[0035] In one embodiment, the first clock signal includes a plurality of falling edges, and the second clock signal includes a plurality of rising edges, wherein each falling edge of the first clock signal is aligned with each rising edge of the second clock signal.

[0036] Understandably, when each falling edge of the first clock signal is aligned with each rising edge of the second clock signal, the charge multiplexing module 100 can continuously and stably complete the power transfer, ensuring that the second clock trace can efficiently draw charge from the first clock trace on the rising edge.

[0037] Specifically, the first clock signal and the second clock signal have the same frequency, thus ensuring that the falling edge of the first clock signal is strictly synchronized with the rising edge of the second clock signal. That is, the moment when the first clock signal begins to transition from high level to low level corresponds exactly to the moment when the second clock signal transitions from low level to high level.

[0038] For example, Figure 3 The clock signals on clock trace CLK1 and clock trace CLK5 shown are shown. The clock signal on clock trace CLK1 is the first clock signal, and the clock signal on clock trace CLK5 is the second clock signal. The falling edge of clock trace CLK1 is aligned with the rising edge of clock trace CLK5.

[0039] In one embodiment, the first condition further includes that the voltage of the first clock signal is greater than the voltage of the second clock signal.

[0040] For example, Figure 3 In the clock signals shown on clock trace CLK1 and clock trace CLK5, during the t1 stage, the clock signal on clock trace CLK1 is a falling edge and the clock signal on clock trace CLK5 is a rising edge. The voltage on clock trace CLK1 is greater than the voltage on clock trace CLK5, and clock trace CLK1 supplies power to clock trace CLK5.

[0041] Understandably, the charge multiplexing module 100 can only drive the charge to be directionally transferred from a high potential to a low potential when there is a voltage difference between the first clock signal and the second clock signal. Specifically, in the first half of the falling edge of the first clock signal, the voltage of the first clock signal is relatively high, while in the first half of the rising edge of the second clock signal, the voltage of the second clock signal is relatively low. At this time, the charge multiplexing module 100 can short-circuit the first clock trace and the second clock trace to form a power conduction path, allowing the charge to flow from the high-potential first clock trace to the low-potential second clock trace, thus completing energy multiplexing.

[0042] In one embodiment, the charge multiplexing module 100 is further configured to supply power to the corresponding first clock line via the charge transfer path using the electrical energy on the second clock line when a second condition is met. The second condition includes: the second clock signal is a falling edge, and the corresponding first clock signal is a rising edge.

[0043] By supplying power to the first clock trace based on the power on the second clock trace, and in conjunction with the power supply scheme of the first clock trace to the second clock trace in the above embodiment, bidirectional charge reuse can be achieved, further improving the overall energy efficiency ratio. In other words, the charge transfer path provided by the charge reuse module 100 is bidirectional. When the first clock signal is a rising edge and the second clock signal is a falling edge, power is supplied from the second clock trace to the first clock trace; when the second clock signal is a rising edge and the first clock signal is a falling edge, power is supplied from the first clock trace to the second clock trace.

[0044] In one embodiment, each rising edge of the first clock signal is aligned with each falling edge of the second clock signal.

[0045] For example, Figure 3 The clock signals on clock trace CLK1 and clock trace CLK5 shown are shown. The clock signal on clock trace CLK1 is the first clock signal, and the clock signal on clock trace CLK5 is the second clock signal. The rising edge of clock trace CLK1 is aligned with the falling edge of clock trace CLK5.

[0046] Understandably, when each rising edge of the first clock signal is aligned with each falling edge of the second clock signal, the charge multiplexing module 100 can continuously and stably complete the power transfer, ensuring that the first clock trace can efficiently draw charge from the second clock trace on the rising edge.

[0047] When the frequencies of the first and second clock signals are the same, their phases are opposite, meaning the phase difference is always 180°. This naturally satisfies the timing relationship of strict alignment between the rising and falling edges. This allows almost every rising edge of the first and second clock signals to receive power from the falling edge of the other clock signal, significantly reducing the overall system power consumption.

[0048] In one embodiment, the second condition further includes that the voltage of the second clock signal is greater than the voltage of the first clock signal.

[0049] For example, Figure 3 In the clock signals shown on clock trace CLK1 and clock trace CLK5, during stage t2, the clock signal on clock trace CLK5 is a falling edge and the clock signal on clock trace CLK1 is a rising edge. The voltage on clock trace CLK5 is greater than the voltage on clock trace CLK1, and clock trace CLK5 supplies power to clock trace CLK1.

[0050] Understandably, the charge multiplexing module 100 can only drive the charge to be directionally transferred from a high potential to a low potential when there is a voltage difference between the first clock signal and the second clock signal. Specifically, in the first half of the falling edge of the second clock signal, the voltage of the second clock signal is relatively high, while in the first half of the rising edge of the first clock signal, the voltage of the first clock signal is relatively low. At this time, the charge multiplexing module 100 can short-circuit the first clock trace and the second clock trace to form a power conduction path, so that the charge flows from the high-potential second clock trace to the low-potential first clock trace, thus completing energy multiplexing.

[0051] The charge multiplexing module 100 can ultimately realize dynamic, bidirectional, and precise transfer of charge between the first clock trace and the second clock trace, significantly reducing system power consumption and improving the energy efficiency of the display panel 20.

[0052] In one embodiment, such as Figure 2 As shown, the charge multiplexing module 100 includes at least one shorting switch. The two ends of the shorting switch are connected to a first clock trace and a corresponding second clock trace, respectively. The control terminal of the shorting switch receives a shorting pulse signal, which controls the shorting switch to turn on when the first clock signal is a falling edge and the second clock signal is a rising edge. Specifically, the shorting switch can be configured to be in an on state when the first clock signal is a falling edge and the second clock signal is a rising edge, and / or to be in an on state when the first clock signal is a rising edge and the second clock signal is a falling edge.

[0053] In some embodiments, the shorting switch is further configured to remain off when the first clock signal and the second clock signal are in a high-level state or a low-level state (i.e., when the first clock signal and the second clock signal are at a non-transition edge). This ensures that charge transfer only occurs during level transitions, avoiding static power consumption and signal interference.

[0054] by Figure 2 For example, at least one shorting switch device may include: shorting switch device Q1. Shorting switch device Q1 is directly connected between clock traces CLK1 and CLK5. The control terminal of shorting switch device Q1 receives a shorting pulse signal CS1. The shorting pulse signal CS1 is used to control shorting switch device Q1 to turn on or off.

[0055] Combination Figure 3 If the shorting pulse signal CS1 can be a narrow pulse at a high level, then CS1 is used to control the shorting switch Q1 to turn on. If the shorting pulse signal CS1 can be a wide pulse at a low level, then CS1 is used to control the shorting switch Q1 to turn off.

[0056] For example, combining Figure 3 The short-circuit pulse signal CS1 can be a periodic level signal, which includes a high level of a narrow pulse with a duration of 0.8ns to 1.2ns within one cycle, and can remain at a low level for the rest of the cycle.

[0057] Combination Figure 2In the timing diagram, at time t1, clock trace CLK1 is at a falling edge and clock trace CLK5 is at a rising edge. At this time, the short-circuit pulse signal CS1 generates a narrow high-level pulse with a duration of 1ns, controlling the short-circuit switch Q1 to turn on. In other words, short-circuit switch Q1 is turned on for the 1ns duration within one cycle. Thus, the charge on clock trace CLK1 flows to clock trace CLK5 through the turned-on short-circuit switch Q1, achieving charge sharing. After the pulse in one cycle ends, i.e., when the short-circuit pulse signal CS1 goes low, short-circuit switch Q1 turns off. In other words, short-circuit switch Q1 is turned off for the remaining time within one cycle, repeating in the next cycle without affecting subsequent normal drive operations.

[0058] In this embodiment, the connection between each shorting switch and the clock trace can be made using the existing vias on the clock trace, which will not be elaborated further. The shorting pulse signal can be generated by an external timing control module in conjunction with a level shift circuit and provided to each shorting switch. Specifically, the transition edge of each clock signal can be used as the trigger signal to generate the corresponding shorting pulse signal.

[0059] Specifically, the timing of the shorting pulse signal needs to be configured according to the timing of the first clock signal and the second clock signal to ensure that the shorting switching device only conducts during the window period when the charge can be reversed and reused (the first half of the rising / falling edge), thereby preventing charge backflow or ineffective conduction and ensuring the effectiveness of energy transfer. The pulse width of the shorting pulse signal (e.g., 0.8~1.2ns) can be optimized according to the size of the parasitic capacitance and the charge transfer speed in the actual circuit to achieve the best energy-saving effect.

[0060] For example, in such Figure 2 The circuit diagram shown contains four shorting switches (Q1, Q2, Q3, and Q4). Shorting switch Q1 is connected between clock traces CK1 and CK5, shorting switch Q2 is connected between clock traces CK2 and CK6, shorting switch Q3 is connected between clock traces CK3 and CK7, and shorting switch Q4 is connected between clock traces CK4 and CK8.

[0061] like Figure 3As shown, when clock trace CK1 experiences a falling edge and clock trace CK5 experiences a rising edge, the pulse of short-circuit pulse signal CS1 controls short-circuit switch Q1 to conduct, enabling energy transfer from CK1 to clock trace CK5. Similarly, when clock trace CK1 experiences a rising edge and clock trace CK5 experiences a falling edge, the pulse of short-circuit pulse signal CS1 controls short-circuit switch Q1 to conduct, enabling energy transfer from CK5 to clock trace CK1. Likewise, short-circuit switches Q2, Q3, and Q4 respond sequentially to the level changes of their respective clock signals, enabling bidirectional charge multiplexing between clock traces CK2 and CK6, CK3 and CK7, and CK4 and CK8.

[0062] In some embodiments, the short-circuit switching device employs a low-temperature polycrystalline silicon thin-film transistor, whose threshold voltage drift characteristics are highly matched with those of the pixel driving transistor, facilitating synchronous compensation through the same calibration mechanism.

[0063] In one embodiment, such as Figure 4 As shown, the charge multiplexing module 100 includes a common node and at least two shorting switching devices, in the case of... Figure 4 The circuit diagram shown contains eight shorting switches (shorting switches T1 to T8). At least two shorting switches correspond one-to-one with at least two clock traces, and the at least two clock traces include at least one first clock trace and at least one second clock trace. The first terminal of each shorting switch is connected to the corresponding clock trace, and the second terminal of each shorting switch is connected to a common node.

[0064] A shorting switch connected to the first clock trace is turned on when the first clock signal is a falling edge, a shorting switch connected to the second clock trace is turned on when the second clock signal is a rising edge, and / or, a shorting switch connected to the first clock trace is turned on when the first clock signal is a falling edge, and a shorting switch connected to the second clock trace is turned on when the second clock signal is a rising edge.

[0065] Understandably, the common node serves as a hub for charge storage and redistribution. Each short-circuit switch can dynamically turn on and off based on voltage changes on its corresponding clock line, enabling on-demand coupling and precise scheduling of charge between multiple clock signals. This embodiment allows for more flexible connection of multiple clock lines through the common node, providing a foundation for more complex multi-phase collaborative charge sharing. For example, multiple short-circuit switches can be simultaneously activated, allowing multiple clock lines on their falling edges to release charge to the common node at the same time, which is then absorbed by clock lines on their rising edges, achieving centralized charge allocation.

[0066] Specifically, when the clock signal of the clock trace is a falling edge or a rising edge, the corresponding short-circuit switching device can be turned on in the first half of the falling edge or the first half of the rising edge, thereby completing the charge transfer under the drive of voltage difference.

[0067] For example, in one embodiment, each clock trace (CLK1-CLK8) is connected to a common node COM via a corresponding shorting switch (T1-T8). Taking the charge sharing between clock traces CLK1 and CLK5 as an example, when a falling edge of clock trace CLK1 and a rising edge of clock trace CLK5 are detected, shorting pulse signals CS1 and CS5 simultaneously generate narrow pulses, controlling the corresponding shorting switches T1 and T5 to turn on. Thus, charge flows from clock trace CLK1, through shorting switch T1, the common node COM, and shorting switch T5, finally flowing to clock trace CLK5, completing the charge transfer.

[0068] In one embodiment, such as Figure 4 As shown, the charge multiplexing module 100 also includes a grounding switch T9. The first terminal of the grounding switch T9 is connected to a common node, and the second terminal of the grounding switch T9 is grounded. The control terminal of the grounding switch T9 can be used to receive a mode control signal CS MODE, which can control the grounding switch T9 to turn on and off.

[0069] When grounding switch T9 is turned on, the common node is pulled down to ground potential, which can effectively release residual charge and avoid voltage accumulation or crosstalk caused by node floating. The turning on of grounding switch T9 is usually performed during the blanking period of each frame refresh cycle to ensure that the common node is at a certain potential at the beginning of the next frame, thereby improving timing control accuracy and system stability.

[0070] For example, Figure 5 The diagram shows the waveforms of each clock signal when the mode control signal CS MODE remains low. Figure 6 The diagram shows the waveforms of each clock signal when the mode control signal CS MODE is high during the initial phase. Figure 7 The waveforms of each clock signal are shown when the mode control signal CS MODE is always kept high.

[0071] It should be noted that the high level of the clock signal is a positive voltage (e.g., 25V), the low level of the clock signal is a negative voltage (e.g., -6V), and the ground potential is 0V. Therefore, by turning on the grounding switch T9, the common node is pulled low to ground potential, allowing power to be supplied to each rising edge of clock traces CLK1, CLK2, CLK3, and CLK4 through the common node, thus achieving charge sharing.

[0072] Figure 8 A schematic diagram of a display panel according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows: A display panel 20 includes a pixel array 30 and a gate driving circuit 10 as described in any of the above embodiments, wherein the pixel array 30 is connected to the gate driving circuit 10.

[0073] Since the display panel 20 includes the gate driving circuit 10 of any of the above embodiments, the display panel 20 has the beneficial effects of the gate driving circuit 10 of any of the above embodiments, which will not be described again here.

[0074] In some embodiments, the display panel 20 may specifically be a liquid crystal display panel.

[0075] From the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0076] It should be understood that the apparatuses and methods disclosed in the several embodiments provided in this application can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division. In actual implementation, there may be other division methods, such as multiple units or components being combined or integrated into another device. In addition, some features may be omitted or not performed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0077] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units. That is, it can be located in one place or distributed in multiple different locations. Depending on the actual needs, some or all of the units can be selected to achieve the purpose of this solution.

[0078] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit; they can also exist physically separately; or some units can be integrated into one unit while others exist physically separately. The integrated units described above can be implemented in hardware or as software functional units.

[0079] It should be noted that all or part of the above embodiments provided in this application (e.g., part or all of any feature) can be arbitrarily combined or combined with each other.

[0080] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A gate driving circuit, characterized in that, include: A charge multiplexing module has at least one first connection terminal and at least one second connection terminal. The first connection terminal is used to connect to a first clock trace, and the second connection terminal is used to connect to a second clock trace. The first clock trace is used to transmit a first clock signal, and the second clock trace is used to transmit a second clock signal. The first clock trace and the second clock trace correspond one-to-one. The charge multiplexing module is provided with a charge transfer path connecting the second clock trace and the corresponding first clock trace. The charge multiplexing module is used to supply power to the corresponding second clock line through the charge transfer path using the electrical energy on the first clock line when a first condition is met. The first condition includes: the first clock signal is a falling edge, and the corresponding second clock signal is a rising edge; and the voltage of the first clock signal is greater than the voltage of the second clock signal. The charge multiplexing module includes a common node and at least two shorting switches, and the at least two shorting switches correspond one-to-one with at least two clock lines. The at least two clock lines include at least one first clock line and at least one second clock line. The first terminal of each of the aforementioned shorting switch devices is connected to the corresponding clock trace, and the second terminal of each of the aforementioned shorting switch devices is connected to the common node. The control terminal of the shorting switch device receives a shorting pulse signal, which is used to control the shorting switch device to be turned on or off. The shorting switch connected to the first clock trace is turned on when the first clock signal is a falling edge, and the shorting switch connected to the second clock trace is turned on when the second clock signal is a rising edge; The common node serves as a hub for charge storage and redistribution. It flexibly connects to multiple clock lines, and each short-circuit switching device dynamically turns on and off according to the voltage changes on the corresponding clock line. In this process, the rising edges of each clock signal are used as trigger signals to generate corresponding short-circuit pulse signals. The timing of the short-circuit pulse signals needs to be configured according to the timing of the first clock signal and the second clock signal to ensure that the short-circuit switching device is turned on only during the window period when the charge can be reversed and reused. The pulse width of the short-circuit pulse signal is optimized according to the size of the parasitic capacitance and the charge transfer speed in the actual circuit. The window period refers to the first half of the rising edge or falling edge. The charge reuse module also includes a grounding switch. The first end of the grounding switch is connected to the common node, and the second end of the grounding switch is grounded. The grounding switch is turned on during the blanking period of each frame refresh cycle. When the grounding switch is turned on, the common node is pulled down to ground potential to ensure that the common node is at a certain potential at the start of the next frame.

2. The gate driving circuit as described in claim 1, characterized in that, The first clock signal includes multiple falling edges, and the second clock signal includes multiple rising edges, wherein each falling edge of the first clock signal is aligned with each rising edge of the second clock signal.

3. The gate driving circuit as described in claim 1, characterized in that, The charge multiplexing module is also used to supply power to the corresponding first clock line through the charge transfer path using the electrical energy on the second clock line when a second condition is met. The second condition includes: the second clock signal is a falling edge, and the corresponding first clock signal is a rising edge.

4. The gate driving circuit as described in claim 3, characterized in that, Each rising edge of the first clock signal is aligned with each falling edge of the second clock signal.

5. The gate driving circuit as described in claim 3, characterized in that, The second condition also includes that the voltage of the second clock signal is greater than the voltage of the first clock signal.

6. The gate driving circuit as described in claim 1, characterized in that, The shorting switch connected to the first clock trace is turned on when the first clock signal is a rising edge, and the shorting switch connected to the second clock trace is turned on when the second clock signal is a falling edge.

7. A display panel, characterized in that, It includes a pixel array and a gate driving circuit as described in any one of claims 1 to 6, wherein the pixel array is connected to the gate driving circuit.

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