A dual-mode TDC implementation method and system based on FPGA

Abstract

The application discloses a dual-mode TDC implementation method and system based on FPGA and relates to the technical field of electronic circuits, and the technical points are as follows: after a dual-mode signal generation circuit receives each STOP pulse, immediately output a logic sequence opposite to the last one as an effective delay signal, without waiting for the last signal to reset in a time delay link (TDL), that is, when the logic signal propagated last time has not completely faded out, the new reverse logic signal can independently propagate in the TDL, and the two will not interfere with each other; at the same time, the rising edge of the system clock only updates the main flip-flop state as the logic reference for the next trigger, without an additional reset process, so that the dead time of single measurement is strictly controlled to be a single period corresponding to the system clock, the double-period dead time of the existing scheme is significantly shortened, and the measurement rate is doubled synchronously; in a high-frequency pulse measurement scene, pulse loss caused by excessively long dead time can be effectively avoided, and the measurement efficiency is significantly improved.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a dual-mode TDC implementation method and system based on FPGA. Background Technology

[0002] In scenarios with stringent requirements for timestamp accuracy and measurement rate, such as radar and laser time-of-flight measurement, single-photon detection, and quantum information processing, the time-to-digital converter (TDC) serves as the core signal processing device, and its performance directly determines the measurement limit of the entire system. The core function of the TDC is to convert the time interval of the input pulse signal into a digital quantity, and dead time and measurement resolution are the core indicators for measuring its performance. Currently, the mainstream implementation paths of TDC are divided into two categories: application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs). Although ASIC solutions have stable performance, they have drawbacks such as long development cycles, high investment costs, and poor flexibility, making it difficult to meet the needs of small-to-medium batch applications or rapid iteration. On the other hand, FPGAs, with their rich on-chip reconfigurable hardware resources, have advantages such as flexible design, short development cycles, and support for online debugging and upgrades, and have become the mainstream platform for TDC implementation, widely used in scientific research experiments, customized equipment, and other scenarios.

[0003] Existing FPGA-TDC solutions generally adopt a design architecture of "single-mode logic propagation + priority encoder decoding + single-mode calibration". The typical implementation process is as follows: after an external STOP pulse triggers, a single logic level (usually logic 1) propagates step-by-step in the time delay chain (TDL) constructed by the FPGA carry chain. When the rising edge of the system clock arrives, the flip-flop latches the logic state of each carry unit and outputs the thermometer code. This code is then decoded by the priority encoder to obtain the initial fine count value, which is superimposed with the coarse count value generated by the coarse count generator to obtain the final timestamp. Finally, a single calibration lookup table is used to compensate for nonlinear errors. However, this inherent design logic exposes two core defects in actual implementation, severely restricting the performance improvement of TDC:

[0004] Firstly, because the existing scheme uses a single logic level for propagation, the next STOP pulse trigger must wait for the previously propagated logic signal to completely propagate and reset in the TDL (all carry units return to their initial state). Otherwise, the measurement signals from the two consecutive measurements will interfere with each other. In actual implementation, the reset process requires at least one system clock cycle, plus the one clock cycle occupied by the signal propagation itself, resulting in a dead time of at least two system clock cycles. For example, when the system clock is 100MHz (period 10ns), the dead time can reach 20ns, limiting the measurement rate to below 50MHz, which cannot meet the measurement requirements of high-frequency pulse signals.

[0005] Secondly, the delay units of the FPGA carry chain are affected by manufacturing processes and temperature drift, resulting in inherent "bubble" interference (abnormal logic state flipping of some carry units), causing the TDL delay characteristics to exhibit nonlinearity. Existing solutions only calibrate for a single logic propagation mode. In practical applications, random triggering of pulse signals may indirectly cause implicit changes in the logic propagation path. Delay deviations in uncovered propagation modes cannot be compensated, ultimately resulting in differential nonlinearity (DNL) typically greater than ±1 LSB and integral nonlinearity (INL) greater than ±2 LSB. The measurement resolution is difficult to break through the 10 ps level, which cannot meet the requirements of high-precision scenarios. Therefore, we propose a dual-mode TDC implementation method and system based on FPGA. Summary of the Invention

[0006] (a) Technical problems to be solved

[0007] To address the shortcomings of existing technologies, this invention provides a dual-mode TDC implementation method and system based on FPGA, solving the technical problems of long dead time, low measurement accuracy, and high resource consumption in existing FPGA-TDC technology.

[0008] (II) Technical Solution

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A dual-mode TDC implementation method based on FPGA is executed by a dedicated hardware circuit deployed inside the FPGA chip and driven synchronously by the FPGA system clock. The dedicated hardware circuit includes a dual-mode signal generation circuit, a time delay chain (TDL), a dual-mode encoder controller, a cascaded adder array, and a dual-mode logic generation circuit.

[0011] The time delay chain (TDL) is constructed using a series of dedicated carry chain modules within the FPGA chip. The total delay length is greater than the FPGA system clock cycle, and the layout is constrained to be within the same logic block.

[0012] Using the FPGA system clock as the timing reference, the steps for implementing dual-mode TDC are as follows:

[0013] Before the first STOP pulse is input, the dual-mode signal generation circuit outputs the preset initial logic, and the internal main flip-flop is preset to the corresponding reference state; after receiving the external STOP pulse, it immediately switches to output a logic 1 or logic 0 sequence that is the opposite of the previous one as an effective delay signal to TDL; the rising edge of the FPGA system clock updates the state of the main flip-flop to the current output logic inverted value, which serves as the reference for the next trigger, and the dead time of a single measurement is 1 system clock cycle;

[0014] After TDL receives a valid signal, the signal propagates step by step in the internal carry chain; when the clock rises, the internal flip-flops synchronously latch the node logic value, output the preset bit width digital signal, and send the first node S[0] and C[0] values ​​to the dual-mode encoder controller.

[0015] The dual-mode encoder controller distinguishes between the values ​​of S[0] and C[0]. When either value is valid, it generates a single valid start signal and resets synchronously. The encoder mode signal is determined based on the value of C[0] and output to the corresponding functional module.

[0016] After receiving the start signal, the cascaded adder array counts the number of logic 1s in the digital signal; the dual-mode logic generation circuit selects and outputs the fine count value before calibration according to the encoding mode signal.

[0017] The fine count value before calibration is nonlinearly calibrated to generate a coarse count value, and the two are superimposed to output the final timestamp.

[0018] Furthermore, the dual-mode signal generation circuit incorporates a series flip-flop and a complementary logic gate circuit, which includes AND gates, OR gates, and NOT gates to perform output logic inversion switching and synchronous update of the flip-flop state.

[0019] The dead time for a single measurement is one FPGA system clock cycle;

[0020] The time delay chain (TDL) consists of multiple sub-delay chains connected end-to-end. Each sub-delay chain contains a full adder, a lookup table, and a flip-flop. Adjacent sub-delay chains are electrically connected through the carry terminal of the full adder, and the output digital signal is synchronized with the rising edge of the FPGA system clock.

[0021] The S-node and C-node of the full adder are mapped one-to-one to the input terminals of the flip-flops.

[0022] Furthermore, the cascaded adder array adopts a multi-stage carry-first adder structure, with the number of sub-full adders at each stage configured according to the pairwise grouping operation requirements, ensuring that all operation results participate in the final total count of logic 1s;

[0023] The logic 0 calculator of the dual-mode logic generation circuit adopts a subtractor structure, with the subtrahend being the total number of delay nodes and the minuend being the total number of logic 1s;

[0024] The 2-to-1 multiplexer selects the output based on the encoding mode signal, and before calibration, the count value is synchronized with the timing of the encoding mode signal.

[0025] Furthermore, the dual-mode encoder controller has multiple sets of flip-flops and XOR gate circuits built in. The flip-flops are divided into two channels to process the S[0] value and C[0] value respectively. The output of the XOR gate circuit is used as the start signal output terminal, and the start signal is generated when the valid logic level is reached.

[0026] The encoding mode signal and the start signal are synchronized in timing;

[0027] The dedicated hardware circuit also includes a dual-mode fine counting calibration circuit, whose parameter storage unit uses FPGA on-chip storage resources;

[0028] The calibration operation unit uses a lookup table mapping combined with an interpolation structure to perform nonlinear calibration and control calibration error.

[0029] Furthermore, the dedicated hardware circuit also includes a coarse counter generator and a coarse counter and fine counter adder. The counting bit width of the coarse counter generator is configurable. When the count overflows, it outputs an overflow flag signal. The counting step size is 1 FPGA system clock cycle.

[0030] The bit width of the coarse and fine count adder is matched to the sum of the bit widths of the coarse and fine counts;

[0031] The triggering method of the STOP pulse signal can be selected through the FPGA configuration register. The dual-mode signal generation circuit uses a preset range of pulse input frequency and the minimum recognition width of the STOP pulse signal.

[0032] Furthermore, the total delay length of the time delay chain TDL exceeds a preset ratio by more than the FPGA system clock cycle, and the effective delay signal is in the propagation state when the rising edge of the clock arrives.

[0033] The delay deviation of each sub-delay chain is compensated by the dual-mode code density calibration parameter;

[0034] Two sets of calibration lookup tables store the cumulative delay values ​​in order of delay unit level.

[0035] A dual-mode TDC implementation system based on FPGA includes an FPGA core control unit, a clock management unit, a signal input interface unit, a data storage unit, a data output interface unit, and a power management unit. The FPGA core control unit has a built-in multi-channel synchronous trigger unit. The input terminal of the multi-channel synchronous trigger unit is electrically connected to the signal input interface unit, and the multiple output terminals are respectively connected to multiple independent dedicated hardware circuits.

[0036] The clock management unit is electrically connected to the system clock port of the FPGA core control unit to provide the system clock signal;

[0037] The input terminal of the signal input interface unit is used to receive external STOP pulse signals, and the output terminal is electrically connected to the input pin of the FPGA core control unit. After preprocessing the STOP pulse signal, it is transmitted to a dedicated hardware circuit.

[0038] The data storage unit communicates bidirectionally with the FPGA core control unit via a bus to store dual-mode code density calibration parameters, intermediate measurement data, historical data, and configuration parameters.

[0039] The data output interface unit is electrically connected to the timestamp output terminal of the FPGA core control unit, and uploads the final timestamp data to the external host computer.

[0040] The power management unit provides stable power to all modules of the system.

[0041] Furthermore, the clock management unit includes an external high-precision crystal oscillator circuit and a phase-locked loop circuit inside the FPGA core control unit. The phase-locked loop circuit performs frequency division, frequency multiplication, phase calibration and jitter suppression on the reference clock signal, and outputs multiple phase-synchronized system clock signals.

[0042] The signal input interface unit has built-in impedance matching, filtering, shaping and level conversion circuits. The output level of the level conversion circuit is matched with the standard level of the FPGA core control unit IO port.

[0043] Furthermore, the data storage unit includes an on-chip register group, on-chip block storage, and off-chip non-volatile memory. The on-chip register group stores real-time measurement intermediate data and control signals, the on-chip block storage stores dual-mode code density calibration parameters, and the off-chip non-volatile memory stores historical data, configuration parameters, and calibration lookup table backups.

[0044] The data output interface unit selects the communication mode through the configuration register and limits the data transmission delay to a preset range.

[0045] Furthermore, the FPGA core control unit uses an FPGA chip, and the time delay chain TDL in the dedicated hardware circuit can adaptively adjust the number of sub-delay chain levels, lookup table configuration, and layout constraint rules according to the carry chain resource structure of the selected FPGA chip.

[0046] The power management unit provides multiple voltage ranges.

[0047] The system includes single-channel and multi-channel operating modes. In multi-channel mode, each channel measures independently, and the crosstalk between channels and the synchronous measurement error are controlled within a preset range.

[0048] (III) Beneficial Effects

[0049] By reconstructing the FPGA-TDC architecture, the core pain points of existing solutions, such as long dead time, insufficient measurement accuracy, high resource consumption, and poor adaptability, are addressed, achieving comprehensive optimization of performance and practicality. It breaks through the inherent limitations of traditional single-mode TDC by using dual-mode alternating logic generation as its core. After the STOP pulse is triggered, it can immediately output the logic sequence opposite to the previous one as an effective delay signal without waiting for the previous signal to be reset in TDL. The dead time of a single measurement is strictly controlled to a single system clock cycle, which can effectively avoid the signal loss problem in high-frequency pulse measurement scenarios. At the same time, a dual-mode calibration mechanism is provided for the characteristics of dual-mode alternating propagation. Two sets of independent calibration lookup tables are used to compensate for the nonlinear errors in the two logic propagation modes respectively. While improving the measurement rate, it effectively suppresses the inherent bubble interference of TDL and the accuracy deviation caused by environmental factors, and simultaneously improves the measurement resolution and linearity, taking into account the dual requirements of high speed and high accuracy.

[0050] This invention replaces the traditional priority encoder with a cascaded adder array, fully reusing the dedicated carry chain resources of the FPGA. This avoids the exponential growth of encoder logic complexity with the TDL bit width, significantly reducing resource consumption. It allows for the parallel deployment of multiple independent TDC channels using the remaining on-chip resources of the FPGA. Combined with a multi-channel synchronous triggering unit, it achieves synchronous measurement from the same source, significantly improving multi-channel scalability. Furthermore, this invention incorporates multiple flexible adaptation mechanisms. The core control unit can be used with mainstream FPGA chips, and the TDL can adaptively adjust its structure and layout according to the chip's carry chain resources. Coarse counting parameters, triggering methods, and communication protocols can all be flexibly selected through configuration registers. It can adapt to different application scenarios without refactoring the core logic, significantly reducing secondary development costs and demonstrating outstanding engineering practicality and scenario compatibility. In addition, the multi-module collaborative design ensures long-term system stability. The clock management unit provides a low-jitter timing reference for the entire process, the signal input interface unit effectively suppresses external noise interference, the data storage unit adopts a multi-level architecture to ensure parameter and data security, and the power management unit provides stable power supply, enabling stable operation in a wide temperature range, comprehensively improving system reliability. Attached Figure Description

[0051] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0052] Figure 1 This is an overall circuit flowchart of an embodiment of the present invention;

[0053] Figure 2 This is a flowchart of the method according to an embodiment of the present invention;

[0054] Figure 3This is an architecture diagram of the system according to an embodiment of the present invention;

[0055] Figure 4 This is a circuit diagram of a dual-mode signal generation system in an embodiment of the present invention;

[0056] Figure 5 This is a time delay chain (TDL) diagram in an embodiment of the present invention;

[0057] Figure 6 This is a diagram of a cascaded addition array in an embodiment of the present invention;

[0058] Figure 7 This is a diagram of a dual-mode encoder controller in an embodiment of the present invention;

[0059] Figure 8 This is a circuit diagram for generating dual-mode logic in an embodiment of the present invention;

[0060] Figure 9 This is a diagram of the coarse counting generator in an embodiment of the present invention;

[0061] Figure 10 This is a diagram of a coarse-counting, fine-counting, and adding unit in an embodiment of the present invention. Detailed Implementation

[0062] This application provides a dual-mode TDC implementation method and system based on FPGA, solving the technical problems of long dead time, low measurement accuracy, and high resource consumption in existing FPGA-TDC technology. Figure 1 As shown.

[0063] Example 1: Single-channel dual-mode TDC

[0064] Reference Figures 1 to 3 As shown, this embodiment is a basic example that implements all the functions of a single-channel, low-dead-time, high-resolution TDC. The overall system adopts a hardware architecture with FPGA core control, clock management, signal input, data storage, and data output, as detailed below:

[0065] It is executed based on a dedicated hardware circuit deployed inside the FPGA chip and driven by the FPGA system clock. The dedicated hardware circuit includes a dual-mode signal generation circuit, a time delay chain TDL, a dual-mode encoder controller, a cascaded adder array, a dual-mode logic generation circuit, a dual-mode fine count calibration circuit, a coarse count generator, and a coarse and fine count adder.

[0066] The Time Delay Chain (TDL) is constructed using a single dedicated carry chain module within the FPGA chip. The total delay length is greater than the duration of a single FPGA system clock cycle, and the overall layout is constrained to have no cross-block breaks within the same logic block.

[0067] The method uses the FPGA system clock as the timing reference throughout, following the TDC working logic: receiving the pulse signal to be measured, converting the time information into a physical delay, encoding the physical quantity into a digital count value, error calibration and correction, and outputting the final timestamp digital result. The steps of the dual-mode TDC implementation method are as follows:

[0068] Step 1: Alternating Logic Sequence Generation: Before the first STOP pulse signal is input, the output signal LOGIC of the dual-mode signal generation circuit is preset to logic 0, and the internal master flip-flop DFF0 is preset to logic 1. When the externally input STOP pulse signal is received, the dual-mode signal generation circuit immediately switches the output signal LOGIC to a logic 1 sequence or logic 0 sequence that is completely opposite to the logic state of the effective delay signal output in response to the previous STOP pulse signal. This sequence is then output as the effective delay signal to the time delay chain TDL. When the rising edge of the FPGA system clock arrives, the state of the internal master flip-flop DFF0 is updated to the inverted value of the current output logic, serving as the effective propagation logic reference for the next STOP pulse signal. This serves as the signal reception and triggering stage for the TDC and is the entry point for the TDC to start a single measurement.

[0069] Step 2, Signal Delay Propagation and State Latching: After receiving the valid delay signal, the time delay chain TDL propagates the signal unidirectionally in the internally serial carry chain, correspondingly changing the logic values ​​of the S and C nodes of each full adder. When the rising edge of the FPGA system clock arrives, each D flip-flop inside the time delay chain TDL synchronously latches the logic value of the corresponding node and outputs DEL_EDP data with a bit width of 180 bits. At the same time, the S[0] value and C[0] value corresponding to the full adder of the first node are output to the dual-mode encoder controller. S[0] is the sum output signal of the full adder of the first node of the time delay chain TDL, and C[0] is the carry output signal of the full adder of the first node of the time delay chain TDL. The two are used to identify whether there is a valid delay signal propagation in TDL and to determine the current signal propagation logic type. It is the time-to-physical quantity conversion link of TDC and the basis for FPGA-TDC to achieve high-precision measurement. Through the delay chain, the extremely short time interval that cannot be directly measured is converted into a latchable circuit node logic state.

[0070] Step 3: Control Signal Generation: The dual-mode encoder distinguishes the level state of the received S[0] and C[0] values. If either of them is logic 1, the start signal is set to logic 1 when the rising edge of the FPGA system clock arrives, and the start signal is reset to logic 0 at the next rising edge of the FPGA system clock, forming a single valid pulse. At the same time, the encoding mode signal is determined according to the level state of the C[0] value. When the C[0] value is logic 1, it is marked as logic 1 encoding mode, and when the C[0] value is logic 0, it is marked as logic 0 encoding mode. The start signal and the encoding mode signal are synchronously output to the corresponding functional module, which is the encoding synchronization control link of TDC, ensuring the timing synchronization of the entire process of signal latching, counting statistics, and calibration output of TDC, and avoiding false triggering and code errors.

[0071] Step 4: Generating Initial Count Values: After receiving the start signal, the cascaded adder array uses the FPGA system clock as the timing reference to perform eight-stage serial full addition on the 180-bit DEL_EDP data. The first-stage full adder groups every two adjacent bits in the DEL_EDP data, calculates the number of logic 1s in each group, and outputs 90 full addends of 2 bits each. Subsequent full adders perform addition on the full addends output by the previous stage in pairs. If the number of full addends output by a certain stage is not a multiple of 2, the last full addend of that stage is directly fed into the next stage of the full adder array. The calculation ultimately outputs the total number of logic 1s through the eighth-stage full adder. The dual-mode logic generation circuit receives the encoding mode signal and the total number of logic 1s. It calculates the total number of logic 0s by subtracting the total number of logic 1s from the fixed total delay node number of 180. Then, it selects and outputs either the total number of logic 1s or the total number of logic 0s according to the encoding mode signal through the built-in two-to-one multiplexer. This output is used as the fine count value before calibration. This is the encoding conversion link between physical and digital quantities in TDC. It is the core conversion step of TDC, which converts the logic state latched by the delay chain into a calculable digital count value, completing the core conversion from time information to digital quantity.

[0072] Step 5: Dual-mode calibration and timestamp output: The bin width of each delay unit in the time delay chain (TDL) is pre-obtained through code density testing in both logic 1 and logic 0 propagation modes. The cumulative delay value corresponding to each delay unit is calculated. The cumulative delay value corresponding to logic 1 propagation mode is stored in the first calibration lookup table, and the cumulative delay value corresponding to logic 0 propagation mode is stored in the second calibration lookup table. These two lookup tables together form the dual-mode code density calibration parameters. After receiving the start signal and the encoding mode signal, the dual-mode fine-count calibration circuit matches and calls the corresponding calibration lookup table according to the encoding mode signal. The fine-count value before calibration is then mapped to the matching calibration lookup table, and the result is... The first step involves a value calculation to complete nonlinear calibration and error correction, outputting a precise fine count value. The second step involves a coarse count generator that, at the rising edge of each FPGA system clock, superimposes the count value with the time length corresponding to one FPGA system clock cycle to generate a continuously updated coarse count value. The third step involves a coarse and fine count adder that performs arithmetic superposition of the precise fine count value and the coarse count value latched under the same FPGA system clock cycle to generate and output a high-precision final timestamp corresponding to the STOP pulse signal. This serves as the error correction and result output stage for the corresponding TDC. By calibrating and compensating for the inherent nonlinear error of the TDC, and superimposing the coarse count to expand the range, the core working result of the TDC, namely the high-precision timestamp digital structure, is finally output.

[0073] Among them, by Figure 4 The dual-mode signal generation circuit shown has two sets of series-connected D flip-flops and complementary logic gates. The complementary logic gates include AND gates, OR gates and NOT gates, which are used to realize the inverted switching of the output logic and the synchronous update of the flip-flop state.

[0074] When the STOP pulse signal is input, the switching response time of the output logic is less than 1ns, ensuring that the dead time of a single measurement is one FPGA system clock cycle.

[0075] like Figure 5 As shown, the time delay chain TDL consists of 45 sub-delay chains connected end-to-end. Each sub-delay chain contains one full adder, four 6-input lookup tables, and four D flip-flops. Adjacent sub-delay chains are electrically connected through the carry output of the previous full adder and the carry input of the next full adder, forming a continuous and unbroken carry propagation path. The synchronization error between the output timing of the 180-bit DEL_EDP data and the rising edge of the FPGA system clock is less than 50ps. The sum output S node and carry output C node of the full adder are mapped one-to-one to the D input of a D flip-flop.

[0076] In addition, all eight full adders in the cascaded adder array adopt a carry-first adder structure, and the operation delay of each full adder is less than 2ns.

[0077] The number of sub-full adders in the first to eighth stage full adders are 90, 45, 22, 11, 6, 3, 2, and 1, respectively. Among the 11 full add values ​​output by the fourth stage full adder, the first 10 are grouped in pairs and input to the fifth stage full adder, and the last one is directly input to the sixth stage full adder. The two full add values ​​output by the seventh stage full adder are directly input to the eighth stage full adder to ensure that all full add values ​​participate in the final operation. The logic 0 calculator of the dual-mode logic generation circuit adopts a subtractor structure with a fixed subtrahend of 180 and a minuend of the total number of logic 1s. The operation delay is less than 1ns.

[0078] The 2-to-1 multiplexer has a gating response time of less than 500 ps to ensure that the output timing of the fine count value before calibration is synchronized with the encoding mode signal. For example, Figure 6 As shown, the function of the cascaded adder array is to calculate the number of 1s output by the TDL delay chain. In the previous stage (TDL delay chain), DEL_EDP[179:0] has been mapped and output logic 1 or 0. Therefore, in the cascaded adder array, the number of 1s in the measured value needs to be accumulated.

[0079] like Figure 8 As shown, the function of the dual-mode logic generation circuit is to calculate the small delay before calibration;

[0080] The input signal ADD_STEP7 is the number of logic 1s calculated by the cascaded adder array, and the logic 0 calculator is the total number of delay nodes minus the number of logic 1s, i.e.: 180 - ADD_STEP7;

[0081] If the encoding mode is equal to 1, that is, the pulse propagated by TDL is logic 1, then MUX_DATA=ADD_STEP7; otherwise, MUX_DATA=180-ADD_STEP7.

[0082] The dual-mode encoder controller has four sets of D flip-flops and two XOR gate circuits built in. The four sets of D flip-flops are divided into two channels, which are used to process the level states of S[0] and C[0] values ​​respectively. The output of each channel is electrically connected to the input of an XOR gate circuit. The output of the XOR gate circuit serves as the start signal output to ensure that the start signal is generated only when the value of S[0] or C[0] is logic 1. Figure 7 As shown, the function of the dual-mode encoder controller is to provide a start signal and encoding mode (logic 0 encoding or logic 1 encoding) to other modules when it receives a delay signal from TDL.

[0083] The dual-mode encoder will distinguish the input signal: (1) As long as either S[0] or C[0] is equal to 1, when the rising edge of the clock arrives, the start signal outputs 1 and is reset to 0 in the next cycle; (2) If the valid logic sequence is logic 1, when the rising edge of the clock arrives, the encoding mode outputs 1 and is reset to 0 in the next cycle.

[0084] The output start signal works as follows: (1) If S[0]=1, the Q terminal of FF0 outputs 1 to the D terminal of FF1. When the rising edge of the clock arrives, the Q port of FF1 outputs 1. At this time, the Q terminal of FF3 is 0. Therefore, the XOR gate outputs the start signal as 1, and the 1 output by the Q port of FF1 will be input to the CLR terminal of FF0 to set FF0. At the next rising edge of the clock, FF1 outputs 0. (2) Similarly, if C[0]=1, the Q terminal of FF2 outputs 1 to the D terminal of FF3. When the rising edge of the clock arrives, the Q port of FF3 outputs 1. At this time, the Q terminal of FF1 is 0. Therefore, the XOR gate outputs the start signal as 1, and the 1 output by the Q port of FF3 will be input to the CLR terminal of FF2 to set FF2. At the next rising edge of the clock, FF3 outputs 0.

[0085] The output encoding mode works as follows: (1) If C[0]=1, the Q terminal of FF2 outputs 1 to the D terminal of FF3. When the rising edge of the clock arrives, the Q port of FF3 outputs 1. At this time, the encoding mode is logic 1 encoding; (2) If C[0]=0, the Q terminal of FF2 does not change, that is, it still outputs 0 to the D terminal of FF3. When the rising edge of the clock arrives, the Q port of FF3 outputs 0. At this time, the encoding mode is logic 0 encoding;

[0086] The output of the coded mode signal and the output of the start signal are synchronized with a delay of less than 1ns; the parameter storage unit of the dual-mode fine counting calibration circuit is implemented using the on-chip BlockRAM of the FPGA, with a storage capacity of not less than 2×180×32bit, and supports single-cycle address access; the calibration operation unit adopts a lookup table mapping + linear interpolation structure, with a calibration delay of less than 3ns, and the fine counting nonlinearity error after calibration is less than 0.5LSB.

[0087] The coarse counter generator has a count bit width that can be configured from 16bit to 64bit. When the count overflows, it generates an overflow flag signal and outputs it synchronously. The count step size is fixed at 1 FPGA system clock cycle, and the count error is 0. The bit width of the coarse counter and fine counter adder is the sum of the coarse counter bit width and the fine counter bit width. It supports unsigned number addition operations, has an operation delay of less than 2.5ns, and has no carry propagation error.

[0088] The STOP pulse signal can be triggered by either rising edge or falling edge, and the triggering method can be selected through the FPGA configuration register; the dual-mode signal generation circuit has a minimum recognition width of less than 10ns for the STOP pulse signal and supports a pulse input frequency of up to 100MHz.

[0089] The total delay length of the time delay chain TDL is 5% to 20% longer than the FPGA system clock cycle to ensure that the effective delay signal is still in the propagation state when the rising edge of the FPGA system clock arrives; the delay deviation of each sub-delay chain is compensated by dual-mode code density calibration parameters, and the delay consistency error of each level after compensation is less than 1ps;

[0090] The code density test uses a random pulse input method. The frequency of the input pulse is 1 / 10 of the FPGA system clock frequency, and the test duration is not less than 10 seconds. The measurement accuracy of the bin width of each delay unit is less than 0.1ps. The first calibration lookup table and the second calibration lookup table are stored in address order. The address is the delay unit level (0-179), and the data is the cumulative delay value (unit: ps). Single-cycle reading is supported.

[0091] The dual-mode code density calibration mechanism has been enhanced and optimized, making it suitable for industrial and military measurement scenarios with wide temperature range and high stability requirements, further improving measurement linearity and long-term stability.

[0092] During the code density testing phase, the bin widths of each level of the TDL for the propagation modes of logic 1 and logic 0 were tested at multiple points under typical operating conditions of low temperature, normal temperature, and high temperature. The cumulative delay values ​​at different temperature points were used to generate multiple sets of temperature compensation calibration lookup tables, which were stored in the off-chip Flash and on-chip BlockRAM.

[0093] The dual-mode fine counting calibration circuit adds temperature matching logic. Based on the ambient temperature collected in real time by the FPGA's built-in temperature sensor, it automatically matches the calibration lookup table for the corresponding temperature range. Combined with the original mode matching mechanism, it achieves accurate error compensation in both propagation mode and temperature dimensions, further suppressing delay drift and nonlinear error caused by temperature drift.

[0094] The coarse counter generator is equipped with a clock temperature drift compensation coefficient, the coarse and fine counter adders dynamically correct the superposition results, and the signal input interface is equipped with a temperature adaptive filtering parameter to ensure stable signal quality across the entire temperature range.

[0095] Example 2: Multi-channel synchronous measurement extension

[0096] Based on Example 1, a multi-channel TDC system is extended to be implemented, which is suitable for scenarios that require multi-channel pulse synchronous time measurement. The overall hardware architecture retains the basic system modules, and a multi-channel synchronous trigger unit is added in the FPGA core control unit. The remaining clock, input, storage, output and power modules remain compatible.

[0097] The multi-channel synchronous triggering unit adopts a common global clock distribution architecture, which synchronously distributes the high-precision clock output by the system clock management unit to multiple independent dual-mode TDC hardware circuits, ensuring that the trigger timing deviation of each channel is at an extremely low level. After parallel preprocessing by the signal input interface unit, the external multiple STOP pulses are sent to the dual-mode signal generation circuit of the corresponding channel. Each channel's TDL, encoder controller, adder array, calibration circuit, and coarse counting unit work completely independently and in parallel without interfering with each other. The channels are isolated by FPGA internal resource partitioning and wiring to reduce crosstalk.

[0098] Each channel independently executes alternating logic generation, delay propagation, latch statistics, dual-mode calibration and timestamp overlay processes, and synchronously outputs multiple independent timestamp data. The data is temporarily stored in the on-chip storage unit and then uniformly uploaded to the host computer through the high-speed interface.

[0099] It can be configured with 1-8 channels for parallel measurement according to the FPGA resource capacity. Each channel fully reuses the core technology solution of Example 1, maintaining the low dead zone and high resolution characteristics of a single channel while realizing the ability of multi-channel synchronous measurement. It fully supports all the technical features of multi-channel system, synchronous triggering, and channel isolation in the claims, and is suitable for multi-channel parallel measurement scenarios such as multi-unit detection of lidar and multi-node quantum signal measurement.

[0100] Example 3 Dual-mode TDC System

[0101] Reference Figure 3 As shown, the FPGA-based dual-mode TDC implementation system based on Embodiment 1 includes an FPGA core control unit, a clock management unit, a signal input interface unit, a data storage unit, a data output interface unit, and a power management unit.

[0102] The FPGA core control unit has a dedicated hardware circuit deployed inside, and a built-in multi-channel synchronous triggering unit. The signal input terminal of the multi-channel synchronous triggering unit is electrically connected to the signal input interface unit, and the multiple signal output terminals are respectively connected to multiple independent dedicated hardware circuits. The synchronous triggering deviation is less than 10ps. The time delay chain TDL in the dedicated hardware circuit can adaptively adjust the number of sub-delay chains, lookup table configuration and layout constraint rules according to the carry chain resource structure of the selected FPGA chip.

[0103] The power management unit provides supply voltages of 3.3V, 2.5V, 1.8V, and 1.0V, with an output voltage ripple of less than 50mV. The system supports both single-channel and multi-channel (up to 8 channels) operating modes. In multi-channel mode, each channel is measured independently, with crosstalk between channels less than -80dB and synchronous measurement error less than 10ps.

[0104] The clock output terminal of the clock management unit is electrically connected to the system clock port of the FPGA core control unit, and is used to provide a highly stable system clock signal for the FPGA core control unit and internal dedicated hardware circuits. The clock management unit includes an external high-precision crystal oscillator circuit and a phase-locked loop circuit inside the FPGA core control unit. The frequency stability of the external high-precision crystal oscillator circuit is ≤±1ppm. The phase-locked loop circuit is used to divide, multiply, phase calibrate and suppress jitter of the reference clock signal input from the external crystal oscillator circuit, and output multiple phase-synchronized system clock signals with a clock jitter of less than 5ps.

[0105] The signal input interface unit has built-in impedance matching circuit, low-pass filter circuit, edge shaping circuit and level conversion circuit. The characteristic impedance of the impedance matching circuit is 50Ω, the cutoff frequency of the low-pass filter circuit is 1GHz, and the output level of the level conversion circuit matches the I / O port level standard (LVCMOS 3.3V / 2.5V, LVDS) of the FPGA core control unit. The rise and fall times of the pre-processed signal are less than 1ns.

[0106] The signal input terminal of the signal input interface unit is used to receive external STOP pulse signals, and the signal output terminal is electrically connected to the external input pin of the FPGA core control unit. It is used to preprocess the externally input STOP pulse signals and then transmit them to the dual-mode signal generation circuit of the dedicated hardware circuit.

[0107] The data storage unit is bidirectionally connected to the FPGA core control unit via a parallel bus. It is used to store dual-mode code density calibration parameters, intermediate data during the measurement process, historical measurement data, and circuit configuration parameters. The data storage unit includes an on-chip register group, an on-chip BlockRAM, and an off-chip non-volatile memory. The on-chip register group is used to store intermediate data and control signals for real-time measurement. The on-chip BlockRAM is used to store dual-mode code density calibration parameters. The off-chip non-volatile memory is used to store historical measurement data, circuit configuration parameters, and calibration lookup table backup data.

[0108] The data output interface unit is compatible with four communication protocols: UART (baud rate up to 115200bps), SPI (clock frequency up to 100MHz), Ethernet (Gigabit Ethernet) and USB 3.0. The communication mode can be selected through the configuration register, and the data transmission delay is less than 1ms.

[0109] The data output interface unit is electrically connected to the timestamp output terminal of the FPGA core control unit, and is used to upload the high-precision final timestamp data output by the dedicated hardware circuit to the external host computer.

[0110] The power management unit provides a stable power supply voltage to each module of the system, ensuring that each module operates stably.

[0111] like Figure 9 As shown, the function of the coarse count generator is to calculate the coarse time of the system; the coarse count generator adds Tclk on each rising edge of the clock, where Tclk is the CLK clock cycle, and the resulting value is the coarse count CNTR.

[0112] like Figure 10 As shown, the function of the coarse and fine count adder is to calculate the precise time of the pulse. The coarse and fine count adder adds the fine count CNTF output by the dual-mode fine count calibration circuit and the coarse count CNTR output by the coarse count generator, and the result is the final timestamp.

[0113] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A dual-mode TDC implementation method based on FPGA, characterized in that, It is executed based on dedicated hardware circuits deployed inside the FPGA chip and driven synchronously by the FPGA system clock. The dedicated hardware circuits include a dual-mode signal generation circuit, a time delay chain (TDL), a dual-mode encoder controller, a cascaded adder array, and a dual-mode logic generation circuit. The time delay chain (TDL) is constructed using a series of dedicated carry chain modules within the FPGA chip. The total delay length is greater than the FPGA system clock cycle, and the layout is constrained to be within the same logic block. Using the FPGA system clock as the timing reference, the steps for implementing dual-mode TDC are as follows: Before the first STOP pulse is input, the dual-mode signal generation circuit outputs the preset initial logic, and the internal main flip-flop is preset to the corresponding reference state; after receiving the external STOP pulse, it immediately switches to output a logic 1 or logic 0 sequence that is the opposite of the previous one as an effective delay signal to TDL; the rising edge of the FPGA system clock updates the state of the main flip-flop to the current output logic inverted value, which serves as the reference for the next trigger, and the dead time of a single measurement is 1 system clock cycle; After receiving a valid signal, the signal propagates step by step in the internal carry chain. When the clock rises, the internal flip-flops synchronously latch the node logic value, output a preset bit width digital signal, and send the first node S[0] and C[0] values ​​to the dual-mode encoder controller. S[0] is the sum output signal of the full adder of the first node of the time delay chain TDL, and C[0] is the carry output signal of the full adder of the first node of the time delay chain TDL. The dual-mode encoder controller distinguishes between the values ​​of S[0] and C[0]. When either value is valid, it generates a single valid start signal and resets synchronously. The encoder mode signal is determined based on the value of C[0] and output to the corresponding functional module. After receiving the start signal, the cascaded adder array counts the number of logic 1s in the digital signal; the dual-mode logic generation circuit selects and outputs the fine count value before calibration according to the encoding mode signal. The fine count value before calibration is nonlinearly calibrated to generate a coarse count value, and the two are superimposed to output the final timestamp.

2. The FPGA-based dual-mode TDC implementation method according to claim 1, characterized in that, The dual-mode signal generation circuit has built-in series flip-flops and complementary logic gates. The complementary logic gates include AND gates, OR gates and NOT gates, which perform output logic inversion switching and synchronous update of flip-flop state. The dead time for a single measurement is one FPGA system clock cycle; The time delay chain (TDL) consists of multiple sub-delay chains connected end-to-end. Each sub-delay chain contains a full adder, a lookup table, and a flip-flop. Adjacent sub-delay chains are electrically connected through the carry terminal of the full adder, and the output digital signal is synchronized with the rising edge of the FPGA system clock. The S-node and C-node of the full adder are mapped one-to-one to the input terminals of the flip-flops.

3. The FPGA-based dual-mode TDC implementation method according to claim 1, characterized in that, The cascaded adder array adopts a multi-stage carry-first adder structure. The number of sub-full adders at each stage is configured according to the pairwise grouping operation requirements, and all operation results are controlled to participate in the final total count of logic 1s. The logic 0 calculator of the dual-mode logic generation circuit adopts a subtractor structure, with the subtrahend being the total number of delay nodes and the minuend being the total number of logic 1s; The 2-to-1 multiplexer selects the output based on the encoding mode signal, and before calibration, the count value is synchronized with the timing of the encoding mode signal.

4. The FPGA-based dual-mode TDC implementation method according to claim 1, characterized in that, The dual-mode encoder controller has multiple sets of flip-flops and XOR gate circuits built in. The flip-flops are divided into two channels to process the S[0] value and C[0] value respectively. The output of the XOR gate circuit is used as the start signal output terminal, and the start signal is generated when the valid logic level is reached. The encoding mode signal and the start signal are synchronized in timing; The dedicated hardware circuit also includes a dual-mode fine counting calibration circuit, whose parameter storage unit uses FPGA on-chip storage resources; The calibration operation unit uses a lookup table mapping combined with an interpolation structure to perform nonlinear calibration and control calibration error.

5. The FPGA-based dual-mode TDC implementation method according to claim 1, characterized in that, The dedicated hardware circuit also includes a coarse counter generator and a coarse counter and fine counter adder. The counting bit width of the coarse counter generator is configurable. When the count overflows, it outputs an overflow flag signal. The counting step size is 1 FPGA system clock cycle. The bit width of the coarse and fine count adder is matched to the sum of the bit widths of the coarse and fine counts; The triggering method of the STOP pulse signal can be selected through the FPGA configuration register. The dual-mode signal generation circuit uses a preset range of pulse input frequency and the minimum recognition width of the STOP pulse signal.

6. The FPGA-based dual-mode TDC implementation method according to claim 1, characterized in that, The total delay length of the time delay chain TDL exceeds a preset proportion by more than the FPGA system clock cycle, and the effective delay signal is in the propagation state when the rising edge of the clock arrives. The delay deviation of each sub-delay chain is compensated by the dual-mode code density calibration parameter; Two sets of calibration lookup tables store the cumulative delay values ​​in order of delay unit level.

7. A dual-mode TDC implementation system based on FPGA, characterized in that, The method for implementing a dual-mode TDC based on FPGA as described in any one of claims 1 to 6 includes an FPGA core control unit, a clock management unit, a signal input interface unit, a data storage unit, a data output interface unit, and a power management unit; the FPGA core control unit has a built-in multi-channel synchronous trigger unit, the input terminal of the multi-channel synchronous trigger unit is electrically connected to the signal input interface unit, and the multiple output terminals are respectively connected to multiple independent dedicated hardware circuits; The clock management unit is electrically connected to the system clock port of the FPGA core control unit to provide the system clock signal; The input terminal of the signal input interface unit is used to receive external STOP pulse signals, and the output terminal is electrically connected to the input pin of the FPGA core control unit. After preprocessing the STOP pulse signal, it is transmitted to a dedicated hardware circuit. The data storage unit communicates bidirectionally with the FPGA core control unit via a bus to store dual-mode code density calibration parameters, intermediate measurement data, historical data, and configuration parameters. The data output interface unit is electrically connected to the timestamp output terminal of the FPGA core control unit, and uploads the final timestamp data to the external host computer. The power management unit provides stable power to all modules of the system.

8. The FPGA-based dual-mode TDC implementation system according to claim 7, characterized in that, The clock management unit includes an external high-precision crystal oscillator circuit and a phase-locked loop circuit inside the FPGA core control unit. The phase-locked loop circuit divides, multiplies, calibrates the phase, and suppresses jitter of the reference clock signal, and outputs multiple phase-synchronized system clock signals. The signal input interface unit has built-in impedance matching, filtering, shaping and level conversion circuits. The output level of the level conversion circuit is matched with the standard level of the FPGA core control unit IO port.

9. The FPGA-based dual-mode TDC implementation system according to claim 7, characterized in that, The data storage unit includes an on-chip register group, on-chip block storage, and off-chip non-volatile memory. The on-chip register group stores real-time measurement intermediate data and control signals. The on-chip block storage stores dual-mode code density calibration parameters. The off-chip non-volatile memory stores historical data, configuration parameters, and calibration lookup table backups. The data output interface unit selects the communication mode through the configuration register and limits the data transmission delay to a preset range.

10. The FPGA-based dual-mode TDC implementation system according to claim 7, characterized in that, The FPGA core control unit uses an FPGA chip, and the time delay chain TDL in the dedicated hardware circuit can adaptively adjust the number of sub-delay chain levels, lookup table configuration and layout constraint rules according to the carry chain resource structure of the selected FPGA chip. The power management unit provides multiple voltage ranges. The system includes single-channel and multi-channel operating modes. In multi-channel mode, each channel measures independently, and the crosstalk between channels and the synchronous measurement error are controlled within a preset range.

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