A method and apparatus for implementing QC-LDPC decoding on an FPGA pipeline

Abstract

This invention discloses a method and apparatus for implementing QC-LDPC decoding on an FPGA pipeline, comprising: constructing first and second lookup tables and first and second memory arrays on the FPGA; receiving demodulated codeword soft information, calculating the log-likelihood ratio of each bit and writing it into the first memory array; performing decoding iterations by row traversal after parameter initialization, updating intermediate messages and the log-likelihood ratio; dividing the operation of each row of parity check equations into multiple serial pipelines; after all parity check nodes have completed one pipeline processing, if the current iteration number is less than the maximum iteration number and there are parity check equations that do not satisfy the parity check constraint, then returning to the iteration, otherwise ending the decoding; performing a hard decision on the sign of the final log-likelihood ratio, and outputting the decoded bit sequence. This invention reduces FPGA storage resource consumption, achieves a trade-off between performance and complexity, improves decoding throughput, and reduces latency.

Description

Technical Field

[0001] This invention relates to the field of channel coding and decoding, and in particular to a method and apparatus for implementing QC-LDPC decoding on an FPGA pipeline. Background Technology

[0002] Many complex or harsh channel environments, such as underwater acoustic communication channels, wireless channels in high-speed mobile scenarios, and satellite or shortwave communication channels, are characterized by significant multipath effects, noticeable Doppler shift, and narrow bandwidth, leading to severe inter-symbol interference and high bit error rates. To ensure reliable communication under limited transmit power and bandwidth conditions, error-correcting channel coding techniques are typically employed at the physical layer, such as convolutional codes, Turbo codes, and low-density parity-check codes (LDPC). Among these, LDPC, due to its error-correcting performance approaching the Shannon limit, has become a core channel coding scheme in various wireless and wired communication standards.

[0003] Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes are a special type of LDPC code with a parity-check matrix obtained by concatenating multiple cyclic shift submatrices according to rules. They are typically described by a small fundamental matrix and a boost factor. QC-LDPCs facilitate real-time, row-by-row, column-by-column regularized storage and parallel access in hardware, making them a mainstream choice for implementing high-throughput decoders on hardware platforms such as FPGAs and ASICs.

[0004] In terms of decoding algorithms, the Sum-Product Algorithm (SPA) can achieve performance close to the theoretical limit, but its hardware implementation requires a large number of multiplications, lookup tables, and nonlinear operations, resulting in high complexity. The Min-Sum (MS) algorithm, by employing a minimum value operation decoding algorithm, approximates the decoding performance of the SPA algorithm with lower complexity and is suitable for FPGA hardware implementation, but it incurs some performance loss. The OffsetMin-Sum (OMS) algorithm introduces an offset based on MS to correct the minimum value, balancing hardware complexity and decoding performance.

[0005] Existing FPGA-based LDPC decoders still have shortcomings in terms of storage and structure utilization. On the one hand, the complete parity check matrix lookup table or the lookup table of the non-zero element positions in each row is stored on the FPGA chip. For QC-LDPC codes with code lengths of hundreds or even thousands of bits, the parity check matrix is ​​large, and a complete lookup table would occupy a large amount of block RAM (BRAM) and lookup table (LUT) resources, limiting deployment on resource-constrained FPGA devices. On the other hand, some LDPC decoders adopt pseudo-parallel or block-parallel structures at the hardware level, where the processing of each row of the parity check equation is relatively independent, and the rows cannot be fully overlapped and parallelized, making it difficult to improve decoding throughput.

[0006] In typical scenarios such as underwater acoustic communication, industrial IoT, satellite or shortwave communication, terminal devices usually use FPGAs or other programmable logic devices for signal processing. However, device resources are limited and power consumption is sensitive. Existing LDPC decoding schemes cannot simultaneously meet engineering requirements in terms of BRAM and LUT resource usage, latency, and throughput. Therefore, it is necessary to propose an FPGA implementation method and corresponding device for LDPC decoding that is designed for complex channel scenarios, adopts a pipelined structure, and fully utilizes the characteristics of the QC-LDPC structure. Summary of the Invention

[0007] To address the shortcomings of existing technologies, this invention proposes a QC-LDPC decoding FPGA pipeline implementation method and apparatus.

[0008] The specific technical solution is as follows:

[0009] A method for implementing QC-LDPC decoding on an FPGA pipeline includes the following steps:

[0010] S1: Construct a first lookup table on the FPGA to store the basic matrix, a second lookup table to record the number of non-zero sub-matrices in each basic row of the basic matrix, a first storage array to store the log-likelihood ratio of each bit of the current frame codeword, and a second storage array to store the intermediate messages from the check node to the variable node.

[0011] S2: Receive the demodulated codeword soft information, calculate the log-likelihood ratio of each bit, and write it into the first storage array in the order of receipt;

[0012] S3: Initialize the second storage array, set the number of iterations to zero, and set the offset and maximum number of iterations;

[0013] S4: Perform decoding iterations by row traversal, update intermediate messages and log-likelihood ratio; divide the operation of each row of check equations into multiple serial pipelines, so that some operation loops overlap and run concurrently during execution;

[0014] S5: After all verification nodes have completed one pipeline process, determine whether the current iteration number is less than the maximum iteration number and whether there is a verification equation that does not satisfy the parity check constraint. If so, return to S4 to execute the iteration; otherwise, end the decoding.

[0015] S6: Perform a hard decision on the final log-likelihood ratio sign to obtain the decoded bit sequence and output it.

[0016] Furthermore, the size of the fundamental matrix is ​​M. b ×N b Its elements are non-negative integers s or specific marker values; if the element is a non-negative integer s, it means that the element position corresponds to a z×z non-zero submatrix, which is a cyclic shift submatrix, where z is the lifting factor and s is the shift amount; if the element is a specific marker value, it means that the element position corresponds to a z×z all-zero submatrix.

[0017] The complete parity check matrix H is obtained after the fundamental matrix is ​​fully expanded. It has a total of M rows and a value of M. b ×z, the total number of columns is N, and its value is N. b ×z; Each row of H is a check node, and each column is a variable node.

[0018] Furthermore, in S4, the decoding iteration is performed by traversing rows, and the intermediate messages and log-likelihood ratio are updated through the following sub-steps:

[0019] S4.1: Based on the row index j and the promotion factor z of the check node, determine the base row number and row offset t corresponding to the check node; the base row number is the row index of the base matrix corresponding to the check node row; the row offset is the row offset position of the check node row relative to the first row of the corresponding base row; obtain the number of non-zero submatrices in the base row according to the second lookup table, and use it as the number of non-zero elements in the current check node row;

[0020] S4.2: Traverse the column indices of each submatrix corresponding to the base row. For each non-zero submatrix, calculate the column index col_idx of the corresponding complete parity check matrix H based on its cyclic shift and row offset. Generate the list of non-zero column indices cols of the current parity check node row in order.

[0021] S4.3: For each element in the non-zero column index list cols, read the log-likelihood ratio of the corresponding variable node from the first storage array, and read the intermediate message from the verification node to the variable node obtained in the previous iteration from the second storage array; subtract the intermediate message from the previous iteration from the initial log-likelihood ratio corresponding to the edge v from the verification node to the variable node to obtain the difference vector.

[0022] S4.4: Calculate the absolute value of each element of the difference vector to obtain the magnitude vector, record the first minimum value and the second minimum value of all magnitude vectors, and record the position k of the first minimum value. min ;

[0023] S4.5: Find the sign of each element of the difference vector to obtain the sign vector; multiply all elements in the sign vector to obtain the overall sign;

[0024] S4.6: Update the intermediate message from the check node to the variable node using the minimum offset sum algorithm:

[0025] For each edge v in the current row of the node, calculate the output message amplitude A of the verification node. If the position of the current edge is k... min If the value is less than or equal to the value of the amplitude vector, then A is taken as the second minimum value of the amplitude vector; otherwise, A is taken as the first minimum value. Calculate the offset-corrected message amplitude, which is the difference between A and the offset. If the difference is negative, it is truncated to zero.

[0026] Update the intermediate message from the verification node to the variable node. The update value is the product of the offset-corrected message magnitude and the overall symbol and the current edge symbol vector. Write the updated value of the intermediate message to the corresponding position in the second storage array for overwriting.

[0027] S4.7: Update the corresponding log-likelihood ratio in the first storage array, the value of which is the sum of the intermediate message update value from the check node to the variable node and the corresponding difference vector.

[0028] Furthermore, the value of the basic row number is: the quotient of the check node row index j divided by the lifting factor z, rounded down;

[0029] The value of the inline offset t is: the remainder when the check node row index j is divided by the lifting factor z;

[0030] The column index col_idx of the complete parity check matrix H is the sum of two polynomials. The first term is the product of the current submatrix column index and the lifting factor, and the second term is the remainder of the sum of the shift amount s and the in-row offset t divided by the lifting factor z.

[0031] Furthermore, the number of rows, columns, and boosting factor of the base matrix are configured according to the code length and code rate of the target LDPC code, and the code length, number of parity check equations, number of information bits, and maximum single-row degree of the LDPC code satisfy the structural constraints of the LDPC code.

[0032] Furthermore, pipeline constraints are applied during FPGA synthesis to make the operation cycle start interval a fixed number of clock cycles; each round of the operation cycle includes: read operation, calculation operation, and write operation; when the read operation in a certain cycle is processing the (j+1)th row of the verification node, the calculation operation is processing the jth row, and the write operation is processing the (j-1)th row.

[0033] Furthermore, the offset β is a constant obtained using density evolution methods or offline simulation.

[0034] Furthermore, the first and second storage arrays are implemented through array partitioning or multi-port block RAM structures, which divide the data into multiple independent storage blocks in the row or column direction to support parallel reading and writing of messages from multiple variable nodes or check nodes within the same clock cycle.

[0035] Furthermore, in S2, the demodulated codeword soft information is received through the streaming interface of the FPGA, and in S6, the decoded bit sequence is output through the streaming interface of the FPGA. The streaming interface of the FPGA is AXI4-Stream or an equivalent streaming bus protocol. The codeword soft information input in S2 and the decoding result output in S6 are both transmitted in frame mode, with each frame corresponding to one LDPC codeword.

[0036] A decoding apparatus for implementing the QC-LDPC decoding FPGA pipeline implementation method, comprising a storage unit and a processing unit;

[0037] The storage unit is used to store the first storage array, the second storage array, the first lookup table, and the second lookup table, and is used to store the log-likelihood ratio, intermediate messages, and QC-LDPC structure information.

[0038] The processing unit includes: a row parameter calculation module, a non-zero column index calculation module, a difference calculation module, an absolute value and minimum value search module, a sign calculation module, an offset minimum and intermediate message update module, a log-likelihood ratio update module, and an iteration control module; the processing unit is configured through a hardware pipeline structure to execute the steps of the QC-LDPC decoding FPGA pipeline implementation method.

[0039] The beneficial effects of this invention are:

[0040] (1) The present invention significantly reduces the storage resource consumption of FPGA: The present invention only stores the small-sized basic matrix and the number of non-zero sub-matrices in the basic row on the FPGA. By using the quasi-cyclic structure and the boosting factor, the non-zero column index of the complete parity check matrix is ​​calculated in real time during the decoding process. There is no need to store the complete parity check matrix lookup table or the parity check matrix non-zero element position lookup table, which greatly reduces the resource consumption of BRAM and LUT, making it possible to deploy LDPC decoders on FPGA devices with limited resources.

[0041] (2) The present invention achieves a trade-off between performance and complexity, improves the decoding performance relative to the standard minimum sum algorithm, and can meet the bit error rate requirements of complex or harsh channel scenarios with a small number of iterations.

[0042] (3) The present invention improves the decoding throughput and reduces the latency by dividing the operation of each row of the check equation into multiple serial pipelines. The processing between rows is performed in an overlapping manner at the clock cycle level to form a pipeline structure, thereby improving the decoding throughput and reducing the decoding latency while ensuring timing convergence.

[0043] (4) The present invention supports extended application capabilities in scenarios with limited resources and power consumption: The present invention can be deployed on FPGA or other programmable logic devices, and can perform real-time decoding of QC-LDPC codewords while maintaining low logic resource usage. It is suitable for application in systems that are sensitive to size and power consumption, such as underwater acoustic communication systems, satellite communication terminals, and industrial IoT nodes. Attached Figure Description

[0044] Figure 1 This is a flowchart illustrating the overall process of the QC-LDPC decoder proposed in this invention in an underwater acoustic communication system.

[0045] Figure 2 This is a flowchart of the QC-LDPC decoding FPGA pipeline implementation method proposed in this invention.

[0046] Figure 3 This is a schematic diagram of the storage and lookup table structure built on an FPGA according to the present invention.

[0047] Figure 4 This is the basic matrix structure table of the QC-LDPC code constructed in this embodiment of the invention.

[0048] Figure 5 This is a schematic diagram illustrating the real-time calculation process of the non-zero column indexes of the base matrix and lifting factor proposed in this invention.

[0049] Figure 6 This is a schematic diagram of the production line structure proposed in this invention, wherein (A) is a non-circulating flow tapping, and (B) is a circulating flow tapping.

[0050] Figure 7 This is a schematic diagram showing the resource usage of the QC-LDPC decoder proposed in this invention implemented on an FPGA. Detailed Implementation

[0051] The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments. The objectives and effects of the present invention will become clearer as a result. The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0052] In one embodiment, such as Figure 1 As shown, the overall process of the method of the present invention in an underwater acoustic communication system is as follows: the transmitter encodes and modulates the information bits using QC-LDPC, and after DAC conversion and power amplification, the transmitter transducer emits the signal underwater; the receiver receives the signal through the receiver transducer (hydrophone), and after power amplification and ADC conversion, it performs equalization, demodulation and LDPC decoding to output the information bits.

[0053] In a preferred embodiment, the LDPC decoding module is deployed on a Xilinx Zynq-7000 series FPGA and integrated with the underwater acoustic communication demodulation algorithm on the same system-on-a-chip. In other embodiments, other FPGAs or programmable logic devices may also be used.

[0054] A QC-LDPC decoding pipelined implementation method is presented, executed on a Field Programmable Gate Array (FPGA), for decoding LDPC codewords encoded according to a quasi-cyclic low-density parity-check matrix H, such as... Figure 2 As shown, the method includes the following steps:

[0055] S1: As Figure 3 As shown, a QC-LDPC code structure lookup table area and a decoding message storage area are constructed on the FPGA. The QC-LDPC code structure lookup table area includes a first lookup table and a second lookup table, used to describe the structural information of the QC-LDPC code. The decoding message storage area includes a first storage array and a second storage array, used to store the continuously updated LLR, messages, and check node messages during the decoding process. The above storage is implemented using on-chip block RAM (BRAM) and a multi-port storage structure, with array partitioning in the row or column direction to support multi-port parallel access.

[0056] The first lookup table is used to store data of size M in the form of a two-dimensional read-only memory. b ×N bThe fundamental matrix. The elements of the fundamental matrix can be non-negative integers or specific marker values. When an element is a non-negative integer s, it means that the element position corresponds to a z×z cyclic shift submatrix (i.e., a non-zero submatrix), and its shift amount is s, where z represents the lifting factor; when an element is a specific marker value (set to -1 in this embodiment), it means that the element position is a z×z all-zero submatrix.

[0057] The complete expansion of the fundamental matrix is ​​called the complete parity check matrix H. The complete parity check matrix H is formed by M. b ×N b H is composed of z×z cyclic displacement submatrices concatenated together, and the total number of rows in H (i.e., the number of check nodes) is The total number of columns (corresponding to the number of variable nodes) is Set the maximum degree d of a single row for the fundamental matrix. max , which is the number of non-zero submatrices in the row with the most non-zero elements in all rows of the basic matrix.

[0058] Furthermore, the number of rows M of the fundamental matrix b Number of columns N b The boost factor z is configured based on the code length and code rate of the target LDPC code, including the code length, number of check equations, number of information bits, and maximum single-line degree d. max The structural constraints of the quasi-cyclic LDPC code are satisfied.

[0059] As one embodiment of the present invention, the QC-LDPC code used in the present invention is determined by the fundamental matrix and the boosting factor, with M being chosen. b =6、N b =24, the basic matrix constructed is as follows Figure 4 As shown.

[0060] In this embodiment, the lifting factor z=27, so the complete parity check matrix H is composed of 6×24 cyclic shift submatrices of 27×27, with a total number of rows. The total number of columns is The information bit count is 486, and the maximum single-line length is d. max The value shall not exceed 15. Those skilled in the art can select other base matrix sizes and boosting factors according to the code length and code rate requirements of the target system, and the implementation method of the present invention will still be applicable.

[0061] The second lookup table has a length of M. b A one-dimensional array is used to record the number of non-zero submatrices in each basic row of the basic matrix, which is used to quickly obtain the row weight of each basic row during decoding. The i-th element in the array represents the number of non-zero submatrices in the i-th row of the basic matrix, that is, the number of non-zero elements in that basic row.

[0062] The first storage array is a one-dimensional array of length N, used to store the log-likelihood ratio (LLR) of each bit of the current frame codeword in the order of variable nodes.

[0063] The second storage array is M×d max Two-dimensional array (d) max (Maximum degree for a single row) is used to store intermediate messages from the check node (corresponding to a row in the complete parity check matrix H, CN) to the variable node (corresponding to a column in the complete parity check matrix H, VN) in a two-dimensional form according to the row index M and the edge index K.

[0064] Furthermore, the first and second storage arrays are implemented through array partitioning or multi-port block RAM structures, dividing the data into multiple independent storage blocks in the row or column direction to support parallel reading and writing of messages from multiple variable nodes or check nodes within the same clock cycle.

[0065] This invention no longer stores the complete parity check matrix H lookup table or its non-zero element position lookup table. Instead, during the decoding process, it calculates the non-zero column index of the complete parity check matrix H in real time using the stored basic matrix and lifting factor.

[0066] S2: Soft Information Input. The demodulated codeword soft information is received via the FPGA's streaming interface. The LLR (Limited Range Ratio) is calculated for each bit, and the data is written to the first storage array in the order of reception, completing the loading of one frame of codeword soft information. In this embodiment, the FPGA's streaming interface is the AXI4-Stream interface.

[0067] S3: Initialization. Initialize the entire second storage array to zero. Set the iteration counter to iter=0, and preset the offset β and the maximum number of iterations. The offset β is a constant obtained using the density evolution method or offline simulation, with a value range of 0.2-0.5, preferably 0.3. In this embodiment, β=0.3, and the maximum number of iterations is 5.

[0068] S4: Pipeline Decoding Iteration. Decoding iteration is performed row-by-row, and the operation of each row of the check equation is divided into multiple sequential pipelines. This allows some loops to overlap and run concurrently. Specifically, this is achieved through the following sub-steps:

[0069] S4.1: Based on the row index j (j=0~M-1) of the check node and the promotion factor z, determine the corresponding base row number base_row and the row offset t, where the base row number base_row is the row index (0~M) of the base matrix corresponding to that row (i.e., the check node). b -1), the calculation expression is: The inline offset t is the row offset position of the current row relative to its first row within the corresponding base row, and is calculated using the following expression: .

[0070] The number of non-zero submatrices in the base row is obtained from the second lookup table and used as the number of non-zero elements in the current row.

[0071] S4.2: Traverse the column indices of each submatrix corresponding to the base row, skipping submatrixes marked with all zeros. For each non-zero submatrix, calculate the column index col_idx of the corresponding complete parity check matrix H in real time based on its cyclic shift and in-row offset. This generates the non-zero column index list cols of the current check node row in sequence.

[0072] like Figure 5 As shown, the expression for calculating the column index col_idx of the complete parity check matrix H is as follows:

[0073]

[0074] In the formula, b is the column index of the current submatrix in the current base row, t is the row offset of the current row in the base row, and mod represents the remainder.

[0075] S4.3: For each element in the non-zero column index list cols, read the LLR value of the corresponding variable node from the first storage array, and read the intermediate message from the check node (CN) to the variable node (VN) of the previous iteration from the second storage array. ,according to Calculate the difference vector v represents the edge from the check node to the variable node, v=1~N.

[0076] S4.4: For the difference vector The magnitude vector is obtained by taking the absolute value of each element. Traverse the magnitude vector to obtain its first minimum value min1, second minimum value min2, and the position k of the first minimum value. min (That is, the v value corresponding to the first minimum value is found).

[0077] S4.5: For the difference vector Find the sign of each element to obtain the sign vector. The overall symbol is obtained by multiplying all elements in the symbol vector. .

[0078] S4.6: Update the intermediate message from the check node to the variable node using the minimum offset sum algorithm (i.e., update...) ): Calculate the output message amplitude of the verification node for each edge v in the current row of the node. Let k be the position of the current edge. The message amplitude is subtracted by a preset offset β. If the result is negative, it is truncated to zero, thus obtaining the offset-corrected message amplitude. .

[0079] Then, based on the product of the value and the overall symbol vector and the current edge symbol vector, the intermediate message update value from the verification node to the variable node is generated. The intermediate message update value is then written to the corresponding location in the second storage array for overwriting and updating.

[0080] S4.7: Update the corresponding LLR value in the first storage array to: the sum of the intermediate message update value from the check node to the variable node and the corresponding difference vector (i.e., ).

[0081] S4.1 to S4.7 are implemented through interconnected pipelines on the FPGA, allowing the processing of different row indices j to be initiated sequentially within each clock cycle or several clock cycles (i.e., the next group of data can be read before the current group of data is completely written), forming a row-level pipeline. During FPGA synthesis, this invention applies pipeline constraints to the difference calculation, amplitude and minimum value search, sign calculation, and LLR update loops, ensuring that the startup interval of these loops is a fixed number of clock cycles.

[0082] Furthermore, such as Figure 6 As shown in this embodiment, by applying pipeline constraints (such as #pragma HLS PIPELINE) to each level of loop in the HLS design, it is possible to achieve a row-level pipeline structure for multi-row overlapping processing when the read operation (RD) in a certain loop is processing row j+1, the compute operation (CMP) is processing row j, and the write operation (WR) is processing row j-1.

[0083] S5: After all verification nodes have completed one pipeline process, determine whether the current iteration number is less than the preset maximum iteration number and whether there is a verification equation that does not meet the parity check constraint. If so, increment the iteration number iter by one and repeat S4; otherwise, stop the iteration and end the decoding.

[0084] S6: Perform hard decision on the symbols of the final LLR stored in the first storage array to obtain the decoded bit sequence, and output it through the FPGA's streaming interface.

[0085] Furthermore, the streaming interface is AXI4-Stream or an equivalent streaming bus protocol. Both soft information input and decoding result output are transmitted in frame mode, with each frame corresponding to an LDPC codeword.

[0086] In one embodiment, such as Figure 7As shown, to verify that the proposed QC-LDPC decoder hardware architecture has superior performance, a comprehensive simulation experiment was conducted using Vivado 2023.2 software with a Xilinx Zynq-7000 chip. The designed decoder operates at a clock frequency of 200MHz, with a throughput R0. thr The calculation expression is as follows:

[0087]

[0088] In the formula, N code N represents the number of information bits. frame T represents the frame number. total This represents the total time to complete the task; in this embodiment, a QC-LDPC code with a code length of 648 and an information bit count of 486 is used, N frame =1, The calculated throughput R thr It is 1 Mbps.

[0089] like Figure 7 As shown in the simulation results, in terms of resource consumption, the decoding module of this invention uses 10 BRAMs, 1417 LUTs, 5 DPSs and 1569 flip-flops (corresponding to FFs), which significantly reduces the amount of BRAM and LUTs used compared with the implementation method of storing the lookup table of the non-zero element positions of the complete parity check matrix (i.e., the comparison scheme).

[0090] Therefore, under the same FPGA device and operating frequency, this invention can still meet the throughput requirements for real-time decoding of QC-LDPC codes with a code length of 648 with relatively low logic resource usage. Those skilled in the art can adjust the implementation details according to the resource availability of the target device without affecting the essence of the method of this invention.

[0091] This invention achieves a trade-off between performance and complexity: by introducing an offset β to modify the minimum amplitude value, this invention improves the decoding performance relative to the standard minimum sum algorithm while maintaining a simple hardware structure and operations mainly consisting of addition, subtraction, comparison, and symbolic operations. It can meet the bit error rate requirements of complex or harsh channel scenarios with a smaller number of iterations.

[0092] This invention improves decoding throughput and reduces latency: The invention divides the steps of row parameter calculation, non-zero column index generation, difference calculation, minimum value search, sign calculation, offset correction and message generation, LLR update into multiple pipelines. The processing between rows is executed in an overlapping manner at the clock cycle level to form a pipeline structure, which improves decoding throughput and reduces decoding latency while ensuring timing convergence.

[0093] To implement the above-described QC-LDPC decoding FPGA pipeline implementation method, this embodiment also proposes a decoding device, which is deployed on a field-programmable gate array (FPGA) or other programmable logic device. The decoding device includes a storage unit and a processing unit.

[0094] The storage unit is used to store the first storage array, the second storage array, the first lookup table, and the second lookup table, and is used to store LLR, messages, and QC-LDPC structure information.

[0095] The processing unit includes: a row parameter calculation module, a non-zero column index calculation module, a difference calculation module, an absolute value and minimum value search module, a sign calculation module, an offset minimum and intermediate message update module, an LLR update module, and an iteration control module; the processing unit is configured through a hardware pipeline structure to execute the steps of the above-described QC-LDPC decoding FPGA pipeline implementation method.

[0096] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0097] It will be understood by those skilled in the art that the above descriptions are merely preferred examples of the invention and are not intended to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the invention should be included within the scope of protection of the invention.

Claims

1. A method for implementing QC-LDPC decoding on an FPGA pipeline, characterized in that, Includes the following steps: S1: Construct a first lookup table on the FPGA to store the basic matrix, a second lookup table to record the number of non-zero sub-matrices in each basic row of the basic matrix, a first storage array to store the log-likelihood ratio of each bit of the current frame codeword, and a second storage array to store the intermediate messages from the check node to the variable node. The size of the fundamental matrix is ​​M. b ×N b Its elements are non-negative integers s or specific marker values; if the element is a non-negative integer s, it means that the element position corresponds to a z×z non-zero submatrix, which is a cyclic shift submatrix, where z is the lifting factor and s is the shift amount; if the element is a specific marker value, it means that the element position corresponds to a z×z all-zero submatrix. The complete parity check matrix H is obtained after the fundamental matrix is ​​fully expanded. It has a total of M rows and a value of M. b ×z, the total number of columns is N, and its value is N. b ×z; Each row of H is a check node, and each column is a variable node; S2: Receive the demodulated codeword soft information, calculate the log-likelihood ratio of each bit, and write it into the first storage array in the order of receipt; S3: Initialize the second storage array, set the number of iterations to zero, and set the offset and maximum number of iterations; S4: Based on the row index j and the promotion factor z of the verification node, determine the base row number and the row offset t corresponding to the verification node; the base row number is the row index of the base matrix corresponding to the row of the verification node, and its value is the floor function of the quotient of the row index j of the verification node divided by the promotion factor z; the row offset is the row offset position of the row of the verification node relative to the first row of the corresponding base row, and its value is the remainder of the row index j of the verification node divided by the promotion factor z. The number of non-zero submatrices in the base row is obtained according to the second lookup table, and is used as the number of non-zero elements in the current check node row; The decoding iteration is performed by traversing the rows, updating intermediate messages and the log-likelihood ratio; the operation of each row of the check equation is divided into multiple serial pipelines, so that some operation loops overlap and run concurrently during execution; S5: After all verification nodes have completed one pipeline process, determine whether the current iteration number is less than the maximum iteration number and whether there is a verification equation that does not satisfy the parity check constraint. If so, return to S4 to execute the iteration; otherwise, end the decoding. S6: Perform a hard decision on the final log-likelihood ratio sign to obtain the decoded bit sequence and output it.

2. The QC-LDPC decoding FPGA pipeline implementation method according to claim 1, characterized in that, In step S4, the decoding iteration is performed by traversing rows, and the intermediate messages and log-likelihood ratio are updated through the following sub-steps: (1) Traverse the column indices of each submatrix corresponding to the base row. For each non-zero submatrix, calculate the column index col_idx of the corresponding complete parity check matrix H based on its cyclic shift and row offset. Generate the list of non-zero column indices cols of the current check node row in order. (2) For each element in the non-zero column index list cols, read the log-likelihood ratio of the corresponding variable node from the first storage array, and read the intermediate message from the verification node to the variable node obtained in the previous iteration from the second storage array. Subtract the intermediate message from the previous iteration from the initial log-likelihood ratio corresponding to the edge v from the verification node to the variable node to obtain the difference vector; (3) Calculate the absolute value of each element of the difference vector to obtain the magnitude vector, record the first minimum value and the second minimum value of all magnitude vectors, and record the position k of the first minimum value. min ; (4) Find the sign of each element of the difference vector to obtain the sign vector; multiply all elements in the sign vector to obtain the overall sign; (5) Update the intermediate message from the check node to the variable node using the minimum offset sum algorithm: For each edge v in the current row of the node, calculate the output message amplitude A of the verification node. If the position of the current edge is k... min If the value is less than or equal to the value of the amplitude vector, then A is taken as the second minimum value of the amplitude vector; otherwise, A is taken as the first minimum value. Calculate the offset-corrected message amplitude, which is the difference between A and the offset. If the difference is negative, it is truncated to zero. Update the intermediate message from the check node to the variable node. The updated value is the product of the offset-corrected message magnitude and the overall symbol and the current edge symbol vector. The intermediate message update value is written to the corresponding location in the second storage array to overwrite the update. (6) Update the corresponding log-likelihood ratio in the first storage array, the value of which is the sum of the intermediate message update value from the check node to the variable node and the corresponding difference vector.

3. The QC-LDPC decoding FPGA pipeline implementation method according to claim 2, characterized in that, The column index col_idx of the complete parity check matrix H is the sum of two polynomials. The first term is the product of the current submatrix column index and the lifting factor, and the second term is the remainder of the sum of the shift amount s and the in-row offset t divided by the lifting factor z.

4. The QC-LDPC decoding FPGA pipeline implementation method according to claim 1, characterized in that, The number of rows, columns, and boosting factor of the base matrix are configured according to the code length and code rate of the target LDPC code. The code length, number of parity check equations, number of information bits, and maximum single-row degree of the LDPC code satisfy the structural constraints of the LDPC code.

5. The QC-LDPC decoding FPGA pipeline implementation method according to claim 1, characterized in that, During FPGA synthesis, pipeline constraints are applied to make the operation cycle start interval a fixed number of clock cycles; each round of the operation cycle includes: read operation, calculation operation, and write operation; when the read operation in a certain cycle is processing the (j+1)th row of the verification node, the calculation operation is processing the jth row, and the write operation is processing the (j-1)th row.

6. The QC-LDPC decoding FPGA pipeline implementation method according to claim 1, characterized in that, The offset β is a constant obtained using density evolution methods or offline simulation.

7. The QC-LDPC decoding FPGA pipeline implementation method according to claim 1, characterized in that, The first and second storage arrays are implemented through array partitioning or multi-port block RAM structures, which divide the data into multiple independent storage blocks in the row or column direction to support parallel reading and writing of messages from multiple variable nodes or check nodes within the same clock cycle.

8. The QC-LDPC decoding FPGA pipeline implementation method according to claim 1, characterized in that, In step S2, the demodulated codeword soft information is received through the streaming interface of the FPGA. In step S6, the decoded bit sequence is output through the streaming interface of the FPGA. The streaming interface of the FPGA is AXI4-Stream or an equivalent streaming bus protocol. The codeword soft information input in step S2 and the decoding result output in step S6 are both transmitted in frame mode, with each frame corresponding to one LDPC codeword.

9. A decoding apparatus for implementing the QC-LDPC decoding FPGA pipeline implementation method according to any one of claims 1-8, characterized in that, Includes storage units and processing units; The storage unit is used to store the first storage array, the second storage array, the first lookup table, and the second lookup table, and is used to store the log-likelihood ratio, intermediate messages, and QC-LDPC structure information. The processing unit includes: a row parameter calculation module, a non-zero column index calculation module, a difference calculation module, an absolute value and minimum value search module, a sign calculation module, an offset minimum and intermediate message update module, a log-likelihood ratio update module, and an iteration control module; the processing unit is configured through a hardware pipeline structure to execute the steps of the QC-LDPC decoding FPGA pipeline implementation method according to any one of claims 1-8.

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