Channel estimation circuit and channel estimation method based on memristor

Abstract

The invention discloses a channel estimation circuit and a channel estimation method based on memristors, and relates to the field of wireless communication and integrated circuits, and the circuit comprises three memristor arrays which are respectively used for mapping a first real number matrix, a second real number matrix and a diagonal matrix, the first real number matrix is composed of absolute values of non-positive elements of a channel estimation pilot frequency sequence cross-correlation mapping matrix, and the second real number matrix is composed of non-diagonal elements in non-negative elements of the channel estimation pilot frequency sequence cross-correlation mapping matrix; the diagonal matrix is composed of diagonal elements in non-negative elements of a channel estimation pilot frequency sequence cross-correlation mapping matrix; the switch module controls the memristor to be connected to or disconnected from the circuit; the inverter array is connected between the first memristor array and the second memristor array and is used for realizing matrix subtraction and positive and negative value compensation; the operational amplifier array is connected with the row lines and the column lines of the memristor array to form a feedback loop, channel estimation values are output, the integration level is high, the calculation speed is high, and energy consumption is low.

Description

Technical Field

[0001] This application relates to the fields of wireless communication and integrated circuits, and in particular to a channel estimation circuit and channel estimation method based on memristors. Background Technology

[0002] In multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) systems, channel estimation is a crucial step in achieving coherent demodulation and signal detection. Traditional channel estimation methods primarily rely on digital signal processors to execute least square (LS) or minimum mean square error (MMSE) algorithms, involving numerous matrix operations, including matrix multiplication, transpose, and inversion. As the number of antennas increases, the dimensionality of matrix calculations in channel estimation algorithms also increases, leading to increased computational complexity, energy consumption, and time. Furthermore, in traditional wireless digital communication technologies, the von Neumann architecture of digital computers necessitates frequent data retrieval from memory to the processor for processing, resulting in additional time and energy consumption due to communication between memory and the processor. Therefore, in MIMO-OFDM systems, the channel estimation step urgently requires alternative communication technologies to address these challenges.

[0003] Traditional fast channel estimation schemes for MIMO wireless communication based on optical matrix computation can achieve fast matrix multiplication, but the system structure is complex, including a large number of optical devices and peripheral circuits such as cascaded light sources, polarization controllers, multi-stage electro-optic modulators, wavelength division multiplexers, wavelength demultiplexers, and photoelectric detection and integration circuits. The system is complex and bulky, making it difficult to achieve high integration. Moreover, the critical matrix inversion operation still relies on the back-end digital processor, which is complex, time-consuming, and energy-intensive.

[0004] Therefore, there is an urgent need for a channel estimation scheme that is highly integrated, fast in computation, and low in energy consumption. Summary of the Invention

[0005] The purpose of this application is to provide a channel estimation circuit and method based on memristors, which has high integration, fast calculation speed and low power consumption.

[0006] To achieve the above objectives, this application provides the following solution: In a first aspect, this application provides a channel estimation circuit based on a memristor, comprising: The memristor array module is used to map the matrix parameters related to the pilot frequency to the device conductance, and to perform matrix-vector multiplication and matrix inversion related operations in the analog domain; the memristor array module includes at least a first memristor array, a second memristor array, and a third memristor array arranged in sequence; A first memristor array is used to map a first real matrix, which is composed of the absolute values ​​of the non-positive elements of the channel estimation pilot sequence cross-correlation mapping matrix; The second memristor array is used to map the second real matrix, which is composed of the off-diagonal elements of the non-negative elements of the channel estimation pilot sequence cross-correlation mapping matrix; the number of memristors on the row and column lines of the first and second memristor arrays is determined by the number of transmit antennas in the MIMO-OFDM system and the maximum delay spread. The third memristor array, with memristors arranged on the diagonal of the array, is used to map a diagonal matrix, which is composed of the diagonal elements of the non-negative elements of the channel estimation pilot sequence cross-correlation mapping matrix; Switching module, used to control the connection or disconnection of memristors from the circuit; An inverter array, connected between the first memristor array and the second memristor array, is used to implement matrix subtraction and positive / negative value compensation; The operational amplifier array is connected to the row and column lines of the memristor array to form a feedback loop, which is used to output the channel estimate.

[0007] Secondly, this application provides a channel estimation method based on the memristor-based channel estimation circuit described in the first aspect, comprising: Determine whether the currently transmitted pilot signal has changed compared to the previous cycle; If the pilot signal changes, the memristor array in the circuit is rewritten to update the mapped matrix parameters. If the pilot signal has not changed, then it is further determined whether the significant multipath location of the current channel has been determined; If a significant multipath location has been determined, the control circuit operates in the first working mode, executes the energy-saving LS algorithm, and outputs the channel estimation result; If the significant multipath location is not determined, the control circuit operates in the second operating mode, executes the complete LS algorithm, outputs the channel estimation result, and determines the significant multipath location.

[0008] According to the specific embodiments provided in this application, this application has the following technical effects: This application provides a channel estimation circuit and method based on memristors. The circuit includes: a memristor array module for mapping pilot-related matrix parameters to device conductances, performing matrix-vector multiplication and matrix inversion correlation operations in the analog domain; the memristor array module includes at least a first memristor array, a second memristor array, and a third memristor array arranged sequentially; the first memristor array is used to map a first real matrix, which is composed of the absolute values ​​of the non-positive elements of the channel estimation pilot sequence cross-correlation mapping matrix; the second memristor array is used to map a second real matrix, which is composed of the non-diagonal elements of the channel estimation pilot sequence cross-correlation mapping matrix. The circuit comprises the following components: the number of memristors on the row and column lines of the first and second memristor arrays is determined by the number of transmit antennas and the maximum delay spread in the MIMO-OFDM system; a third memristor array, with memristors arranged diagonally, is used to map a diagonal matrix, which is composed of the diagonal elements of the non-negative elements of the channel estimation pilot sequence cross-correlation mapping matrix; a switching module is used to control the connection or disconnection of memristors from the circuit; an inverter array is connected between the first and second memristor arrays to perform matrix subtraction and positive / negative value compensation; and an operational amplifier array is connected to the row and column lines of the memristor arrays to form a feedback loop for outputting the channel estimate. The circuit provided in this application can achieve channel estimation on a memristor array circuit without relying on digital chips for received signal processing and inverse matrix solving, resulting in lower circuit complexity, faster computation speed, and lower power consumption; it also avoids the use of numerous optical components and peripheral circuits found in related technologies, thus achieving high integration. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a channel estimation circuit based on a memristor provided in Embodiment 1 of this application.

[0011] Figure 2 This is a flowchart illustrating a channel estimation method provided in Embodiment 2 of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] A memristor is a nonlinear circuit element with memory function. Its fundamental characteristic is that its resistance value can continuously and non-volatilely change with the amount of charge flowing through the device, thus retaining historical charge information even after power is turned off. By applying a controllable electrical signal, the resistance state of the memristor can be reversibly adjusted, transitioning between a high-resistance state and a low-resistance state. This characteristic not only allows it to be used as a non-volatile memory, but more importantly, its resistance value can be continuously adjusted within a certain range, providing a foundation for applications such as analog signal processing, reconfigurable circuits, and in-memory computing.

[0014] Memristors possess continuously adjustable resistance within their physical range, enabling a single device to characterize multi-bit information by setting multiple discrete resistance states, thus significantly increasing storage density. More importantly, this continuously variable resistance characteristic allows for direct analog computation based on Ohm's law: when a memristor is set to a specific conductance value, applying an input voltage results in an output current that is the product of that voltage and conductance, essentially performing a multiplication operation. By integrating multiple memristors into a cross-array structure, not only can data be stored, but core operations such as vector-matrix multiplication can also be performed in parallel, achieving in-memory computing or on-memory computation. Because this process occurs directly in the analog domain, it avoids the frequent data transfer and analog-to-digital conversion overhead of traditional digital computing. Therefore, when performing specific computational tasks, memristor arrays can achieve orders-of-magnitude improvements in energy efficiency and area efficiency, providing a new technological path to overcome the bottlenecks of traditional computing architectures.

[0015] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] Example 1 In one exemplary embodiment, a memristor-based channel estimation circuit is provided, including a memristor array module, a switching module, an inverter array, and an operational amplifier array.

[0017] The memristor array module is used to map the matrix parameters related to the pilot frequency to the device conductance and to perform matrix-vector multiplication and matrix inversion related operations in the analog domain; the memristor array module includes at least a first memristor array, a second memristor array, and a third memristor array arranged in sequence.

[0018] A first memristor array is used to map a first real matrix, which is composed of the absolute values ​​of the non-positive elements of the channel estimation pilot sequence cross-correlation mapping matrix.

[0019] A second memristor array is used to map a second real matrix, which is composed of the off-diagonal elements of the non-negative elements of the channel estimation pilot sequence cross-correlation mapping matrix. The number of memristors on the row and column lines of the first and second memristor arrays is determined by the number of transmit antennas and the maximum delay spread in the MIMO-OFDM system. A third memristor array, with memristors arranged on the diagonal of the array, is used to map a diagonal matrix, which is composed of the diagonal elements of the non-negative elements of the channel estimation pilot sequence cross-correlation mapping matrix.

[0020] The switching module is used to control the connection or disconnection of the memristor from the circuit.

[0021] An inverter array, connected between the first memristor array and the second memristor array, is used to perform matrix subtraction and positive / negative value compensation.

[0022] The operational amplifier array is connected to the row and column lines of the memristor array to form a feedback loop, which is used to output the channel estimate.

[0023] The system model for the application scenario in this application is as follows: In a MIMO-OFDM system, there are One transmitting antenna, with Root receiving antenna, each OFDM symbol is Composed of subcarriers, in Time of the first The information carried by the OFDM symbols transmitted by the transmitting antenna is vector , After serial-to-parallel conversion, multiple data streams are obtained. These multiple data streams then undergo IFFT transformation and are further supplemented with a segment of length [length missing]. The cyclic prefix, whose length is greater than the maximum delay spread. To overcome inter-symbol interference caused by multipath effects, for any receiving antenna, the received signal is composed of... It is formed by the superposition of OFDM signals emitted by the transmitting antennas. Time of the first At the root receiving antenna, after removing the cyclic prefix of the received signal, a result can be obtained. vector , can be represented as: (1); in, Indicates the first root transmitting antenna to the first The cyclic matrix of the root receiving antenna is obtained by cyclically obtaining the first column, which is composed of... constitute; Represents the unit DFT matrix. express The conjugate transpose of; express At the moment The variance superimposed on the root receiving antenna is Given Gaussian white noise, and based on the properties of the circulant matrix, equation (1) can be written as follows: (2); Right now: (3); in, Indicates the diagonal symbol; It is The vector represents the first... root transmitting antenna to the first Channel impulse response between the root receiving antennas; To The result after performing a Fourier transform.

[0024] By analyzing the signals at different frequencies, we can obtain Time of the first The first receiving antenna The signals on each subcarrier channel are: (4); in, for Time of the first The first receiving antenna Signals on each subcarrier channel; for Time of the first root transmitting antenna to the first Root receiving antenna Channel frequency response of each subcarrier channel; for Time of the first The OFDM symbol transmitted by the root transmitting antenna on the first Information vectors carried by each subcarrier channel; for time In the Noise components on each subcarrier channel.

[0025] Due to the symmetry of the receiving antenna, considering a specific receiving antenna, the above equation (4) can be simplified to the following equation: (5); in, for The first time the receiving antenna is on Signals on each subcarrier channel; for Time of the first The first transmitting antenna Channel frequency response of each subcarrier channel; for Time of the first Noise components on each subcarrier channel.

[0026] Channel estimation using the LS algorithm: The principle of LS estimation is to find an estimate that minimizes the sum of squared differences between the actual and estimated values. Therefore, the cost function for LS channel estimation can be obtained as follows: (6); in, The cost function for LS channel estimation; for The estimated value.

[0027] And because of the channel frequency response and channel impulse response The following relationship exists: (7); Among them, intermediate quantity Therefore, if you want to get You can start with Time of the first The first transmitting antenna Channel impulse response of a multipath delay tap Therefore, the cost function can be rewritten as follows: (Estimation is performed.) (8); in, This is the rewritten cost function; for Time of the first The first transmitting antenna Channel estimates for each multipath delay tap.

[0028] The rewritten cost function is paired Taking the partial derivative and setting it equal to zero yields the channel estimate. : (9); in, , ; ; ; ; for Time of the first Channel estimates for each transmit antenna; =1, 2, 3, ... The superscript T indicates transpose. for Time of the first The root transmit antenna channel Estimates of the multipath delay taps; =0, 1, 2, ... ; It is a complex vector; for Time of the first The vector corresponding to the root transmitting antenna; for Time of the first root transmitting antenna to the first The vector between the root receiving antennas; It is a complex matrix; The first complex matrix is ​​the nth complex matrix. Line 1 A matrix of columns; For matrix The elements in =0, 1, 2, ... ; for Time of the first The OFDM symbol transmitted by the root transmitting antenna on the first Information vectors carried by each subcarrier channel; for The conjugate; for Conjugate; intermediate quantity , The base is the natural number; It is an imaginary number; Pi; This represents the total number of subcarriers. for The first time the receiving antenna is on Signals on each subcarrier channel.

[0029] Circuit Design and Functional Analysis: The matrices and vectors in the system model are in complex form, but the memristor array can only operate in the real domain. To perform complex domain calculations using the memristor array, the complex matrices and vectors must be mapped to their corresponding real matrices and vectors. Complex Matrices By converting the mapping relationship into a real number matrix, we obtain the cross-correlation mapping matrix of the channel estimation pilot sequence. : (10); When complex vector Mapping to real vectors When doing so, the following mapping should be followed: (11); in and These represent the real part and the imaginary part, respectively.

[0030] Channel estimation pilot sequence cross-correlation mapping matrix Separate into real matrices and the first real matrix From real matrix Extracting elements from the main diagonal yields a diagonal matrix. The elements excluding those on the diagonal form the second real matrix. .

[0031] After mapping is complete, the memristor array can be used to perform calculations. However, since the conductance of the memristor must be positive, and the channel estimation pilot sequence cross-correlation mapping matrix... The values ​​in the matrix are not all positive, so an inverter is needed to convert the real matrix to positive. and the first real matrix Only by connecting them can we apply Kirchhoff's laws to... Perform valid calculations. The two matrices are defined as follows: (12); (13); in, Represents the cross-correlation mapping matrix of the pilot sequences for channel estimation. The One element; Represents a real matrix The One element; Represents the first real matrix The Each element.

[0032] The following analysis of the matrix The characteristics of. When At that time, all off-diagonal elements of the matrix are zero or close to zero. Furthermore, The diagonal elements of the matrix are not only positive, but their values ​​are also significantly larger than those of a complex matrix. The other elements in the matrix. Since these matrix elements are mainly distributed in two intervals, directly mapping them to memristor devices would increase write errors. To solve this problem, from the real matrix... Extract elements from the main diagonal and split them into... and ,Right now Among them, the diagonal matrix From real matrix It is composed of diagonal elements.

[0033] Based on the above mapping rules, a design was created as follows: Figure 1 The circuit structure shown employs a one-to-one correspondence between a memristor and a switching device, with the connection state determined by the switching state of the switching device. In the LS algorithm, all switching devices remain on to maintain the connection of all memristors. Furthermore, Figure 1 The second switching device at the output of the operational amplifier is specifically designed for energy-saving LS algorithm implementation.

[0034] like Figure 1 As shown, the switching module includes several first switching devices; the first switching devices in the switching module are connected in series with each memristor in the first memristor array and the second memristor array, respectively, to control the corresponding memristor to be connected to or disconnected from the circuit. The first switching devices can be transistors or other components with switching functions, and are not limited here.

[0035] In this circuit, the three memristor arrays arranged from top to bottom are used to map the first real matrix. The second real matrix and diagonal matrix Between the two memristor arrays at the top layer, a row of inverters performs matrix subtraction. (Real vector) The current is input to the rows of three memristor arrays. By connecting the rows and columns of the memristor arrays with an operational amplifier, a feedback loop is formed, allowing the output of the operational amplifier to immediately obtain the channel. The estimated value .

[0036] The first memristor array, the second memristor array, and the third memristor array adopt a grid structure with intersecting row and column lines. The first switching device in each row of the first memristor array and the second memristor array are connected. The end of the first switching device connected to the memristor is connected to the column line, and the end of the first switching device not connected to the memristor is connected to the row line.

[0037] The inverters in the inverter array are arranged in rows, and each inverter is connected to its corresponding column line.

[0038] real vector The current is input to the rows of the first, second, and third memristor arrays; the operational amplifiers in the operational amplifier array are arranged in columns, and the number of operational amplifiers is the same as the number of transmit antennas multiplied by the maximum time delay spread; the inverting input of the operational amplifier is connected to the row line of the same number of rows in each memristor array; the non-inverting input of the operational amplifier is grounded; the output of the operational amplifier is connected to the column line, and the outputs of all operational amplifiers constitute the channel estimate.

[0039] A second switching device is also provided on the connection line between the output terminal of each operational amplifier and the row line. The second switching device can be a transistor or other components with switching function, which is not limited here.

[0040] When all first and second switching devices are in the on state, the memristor-based channel estimation circuit executes the LS algorithm to perform initial channel estimation and determine significant multipath locations in the channel. Significant multipath locations refer to the locations of distinguishable multipath components in the channel impulse response whose amplitude or power exceeds a set threshold and makes a major contribution to the received signal energy. The number of significant multipath locations depends on the actual channel characteristics to be estimated and the channel estimation accuracy requirements.

[0041] When the first and second switching devices corresponding to the significant multipath location are in the on state, while the other first and second switching devices are in the off state, the memristor-based channel estimation circuit executes an energy-efficient LS algorithm to estimate the channel for subsequent time slots.

[0042] The significant multipath locations are determined as follows: the channel impulse response estimate is obtained by performing the LS algorithm once, and the significant multipath locations are selected according to the target selection method. The target selection method includes threshold-based methods, sparse reconstruction methods, and statistical probability models. Other methods may also be used, which are not limited here.

[0043] In a specific example, the threshold-based method includes: determining the power value of the multipath location based on the channel impulse response estimate, and identifying multipath locations with power values ​​greater than a set power threshold as significant multipath locations.

[0044] Because of the typical characteristics of operational amplifiers ("virtual short and virtual open"), each of its rows satisfies Therefore, once the circuit stabilizes, the operational amplifier's output voltage (signal estimate) will... It can be represented as .because The values ​​in the table are only related to the pilot signals transmitted by each antenna, and these pilot signals are determined before transmission. The values ​​can be pre-calculated and written into the memristor array, which greatly saves the total computation time. When the receiver receives the signal, it calculates the vector... By inputting the value into the memristor array, the channel estimate can be obtained. .

[0045] Analysis of the LS algorithm reveals that channel estimation is essentially a combination of matrix inversion and matrix-vector multiplication. Increasing the number of antennas increases the memristor hardware resources required for channel estimation. However, considering the sparsity of the channel, only a few paths play a significant role in signal transmission, while the contributions of other paths are relatively small or negligible. To address this issue, the LS algorithm is optimized, and an energy-efficient implementation is proposed. Specifically, leveraging the sparsity of the channel, low-power multipath propagation is omitted to simplify the LS algorithm. This reduces the number of multipath paths that need to be estimated to far fewer than the total number required for complete channel estimation. Therefore, the dimensionality of the parameters to be estimated is reduced, saving hardware resources and improving energy efficiency.

[0046] The entire channel estimation process is as follows: First, channel estimation is performed using the LS algorithm. Next, significant multipath propagation is determined using the estimated channel parameters. It is assumed that a high retention power is achieved. A significant multipath event can be estimated in just a few subsequent time slots. Multiple paths. Assume , ,..., For these significant multipath indices, the formula is as follows: ; in, ; ; in, ; ; .

[0047] In implementing the energy-efficient LS algorithm, the first switching device corresponding to the row of low-power multipaths is turned off, separating these rows from the entire circuit. Correspondingly, the second switching device in the feedback circuit remains off, isolating these columns from the circuit. By inputting current into the circuit and setting other locations to zero, the circuit output is the channel estimation result. It should be noted that as long as the transmitted pilot sequence remains unchanged, there is no need to rewrite the memristor array. Furthermore, after estimating the channel impulse response for several time slots and identifying significant multipaths, the energy-efficient LS algorithm implementation can be applied. The number of significant multipaths... It depends on the actual channel characteristics to be estimated and the required channel estimation accuracy.

[0048] Using the circuit proposed in this application, the complexity of a single channel estimation calculation can be reduced to [value missing]. (Whether implementing the LS algorithm or an energy-efficient LS algorithm) significantly reduces the computational load of channel estimation. For the LS algorithm, the memristor array circuit can complete a calculation within 80ns, with power consumption far lower than that of a digital processor performing the same task. Furthermore, after completing a channel estimation using the LS algorithm, the location of significant multipath paths can be determined, and then an energy-efficient LS algorithm can be implemented using the memristor array circuit to complete another channel estimation. For the energy-efficient LS algorithm, the memristor array circuit can complete a calculation within 50ns, further reducing the power consumption required for a single channel estimation calculation.

[0049] Meanwhile, since the pilot signal is known in the system model, the resistance value mapped in the memristor array is only related to the resistance value of the pilot signal. Therefore, the step of writing the resistance value of the memristor array can be completed in advance, which can save the time of subsequent memristor array resistance value writing and further reduce the total time of channel estimation. Only when the pilot signal changes will it be necessary to rewrite the resistance value of the memristor array.

[0050] Example 2 Based on the same inventive concept, this application also provides a channel estimation method based on the memristor-based channel estimation circuit described in Embodiment 1. Specific limitations of the one or more channel estimation method embodiments provided by this method can be found in the limitations of the memristor-based channel estimation circuit described above, and will not be repeated here.

[0051] In an exemplary embodiment, a channel estimation method based on the memristor-based channel estimation circuit described in Embodiment 1 is provided, comprising the following steps: Determine whether the currently transmitted pilot signal has changed compared to the previous cycle; If the pilot signal changes, the memristor array in the circuit is rewritten to update the mapped matrix parameters. If the pilot signal has not changed, then it is further determined whether the significant multipath location of the current channel has been determined; If a significant multipath location has been determined, the control circuit operates in the first working mode, executes the energy-saving LS algorithm, and outputs the channel estimation result; If the significant multipath location is not determined, the control circuit operates in the second operating mode, executes the complete LS algorithm, outputs the channel estimation result, and determines the significant multipath location.

[0052] As an optional implementation, the first operating mode includes: turning on the first and second switching devices corresponding to significant multipath positions, inputting the received signal vector into the circuit, and outputting a simplified channel estimate through an operational amplifier.

[0053] The second operating mode includes: turning on all switching devices, inputting the received signal vector into the circuit, and outputting a complete channel estimate through an operational amplifier.

[0054] The significant multipath locations are determined by performing an LS algorithm once to obtain the channel impulse response estimate, and then selecting significant multipath locations according to a target selection method; the target selection method includes a threshold-based method, a sparse reconstruction method, and a statistical probability model.

[0055] like Figure 2 As shown, the system first determines whether the transmitted pilot signal has changed. If the transmitted pilot signal has changed, the memristor array needs to be rewritten to update the system parameters. If the transmitted pilot signal has not changed, the system proceeds to the next step: determining whether the significant multipath location has been determined. If the significant multipath location has been determined, the energy-efficient LS algorithm is directly implemented using the memristor array circuit to complete an efficient channel estimation. This method further reduces energy consumption while maintaining estimation accuracy. If the significant multipath location has not yet been determined, the system must first implement the LS algorithm using the memristor array circuit to perform a channel estimation and confirm the significant multipath location in the current channel, facilitating the use of the energy-efficient LS algorithm in the next channel estimation.

[0056] It is worth noting that regardless of whether the transmitted pilot signal changes or whether the location of a significant multipath path is determined, a channel estimation process will eventually be completed, ending the current processing cycle. This channel estimation process, through the joint judgment of whether the transmitted pilot signal has changed and whether the location of a significant multipath path has been determined, achieves intelligent control and algorithm selection of the memristor array, improving channel estimation efficiency while optimizing system power consumption.

[0057] In recent years, memristor array-based analog in-memory computing has been developed for fast and efficient matrix computation. A memristor array naturally represents a physical analog matrix, upon which basic matrix operations can be performed. Based on this, corresponding circuits can be designed to optimize channel estimation algorithms for MIMO-OFDM systems, shortening computation time. Furthermore, due to the low power consumption of memristor components and the high spatial parallelism of memristor arrays, the energy consumption and complexity of analog matrix computation are significantly reduced. Simultaneously, memristor-based in-memory computing is an emerging computing paradigm that utilizes the physical characteristics of memristors to perform computational tasks and integrates the computation process within memory. Since computation is performed within the memory array and peripheral circuitry, this method achieves in-memory computation, saving communication costs. This computing approach can solve the data transmission bottleneck problem in the von Neumann architecture by reducing the need for data transfer between the processor and memory, thereby improving computational efficiency, reducing energy consumption, and shortening computation time.

[0058] The related technology provides a hardware acceleration circuit based on analog in-memory computing, which relies on accurate channel state information. However, this solution does not solve the problem of how to quickly acquire channel information. This related technology can complete the detection, decoding, and precoding functions of a MIMO system, but because channel characteristics change over time, frequent adjustments to the memristor resistance are required, and the time spent on this step remains significant.

[0059] This application provides a memristor-based channel estimation circuit and method, relating to signal processing in wireless communication and semiconductor integrated circuits. The memristor-based channel estimation circuit proposed in this application can replace the channel estimation function of digital baseband chips, reducing signal processing complexity and power consumption while achieving in-memory and analog computation. Furthermore, the memristor-based channel estimation circuit of this application can perform channel estimation on a memristor array circuit without relying on digital chips for received signal processing and inverse matrix solving, resulting in lower circuit complexity. The circuit proposed in this application not only performs channel estimation calculations faster and with lower power consumption than digital chips, but also, due to the characteristics of channel estimation, does not require frequent adjustments to the memristor resistance values ​​when using a memristor array circuit for channel estimation, thus significantly reducing the total computation time and effectively solving the computational bottleneck faced in MIMO-OFDM communication systems.

[0060] This application has the following advantages: 1. A channel estimation circuit based on memristors is provided (an analog in-memory calculation channel estimation circuit based on memristor array).

[0061] In related technologies, channel estimation modules are commonly implemented in the digital domain using a von Neumann computing architecture. This requires frequent data transfer between memory and the computer, significantly increasing computation time and energy consumption. Furthermore, in MIMO-OFDM systems, the matrix calculation dimension in the channel estimation algorithm increases with the number of antennas and subcarriers, further increasing computational complexity, time requirements, and energy consumption. This application designs a memristor-based channel estimation circuit, using memristor arrays, operational amplifiers, inverters, current sources, voltage sources, and switches to perform in-memory computation in the analog domain. Compared to digital domain solutions, the proposed circuit significantly reduces computational complexity, time requirements, and energy consumption.

[0062] 2. The structure of one memristor corresponding to one switching device in the circuit can realize the LS algorithm and the energy-saving LS algorithm by controlling the switching device.

[0063] The proposed analog in-memory channel estimation circuit based on a memristor array uses a one-to-one switching device structure for each memristor. This design allows for changes in the circuit structure through control of the switching devices, enabling different functionalities. Specifically, when the switching devices remain on to maintain all memristors connected to the circuit, the proposed circuit can implement the Last-Range (LS) algorithm. When only the switching devices at the locations corresponding to significant multipaths remain on while the switching devices at other locations are off, some memristors are disconnected from the circuit, thus implementing an energy-efficient LS algorithm. Before determining the significant multipath locations, the switching devices can be controlled to enable the circuit to implement the LS algorithm for channel estimation and determine the significant multipath locations. After determining the significant multipath locations, the switching devices can be controlled to enable the circuit to implement the energy-efficient LS algorithm for channel estimation. The number of significant multipaths depends on the actual channel characteristics to be estimated and the required channel estimation accuracy. Simultaneously, this structural design further increases the circuit's stability. Since the structure of one memristor corresponding to one switching device allows the switching device to control the memristor elements connected to the circuit, when some memristor elements in the memristor array fail, the switching device can be controlled to disconnect the failed memristors from the circuit, map the required values ​​onto the unfaulty memristors, and keep the switching device on to connect them to the circuit. This avoids circuit calculation errors caused by the failure of some memristor elements and further increases the stability of the circuit.

[0064] 3. Channel estimation process for the proposed circuit.

[0065] The proposed channel estimation process using an analog in-memory computational channel estimation circuit based on a memristor array is as follows: First, it is determined whether the transmitted pilot signal has changed. If the transmitted pilot signal has changed, the memristor array needs to be rewritten to update the system parameters. If the transmitted pilot signal has not changed, the next step is to determine whether the significant multipath location has been determined. If the significant multipath location has been determined, an energy-efficient LS algorithm is directly implemented using the memristor array circuit to complete an efficient channel estimation. This method further reduces energy consumption while ensuring estimation accuracy. If the significant multipath location has not yet been determined, the system must first implement the LS algorithm using the memristor array circuit to perform a channel estimation and confirm the significant multipath location in the current channel, facilitating the use of the energy-efficient LS algorithm in the next channel estimation.

[0066] (1) In related technologies, the common implementation of channel estimation modules is a digital domain scheme, which uses the von Neumann computing architecture. This requires frequent data transfer between memory and computer, which greatly increases the computation time and energy consumption. At the same time, in MIMO-OFDM systems, as the number of antennas and subcarriers increases, the matrix calculation dimension in the channel estimation algorithm will increase accordingly, resulting in a further increase in computational complexity, time required, and energy consumption. This application designs an analog in-memory computation channel estimation circuit based on a memristor array, realizing in-memory computation in the analog domain. Compared with the digital domain scheme, the proposed circuit significantly reduces computational complexity, time required, and energy consumption.

[0067] (2) The relevant technical solutions can complete the detection, decoding and precoding functions of the MIMO system, but since the channel characteristics change over time, the memristor resistance value needs to be adjusted frequently, and the time spent on this step is still quite significant. Due to the characteristics of channel estimation, this application does not require frequent adjustment of the memristor resistance value when using a memristor array circuit for channel estimation, thereby greatly reducing the total calculation time and effectively solving the computational bottleneck faced by the MIMO-OFDM communication system.

[0068] (3) The structure of one memristor corresponding to one switching device in this application allows for the selection of memristor elements connected to the circuit by controlling the switching device, thereby achieving different functions. This application can implement both the LS algorithm and an energy-saving LS algorithm, which can further reduce the complexity, time, and energy consumption of implementing the channel estimation algorithm. At the same time, when some memristor elements fail, they can be disconnected from the circuit to avoid errors in circuit calculations.

[0069] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A channel estimation circuit based on memristors, characterized in that, The memristor-based channel estimation circuit includes: The memristor array module is used to map the matrix parameters related to the pilot frequency to the device conductance, and to perform matrix-vector multiplication and matrix inversion related operations in the analog domain; the memristor array module includes at least a first memristor array, a second memristor array, and a third memristor array arranged in sequence; A first memristor array is used to map a first real matrix, which is composed of the absolute values ​​of the non-positive elements of the channel estimation pilot sequence cross-correlation mapping matrix; The second memristor array is used to map the second real matrix, which is composed of the off-diagonal elements of the non-negative elements of the channel estimation pilot sequence cross-correlation mapping matrix; the number of memristors on the row and column lines of the first and second memristor arrays is determined by the number of transmit antennas in the MIMO-OFDM system and the maximum delay spread. The third memristor array, with memristors arranged on the diagonal of the array, is used to map a diagonal matrix, which is composed of the diagonal elements of the non-negative elements of the channel estimation pilot sequence cross-correlation mapping matrix; Switching module, used to control the connection or disconnection of memristors from the circuit; An inverter array, connected between the first memristor array and the second memristor array, is used to implement matrix subtraction and positive / negative value compensation; The operational amplifier array is connected to the row and column lines of the memristor array to form a feedback loop, which is used to output the channel estimate.

2. The channel estimation circuit based on memristor according to claim 1, characterized in that, The switching module includes several first switching devices; the first switching devices in the switching module are connected in series with each memristor in the first memristor array and the second memristor array, respectively, to control the corresponding memristor to be connected to or disconnected from the circuit.

3. The channel estimation circuit based on memristors according to claim 2, characterized in that, The channel estimate is expressed as ; in, , ; ； ； ； for Time of the first Channel estimates for each transmit antenna; =1, 2, 3, ... The superscript T indicates transpose. for Time of the first The root transmit antenna channel Estimates of the multipath delay taps; =0, 1, 2, ... ; It is a complex vector; for Time of the first The vector corresponding to the root transmitting antenna; for Time of the first root transmitting antenna to the first The vector between the root receiving antennas; It is a complex matrix; The first complex matrix is ​​the nth complex matrix. Line number A matrix of columns; For matrix The elements in =0, 1, 2, ... ; for Time of the first The OFDM symbol transmitted by the root transmitting antenna on the first Information vectors carried by each subcarrier channel; for The conjugate; for Conjugate; intermediate quantity , The base is the natural number; It is an imaginary number; Pi; This represents the total number of subcarriers. for The first time the receiving antenna is on Signals on each subcarrier channel; Complex matrix By converting the mapping relationship into a real number matrix, we obtain the cross-correlation mapping matrix of the channel estimation pilot sequence. : ； When complex vector Mapping to real vectors When doing so, the following mapping should be followed: ； in and They represent the real part and the imaginary part, respectively. Channel estimation pilot sequence cross-correlation mapping matrix Separate into real matrices and the first real matrix From real matrix Extracting elements from the main diagonal yields a diagonal matrix. The elements excluding those on the diagonal form the second real matrix. ; .

4. The channel estimation circuit based on memristors according to claim 3, characterized in that, The first memristor array, the second memristor array, and the third memristor array adopt a grid structure with intersecting row lines and column lines; the first switching device in each row of the first memristor array and the second memristor array are connected, the end of the first switching device connected to the memristor is connected to the column line, and the end of the first switching device not connected to the memristor is connected to the row line. In an inverter array, the inverters are arranged in rows, and each inverter is connected to its corresponding column line. real vector It is used as a current input to the rows of the first memristor array, the second memristor array, and the third memristor array; The operational amplifiers in the operational amplifier array are arranged in columns, and the number of operational amplifiers is the same as the number of transmit antennas multiplied by the maximum time delay spread. The inverting input of the operational amplifier is connected to the row line of the same number of rows in each memristor array. The non-inverting input of the operational amplifier is grounded. The output of the operational amplifier is connected to the column line, and the output of all operational amplifiers constitutes the channel estimate.

5. The channel estimation circuit based on memristors according to claim 4, characterized in that, A second switching device is also provided on the connection line between the output terminal of each operational amplifier and the row line; When all first and second switching devices are in the ON state, the memristor-based channel estimation circuit executes the LS algorithm to perform initial channel estimation and determine significant multipath locations in the channel; the number of significant multipath locations depends on the actual channel characteristics to be estimated and the channel estimation accuracy requirements. When the first and second switching devices corresponding to the significant multipath location are in the on state, while the other first and second switching devices are in the off state, the memristor-based channel estimation circuit executes an energy-efficient LS algorithm to estimate the channel for subsequent time slots.

6. The channel estimation circuit based on memristors according to claim 5, characterized in that, The significant multipath locations are determined by performing an LS algorithm once to obtain the channel impulse response estimate, and then selecting significant multipath locations according to a target selection method; the target selection method includes a threshold-based method, a sparse reconstruction method, and a statistical probability model.

7. A channel estimation method based on the memristor-based channel estimation circuit according to any one of claims 1-6, characterized in that, The channel estimation method includes: Determine whether the currently transmitted pilot signal has changed compared to the previous cycle; If the pilot signal changes, the memristor array in the circuit is rewritten to update the mapped matrix parameters. If the pilot signal has not changed, then it is further determined whether the significant multipath location of the current channel has been determined; If a significant multipath location has been determined, the control circuit operates in the first working mode, executes the energy-saving LS algorithm, and outputs the channel estimation result; If the significant multipath location is not determined, the control circuit operates in the second operating mode, executes the complete LS algorithm, outputs the channel estimation result, and determines the significant multipath location.

8. The channel estimation method according to claim 7, characterized in that, The first operating mode includes: turning on the first and second switching devices corresponding to significant multipath positions, inputting the received signal vector into the circuit, and outputting a simplified channel estimate value through an operational amplifier.

9. The channel estimation method according to claim 7, characterized in that, The second operating mode includes: turning on all switching devices, inputting the received signal vector into the circuit, and outputting a complete channel estimate through an operational amplifier.

10. The channel estimation method according to claim 7, characterized in that, The significant multipath locations are determined by performing an LS algorithm once to obtain the channel impulse response estimate, and then selecting significant multipath locations according to a target selection method; the target selection method includes a threshold-based method, a sparse reconstruction method, and a statistical probability model.

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