Display driving device and manufacturing method thereof, display panel

Abstract

The application discloses a display driving device and a manufacturing method thereof and a display panel. The display driving device comprises a first device layer, a second device layer and a conductive interconnection structure. The first device layer is integrated with a logic control circuit based on monocrystalline silicon; the second device layer is integrated with an oxide semiconductor transistor; and the conductive interconnection structure electrically connects the first device layer and the second device layer. The display driving device is configured to store a data voltage by using a parasitic capacitor, the parasitic capacitor is located at a connection node of the oxide semiconductor transistor, and no independent physical capacitor is arranged at the connection node. The application provides a silicon-based CMOS circuit and oxide semiconductor heterogeneous integration scheme, which takes into account the complementary advantages of the two in speed, voltage resistance and leakage indicators, and uses a parasitic capacitor instead of a physical capacitor in a traditional process, thereby reducing the circuit area.

Description

Technical Field

[0001] This invention relates to the field of display driving technology, and more specifically, to a display driving device, a method for manufacturing the same, and a display panel. Background Technology

[0002] In microdisplay chips, pixel density continues to increase, and pixel pitch has been reduced to below 5μm. Traditional pixel circuits require the fabrication of a storage capacitor within each pixel to maintain the driving voltage for one frame. This capacitor typically occupies more than half of the pixel area, becoming a major bottleneck for further improving resolution or aperture ratio.

[0003] On the other hand, high-performance logic circuits require advanced complementary metal-oxide-semiconductor (CMOS) processes, while high-voltage, low-leakage pixel drivers are better suited to oxide semiconductor processes. If both types of devices are fabricated on the same wafer, the high-temperature activation of silicon processes and the low-temperature requirements of oxide thin films conflict, making it difficult to coordinate thermal budgets. Summary of the Invention

[0004] In view of the above problems, the purpose of this invention is to provide a display driving device and its manufacturing method, as well as a display panel, so as to balance speed, voltage resistance and leakage current indicators, and reduce the circuit area occupied.

[0005] According to a first aspect of the present invention, a display driving device is provided, comprising:

[0006] The first device layer integrates a control circuit based on single-crystal silicon.

[0007] The second device layer integrates oxide semiconductor transistors; and

[0008] A conductive interconnect structure electrically connects the first device layer and the second device layer.

[0009] The display driving device is configured to store data voltage using parasitic capacitance, which is located at the connection node of the oxide semiconductor transistor, and no independent physical capacitor is provided at the connection node.

[0010] Optionally, the oxide semiconductor transistor includes a write transistor and a drive transistor, the gate of the drive transistor is connected to the source or drain of the write transistor, the connection node between the write transistor and the drive transistor has the parasitic capacitance, the write transistor receives a data voltage and is controlled by a scan signal, and the drive transistor provides a drive signal according to the data voltage.

[0011] During the data writing phase, the scan signal controls the writing transistor to turn on, and stores the data voltage in the parasitic capacitance.

[0012] During the light-emitting phase, the driving transistor provides a driving signal based on the data voltage across the parasitic capacitance.

[0013] The parasitic capacitance maintains the gate voltage of the driving transistor during the display frame period.

[0014] Optionally, the oxide semiconductor transistor includes a write transistor, the first device layer includes a drive transistor, the drive transistor being a silicon-based transistor, the gate of the drive transistor being connected to the source or drain of the write transistor, the connection node between the write transistor and the drive transistor having the parasitic capacitance, the write transistor receiving a data voltage and being controlled by a scan signal, and the drive transistor providing a drive signal according to the data voltage.

[0015] During the data writing phase, the scan signal controls the writing transistor to turn on, and stores the data voltage in the parasitic capacitance.

[0016] During the light-emitting phase, the driving transistor provides a driving signal based on the data voltage across the parasitic capacitance.

[0017] The transistors in the second device layer have a higher withstand voltage than those in the first device layer, and the parasitic capacitance maintains the gate voltage of the driving transistor during the display frame period.

[0018] Optionally, the parasitic capacitance includes the gate parasitic capacitance of the driving transistor, or the parasitic capacitance includes the gate parasitic capacitance of the driving transistor and the wiring parasitic capacitance between the write transistor and the driving transistor.

[0019] Optionally, the conductive interconnect structure is any one of the following: a top metal layer located on top of the first device layer, a hybrid bonding structure located between the first device layer and the second device layer, a metal microbump, and a through-silicon via interconnect layer, wherein the hybrid bonding includes metal-metal bonding and dielectric-dielectric bonding.

[0020] According to a second aspect of the present invention, a method for manufacturing a display driving device is provided, comprising:

[0021] A first device layer is formed, wherein the first device layer integrates a logic control circuit based on a single crystal silicon.

[0022] A second device layer is formed, stacked on top of the first device layer, the second device layer integrating oxide semiconductor transistors; and

[0023] The first device layer and the second device layer are electrically connected using a conductive interconnect structure.

[0024] The display driving device is configured to store data voltage using parasitic capacitance, which is located at the connection node of the oxide semiconductor transistor, and no independent physical capacitor is provided at the connection node.

[0025] Optionally, the first device layer and the second device layer are vertically interconnected by any one of in-situ growth, hybrid bonding, metal microbump bonding, and back-end via interconnection, wherein the hybrid bonding includes metal-metal bonding and dielectric-dielectric bonding.

[0026] Optionally, the second device layer is deposited in situ directly on the back-end interconnect layer of the first device layer.

[0027] Optionally, the second device layer and the first device layer are bonded face-to-face through metal-to-metal bonding and dielectric-to-dielectric bonding, and the second device layer and the first device layer are bonded after being independently manufactured on different wafers.

[0028] Optionally, the second device layer and the first device layer are interconnected by flip-chip stacking through metal microbumps and / or through-silicon via interconnect layers, and the second device layer and the first device layer are bonded after being independently manufactured on different wafers.

[0029] Optionally, forming the second device layer includes:

[0030] Forming an oxide semiconductor transistor, the oxide semiconductor transistor including a write transistor and a drive transistor; and

[0031] Connect the gate of the driving transistor to the source or drain of the writing transistor.

[0032] The connection node between the write transistor and the drive transistor has the parasitic capacitance. The write transistor is used to receive data voltage and is controlled by a scan signal. The drive transistor is used to provide a drive signal according to the data voltage. The parasitic capacitance is used to store the data voltage and maintains the gate voltage of the drive transistor during the display frame period.

[0033] Optionally, forming the first device layer includes: forming a logic control circuit based on monocrystalline silicon, and forming a driving transistor based on monocrystalline silicon.

[0034] Forming the second device layer includes: forming an oxide semiconductor transistor, the oxide semiconductor transistor including a write transistor, and connecting the gate of the drive transistor to the source or drain of the write transistor.

[0035] The transistor in the second device layer has a higher breakdown voltage than the transistor in the first device layer. The connection node between the write transistor and the drive transistor has the parasitic capacitance. The write transistor is used to receive data voltage and is controlled by a scan signal. The drive transistor is used to provide a drive signal according to the data voltage. The parasitic capacitance is used to store the data voltage. The parasitic capacitance maintains the gate voltage of the drive transistor during the display frame period.

[0036] According to a third aspect of the present invention, a display panel is provided, comprising a plurality of pixel circuits, the pixel circuits comprising:

[0037] The display driver device as described above, or the display driver device manufactured by the manufacturing method described above; and

[0038] The light-emitting element is controlled by the display driver.

[0039] Optionally, the light-emitting element is one of a micro light-emitting diode, a micro organic light-emitting diode, or a silicon-based liquid crystal unit.

[0040] This invention proposes a heterogeneous integration scheme of silicon-based CMOS and oxide semiconductor, which takes into account the complementary advantages of both in terms of speed, voltage withstand capability, and leakage current. By vertically stacking, the single-crystal silicon-based logic control circuit and oxide semiconductor transistor are physically separated, and electrical connection is achieved through conductive interconnect structures. This allows high-speed, low-voltage computing functions and high-voltage, low-leakage retention functions to work collaboratively within the same chip, thereby overcoming the inherent limitations of single-wafer systems in terms of thermal budget and process compatibility. In an optional embodiment, the first device layer integrates low-voltage CMOS devices, undertaking tasks such as data decoding, timing generation, high-speed interface, and pulse width modulation; the second device layer integrates high-voltage oxide semiconductor transistors, undertaking pixel switching, driving, and charge retention tasks. The two layers can be vertically integrated after being independently completed within their respective optimal temperature windows, avoiding performance degradation caused by mutual compromise.

[0041] Furthermore, at the pixel circuit level, this invention utilizes the characteristic that the off-state leakage current of oxide thin-film transistors is six orders of magnitude lower than that of silicon devices. It replaces traditional physical storage capacitors with gate parasitic capacitance and wiring parasitic capacitance, forming a 2TOC topology containing only two transistors and no independent capacitors. This reduces the pixel area to the physical limit determined by the transistor size and interconnect width, while maintaining voltage stability within one frame cycle. It completely avoids the constraints of large-size storage capacitors on aperture ratio and pixel density, and can provide driving signals for light-emitting or dimming mechanisms such as micro light-emitting diodes (Micro-LEDs), micro organic light-emitting diodes (Micro-OLEDs), and liquid crystal on silicon (LCoS). Attached Figure Description

[0042] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0043] Figure 1 A cross-sectional view of a display driver device according to a first embodiment of the present invention is shown;

[0044] Figure 2 A cross-sectional view of a display driver device according to a second embodiment of the present invention is shown;

[0045] Figure 3 A cross-sectional view of a display driver device according to a third embodiment of the present invention is shown;

[0046] Figure 4 A schematic diagram of a pixel circuit according to an embodiment of the present invention is shown;

[0047] Figure 5 A flowchart illustrating a method for manufacturing a display driver device according to an embodiment of the present invention is shown. Detailed Implementation

[0048] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0049] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0050] It should be understood that the connection / coupling of A and B in the embodiments of this application means that A and B can be connected in series or in parallel, or A and B can be connected through other devices. The embodiments of this application do not limit this.

[0051] The following description, in conjunction with the accompanying drawings, describes embodiments of the display driving device and its manufacturing method, as well as the pixel circuit provided in this application.

[0052] Figure 1 A cross-sectional view of a display driver device according to a first embodiment of the present invention is shown. Figure 1 The basic stacking relationship of the display driving device 10 in this embodiment is illustrated in longitudinal cross-section.

[0053] In this embodiment, the display driving device 10 includes a first device layer 110 and a second device layer 120. The first device layer 110 integrates a single-crystal silicon-based logic control circuit. The second device layer 120 integrates an oxide semiconductor transistor. The first device layer 110 and the second device layer 120 are electrically connected through a conductive interconnect structure. This display driving device 10 is configured to store data voltage using parasitic capacitance located at the connection nodes of the oxide semiconductor transistors, and no independent physical capacitors are provided at the connection nodes, thus significantly reducing the footprint of the pixel circuitry. For example, the oxide semiconductor transistor integrated in the second device layer 120 includes a write transistor for writing data voltage, whose off-state leakage current is close to 0, so that the data voltage is maintained within the parasitic capacitance. Optionally, the write transistor is an oxide thin-film transistor. Optionally, the transistor breakdown voltage of the second device layer 120 is higher than that of the transistor breakdown voltage of the first device layer 110.

[0054] It should be noted that the parasitic capacitance described in this invention refers to the capacitance effect naturally formed by the gate capacitance (Cgs, Cgd) of the transistor and the coupling capacitance between the metal wiring. Unlike traditional technologies that require independent physical capacitors with metal-insulator-metal (MIM) or polysilicon-insulator-polysilicon (PIP) structures, this embodiment directly utilizes the parasitic parameters of the device itself. Because the leakage current of oxide semiconductor transistors is extremely low (e.g., <10^-15 A), at refresh rates of 60Hz or even 1Hz, voltage variations can be controlled within a grayscale range imperceptible to the human eye using only parasitic capacitance in the fF (flaffar) range. This design eliminates the chip area occupied by physical capacitors, resulting in a significant improvement in pixel aperture ratio and circuit density in ultra-small pitch applications such as Micro-LED.

[0055] Therefore, the parasitic capacitance of the present invention is sufficient to maintain the gate voltage of the driving transistor during the display frame period.

[0056] In this embodiment, the first device layer 110 is located below the second device layer 120, and a low-voltage CMOS logic control circuit is formed within its single-crystal silicon substrate 111. The top surface of the single-crystal silicon substrate 111 is covered with a back-end interconnect layer 112, and the top metal layer of the back-end interconnect layer 112 is exposed on the surface and serves as a conductive interconnect structure to achieve conductive interconnection with the second device layer 120.

[0057] In this embodiment, a first device layer 110 is first formed. For example, shallow trench isolation, well implantation, gate stacking, source / drain activation, and silicide alloying are sequentially performed on the surface of a single-crystal silicon substrate 111 using a standard front-end of line (FEOL) process to construct a low-voltage CMOS logic control circuit. The peak temperature of this front-end process does not exceed a first preset temperature, such as 1050°C. The feature size of the CMOS logic control circuit is, for example, 3~28nm. For example, the fabrication temperature of the first device layer 110 is controlled within a range where the peak temperature of rapid thermal annealing does not exceed 1050°C and the duration of this peak is less than five seconds. Optionally, after completing the front-end process, a silicon nitride etch stop layer is deposited above the low-voltage CMOS logic control circuit to improve the electron mobility of the device and serve as a stop interface for subsequent chemical-mechanical polishing (CMP).

[0058] After the front-end process is completed, the back-end process (BEOL) begins. The peak temperature of this back-end process does not exceed a second preset temperature, such as 450°C. For example, a multilayer metal interconnect structure is sequentially constructed to form the back-end interconnect layer 112. The top metal layer of the back-end interconnect layer 112 is, for example, a copper-manganese alloy with a cobalt cap layer, and its surface is treated with low-pressure chemical mechanical polishing. The top metal layer can serve as a conductive interconnect structure to realize the metal interconnection between the first device layer and the second device layer. Optionally, after the top metal layer is patterned and its bonding surface is exposed, in-situ pre-cleaning is performed using argon-hydrogen mixed plasma to remove surface oxide films and organic contaminants, thereby providing atomically flat interface conditions for the subsequent dense deposition of the hydrogen barrier layer and the low-defect epitaxial growth of the oxide semiconductor layer.

[0059] In this example, during the back-end process stage of forming the back-end interconnect layer, the upper temperature limit is set to no more than 450°C to avoid interface defects caused by thermal stress in the ultra-thin gate stack or stress voids in the copper interconnect. This ensures that the low-voltage CMOS logic control circuit can still maintain low leakage current, high drive current and reliable electromigration lifetime at the sub-5nm node, and provides thermal budget space for subsequent low-temperature integration with the oxide semiconductor layer.

[0060] The second device layer 120 is formed on the top metal layer of the back-end interconnect layer 112 by in-situ growth, for example, by deposition on the top metal layer of the back-end interconnect layer 112. The second device layer 120 includes an oxide semiconductor layer, which is patterned to form a high-voltage oxide semiconductor transistor. In the process of forming the second device layer 120, the peak temperature does not exceed a third preset temperature, such as 300°C.

[0061] As an example, a hydrogen barrier layer is formed on the top metal layer of the back-end interconnect layer 112 using a plasma-enhanced atomic layer deposition (PEALD) process. The deposition temperature is controlled, for example, between 200 °C and 250 °C, to ensure that the hydrogen barrier layer has both density and step coverage. The material of the hydrogen barrier layer is selected from at least one of silicon nitride, silicon oxynitride, or carbon-doped silicon nitride. By providing the hydrogen barrier layer, it can be ensured that the diffusion flux of hydrogen atoms into the oxide semiconductor layer is within a predetermined range during the long annealing process of subsequent processes, thereby suppressing abnormal increases in the channel carrier concentration of the second device layer 120.

[0062] Optionally, after forming the hydrogen barrier layer, its surface hydrophilicity is modulated using a combined ultraviolet-ozone treatment to improve the uniformity of the oxide semiconductor layer in the subsequent second device layer 120. Subsequently, an amorphous indium gallium zinc oxide (In-Ga-Zn-O) film is deposited by radio frequency sputtering in the same vacuum cluster equipment. After forming the IGZO film, oxygen-enriched annealing is performed, for example, at a temperature not exceeding 300°C, to further reduce the oxygen vacancy density. Then, the IGZO film is patterned, source / drain metals are stacked, and a passivation layer is applied, ultimately completing the integration of the indium gallium zinc oxide thin-film transistor (IGZO TFT) in the second device layer 120.

[0063] In this embodiment, the front-end process for forming the first device layer 110, the back-end process, and the process for forming the second device layer 120 are executed sequentially, with the peak temperature decreasing accordingly. Therefore, the second device layer 120 and the first device layer 110 form a thermally budget-compatible heterogeneous stacked structure.

[0064] In one embodiment, a write transistor and a drive transistor are integrated simultaneously in the second device layer 120. The gate of the drive transistor is connected to the source or drain of the write transistor, and the connection node between the write transistor and the drive transistor has a parasitic capacitance. The write transistor receives a data voltage and is controlled by a scan signal, while the drive transistor provides a drive signal based on the data voltage. During the data writing phase, the scan signal controls the write transistor to turn on and stores the data voltage in the parasitic capacitance; during the light emission phase, the drive transistor provides a drive signal based on the data voltage on the parasitic capacitance. In this embodiment, the write transistor and the drive transistor are indium gallium zinc oxide thin-film transistors (IGZO TFTs).

[0065] In another embodiment, a write transistor is integrated in the second device layer 120, and a drive transistor is integrated in the first device layer 110. The gate of the drive transistor is connected to the source or drain of the write transistor via a back-end interconnect layer 112. The write transistor receives a data voltage and is controlled by a scan signal, while the drive transistor provides a drive signal based on the data voltage. During the data writing phase, the scan signal controls the write transistor to turn on and stores the data voltage in a parasitic capacitance; during the light emission phase, the drive transistor provides a drive signal based on the data voltage on the parasitic capacitance. In this embodiment, the write transistor is an indium gallium zinc oxide thin-film transistor (IGZO TFT), and the drive transistor is a silicon-based transistor.

[0066] In the above embodiments, the parasitic capacitance includes the gate parasitic capacitance of the driving transistor, or the parasitic capacitance includes the gate parasitic capacitance of the driving transistor and the wiring parasitic capacitance between the writing transistor and the driving transistor.

[0067] Figure 2 A cross-sectional view of a display driver device according to a second embodiment of the present invention is shown. In this embodiment, a hybrid bonding process is used to interconnect the first device layer 110 and the second device layer 120. Specifically, the first device layer 110 includes a single-crystal silicon substrate 111 and a back-end interconnect layer 112. A low-voltage CMOS logic control circuit is formed on the surface of the single-crystal silicon substrate 111, and a first bonding pad 113 is disposed on the top of the back-end interconnect layer 112. The second device layer 120 includes an oxide semiconductor layer 122 formed on a substrate 121. A high-voltage oxide semiconductor transistor is integrated in the oxide semiconductor layer 122, and second bonding pads 123 are disposed on its surface corresponding to the first bonding pads 113.

[0068] In this embodiment, a first device layer 110 is formed independently. For example, shallow trench isolation, well implantation, gate stacking, source / drain activation, and silicide alloying are sequentially performed on the surface of a single-crystal silicon substrate 111 using a standard front-end of line (FEOL) process to construct a low-voltage CMOS logic control circuit. The feature size of the CMOS logic control circuit is, for example, 3~28nm. For example, the fabrication temperature of the first device layer 110 is controlled within a range where the peak value of rapid thermal annealing does not exceed 1050°C and the duration of this peak value is less than five seconds. Optionally, after completing the front-end process, a silicon nitride etch stop layer is deposited above the low-voltage CMOS logic control circuit to improve the electron mobility of the device and serve as a stop interface for subsequent chemical-mechanical polishing (CMP).

[0069] After the front-end process is completed, the back-end process (BEOL) begins. For example, a multi-layer metal interconnect structure is sequentially constructed to form the back-end interconnect layer 112. The top metal layer of the back-end interconnect layer 112 is, for example, a copper-manganese alloy with a cobalt cap layer, and its surface is treated with low-pressure chemical mechanical polishing. The top metal layer can serve as a conductive interconnect structure to realize the metal interconnection between the first device layer and the second device layer.

[0070] Optionally, during the back-end process stage of forming the back-end interconnect layer, the upper temperature limit is set to no more than 450°C to avoid interface defects caused by thermal stress in the ultra-thin gate stack or stress voids in the copper interconnect, thereby ensuring that the low-voltage CMOS logic control circuit can still maintain low leakage current, high drive current and reliable electromigration lifetime at the sub-5 nanometer node.

[0071] After the back-end fabrication process is completed, an array of first bonding pads 113 is formed on the surface of the back-end interconnect layer 112 using a patterning process. For example, a dielectric layer is deposited on the surface of the back-end interconnect layer 112, and then an opening corresponding to the underlying metal line is defined in the dielectric layer using photolithography and etching processes. The opening is then filled with conductive material to form the first bonding pad 113. The upper surface of the first bonding pad 113 is substantially flush with the upper surface of the dielectric layer, thereby forming a flat bonding interface, providing a basis for subsequent alignment and bonding with its second device layer.

[0072] After the formation of the first bonding pad 113 is completed, the surface of the dielectric layer can be further surface-treated, for example, by plasma treatment or chemical cleaning to remove surface contaminants and oxide layers, in order to enhance the interfacial bonding strength in subsequent bonding processes. At the same time, stress buffer structures or microstructures can be introduced into the dielectric layer to alleviate interfacial warping or cracking problems caused by differences in thermal expansion coefficients or mechanical stress, thereby improving the reliability and stability of the bonding structure.

[0073] In this embodiment, a second device layer 120 is formed independently. The second device layer 120 includes a substrate 121 and an oxide semiconductor layer 122, which is formed on the substrate 121, for example, using a deposition process. The oxide semiconductor layer 122 is patterned to form a high-voltage oxide semiconductor transistor.

[0074] As an example, an amorphous indium gallium zinc oxide (In-Ga-Zn-O) film is deposited on substrate 121 by radio frequency sputtering. After the IGZO film is formed, an oxygen-rich annealing process is performed, for example, at a temperature not exceeding 300°C, to further reduce the oxygen vacancy density. Subsequently, the IGZO film is patterned, source / drain metals are stacked, and a passivation layer is applied to complete the integration of the indium gallium zinc oxide thin-film transistor (IGZO TFT) in the second device layer 120.

[0075] After forming the second device layer 120, an array of second bonding pads 123 are formed on the surface of the second device layer 120 using a patterning process. For example, a dielectric layer is deposited on the surface of the second device layer 120, and then an opening corresponding to the underlying metal line is defined in the dielectric layer using photolithography and etching processes. The opening is then filled with conductive material to form the second bonding pad 123. The upper surface of the second bonding pad 123 is substantially flush with the upper surface of the dielectric layer, thereby forming a flat bonding interface, providing a basis for subsequent alignment and bonding with the first device layer.

[0076] After the formation of the second bonding pad 123 is completed, the surface of the dielectric layer can be further surface-treated, for example, by plasma treatment or chemical cleaning to remove surface contaminants and oxide layers, in order to enhance the interfacial bonding strength in subsequent bonding processes. At the same time, stress buffer structures or microstructures can be introduced into the dielectric layer to alleviate interfacial warping or cracking problems caused by differences in thermal expansion coefficients or mechanical stress, thereby improving the reliability and stability of the bonding structure.

[0077] After independently forming the first device layer 110 and the second device layer 120, the first device layer 110 and the second device layer 120 are stacked in a face-to-face alignment manner, and uniform pressure is applied at room temperature to achieve direct metal-to-metal bonding between the first bonding pad 113 and the second bonding pad 123. Simultaneously, the dielectric surfaces surrounding the bonding pads achieve dielectric-to-dielectric bonding through plasma activation, thereby forming a hybrid bonding structure with both electrical conductivity and mechanical connection within the same interface. After forming the hybrid bonding structure, the substrate 121 can be peeled off from the oxide semiconductor layer 122, retaining only the portion of the oxide semiconductor layer 122 as the final formed second device layer 120.

[0078] Optionally, after hybrid bonding is completed, a stress compensation layer is deposited on the top surface of the second device layer 120 away from the bonding interface to balance the local stress introduced by the difference in thermal expansion coefficients between the copper-copper bonding region and the surrounding dielectric. Subsequently, a laser drill is used to penetrate the stress compensation layer and the second device layer 120 to expose the corresponding interconnect pads in the first device layer 110. A barrier layer, a seed layer, and a metal filler are formed sequentially in the hole to prepare a vertical conduction pillar. This conduction pillar is connected in parallel with the metal bonding region in the hybrid bonding structure to provide a bidirectional low-resistance channel for the low-voltage CMOS logic control circuit and the high-voltage oxide semiconductor transistor. This allows the display driver device to simultaneously realize the vertical stacking transmission of high-speed logic signals and high-voltage drive signals when driving a high-resolution panel, without the need for additional leads or bumps, significantly reducing the package size and parasitic inductance.

[0079] In this embodiment, the first device layer 110 and the second device layer 120 are formed independently, so the first device layer 110 and the second device layer 120 can form a thermally budget-compatible heterogeneous stacked structure.

[0080] In one embodiment, a write transistor and a drive transistor are integrated simultaneously in the second device layer 120. The gate of the drive transistor is connected to the source or drain of the write transistor, and the connection node between the write transistor and the drive transistor has a parasitic capacitance. The write transistor receives a data voltage and is controlled by a scan signal, while the drive transistor provides a drive signal based on the data voltage. During the data writing phase, the scan signal controls the write transistor to turn on and stores the data voltage in the parasitic capacitance; during the light emission phase, the drive transistor provides a drive signal based on the data voltage on the parasitic capacitance. In this embodiment, the write transistor and the drive transistor are indium gallium zinc oxide thin-film transistors (IGZO TFTs).

[0081] In another embodiment, a write transistor is integrated in the second device layer 120, and a drive transistor is integrated in the first device layer 110. The gate of the drive transistor is connected to the source or drain of the write transistor via a back-end interconnect layer 112. The write transistor receives a data voltage and is controlled by a scan signal, while the drive transistor provides a drive signal based on the data voltage. During the data writing phase, the scan signal controls the write transistor to turn on and stores the data voltage in a parasitic capacitance; during the light emission phase, the drive transistor provides a drive signal based on the data voltage on the parasitic capacitance. In this embodiment, the write transistor is an indium gallium zinc oxide thin-film transistor (IGZO TFT), and the drive transistor is a silicon-based transistor.

[0082] In the above embodiments, the parasitic capacitance includes the gate parasitic capacitance of the driving transistor, or the parasitic capacitance includes the gate parasitic capacitance of the driving transistor and the wiring parasitic capacitance between the writing transistor and the driving transistor.

[0083] Figure 3 A cross-sectional view of a display driver device according to a third embodiment of the present invention is shown. In this embodiment, a flip-chip process is used to interconnect the first device layer 110 and the second device layer 120. Specifically, the first device layer 110 includes a single-crystal silicon substrate 111 and a back-end interconnect layer 112. A low-voltage CMOS logic control circuit is formed on the surface of the single-crystal silicon substrate 111, and an array of interconnect pads 114 are arranged on the top of the back-end interconnect layer 112. The second device layer 120 includes an oxide semiconductor layer 122 formed on a substrate 121. A high-voltage oxide semiconductor transistor is integrated in the oxide semiconductor layer 122, and metal microbumps 124 are arranged on its surface corresponding to the interconnect pads 114.

[0084] In this embodiment, the first device layer 110 and the second device layer 120 are formed independently, so the first device layer 110 and the second device layer 120 can form a thermally budget-compatible heterogeneous stacked structure. Specific processes for forming the first device layer 110 and the second device layer 120 can be found in [reference needed]. Figure 2 The relevant description of the second embodiment shown will not be repeated here.

[0085] After the first device layer 110 and the second device layer 120 are formed independently, a flip-chip process is used to interconnect the first device layer 110 and the second device layer 120. Specifically, metal microbumps 124 are formed on the surface of the second device layer 120. The metal microbumps 124 are formed, for example, by sputtering a titanium-copper adhesion layer, electroplating copper pillars, and covering them with a nickel-palladium-gold anti-oxidation layer. Subsequently, the interconnect pads 114 and the metal microbumps 124 are plasma cleaned to remove surface oxide films and organic residues. Then, the second device layer 120 is flipped and aligned so that the interconnect pads 114 correspond one-to-one with the metal microbumps 124. Uniform pressure is applied and heated in an inert atmosphere to form an intermetallic compound between the interconnect pads 114 and the metal microbumps 124, thereby completing electrical conduction and mechanical fixation. At the same time, underfill is filled into the gaps between the bumps. After curing, a sealing layer is formed to buffer stress and prevent moisture intrusion, ensuring that the flip-chip structure maintains low contact resistance and high reliability during subsequent thermal cycling.

[0086] In one embodiment, a write transistor and a drive transistor are integrated simultaneously in the second device layer 120. The gate of the drive transistor is connected to the source or drain of the write transistor, and the connection node between the write transistor and the drive transistor has a parasitic capacitance. The write transistor receives a data voltage and is controlled by a scan signal, while the drive transistor provides a drive signal based on the data voltage. During the data writing phase, the scan signal controls the write transistor to turn on and stores the data voltage in the parasitic capacitance; during the light emission phase, the drive transistor provides a drive signal based on the data voltage on the parasitic capacitance. In this embodiment, the write transistor and the drive transistor are indium gallium zinc oxide thin-film transistors (IGZO TFTs).

[0087] In another embodiment, a write transistor is integrated in the second device layer 120, and a drive transistor is integrated in the first device layer 110. The gate of the drive transistor is connected to the source or drain of the write transistor via a back-end interconnect layer 112. The write transistor receives a data voltage and is controlled by a scan signal, while the drive transistor provides a drive signal based on the data voltage. During the data writing phase, the scan signal controls the write transistor to turn on and stores the data voltage in a parasitic capacitance; during the light emission phase, the drive transistor provides a drive signal based on the data voltage on the parasitic capacitance. In this embodiment, the write transistor is an indium gallium zinc oxide thin-film transistor (IGZO TFT), and the drive transistor is a silicon-based transistor.

[0088] In the above embodiments, the parasitic capacitance includes the gate parasitic capacitance of the driving transistor, or the parasitic capacitance includes the gate parasitic capacitance of the driving transistor and the wiring parasitic capacitance between the writing transistor and the driving transistor.

[0089] Furthermore, in this embodiment, the through-silicon via (TSV) interconnect layer can completely replace the array of interconnect pads 114 and metal microbumps 124. Alternatively, while retaining the local interconnection of microbumps, blind vias with an aspect ratio greater than 10:1 can be etched in the single-crystal silicon substrate 111 of the first device layer 110. After sidewall insulation, barrier layer deposition, and copper plating, through-silicon vias (TSVs) are formed through the silicon substrate. A redistribution layer is then fabricated on the top of the TSV, so that the oxide semiconductor layer 122 of the second device layer 120 is directly connected to the low-voltage CMOS of the first device layer 110 through a short vertical path. This shortens the critical signal path that originally had to go around the back-end interconnect layer 112 by more than half, significantly reducing the RC delay of the high-speed scan clock and data bus, and suppressing the current congestion effect that occurs in the microbump array at high frequencies.

[0090] Furthermore, the present invention proposes, such as Figure 1-3The display driver devices shown are not limited to driving inorganic micro-light-emitting diodes. In the micro-organic light-emitting diode on silicon (OLEDoS) scheme, the IGZO film can be directly deposited on the silicon substrate with the logic circuit already completed. The anode metal layer is then covered on the IGZO drain region to form a top-emitting microcavity structure, which is suitable for ultra-high resolution near-eye displays for virtual reality or augmented reality glasses. In the liquid crystal on silicon (LCoS) light valve, the IGZO transistor utilizes its breakdown voltage of over 10V and low leakage current characteristics to provide a liquid crystal torsion voltage of over 5V on the top layer, while the bottom CMOS only needs to implement low-voltage logic. This avoids the thick oxide and deep well implantation required by high-voltage processes, significantly reducing silicon wafer costs and process complexity.

[0091] Figure 4 A schematic diagram of a pixel circuit according to an embodiment of the present invention is shown. Figure 4 The pixel circuit will be described in detail using a current-driven OLED pixel circuit as an example. It should be understood that the display driving device of the present invention can also be applied to other types of pixel circuits, such as voltage-driven OLED pixel circuits, LED pixel circuits, and LCD pixel circuits.

[0092] like Figure 4 As shown, Figure 4 As shown, the pixel circuit 400 includes a driving transistor T_DRIVE, a writing transistor T_WRITE, a parasitic capacitance Cp, and a light-emitting element OLED. The drain of the driving transistor T_DRIVE is connected to the first power line ELVDD, the source is coupled to the anode of the OLED via node N1, and the gate is connected to node N2 along with the first end of the parasitic capacitance Cp. The gate of the writing transistor T_WRITE is controlled by the scan signal Scan. Its source receives the data voltage Vdata, and its drain is connected to node N2, thereby writing the data voltage Vdata into the parasitic capacitance Cp during the active period of the scan signal Scan. The parasitic capacitance Cp is used to maintain the gate-source voltage Vgs of the driving transistor T_DRIVE during the light-emitting phase, so that the driving transistor T_DRIVE generates a driving current corresponding to the data voltage Vdata and flows through the light-emitting element OLED to achieve grayscale light emission. The cathode of the light-emitting element OLED is connected to the second power line ELVSS, forming a current loop.

[0093] During the writing phase, the scan signal Scan goes high, turning on the write transistor T_WRITE. The data voltage Vdata charges the parasitic capacitance Cp through the write transistor T_WRITE, setting the potential of node N2 to the data voltage Vdata, while the potential of node N1 remains temporarily at the potential of the previous frame. Subsequently, the scan signal Scan goes low, turning off the write transistor T_WRITE, and the voltage Vgs = Vdata - VN1 across the parasitic capacitance Cp is maintained. After entering the light-emitting phase, the driving transistor T_DRIVE operates in the saturation region, and its output current Ioled is approximately proportional to the square of Vgs. Thus, the OLED light-emitting element continuously emits light with a brightness corresponding to the data voltage Vdata until the next frame's writing phase updates the data voltage Vdata again.

[0094] In this embodiment of the invention, since the active region of the write transistor T_Write is an indium gallium zinc oxide semiconductor, its subthreshold swing is steep and its off-state current density can be as low as 10⁻¹. 5 On the order of A·μm⁻¹, it can almost be considered an ideal switch. Therefore, the distributed charge storage node formed by the gate-source, gate-drain parasitic capacitances, and inter-line coupling capacitances of the driving transistor T_Drive is sufficient to maintain a stable gate voltage throughout the entire frame cycle, eliminating the need for any planar or trench-type physical capacitors. By eliminating this capacitor, the pixel aperture ratio is no longer obstructed by the metal plates of the storage capacitor, and the lateral size of the pixel unit can be reduced to the theoretical limit defined only by the transistor channel length, contact hole spacing, and minimum linewidth. This significantly reduces the panel area at the same resolution or achieves a higher pixel density within the same area.

[0095] When the leakage current of a silicon-based transistor is approximately 10 -9 The leakage current is on the order of A, while that of IGZO devices is only 10. -15 At the A-level, even if the total storage capacitance C is reduced by three orders of magnitude due to the elimination of physical capacitors, the equivalent voltage drift is still three orders of magnitude smaller than that of the traditional scheme. Thus, grayscale accuracy can still be maintained for one frame or even longer holding time, meeting the display specifications' requirements for brightness stability.

[0096] Figure 5 A flowchart illustrating a method for manufacturing a display driver device according to an embodiment of the present invention is shown.

[0097] In step S501, a first device layer is formed, which integrates a logic control circuit based on a single crystal silicon.

[0098] In step S502, a second device layer is formed, stacked on top of the first device layer. The second device layer integrates an oxide semiconductor transistor (OST). The display driver is configured to store a data voltage using parasitic capacitance located at the connection node of the OST, where no separate physical capacitor is provided. For example, the OST includes a write transistor for writing the data voltage, whose off-state leakage current is close to zero, so that the data voltage is held within the parasitic capacitance. Optionally, the write transistor is an OST thin-film transistor.

[0099] In step S503, the first device layer and the second device layer are electrically connected. Optionally, the first device layer and the second device layer are vertically interconnected by any one of in-situ growth, hybrid bonding, metal microbump bonding, and back-end via interconnection.

[0100] For example, the second device layer is deposited in situ directly on the back-end interconnect layer of the first device layer, and the top metal layer of the back-end interconnect layer serves as a conductive connection structure to realize the electrical connection between the first device layer and the second device layer.

[0101] For example, a hybrid bonding process can be used to achieve the electrical connection between the first device layer and the second device layer. The second device layer and the first device layer are bonded face-to-face through Cu-Cu hybrid bonding, and the second device layer and the first device layer are manufactured independently on different wafers and then bonded together.

[0102] For example, a flip-chip process can be used to achieve the electrical connection between the first device layer and the second device layer. The second device layer and the first device layer are interconnected by flip-chip stacking through metal microbumps and / or through-silicon via interconnect layers, and the second device layer and the first device layer are independently manufactured on different wafers and then bonded.

[0103] In one embodiment, forming the second device layer includes: forming an oxide semiconductor transistor, the oxide semiconductor transistor including a write transistor and a drive transistor; and connecting the gate of the drive transistor to the source or drain of the write transistor, wherein the connection node between the write transistor and the drive transistor has a parasitic capacitance, the write transistor is used to receive a data voltage and is controlled by a scan signal, the drive transistor is used to provide a drive signal according to the data voltage, the parasitic capacitance is used to store the data voltage, and the parasitic capacitance maintains the gate voltage of the drive transistor during a display frame period. Optionally, the write transistor and the drive transistor are indium gallium zinc oxide thin film transistors (IGZO TFTs).

[0104] In another embodiment, forming the first device layer includes: forming a logic control circuit based on monocrystalline silicon, forming a driving transistor based on monocrystalline silicon, and forming the second device layer includes: forming an oxide semiconductor transistor, the oxide semiconductor transistor including a write transistor, connecting the gate of the driving transistor to the source or drain of the write transistor, wherein the transistor breakdown voltage of the second device layer is higher than that of the transistor in the first device layer, the connection node between the write transistor and the driving transistor has a parasitic capacitance, the write transistor is used to receive a data voltage and is controlled by a scan signal, the driving transistor is used to provide a drive signal according to the data voltage, the parasitic capacitance is used to store the data voltage, and the parasitic capacitance maintains the gate voltage of the driving transistor during the display frame period. Optionally, the write transistor is an indium gallium zinc oxide thin film transistor (IGZO TFT), and the driving transistor is a silicon-based transistor.

[0105] In summary, this invention proposes a heterogeneous integration scheme of silicon-based CMOS and oxide semiconductor, which takes into account the complementary advantages of both in terms of speed, voltage withstand capability, and leakage current. By vertically stacking, the single-crystal silicon-based logic control circuit and oxide semiconductor transistor are physically separated, and electrical connection is achieved through conductive interconnect structures. This allows high-speed, low-voltage computing functions and high-voltage, low-leakage retention functions to work collaboratively within the same chip, thereby overcoming the inherent limitations of single-wafer systems in terms of thermal budget and process compatibility. In an optional embodiment, the first device layer integrates low-voltage CMOS devices, undertaking tasks such as data decoding, timing generation, high-speed interface, and pulse width modulation; the second device layer integrates high-voltage oxide semiconductor transistors, undertaking pixel switching, driving, and charge retention tasks. The two layers can be vertically integrated after being independently completed within their respective optimal temperature windows, avoiding performance degradation caused by mutual compromise.

[0106] Furthermore, at the pixel circuit level, this invention utilizes the characteristic that the off-state leakage current of oxide thin-film transistors is six orders of magnitude lower than that of silicon devices. It replaces traditional physical storage capacitors with gate parasitic capacitance and wiring parasitic capacitance, forming a 2TOC topology containing only two transistors and no independent capacitors. This reduces the pixel area to the physical limit determined by the transistor size and interconnect width, while maintaining voltage stability within one frame cycle. It completely eliminates the constraints of large-size storage capacitors on aperture ratio and pixel density, and can provide driving signals for light-emitting or dimming mechanisms such as Micro-LED, Micro-OLED, and LCoS.

[0107] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0108] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A display driving device, comprising: The first device layer integrates a control circuit based on single-crystal silicon. The second device layer integrates oxide semiconductor transistors, and the second device layer is stacked on top of the first device layer. as well as A conductive interconnect structure electrically connects the first device layer and the second device layer. The display driving device is configured to store data voltage using parasitic capacitance, which is located at the connection node of the oxide semiconductor transistor, and no independent physical capacitor is provided at the connection node. The oxide semiconductor transistor includes a write transistor, the first device layer includes a drive transistor, the gate of the drive transistor is connected to the source or drain of the write transistor through the conductive interconnect structure, and the connection node between the write transistor and the drive transistor has the parasitic capacitance to maintain the gate voltage of the drive transistor during the display frame cycle.

2. The display driving device according to claim 1, wherein, The driving transistor is a silicon-based transistor. The write transistor receives the data voltage and is controlled by the scan signal. The driving transistor provides a drive signal according to the data voltage. During the data writing phase, the scan signal controls the writing transistor to turn on, and stores the data voltage in the parasitic capacitance. During the light-emitting phase, the driving transistor provides a driving signal based on the data voltage across the parasitic capacitance. The transistors in the second device layer have a higher withstand voltage than those in the first device layer, and the parasitic capacitance maintains the gate voltage of the driving transistor during the display frame period.

3. The display driving device according to claim 2, wherein, The parasitic capacitance includes the gate parasitic capacitance of the driving transistor, or the parasitic capacitance includes the gate parasitic capacitance of the driving transistor and the wiring parasitic capacitance between the writing transistor and the driving transistor.

4. The display driving device according to claim 1, wherein, The conductive interconnect structure is any one of the following: a top metal layer located on top of the first device layer, a hybrid bonding structure located between the first device layer and the second device layer, a metal microbump, and a through-silicon via interconnect layer. The hybrid bonding includes metal-metal bonding and dielectric-dielectric bonding.

5. A method for manufacturing a display driving device, comprising: A first device layer is formed, wherein the first device layer integrates a logic control circuit based on a single crystal silicon. A second device layer is formed stacked on top of the first device layer, and the second device layer integrates oxide semiconductor transistors; as well as The first device layer and the second device layer are electrically connected using a conductive interconnect structure. The display driving device is configured to store data voltage using parasitic capacitance, which is located at the connection node of the oxide semiconductor transistor, and no independent physical capacitor is provided at the connection node. The oxide semiconductor transistor includes a write transistor, the first device layer includes a drive transistor, the gate of the drive transistor is connected to the source or drain of the write transistor through the conductive interconnect structure, and the connection node between the write transistor and the drive transistor has the parasitic capacitance to maintain the gate voltage of the drive transistor during the display frame cycle.

6. The manufacturing method according to claim 5, wherein, The first device layer and the second device layer are vertically interconnected by any one of the following methods: in-situ growth, hybrid bonding, metal microbump bonding, and back-end via interconnection. The hybrid bonding includes metal-metal bonding and dielectric-dielectric bonding.

7. The manufacturing method according to claim 6, wherein, The second device layer is formed by in-situ deposition directly on the back-end interconnect layer of the first device layer.

8. The manufacturing method according to claim 6, wherein, The second device layer and the first device layer are bonded face-to-face through metal-metal bonding and dielectric-dielectric bonding, and the second device layer and the first device layer are bonded after being independently manufactured on different wafers.

9. The manufacturing method according to claim 6, wherein, The second device layer and the first device layer are interconnected by flip-chip stacking through metal microbumps and / or through-silicon via interconnect layers, and the second device layer and the first device layer are bonded after being independently manufactured on different wafers.

10. The manufacturing method according to claim 5, wherein, Forming the first device layer includes: forming a logic control circuit based on monocrystalline silicon, and forming the driving transistor based on monocrystalline silicon. The transistor in the second device layer has a higher voltage rating than the transistor in the first device layer. The write transistor is used to receive the data voltage and is controlled by the scan signal. The drive transistor is used to provide a drive signal according to the data voltage. The parasitic capacitance is used to store the data voltage.

11. A display panel comprising a plurality of pixel circuits, the pixel circuits comprising: The display driver device as described in any one of claims 1 to 4, or the display driver device manufactured by the manufacturing method as described in any one of claims 5 to 10; as well as The light-emitting element is controlled by the display driver.

12. The display panel according to claim 11, wherein, The light-emitting element is one of a micro light-emitting diode, a micro organic light-emitting diode, or a silicon-based liquid crystal unit.

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