Event synchronization method and system, programmable control interface device, and medium

Abstract

This disclosure relates to an event synchronization method and system, a programmable control interface device, and a medium. An event synchronization method is provided, comprising: receiving configuration instructions from a CPU unit by an interface control module of a programmable control interface device, and storing configuration parameters in the configuration instructions to a configuration storage module of the programmable control interface device; receiving event signals sent in real time by multiple asynchronous acceleration units during operation by an event synchronization module of the programmable control interface device, and extracting event information from the event signals; generating an event synchronization control signal by the interface control module based on synchronization rules stored in the configuration storage module, configuration information and processing priorities of the multiple asynchronous acceleration units, and the event information extracted by the event synchronization module; and sending a trigger signal to a target asynchronous acceleration unit according to the event synchronization control signal to trigger the target asynchronous acceleration unit to perform a corresponding operation.

Description

Technical Field

[0001] This disclosure relates to the field of asynchronous acceleration unit synchronization technology, and more specifically, to event synchronization methods and systems, programmable control interface devices, and media. Background Technology

[0002] With the rapid development of artificial intelligence training and inference, high-performance computing, many-core processors, and distributed systems, computing tasks are generally executed collaboratively by multiple computing units in an asynchronous parallel manner. Currently, the mainstream synchronization mechanisms between asynchronous acceleration units fall into two categories: one is coarse-grained global barrier synchronization, which requires waiting for all computing units to complete before proceeding, easily leading to fast computing units idling and slow computing units trailing, with synchronization overhead potentially accounting for more than 30% of the total execution time; the other is pure asynchronous lock-free synchronization, which, while reducing waiting overhead, is prone to data races, state inconsistencies, and write conflicts, and lacks unified dependency management and exception recovery capabilities. Existing solutions generally suffer from common defects such as strong coupling between synchronization and computation, uncontrollable communication overhead, poor heterogeneous adaptability, insufficient robustness, and limited scalability, making it difficult to simultaneously meet the requirements of low latency, high throughput, strong consistency, and high reliability in asynchronous parallel collaboration.

[0003] Therefore, a new event synchronization method and system are needed. Summary of the Invention

[0004] Embodiments of this application provide an event synchronization method and system, a programmable control interface device, and a medium that do not require CPU polling intervention, significantly reducing CPU load and synchronization latency, and support configurable synchronization rules and data scheduling strategies, thereby improving the collaborative efficiency, flexibility, and robustness of asynchronous acceleration units.

[0005] According to a first aspect of this disclosure, an event synchronization method is provided for event synchronization between a CPU unit and multiple asynchronous acceleration units. The method includes: receiving a configuration instruction from the CPU unit by an interface control module of a programmable control interface device, and storing configuration parameters in the configuration instruction to a configuration storage module of the programmable control interface device, wherein the configuration parameters include synchronization rules, data scheduling strategies, and configuration information and processing priorities of the multiple asynchronous acceleration units; receiving event signals sent in real time by the multiple asynchronous acceleration units during operation by an event synchronization module of the programmable control interface device, and extracting event information from the event signals, wherein the event information includes event type, trigger time, identifier of the target asynchronous acceleration unit, and associated data; and the interface control module performing the synchronization according to the configuration instructions. The synchronization rules stored in the storage module, the configuration information and processing priorities of the multiple asynchronous acceleration units, and the event information extracted by the event synchronization module generate an event synchronization control signal. The event synchronization module then sends a trigger signal to the target asynchronous acceleration unit based on the event synchronization control signal, triggering the target asynchronous acceleration unit to perform a corresponding operation. The data scheduling module of the programmable control interface device schedules the flow of associated data between the multiple asynchronous acceleration units, or between the multiple asynchronous acceleration units and the CPU unit, based on the data scheduling strategy stored in the configuration storage module and the event information extracted by the event synchronization module.

[0006] In some embodiments, the data scheduling module includes a data routing unit and a caching unit. The data routing unit is configured to allocate a data transmission path based on the type of the associated data and the processing priority and working status of the target asynchronous acceleration unit. The caching unit is configured to cache the associated data. The data scheduling module supports data fragmentation transmission mode and batch transmission mode.

[0007] In some embodiments, the programmable control interface device further includes a communication interface module, through which the programmable control interface device communicates with the CPU unit and the plurality of asynchronous acceleration units.

[0008] In some embodiments, the event synchronization module includes an event trigger and a synchronization timer. The event trigger is configured to receive the event signal from the plurality of asynchronous acceleration units and send the trigger signal to the target asynchronous acceleration unit. The synchronization timer is configured to start timing after the event trigger sends the trigger signal, and if no expected feedback is received from the target asynchronous acceleration unit within a preset timing threshold, generate a synchronization timeout signal and send it to the interface control module.

[0009] In some embodiments, the event synchronization method further includes: the interface control module monitoring the working status of the event synchronization module, the data scheduling module, and the plurality of asynchronous acceleration units in real time; and when an abnormal event occurs in the working status of the event synchronization module, the data scheduling module, or the plurality of asynchronous acceleration units, the interface control module sending an alarm signal to the CPU unit and initiating an abnormal handling process according to a preset abnormal handling strategy. The abnormal event includes at least one of the following: data transmission failure, asynchronous acceleration unit failure, and synchronization timeout.

[0010] In some embodiments, the event synchronization method further includes: the interface control module reporting the working status of the event synchronization module, the data scheduling module, and the plurality of asynchronous acceleration units to the CPU unit; the interface control module receiving a configuration adjustment instruction sent from the CPU unit based on the working status of the event synchronization module, the data scheduling module, and the plurality of asynchronous acceleration units; and the interface control module updating one or more of the synchronization rules, the data scheduling strategy, and the configuration information and processing priorities of the plurality of asynchronous acceleration units in the configuration storage module based on the configuration adjustment instruction.

[0011] According to a second aspect of this disclosure, a programmable control interface device is provided for event synchronization between a CPU unit and multiple asynchronous acceleration units. The programmable control interface device includes an interface control module, an event synchronization module, a data scheduling module, and a configuration storage module. The interface control module is configured to receive configuration instructions from the CPU unit and store configuration parameters from the configuration instructions in the configuration storage module. The configuration parameters include synchronization rules, data scheduling strategies, and configuration information and processing priorities of the multiple asynchronous acceleration units. The event synchronization module is configured to receive event signals sent in real-time by the multiple asynchronous acceleration units during operation and extract event information from the event signals. The event information includes event type, trigger time, identifier of the target asynchronous acceleration unit, and associated data. The interface control module is further configured to, based on the configuration information stored in the configuration storage module... The synchronization module generates an event synchronization control signal based on the synchronization rules, configuration information and processing priorities of the multiple asynchronous acceleration units, and the event information extracted by the event synchronization module. The event synchronization module is further configured to send a trigger signal to the target asynchronous acceleration unit according to the event synchronization control signal to trigger the target asynchronous acceleration unit to perform a corresponding operation. The data scheduling module is configured to schedule the flow of the associated data between the multiple asynchronous acceleration units or between the multiple asynchronous acceleration units and the CPU unit according to the data scheduling strategy stored in the configuration storage module and the event information extracted by the event synchronization module.

[0012] In some embodiments, the data scheduling module includes a data routing unit and a caching unit. The data routing unit is configured to allocate a data transmission path based on the type of the associated data and the processing priority and working status of the target asynchronous acceleration unit. The caching unit is configured to cache the associated data. The data scheduling module supports data fragmentation transmission mode and batch transmission mode.

[0013] In some embodiments, the programmable control interface device further includes a communication interface module, through which the programmable control interface device communicates with the CPU unit and the plurality of asynchronous acceleration units.

[0014] In some embodiments, the event synchronization module includes an event trigger and a synchronization timer. The event trigger is configured to receive the event signal from the plurality of asynchronous acceleration units and send the trigger signal to the target asynchronous acceleration unit. The synchronization timer is configured to start timing after the event trigger sends the trigger signal, and if no expected feedback is received from the target asynchronous acceleration unit within a preset timing threshold, generate a synchronization timeout signal and send it to the interface control module.

[0015] In some embodiments, the interface control module is further configured to monitor the working status of the event synchronization module, the data scheduling module, and the plurality of asynchronous acceleration units in real time; and the interface control module is further configured to send an alarm signal to the CPU unit when an abnormal event occurs in the working status of the event synchronization module, the data scheduling module, or the plurality of asynchronous acceleration units, and to initiate an abnormal handling process according to a preset abnormal handling strategy. The abnormal event includes at least one of the following: data transmission failure, asynchronous acceleration unit failure, and synchronization timeout.

[0016] In some embodiments, the interface control module is further configured to report the working status of the event synchronization module, the data scheduling module, and the plurality of asynchronous acceleration units to the CPU unit; the interface control module is further configured to receive a configuration adjustment instruction sent from the CPU unit based on the working status of the event synchronization module, the data scheduling module, and the plurality of asynchronous acceleration units; and the interface control module is further configured to update one or more of the synchronization rules, the data scheduling strategy, and the configuration information and processing priorities of the plurality of asynchronous acceleration units in the configuration storage module based on the configuration adjustment instruction.

[0017] According to a third aspect of this disclosure, an event synchronization system is provided for event synchronization between a CPU unit and a plurality of asynchronous acceleration units, the event synchronization system including any of the programmable control interface devices described above.

[0018] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided storing instructions that, when executed by a processor, cause the processor to perform any of the above-described event synchronization methods.

[0019] According to the event synchronization method and system, programmable control interface device, and medium provided in the embodiments of this application, event synchronization and data scheduling between the CPU unit and multiple asynchronous acceleration units are realized by setting a programmable control interface device between the CPU unit and multiple asynchronous acceleration units. This scheme offloads the synchronization logic from the CPU to the programmable control interface device, directly triggering the target computing unit in an event-driven manner without CPU polling intervention, significantly reducing CPU load and synchronization latency. Simultaneously, through the configuration storage module in the programmable control interface device, users can flexibly modify synchronization rules and data scheduling strategies to adapt to different application scenarios and heterogeneous hardware without modifying the hardware structure. Furthermore, the synchronization timer and exception handling mechanism enhance the robustness and fault tolerance of the system. Therefore, this disclosure effectively solves the problems of low synchronization efficiency, high CPU load, poor flexibility, and insufficient robustness in the prior art, and can be widely applied in fields such as artificial intelligence training and inference, high-performance computing, and embedded systems. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of a programmable control interface device according to an embodiment of this application.

[0022] Figure 2 This is a flowchart of an event synchronization method according to an embodiment of this application. Detailed Implementation

[0023] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0024] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0025] The features and exemplary embodiments of various aspects of this application will now be described in detail. Furthermore, the features, structures, or characteristics described below may be combined in any suitable manner in one or more embodiments.

[0026] In the field of parallel computing tasks performed collaboratively by a CPU unit and multiple asynchronous acceleration units (e.g., graphics processing unit (GPU), digital signal processing unit (DSP), application-specific integrated circuit (ASIC), etc.), existing technical solutions suffer from defects such as strong coupling between synchronization and computation, uncontrollable communication overhead, poor heterogeneous adaptability, insufficient robustness, and limited scalability.

[0027] For example, the mainstream synchronization mechanisms between asynchronous acceleration units can be divided into two categories: one is coarse-grained global barrier synchronization, which requires waiting for all computing units to complete before proceeding, easily leading to fast computing units idling and slow computing units trailing, with synchronization overhead potentially accounting for more than 30% of the total execution time; the other is pure asynchronous lock-free synchronization, which, while reducing waiting overhead, is prone to data races, state inconsistencies, and write conflicts, and lacks unified dependency management and exception recovery capabilities. These limitations result in technical consequences such as high synchronization overhead, high CPU load, low system efficiency, and difficulty in guaranteeing reliability.

[0028] To address the aforementioned issues, embodiments of this application provide an event synchronization method and system, a programmable control interface device, and a medium that eliminate the need for CPU polling intervention, significantly reducing CPU load and synchronization latency. Furthermore, it supports dynamically configurable synchronization rules and data scheduling strategies, thereby improving the collaborative efficiency, flexibility, and robustness of the asynchronous acceleration unit.

[0029] Figure 1 This is a schematic diagram of the structure of a programmable control interface device according to an embodiment of this application. Figure 1As shown, the programmable control interface device 100 according to an embodiment of this application includes an interface control module 110, an event synchronization module 120, a data scheduling module 130, a configuration storage module 140, and a communication interface module 150. Figure 2 This is a flowchart of an event synchronization method according to an embodiment of this application. Figure 2 As shown, the event synchronization method according to an embodiment of this application includes the following steps S210 to S250: S210: The interface control module 110 receives the configuration instruction from the CPU unit and stores the configuration parameters in the configuration instruction to the configuration storage module 140. The configuration parameters include synchronization rules, data scheduling strategies, and configuration information and processing priorities of multiple asynchronous acceleration units. S220: The event synchronization module 120 receives event signals sent in real time by multiple asynchronous acceleration units during operation, and extracts event information from the event signals. The event information includes event type, trigger time, identifier of target asynchronous acceleration unit, and associated data. S230: The interface control module 110 generates an event synchronization control signal based on the synchronization rules stored in the configuration storage module 140, the configuration information and processing priority of multiple asynchronous acceleration units, and the event information extracted by the event synchronization module 120. S240: The event synchronization module 120 sends a trigger signal to the target asynchronous acceleration unit based on the event synchronization control signal, thereby triggering the target asynchronous acceleration unit to perform corresponding operations; and S250: The data scheduling module 130 schedules the flow of related data between multiple asynchronous acceleration units or between multiple asynchronous acceleration units and the CPU unit according to the data scheduling strategy stored in the configuration storage module 140 and the event information extracted by the event synchronization module 120.

[0030] The following is combined Figure 1 and Figure 2 The structure and working principle of the programmable control interface device 100, as well as the process of the event synchronization method, are described in detail.

[0031] In one embodiment, the CPU unit can manage multiple asynchronous acceleration units through the programmable control interface device 100. For example, the asynchronous acceleration units may include graphics processing units (GPUs), digital signal processing units (DSPs), and application-specific integrated circuits (ASICs), etc. Each of these asynchronous acceleration units has multiple states such as idle, ready, running, waiting, and completed, and they complete state transitions and task execution under the coordination of the programmable control interface device 100.

[0032] In one embodiment, the interface control module 110 can communicate bidirectionally with the CPU unit, receive instructions sent by the CPU, parse the instruction content and generate corresponding control signals, and send them to the event synchronization module 120, the data scheduling module 130 and the configuration storage module 140; at the same time, it collects the working status information of the event synchronization module 120 and the data scheduling module 130 and feeds it back to the CPU unit, so as to realize the real-time control of the programmable control interface device 100 by the CPU.

[0033] In one embodiment, the interface control module 110 may include an instruction parser that supports multiple instruction formats and can expand the instruction set according to user needs, thereby achieving programmable control. For example, the interface control module 110 may be implemented using an FPGA (Field Programmable Gate Array) chip, which has a built-in instruction parser that supports custom instruction sets and can parse configuration instructions, control instructions, and query instructions sent by the CPU unit to generate corresponding control signals; at the same time, it collects the working status of the event synchronization module 120 and the data scheduling module 130 and feeds it back to the CPU unit through the PCIe interface of the communication interface module 150.

[0034] In one embodiment, the programmable control interface device 100 communicates with the CPU unit and multiple asynchronous acceleration units using the communication interface module 150. In one embodiment, the communication interface module 150 may integrate one or more of the following standard communication interfaces: PCIe interface, AXI interface, and UART interface, etc., and this application does not limit this.

[0035] For example, the communication interface module 150 can provide multiple standard communication interfaces to support the access of asynchronous acceleration units of different types and specifications. In some embodiments, the communication interface module 150 can integrate three standard interfaces: PCIe 4.0, AXI 4.0, and UART. The PCIe 4.0 interface is used for communication with the CPU unit, the AXI 4.0 interface is used for communication with multiple asynchronous acceleration units, and the UART interface is used for debugging and maintenance. In other embodiments, the communication interface module 150 can integrate only the AXI 4.0 and UART interfaces to adapt to resource-constrained scenarios such as embedded systems.

[0036] In one embodiment, the interface control module 110 can be configured to receive configuration instructions from the CPU unit and store the configuration parameters in the configuration instructions to the configuration storage module 140. The configuration parameters include synchronization rules, data scheduling strategies, and configuration information and processing priorities of multiple asynchronous acceleration units.

[0037] In one embodiment, the synchronization rule could be, for example, "the GPU triggers the DSP to start feature extraction after completing preprocessing, and the DSP triggers the ASIC for recognition after completion"; the data scheduling strategy could be, for example, "prioritizing the use of the AXI interface for transmission, setting the data cache timeout threshold to 100ms, and supporting batch transmission mode"; and the configuration information and processing priority of multiple asynchronous acceleration units could be, for example, the GPU being identified as "GPU_01", with an interface specification of PCIe 4.0 x16 (theoretical bandwidth 32GB / s), a peak computing power of 10 TFLOPS (FP16), a local storage capacity of 16GB HBM2, a data transfer rate of 32GB / s (read) and 28GB / s (write), and a priority weight of 0.7; and the DSP being identified as "DSP_01", with an interface specification of AXI 4.0 128-bit @500MHz (theoretical bandwidth 8GB / s), a peak computing power of 2 GFLOPS (fixed-point), and a local storage capacity of 1MB. The configuration features include SRAM, a data transfer rate of 6.4 GB / s, a priority weight of 0.2, and an ASIC identifier of "ASIC_01". The interface specification is AXI 4.064-bit @400MHz (theoretical bandwidth 3.2 GB / s), with a peak computing power of 5 TOPS (INT8). Local storage capacity is 8 MB SRAM, with a data transfer rate of 3.0 GB / s and a priority weight of 0.1. These detailed configuration parameters can be pre-written into the configuration storage module 140 via CPU configuration instructions, enabling the programmable control interface device 100 to adapt to the complex scheduling requirements of heterogeneous computing scenarios.

[0038] In one embodiment, the configuration storage module 140 may be an erasable and rewritable non-volatile memory, such as an EEPROM chip or a Flash chip. For example, the user can also send instructions via the CPU to modify the storage configuration parameters, thereby enabling programmable configuration of the control interface.

[0039] In one embodiment, the event synchronization module 120 can establish a communication connection with multiple asynchronous acceleration units through the communication interface module 150 to receive event signals (e.g., including but not limited to data processing completion signals, data request signals, abnormal alarm signals, etc.) sent by multiple asynchronous acceleration units, and synchronize and coordinate the events of multiple asynchronous acceleration units according to the control signals sent by the interface control module 110.

[0040] In one embodiment, the event synchronization module 120 can be configured to receive event signals sent in real time by multiple asynchronous acceleration units during operation, and extract event information from the event signals, wherein the event information includes event type, trigger time, identifier of target asynchronous acceleration unit, and associated data.

[0041] In one embodiment, for example, when the GPU completes image preprocessing, it sends an event signal containing preset fields, from which the event synchronization module 120 can parse the following: the event type is "data processing completed" (encoded 0x01), the trigger time is the system clock count value 0xA2B3C400, the identifier of the target asynchronous acceleration unit is "DSP_01", and the associated data points to the address and length of the preprocessed result data block stored in the shared cache.

[0042] In one embodiment, the interface control module 110 can also be configured to generate an event synchronization control signal based on the synchronization rules stored in the configuration storage module 140, the configuration information and processing priority of multiple asynchronous acceleration units, and the event information extracted by the event synchronization module.

[0043] In one embodiment, for example, the interface control module 110 reads a preset synchronization rule from the configuration storage module 140 (e.g., triggering DSP startup after GPU processing is complete), and combines it with the processing priority of each asynchronous acceleration unit (e.g., GPU priority weight is 0.7, DSP priority weight is 0.2) and event information reported by the event synchronization module (e.g., event type is "GPU processing complete", target asynchronous acceleration unit identifier is "DSP_01"). Based on this information, the interface control module 110 can generate an event synchronization control signal (e.g., triggering DSP_01 to start data reading) and send it to the event synchronization module 120. For example, the event synchronization control signal can carry the identifier of the target asynchronous acceleration unit (DSP_01) and the expected operation type (start data reading), thereby ensuring that subsequent triggering operations are accurate and efficient.

[0044] In one embodiment, the event synchronization module 120 can also be configured to send a trigger signal to the target asynchronous acceleration unit according to the event synchronization control signal, so as to trigger the target asynchronous acceleration unit to perform corresponding operations.

[0045] In one embodiment, for example, after receiving an event synchronization control signal (e.g., triggering DSP_01 to start data reading) from the interface control module 110, the event synchronization module 120 can immediately send a trigger signal to the target asynchronous acceleration unit identified as DSP_01 through the corresponding communication interface (e.g., AXI bus). This trigger signal can, for example, adopt a preset handshake protocol format, containing information such as the opcode (e.g., 0x01 indicating "start data reading"), source data address, and length. Upon receiving the trigger signal, the target asynchronous acceleration unit DSP_01 can directly read data from the specified address and begin feature extraction processing without waiting for CPU polling. The entire triggering process is completed by the event trigger of the event synchronization module 120, with a delay of only a few clock cycles, thereby achieving direct inter-unit synchronization at the microsecond level.

[0046] In one embodiment, the event synchronization module 120 may include an event trigger and a synchronization timer. The event trigger may be configured to receive event signals from multiple asynchronous acceleration units and send a trigger signal to a target asynchronous acceleration unit. The synchronization timer may be configured to start timing after the event trigger sends a trigger signal and generate a synchronization timeout signal and send it to the interface control module 110 if no expected feedback is received from the target asynchronous acceleration unit within a preset timing threshold.

[0047] In one embodiment, for example, the synchronization timer can start timing at the same time as the event trigger sends a trigger signal, and begin counting down (e.g., counting down from 100ms to 0). If the event trigger does not receive the expected feedback signal (e.g., "data read complete" or "operation ready") from the target asynchronous acceleration unit within a preset timing threshold, the synchronization timer determines that the synchronization operation has timed out, immediately generates a synchronization timeout signal, and sends it to the interface control module 110. After receiving the signal, the interface control module 110 can report alarm information to the CPU or initiate abnormal handling processes such as retry or path switching, thereby preventing the system from falling into an infinite wait due to a slow or unresponsive unit, significantly improving the robustness of the system.

[0048] In one embodiment, the data scheduling module 130 can be configured to schedule the flow of associated data between multiple asynchronous acceleration units or between multiple asynchronous acceleration units and the CPU unit according to the data scheduling strategy stored in the configuration storage module 140 and the event information extracted by the event synchronization module 120.

[0049] In one embodiment, the data scheduling module 130 may include a data routing unit and a caching unit. The data routing unit is configured to allocate data transmission paths based on the type of associated data and the processing priority and working status of the target asynchronous acceleration unit. The caching unit is configured to cache associated data. The data scheduling module supports data fragmentation transmission mode and batch transmission mode.

[0050] In one embodiment, for example, the data scheduling module 130 can obtain the location and size of the associated data in the event information from the event synchronization module 120, and simultaneously read the data scheduling strategy stored in the configuration storage module 140 (e.g., prioritizing AXI interface transmission and supporting batch transmission mode). For example, based on the processing priority and current working state of the target asynchronous acceleration unit, the data scheduling module 130 allocates the optimal data transmission path: if the target asynchronous acceleration unit is a high-priority GPU and the current AXI bus is idle, the associated data is immediately read from the cache of the source asynchronous acceleration unit and transmitted to the GPU via the AXI interface; at the same time, the cache unit of the data scheduling module 130 will temporarily store a copy of the data in case of transmission failure. When data needs to be cascaded between multiple asynchronous acceleration units (e.g., from GPU to DSP to ASIC), the data scheduling module 130 schedules them sequentially until the final processing result is transmitted back to the CPU unit via the PCIe interface, thereby achieving efficient data flow throughout the entire process.

[0051] In one embodiment, the interface control module 110 is further configured to monitor the working status of the event synchronization module 120, the data scheduling module 130, and the plurality of asynchronous acceleration units in real time. The interface control module 110 is also configured to send an alarm signal to the CPU unit when an abnormal event occurs in the working status of the event synchronization module 120, the data scheduling module 130, or the plurality of asynchronous acceleration units, and to initiate an abnormal handling process according to a preset abnormal handling strategy. The abnormal event includes at least one of the following: data transmission failure, asynchronous acceleration unit failure, and synchronization timeout.

[0052] In one embodiment, for example, the interface control module 110 can monitor the working status of the event synchronization module 120 (e.g., the waiting timeout status of each event trigger), the working status of the data scheduling module 130 (e.g., transmission completion flag, retry flag, failure flag), and the heartbeat signals or ready signals of multiple asynchronous acceleration units in real time via the internal status bus. When abnormal events such as data transmission failure (e.g., the data scheduling module 130 does not receive an acknowledgment after sending data to the DSP), asynchronous acceleration unit failure (e.g., the GPU does not respond to the status query after exceeding the threshold time), or synchronization timeout (e.g., the synchronization timer in the event synchronization module 120 reports a timeout signal) are detected, the interface control module 110 can immediately send an interrupt or alarm signal containing the exception type and location to the CPU unit through the communication interface module 150, and automatically initiate an exception handling process according to the preset exception handling strategy in the configuration storage module 140 (e.g., pausing the current pipeline, reallocating the transmission path, resetting the faulty unit, or degrading operation, etc.), thereby preventing a single point of failure from causing the entire system to hang or crash, significantly improving the system's fault tolerance and operational reliability.

[0053] In one embodiment, the interface control module 110 is further configured to report the working status of the event synchronization module 120, the data scheduling module 130, and the multiple asynchronous acceleration units to the CPU unit. The interface control module 110 is also configured to receive configuration adjustment instructions sent from the CPU unit based on the working status of the event synchronization module 120, the data scheduling module 130, and the multiple asynchronous acceleration units. Furthermore, the interface control module 110 is also configured to update one or more of the synchronization rules, data scheduling strategies, configuration information, and processing priorities of the multiple asynchronous acceleration units in the configuration storage module 140 based on the configured adjustment instructions.

[0054] In one embodiment, for example, the CPU unit can determine whether the current synchronization rule is reasonable, whether the data scheduling strategy needs optimization, or whether the processing priority should be adjusted based on this working status information, and generate a corresponding configuration adjustment instruction to send to the interface control module 110. The interface control module 110 can receive and parse the configuration adjustment instruction, and then update the synchronization rule, data scheduling strategy, and configuration information and processing priority of multiple asynchronous acceleration units in the configuration storage module 140 (e.g., changing the timeout threshold from 100ms to 150ms, or swapping the priority order of the DSP and ASIC, etc.), thereby realizing dynamic reconfiguration during system operation without interrupting tasks or restarting the device.

[0055] The event synchronization method and programmable control interface device provided in the embodiments of this application realize event synchronization and data scheduling between the CPU unit and multiple asynchronous acceleration units by setting a programmable control interface device between the CPU unit and multiple asynchronous acceleration units. This scheme offloads the synchronization logic from the CPU to the programmable control interface device, directly triggering the target computing unit in an event-driven manner without CPU polling intervention, significantly reducing CPU load and synchronization latency. Simultaneously, through the configuration storage module in the programmable control interface device, users can flexibly modify synchronization rules and data scheduling strategies to adapt to different application scenarios and heterogeneous hardware without modifying the hardware structure. Furthermore, the synchronization timer and exception handling mechanism enhance the robustness and fault tolerance of the system. Therefore, this disclosure effectively solves the problems of low synchronization efficiency, high CPU load, poor flexibility, and insufficient robustness in the prior art, and can be widely applied in fields such as artificial intelligence training and inference, high-performance computing, and embedded systems.

[0056] This application also provides an event synchronization system for event synchronization between a CPU unit and multiple asynchronous acceleration units, the event synchronization system including the aforementioned programmable control interface device. For example, the following specific application embodiments 1 and 2 describe the event synchronization system in detail.

[0057] Specific Application Example 1 (High-Performance Computing System) This embodiment provides a high-performance computing system, including the aforementioned programmable control interface device. In this system, the CPU unit manages three asynchronous acceleration units: a GPU (Graphics Processing Unit), a DSP (Digital Signal Processing Unit), and an ASIC (Application-Specific Integrated Circuit). These asynchronous acceleration units work together to complete large-scale data processing tasks.

[0058] The interface control module is implemented using an FPGA chip, with a built-in instruction parser supporting custom instruction sets. The event synchronization module establishes communication connections with the GPU, DSP, and ASIC via an AXI interface, and includes three event triggers and one synchronization timer, capable of simultaneously acquiring event signals from three asynchronous acceleration units. The data scheduling module uses a high-speed cache chip, with a built-in data routing unit and 2MB of cache space, supporting a PCIe 4.0 interface. The configuration storage module uses an EEPROM chip, capable of erasing and rewriting synchronization rules, data scheduling strategies, and configuration information for each asynchronous acceleration unit. The communication interface module integrates three standard interfaces: PCIe 4.0, AXI 4.0, and UART.

[0059] The event synchronization process based on the above-mentioned programmable control interface device may include the following operations: Operation 1: Configuration initialization. Based on the needs of large-scale data processing, the user sends configuration instructions to the programmable control interface device through the CPU unit. These instructions include synchronization rules (GPU processing triggers DSP startup, DSP processing triggers ASIC startup), data scheduling strategy (preferential use of the AXI interface for transmission, data buffering time is 100ms), configuration information and processing priorities of the three asynchronous acceleration units (GPU has the highest priority, followed by DSP, and lastly ASIC). The interface control module parses the configuration instructions and stores the relevant configuration parameters in the configuration storage module. Operation 2: Event acquisition and reporting. After the GPU completes image data preprocessing, it sends a "data processing complete" event signal to the event synchronization module. The event synchronization module acquires this event signal, parses it to show the event type as "processing complete" and the associated data as the preprocessed image data, and feeds the event information back to the interface control module. The interface control module then synchronously reports this event information to the CPU unit. Operation 3: Event Synchronization Coordination. The interface control module generates a "trigger DSP startup" control signal according to the synchronization rules. The event synchronization module sends a "data read start" signal to the DSP via the AXI interface to trigger DSP startup, while recording the synchronization time and providing feedback on the synchronization status. Operation 4: Data Scheduling Execution. The data scheduling module reads the GPU-preprocessed image data from the GPU cache and transmits it to the DSP via the AXI interface, while simultaneously storing a data copy in its own cache unit. After the DSP completes feature extraction, the event synchronization module triggers ASIC startup. The data scheduling module transmits the DSP-processed feature data to the ASIC. After the ASIC completes recognition processing, the data scheduling module transmits the recognition result to the CPU unit via the PCIe interface. Operation 5: Status Monitoring and Dynamic Adjustment. The interface control module collects the operating status of each unit in real time. When a data read timeout (exceeding 100ms) is detected in the DSP, an alarm signal is immediately sent to the CPU, and an emergency handling strategy is initiated, suspending data transmission and reallocating the transmission path. After viewing the alarm information through the CPU, the user sends an adjustment command to modify the data cache time to 150ms. The interface control module updates the configuration parameters and resumes data transmission.

[0060] Specific Application Example 2 (Embedded System) This embodiment provides an embedded system including the aforementioned programmable control interface device. The difference between this embodiment and Embodiment 1 is that the CPU unit manages two asynchronous acceleration units (DSP and ASIC), primarily used for real-time processing of industrial data; the communication interface module integrates only AXI and UART interfaces; the configuration storage module uses a Flash chip; and the data scheduling module has a 1MB cache.

[0061] Furthermore, its event synchronization process is similar to that of Embodiment 1, except that the synchronization rule is "after the ASIC completes processing, the data is fed back to the DSP for secondary processing, and after the secondary processing is completed, it is transmitted to the CPU." The data scheduling strategy adopts a batch transmission mode, which is suitable for the batch processing needs of industrial data. In this way, through this programmable control interface device, efficient flow and event synchronization of industrial data between two asynchronous acceleration units are realized, reducing CPU load and improving the real-time processing capability of the embedded system.

[0062] This application also provides a computer-readable storage medium having instructions stored thereon, which, when executed by a processor, cause the processor to perform the above-described event synchronization method.

[0063] Examples of computer-readable storage media include non-transitory computer-readable storage media such as portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, etc.

[0064] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0065] The above description is merely a specific embodiment of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. An event synchronization method for event synchronization between a CPU unit and a plurality of asynchronous acceleration units, characterized by, The event synchronization method includes: The interface control module of the programmable control interface device receives configuration instructions from the CPU unit and stores the configuration parameters in the configuration instructions into the configuration storage module of the programmable control interface device. The configuration parameters include synchronization rules, data scheduling strategies, and configuration information and processing priorities of the multiple asynchronous acceleration units. The event synchronization module of the programmable control interface device receives event signals sent in real time by the multiple asynchronous acceleration units during operation, and extracts event information from the event signals, wherein the event information includes event type, trigger time, identifier of target asynchronous acceleration unit, and associated data; The interface control module generates an event synchronization control signal based on the synchronization rules stored in the configuration storage module, the configuration information and processing priority of the multiple asynchronous acceleration units, and the event information extracted by the event synchronization module. The event synchronization module sends a trigger signal to the target asynchronous acceleration unit based on the event synchronization control signal, thereby triggering the target asynchronous acceleration unit to perform corresponding operations; and The data scheduling module of the programmable control interface device schedules the flow of the associated data between the multiple asynchronous acceleration units, or between the multiple asynchronous acceleration units and the CPU unit, based on the data scheduling strategy stored in the configuration storage module and the event information extracted by the event synchronization module. The data scheduling module includes a data routing unit and a caching unit. The data routing unit is configured to allocate data transmission paths according to the type of the associated data and the processing priority and working status of the target asynchronous acceleration unit. The caching unit is configured to cache the associated data. The data scheduling module supports data fragmentation transmission mode and batch transmission mode.

2. The event synchronization method of claim 1, wherein, The programmable control interface device further includes a communication interface module, through which the programmable control interface device communicates with the CPU unit and the plurality of asynchronous acceleration units.

3. The event synchronization method of claim 1, wherein, The event synchronization module includes an event trigger and a synchronization timer. The event trigger is configured to receive the event signal from the plurality of asynchronous acceleration units and send the trigger signal to the target asynchronous acceleration unit, wherein... The synchronization timer is configured to start timing after the event trigger sends the trigger signal, and if no expected feedback is received from the target asynchronous acceleration unit within a preset timing threshold, generate a synchronization timeout signal and send it to the interface control module.

4. The event synchronization method of claim 1, wherein, The event synchronization method also includes: The interface control module monitors the working status of the event synchronization module, the data scheduling module, and the multiple asynchronous acceleration units in real time; and When an abnormal event occurs in the operation of the event synchronization module, the data scheduling module, or the multiple asynchronous acceleration units, the interface control module sends an alarm signal to the CPU unit and initiates an abnormal handling process according to a preset abnormal handling strategy. The abnormal events include at least one of the following: data transmission failure, asynchronous acceleration unit failure, and synchronization timeout.

5. The event synchronization method of claim 4, wherein, The event synchronization method also includes: The interface control module reports the working status of the event synchronization module, the data scheduling module, and the multiple asynchronous acceleration units to the CPU unit. The interface control module receives configuration adjustment instructions from the CPU unit based on the operating states of the event synchronization module, the data scheduling module, and the plurality of asynchronous acceleration units; and The interface control module updates one or more of the synchronization rules, data scheduling strategies, configuration information, and processing priorities of the multiple asynchronous acceleration units in the configuration storage module based on the configuration adjustment instructions.

6. A programmable control interface device for event synchronization between a CPU unit and multiple asynchronous acceleration units, characterized in that, The programmable control interface device includes an interface control module, an event synchronization module, a data scheduling module, and a configuration storage module, wherein... The interface control module is configured to receive configuration instructions from the CPU unit and store the configuration parameters in the configuration instructions to the configuration storage module. The configuration parameters include synchronization rules, data scheduling strategies, and configuration information and processing priorities of the multiple asynchronous acceleration units. The event synchronization module is configured to receive event signals sent in real time by the multiple asynchronous acceleration units during operation, and extract event information from the event signals, wherein the event information includes event type, trigger time, identifier of target asynchronous acceleration unit, and associated data; The interface control module is further configured to generate an event synchronization control signal based on the synchronization rules stored in the configuration storage module, the configuration information and processing priority of the plurality of asynchronous acceleration units, and the event information extracted by the event synchronization module. The event synchronization module is further configured to send a trigger signal to the target asynchronous acceleration unit based on the event synchronization control signal, thereby triggering the target asynchronous acceleration unit to perform a corresponding operation; and The data scheduling module is configured to schedule the flow of associated data between the multiple asynchronous acceleration units, or between the multiple asynchronous acceleration units and the CPU unit, based on the data scheduling strategy stored in the configuration storage module and the event information extracted by the event synchronization module. The data scheduling module includes a data routing unit and a caching unit. The data routing unit is configured to allocate data transmission paths according to the type of the associated data and the processing priority and working status of the target asynchronous acceleration unit. The caching unit is configured to cache the associated data. The data scheduling module supports data fragmentation transmission mode and batch transmission mode.

7. The programmable control interface device of claim 6, wherein, The programmable control interface device further includes a communication interface module, through which the programmable control interface device communicates with the CPU unit and the plurality of asynchronous acceleration units.

8. The programmable control interface device of claim 6, wherein, The event synchronization module includes an event trigger and a synchronization timer. The event trigger is configured to receive the event signal from the plurality of asynchronous acceleration units and send the trigger signal to the target asynchronous acceleration unit, wherein... The synchronization timer is configured to start timing after the event trigger sends the trigger signal, and if no expected feedback is received from the target asynchronous acceleration unit within a preset timing threshold, generate a synchronization timeout signal and send it to the interface control module.

9. The programmable control interface device of claim 6, wherein, The interface control module is also configured to monitor the working status of the event synchronization module, the data scheduling module, and the multiple asynchronous acceleration units in real time; and The interface control module is also configured to send an alarm signal to the CPU unit when an abnormal event occurs in the working state of the event synchronization module, the data scheduling module, or the multiple asynchronous acceleration units, and to initiate an abnormal handling process according to a preset abnormal handling strategy. The abnormal events include at least one of the following: data transmission failure, asynchronous acceleration unit failure, and synchronization timeout.

10. The programmable control interface device according to claim 9, characterized in that, The interface control module is also configured to report the working status of the event synchronization module, the data scheduling module, and the plurality of asynchronous acceleration units to the CPU unit; The interface control module is also configured to receive configuration adjustment instructions from the CPU unit based on the operating states of the event synchronization module, the data scheduling module, and the plurality of asynchronous acceleration units; and The interface control module is also configured to update one or more of the synchronization rules, the data scheduling strategy, and the configuration information and processing priorities of the plurality of asynchronous acceleration units in the configuration storage module based on the configuration adjustment instructions.

11. An event synchronization system for event synchronization between a CPU unit and a plurality of asynchronous acceleration units, characterized in that, The event synchronization system includes a programmable control interface device according to any one of claims 6-10.

12. A computer-readable storage medium storing instructions, the instructions comprising: When executed by a processor, the instructions cause the processor to perform the event synchronization method according to any one of claims 1-5.

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