A method for SRIO communication fault self-recovery and reconnection between FPGA and DSP

Abstract

The application discloses a method for SRIO communication fault self-recovery and reconnection between FPGA and DSP, and belongs to the technical field of high-speed serial communication and embedded system reliability. A link monitoring module is started at the FPGA end, and the port initialization state, the link initialization state, the port error state and the initialization timeout condition of the SRIO link are jointly monitored. When the link interruption, error or initialization completion flag of the DSP is not received within the preset time is detected, the FPGA generates a reset trigger signal and sends the same to the DSP, so that the DSP re-executes the SRIO initialization. After the initialization of the DSP is completed, the FPGA end SRIO module is reset through a conventional interface, so that the SRIO modules at both ends restore the consistent initialization state, and the link automatic reconstruction is realized. The application only realizes the double-end cooperative reset through the existing interface, effectively solves the single-end reset and the link "false normal" problem, and has the advantages of simple structure and high reliability.

Description

Technical Field

[0001] This invention belongs to the field of high-speed serial communication and embedded system reliability technology, specifically relating to a method for self-healing and reconnection of SRIO communication faults between FPGA and DSP. Background Technology

[0002] SRIO (Serial RapidIO) bus, as a high-performance, low-latency serial communication protocol, has been widely used in high-speed digital signal processing systems due to its high bandwidth and strong real-time performance, especially in point-to-point high-speed interconnection scenarios consisting of FPGA and DSP.

[0003] In a typical FPGA-DSP SRIO communication system, both sides initialize their SRIO modules after power-on, and data exchange can begin once the link is successfully established. However, in practical engineering applications, especially in real-time systems with high reliability requirements such as airborne and vehicle-mounted systems, abnormal resets, program reloading, or dynamic updates may occur on the FPGA or DSP end during system operation. In such cases, the SRIO communication link often fails to recover automatically, leading to communication interruption. More problematic is that in certain fault scenarios, the SRIO port initialization flag (port_initialized) and link initialization flag (link_initialized) still show as normal, but the port error flag (port_error) is set, indicating that the actual data path has failed, creating a "false normal" state—"appearing normal, but actually unusable." This state is difficult to identify effectively using traditional monitoring methods and usually requires manual intervention or a global system reset to restore communication, severely impacting system reliability and availability.

[0004] Existing technologies have proposed several solutions to address the SRIO link recovery problem. For example, one method involves monitoring the port_initialized and link_initialized states and resetting its own SRIO module to attempt link reconstruction. However, this method relies on a single fault criterion and cannot effectively address the aforementioned "false normal" state. Furthermore, when a single-end device malfunctions, resetting only the local device often proves ineffective, requiring the resetting of the peer device as well. Another approach involves introducing auxiliary communication buses such as CAN_FD to construct a complex fault detection and recovery network. While suitable for multi-device topologies, this approach introduces complex system architecture, high hardware and software overhead, and high design costs, making it unsuitable for point-to-point communication scenarios between FPGAs and DSPs that prioritize simplicity and efficiency.

[0005] Therefore, for FPGA and DSP point-to-point SRIO communication systems, there is an urgent need for a reliable method that can accurately detect various link faults (including "false normal" states) without increasing the burden on the additional communication bus, and can automatically trigger collaborative reset and quickly restore the link when any end is abnormal, so as to improve the overall robustness and self-healing capability of the system. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a method for self-healing and reconnection of SRIO communication faults between FPGA and DSP. Without adding an extra communication bus, it achieves automatic detection and rapid recovery of the SRIO link under conditions such as single-end reset, abnormal interruption, and initialization failure through multi-condition link status criteria and dual-end collaborative reset mechanism, thereby improving the reliability of system communication and engineering practicality.

[0007] To achieve the above objectives, the present invention adopts the following technical solution:

[0008] A method for self-healing and reconnection based on SRIO communication failure between FPGA and DSP, applied to a point-to-point SRIO communication system between FPGA and DSP, includes:

[0009] After the FPGA is powered on or reset, the SRIO module is initialized, and the link monitoring module is started to jointly monitor the port initialization status, link initialization status, port error status, and whether the DSP terminal initialization completion flag is received within a preset time.

[0010] When any of the following anomalies are detected, the FPGA generates a reset trigger signal and sends it to the DSP:

[0011] Port initialization status and link initialization status were abnormally interrupted;

[0012] The port error status is set;

[0013] No DSP-side SRIO initialization completion flag was received within the preset time;

[0014] After receiving the reset trigger signal, the DSP re-executes the SRIO initialization process. After completing the initialization, it triggers the FPGA-side SRIO module to reset through the communication interface, so that the SRIO modules of both sides re-enter a consistent initialization state, thereby realizing the automatic reconstruction of the SRIO communication link.

[0015] Furthermore, the link monitoring module also monitors when the port initialization status and link initialization status are both normal, but the port error flag is set, and determines it to be a link error state.

[0016] Furthermore, the preset time is a time window used to wait for the DSP to complete SRIO initialization after the FPGA is powered on or reset. If the SRIO initialization completion flag of the DSP is not received within this time window, the SRIO initialization is determined to have timed out.

[0017] Furthermore, the DSP writes the SRIO initialization completion status into a status register through the EMIF interface, and the status register is read by the FPGA through the EMIF interface to determine the DSP initialization status.

[0018] Furthermore, the reset signal on the FPGA side is triggered by the DSP setting the reset control register or controlling the GPIO pin level through the EMIF interface to activate the reset operation of the FPGA-side SRIO module.

[0019] Furthermore, the reset trigger signal of the DSP port is generated by the FPGA, and the DSP chip is reset by controlling the reset pin of the DSP chip.

[0020] Furthermore, the reset trigger signal generated by the FPGA is a level signal or a pulse signal, and its duration or pulse width ensures that the DSP can reliably recognize and respond to the reset trigger.

[0021] Furthermore, the method can automatically detect faults and rebuild the communication link when an abnormal reset, reload, or link error occurs at either end of the FPGA or DSP.

[0022] In a second aspect, the present invention provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; wherein, when the one or more programs are executed by the one or more processors, the one or more processors enable the aforementioned method for self-healing and reconnection of SRIO communication faults between FPGA and DSP.

[0023] Thirdly, the present invention provides a computer-readable storage medium storing executable instructions thereon, which, when executed by a processor, enable the processor to implement the aforementioned method for self-healing and reconnection of SRIO communication faults between an FPGA and a DSP.

[0024] The beneficial effects of this invention are as follows:

[0025] Comprehensive and reliable fault detection: By jointly monitoring port initialization status, link initialization status, port error status, and initialization timeout, it effectively identifies hidden faults such as "false normality" of links that are difficult to detect by traditional methods, greatly improving the coverage and accuracy of fault detection.

[0026] The self-healing mechanism is highly efficient and collaborative: It innovatively introduces a dual-end collaborative reset mechanism in the point-to-point architecture. When a fault is detected at either end, it can actively trigger the re-initialization of the peer device, realizing the linkage recovery of "faulty end-peer end". This avoids the problem of only resetting the local end being ineffective or requiring a complete system reset, and significantly shortens the link recovery time.

[0027] Enhanced system robustness: Through a preset timeout determination mechanism, communication deadlocks caused by abnormal startup sequence or initialization failure can be properly handled, enhancing the system's fault tolerance and robustness under non-ideal operating conditions.

[0028] Simple structure and low cost: This invention does not rely on additional communication buses such as CAN or Ethernet. It can achieve complete fault detection and recovery functions by making full use of the existing conventional interfaces (such as EMIF) and reset control signals between FPGA and DSP. This greatly simplifies the system hardware design and software protocol stack, and reduces implementation complexity and cost.

[0029] Highly practical for engineering applications: The solution is specifically optimized for point-to-point SRIO communication scenarios between FPGAs and DSPs. It has clear logic, is easy to implement and integrate on existing engineering platforms, and has good operability and promotion value. It is especially suitable for embedded signal processing systems with stringent requirements for reliability and real-time performance. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a method for self-healing and reconnection of SRIO communication faults between FPGA and DSP according to the present invention.

[0031] Figure 2 This is a block diagram of the hardware connection between the FPGA and DSP for SRIO communication in this invention. Detailed Implementation

[0032] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0033] like Figure 1 The diagram shown illustrates the principle of a self-healing and reconnection method for SRIO communication faults between an FPGA and a DSP according to the present invention. The implementation of this method relies on the collaborative work of the FPGA and DSP software, as detailed below:

[0034] (a) FPGA-side processing flow;

[0035] As the primary monitor of the link status and the initiator of the recovery process, the FPGA's software logic executes the following steps:

[0036] Power-on / Reset and SRIO Initialization: After the FPGA is powered on or receives a global reset signal, it first initializes and configures its internal SRIO IP core, completing necessary operations such as register settings and clock training.

[0037] Start the link monitoring module: After the FPGA completes its own SRIO module initialization, it starts a dedicated link monitoring module. The core responsibility of this module is to continuously and in real-time monitor the health status of the SRIO link.

[0038] Multi-dimensional link status monitoring: The link monitoring module jointly monitors the following four key states:

[0039] SRIO port initialization status (port_initialized): Indicates whether the SRIO physical port has been initialized.

[0040] SRIO link initialization status (link_initialized): Indicates whether the logical link connection with the peer (DSP) has been successfully established.

[0041] SRIO port error status (port_error): indicates whether the port has detected a communication error (such as 8B / 10B decoding error, link layer packet error, etc.).

[0042] Initialization timeout determination: After the FPGA is powered on or reset, a timer is started to monitor whether an SRIO initialization completion flag is received from the DSP side within a preset time window (this flag is transmitted through the status register of the EMIF interface).

[0043] Fault Determination and Signal Generation: When the link monitoring module detects any of the following abnormal conditions, it determines that an SRIO communication failure has occurred and immediately generates a reset trigger signal:

[0044] Condition A: When the port_initialized or link_initialized signal changes from a normal state (usually logic '1') to an abnormal state (logic '0'), it indicates that the link has been interrupted.

[0045] Condition B: Both port_initialized and link_initialized show normal operation, but the port_error signal is set (logic '1'), indicating that there is a communication error in the link (i.e., a "false normal" state).

[0046] Condition C: If the SRIO initialization completion flag declared by the DSP through the EMIF interface is not detected within the preset timeout window, it indicates that the DSP initialization has failed or the startup sequence is abnormal.

[0047] FPGA triggers peer reset: The FPGA generates a reset trigger signal, which controls the reset pin of the DSP chip to reset the DSP chip.

[0048] Normal communication: When all monitoring statuses are normal and the DSP initialization completion flag has been received, the SRIO module on the FPGA side enters a stable data transmission and reception state.

[0049] (II) DSP-side processing flow;

[0050] As the responder and executor of the collaborative recovery process, the DSP executes its software logic according to the following steps:

[0051] Power-on / Reset and SRIO Initialization: After the DSP is powered on or reset, it first completes the initialization of its internal SRIO module.

[0052] Status Notification and Peer Reset: After its own SRIO initialization is complete, the DSP performs two key operations to synchronize its status with the FPGA via the EMIF interface:

[0053] DSP status announcements are made by writing the SRIO initialization completion status (e.g., setting a status register named Srio_Rdy to '1') into the FPGA-accessible address space via the EMIF interface.

[0054] DSP-side reset is achieved by setting the reset control register (e.g., Srio_rst) of the EMIF interface or generating a pulse signal to control the FPGA pin level via the GPIO interface, triggering a reset of the FPGA-side SRIO module. This step ensures that during normal system startup, the SRIO modules at both ends can establish a link from a known and consistent initial state.

[0055] Normal communication begins: After completing the above operations, the DSP-side SRIO module enters the normal data transmission and reception state.

[0056] Responding to fault reset requests: During operation, the DSP continuously monitors the reset trigger signal from the FPGA. Once the signal is received, the DSP immediately re-executes its SRIO initialization process, i.e., jumps back to power-on / reset and SRIO initialization, and after initialization is complete, performs status notification and peer reset operations again.

[0057] (III) Dual-end collaborative reconnection mechanism:

[0058] The above processes together form a complete closed loop of "detection-triggering-coordinated recovery":

[0059] Fault detection: This is handled by the link monitoring module on the FPGA side, which uses multiple criteria to ensure that no faults are missed.

[0060] Reset at the other end: The faulty end (FPGA) actively triggers the peer device (DSP) to reinitialize.

[0061] Local Reset and Status Synchronization: After completing its own initialization, the triggered peer (DSP) not only announces its status but also actively resets the SRIO module of the initiating end, forcing both parties to return to a consistent initialization starting point, thereby completing the automatic reconstruction of the link.

[0062] refer to Figure 2 In this embodiment, the FPGA and DSP are interconnected via an SRIO link. Simultaneously, the DSP's EMIF interface is connected to the FPGA for transmitting configuration, status, and other information. Furthermore, a GPIO pin of the DSP (e.g., GPIO 15) is connected to a dedicated input pin of the FPGA, which can be configured as the reset signal input (srio_reset) for the FPGA's internal SRIO IP core.

[0063] Example 1: Normal system startup and communication;

[0064] After the FPGA and DSP are powered on simultaneously, they each complete the initialization of their SRIO modules. After initialization, the DSP sets the Srio_Rdy state to 1 via the EMIF interface and controls the Srio_rst signal to trigger a reset of the FPGA's SRIO module, ensuring that both SRIO modules are in the same initial state. Subsequently, the FPGA and DSP enter normal SRIO data transmission and reception mode.

[0065] Example 2: Fault recovery from single-ended reloading of FPGA;

[0066] During normal system communication, if the FPGA is reloaded, after the FPGA-side SRIO initialization is complete, the link monitoring module detects that port_error is set and the transmit interface is unavailable, and then generates a reset trigger signal. Upon receiving this signal, the DSP re-executes the SRIO initialization process and resets the FPGA-side SRIO module after initialization, thereby achieving automatic link recovery without the need for manual DSP reset.

[0067] Example 3: Fault recovery from single-ended reloading of DSP;

[0068] When the DSP is reset or reloaded during system operation, the FPGA detects any of the following situations, the link monitoring module determines that the communication is abnormal and triggers the DSP re-initialization process. After the DSP is initialized, the SRIO link resumes normal communication.

[0069] 1) port_initialized==0;

[0070] 2) link_initialized==0;

[0071] 3) port_error == 1;

[0072] 4) The Srio_Rdy flag was not received from the DSP within the preset time.

[0073] Example 4: Handling power-on initialization failure;

[0074] When the system is powered on, if the DSP fails to complete the SRIO initialization within the preset time due to the startup sequence or abnormal reasons, the FPGA end link monitoring module triggers the DSP to reset through the timeout judgment mechanism to prevent the system from entering an unrecoverable communication abnormal state.

[0075] In summary, this invention can automatically detect and self-heal the SRIO communication link when an anomaly occurs at either end of the FPGA or DSP, significantly improving the reliability and stability of the system.

[0076] In a second aspect, the present invention provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; wherein, when the one or more programs are executed by the one or more processors, the one or more processors enable the aforementioned method for self-healing and reconnection of SRIO communication faults between FPGA and DSP.

[0077] Thirdly, the present invention provides a computer-readable storage medium storing executable instructions thereon, which, when executed by a processor, enable the processor to implement the aforementioned method for self-healing and reconnection of SRIO communication faults between an FPGA and a DSP.

[0078] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for self-recovery and reconnection based on SRIO communication failure between FPGA and DSP, characterized in that, Applications include FPGA and DSP point-to-point SRIO communication systems, including: After the FPGA is powered on or reset, the SRIO module is initialized, and the link monitoring module is started to jointly monitor the port initialization status, link initialization status, port error status, and whether the DSP terminal initialization completion flag is received within a preset time. When any of the following anomalies are detected, the FPGA generates a reset trigger signal and sends it to the DSP: Port initialization status and link initialization status were abnormally interrupted; The port error status is set; No DSP-side SRIO initialization completion flag was received within the preset time; After receiving the reset trigger signal, the DSP re-executes the SRIO initialization process. After completing the initialization, it triggers the FPGA-side SRIO module to reset through the communication interface, so that the SRIO modules of both sides re-enter a consistent initialization state, thereby realizing the automatic reconstruction of the SRIO communication link.

2. The method for SRIO communication fault self-recovery and reconnection between FPGA and DSP according to claim 1, characterized in that, The link monitoring module also monitors when the port initialization status and link initialization status are both normal, but the port error flag is set, and determines it to be a link error state.

3. The method for self-healing and reconnection of SRIO communication faults between FPGA and DSP according to claim 1, characterized in that, The preset time is a time window used to wait for the DSP to complete SRIO initialization after the FPGA is powered on or reset. If the DSP's SRIO initialization completion flag is not received within this time window, the SRIO initialization is determined to have timed out.

4. The method for self-healing and reconnection of SRIO communication between FPGA and DSP based on claim 1, characterized in that, The DSP writes the SRIO initialization completion status into a status register through the EMIF interface. The status register is read by the FPGA through the EMIF interface to determine the DSP initialization status.

5. The method for self-healing and reconnection of SRIO communication between FPGA and DSP according to claim 1, characterized in that, The reset signal on the FPGA side is triggered by the DSP setting the reset control register through the EMIF interface or controlling the GPIO pin level to activate the reset operation of the FPGA-side SRIO module.

6. The method for self-healing and reconnection of SRIO communication between FPGA and DSP according to claim 1, characterized in that, The reset trigger signal of the DSP port is generated by the FPGA, and the DSP chip is reset by controlling the reset pin of the DSP chip.

7. The method for self-healing and reconnection of SRIO communication faults between FPGA and DSP according to claim 1, characterized in that, The reset trigger signal generated by the FPGA is a level signal or a pulse signal, and its duration or pulse width ensures that the DSP can reliably recognize and respond to the reset trigger.

8. The method for self-healing and reconnection of SRIO communication between FPGA and DSP according to claim 1, characterized in that, The method can automatically detect faults and rebuild the communication link when an abnormal reset, reload, or link error occurs at either end of the FPGA or DSP.

9. An electronic device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When one or more programs are executed by the one or more processors, the one or more processors implement the method for self-healing and reconnection of SRIO communication faults between FPGA and DSP as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, It stores executable instructions that, when executed by a processor, enable the processor to implement the self-healing and reconnection method for SRIO communication failures between an FPGA and a DSP, as described in any one of claims 1-8.

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