Data processing method, data processing apparatus, electronic device, and storage medium

Abstract

Embodiments of the present disclosure provide a data processing method and device, electronic equipment and storage medium. The method comprises: receiving a data read-write request carrying logical block index information, the logical block index information being used to indicate a target logical block to which target data belongs; obtaining a physical address offset of the target logical block in a physical storage space through a data index interface according to the logical block index information; and performing reading or writing of the target data in the physical storage space based on the physical address offset, wherein the physical storage space is used to store data in at least one logical block, a plurality of index-continuous logical blocks are mapped to non-continuous physical address regions in the physical storage space, and the data index interface is constructed based on a logical block data arrangement manner. The method provides a unified data index interface, supports accurate acquisition of a logical block physical address corresponding to a logical block index identifier, and adapts to a case where a physical arrangement order and a logical arrangement order are inconsistent under a specific storage architecture.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of artificial intelligence, and more specifically to a data processing method, a data processing apparatus, an electronic device, and a storage medium. Background Technology

[0002] In recent years, with the rapid development of Artificial Intelligence (AI) technology, significant progress has been made in large-scale models based on the Transformer architecture. Pre-trained models are constantly emerging and their performance is continuously improving, leading to the widespread adoption of AI applications across various industries. Against this backdrop, the inference service framework within AI application infrastructure has become a crucial support. How to build an efficient inference service framework based on existing hardware resources to achieve the large-scale application of large models has become one of the key technical challenges that need to be addressed. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a data processing method, comprising: receiving a data read / write request carrying logical block index information, wherein the logical block index information is used to indicate the target logical block to which the target data belongs; obtaining the physical address offset of the target logical block in physical storage space through a data index interface according to the logical block index information; and performing reading or writing of the target data in the physical storage space based on the physical address offset, wherein the physical storage space is used to store data in at least one logical block, and multiple logical blocks with consecutive indexes are mapped to non-consecutive physical address regions in the physical storage space, wherein the data index interface is constructed based on the logical block data arrangement.

[0004] In the data processing method provided in at least one embodiment of this disclosure, the data in the same logical block are not distributed discontinuously in the physical storage space.

[0005] In at least one embodiment of the data processing method provided in this disclosure, the physical storage space is organized into a multi-dimensional logical storage space, and the logical storage space is divided into multiple logical blocks with consecutive indexes. The step of obtaining the physical address offset of the target logical block in the physical storage space through a data index interface based on the logical block index information includes: using the data index interface to perform the following operations: obtaining the first coordinate of the target logical block in the logical storage space based on the logical block index information; and obtaining the physical address offset corresponding to the first coordinate based on the first coordinate and in combination with the logical block data arrangement method, as the physical address offset of the target logical block in the physical storage space.

[0006] In a data processing method provided in at least one embodiment of this disclosure, the plurality of logical blocks have the same size, and the step of obtaining the first coordinates of the target logical block in the logical storage space based on the logical block index information includes: obtaining the first coordinates of the target logical block in the logical storage space based on the logical block index information, combined with the size of the logical storage space and the size of the logical block.

[0007] In at least one embodiment of the data processing method provided in this disclosure, the step of obtaining the first coordinates of the target logical block in the storage space based on the logical block index information, combined with the size of the logical storage space and the logical block size, includes: obtaining the number of logical blocks in the logical storage space in the first dimension and the second dimension, respectively, based on the size of the logical storage space and the logical block size; obtaining the third dimension coordinates, the first dimension logical block index, and the second dimension logical block index of the target logical block based on the number of logical blocks in the first dimension and the second dimension, and the logical block index information, wherein the first dimension logical block index and the second dimension logical block index represent the arrangement sequence number of the target logical block in the first dimension and the second dimension of the logical storage space, respectively; obtaining the first dimension coordinates and the second dimension coordinates based on the logical block size, the first dimension logical block index, and the second dimension logical block index; and combining the first dimension coordinates, the second dimension coordinates, and the third dimension coordinates to obtain the first coordinates.

[0008] In the data processing method provided in at least one embodiment of this disclosure, each logical block includes multiple sub-blocks of the same size, and the data in the same sub-block is stored continuously in the physical storage space in a column-major manner. The size of the sub-block is determined according to the data type of the data in the sub-block.

[0009] In at least one embodiment of the data processing method provided in this disclosure, the step of obtaining the physical address offset corresponding to the first coordinate based on the first coordinate and in combination with the logical block data arrangement includes: obtaining a first physical address offset based on the first coordinate and in combination with the size of the logical storage space; obtaining a second physical address offset based on the sub-block size and the first coordinate, in combination with the size of the logical storage space; and obtaining the physical address offset corresponding to the first coordinate based on the first physical address offset and the second physical address offset.

[0010] In at least one embodiment of the data processing method provided in this disclosure, obtaining the first physical address offset based on the first coordinates and the size of the logical storage space includes: obtaining the first physical address offset based on the third dimension coordinate in the first coordinates, the first dimension size and the second dimension size of the logical storage space.

[0011] In at least one embodiment of the data processing method provided in this disclosure, the step of obtaining a second physical address offset based on the sub-block size and the first coordinates, combined with the size of the logical storage space, includes: determining a first sub-address offset based on the first dimension coordinates in the first coordinates, the second dimension size of the logical storage space, and the first dimension size of the sub-block; determining a second sub-address offset based on the second dimension coordinates in the first coordinates, the first dimension size of the sub-block, and the second dimension size of the sub-block; and obtaining the second physical address offset based on the first sub-address offset and the second sub-address offset.

[0012] In at least one embodiment of the data processing method provided in this disclosure, the method further includes: obtaining at least one address contiguous block in the target logical block through the data index interface, wherein data in the same address contiguous block is continuously distributed in the physical storage space, and different address contiguous blocks are mapped to non-contiguous physical address regions in the physical storage space.

[0013] In a data processing method provided in at least one embodiment of this disclosure, obtaining at least one address contiguous block in the target logical block through a data indexing interface includes: using the data indexing interface to perform the following operations: determining the number of address contiguous blocks in the target logical block based on the sub-block size and the logical block size; and determining the physical address offset and length of the at least one address contiguous block based on the sub-block size, the logical block size, and the size of the logical storage space.

[0014] In at least one embodiment of the data processing method provided in this disclosure, the target data includes key-value cache data.

[0015] At least one embodiment of this disclosure provides a data processing apparatus, comprising: a receiving module configured to receive a data read / write request carrying logical block index information, the logical block index information being used to indicate a target logical block to which the target data belongs; an obtaining module configured to obtain, based on the logical block index information, the physical address offset of the target logical block in physical storage space through a data index interface; and a read / write module configured to perform reading or writing of the target data in the physical storage space based on the physical address offset, wherein the physical storage space is used to store data in at least one logical block, and multiple logical blocks with consecutive indexes are mapped to non-consecutive physical address regions in the physical storage space, wherein the data index interface is constructed based on a logical block data arrangement.

[0016] At least one embodiment of this disclosure provides an electronic device, including at least one processor and at least one memory, wherein the at least one memory stores program code that, when executed by the at least one processor, causes the at least one processor to perform a data processing method according to at least one embodiment of this disclosure.

[0017] At least one embodiment of this disclosure provides a non-transitory computer-readable storage medium having computer-readable instructions stored thereon, which, when executed by at least one processor, cause the at least one processor to perform a data processing method according to at least one embodiment of this disclosure.

[0018] In at least one embodiment of the data processing method, data processing apparatus, electronic device, and storage medium provided in this disclosure, a general and efficient indexing operation implementation scheme is proposed. By providing a unified data indexing interface, the underlying data arrangement is encapsulated, and an efficient logical block indexing mechanism is constructed. This supports the accurate retrieval of the physical address of the logical block corresponding to any logical block index identifier in any request, adapting to situations where the physical and logical arrangement orders are inconsistent under a specific storage architecture. Based on this fine-grained addressing capability, the system can flexibly execute efficient KV-Cache data access operations according to specific business needs, thereby significantly accelerating tasks such as the development of artificial intelligence processor operators and data transmission.

[0019] Furthermore, the data indexing interface provided in at least one embodiment of this disclosure also supports indexing of address-contiguous blocks, thereby facilitating quick access to storage space with contiguous addresses in the target logical block and improving data transmission efficiency. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0021] Figure 1A This is a schematic diagram of storage space partitioning for KV-Cache storage.

[0022] Figure 1B This is a schematic diagram of a general block partitioning method under a storage architecture and storage organization method provided in at least one embodiment of the present disclosure.

[0023] Figure 2A This is a schematic diagram of sub-block partitioning under a storage architecture and storage organization method provided in at least one embodiment of the present disclosure.

[0024] Figure 2B This is a schematic diagram of the sub-block data arrangement under the storage architecture and storage organization method provided in at least one embodiment of the present disclosure.

[0025] Figure 3 This is a flowchart illustrating a data processing method provided in at least one embodiment of the present disclosure.

[0026] Figure 4 This is a schematic diagram of a logical block data arrangement method provided in at least one embodiment of the present disclosure.

[0027] Figure 5 Another flowchart of a data processing method provided for at least one embodiment of this disclosure.

[0028] Figure 6 This is a schematic block diagram of a data processing apparatus provided for at least one embodiment of the present disclosure.

[0029] Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0030] Figure 8 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0031] Figure 9 This is a schematic block diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0034] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0035] With the development of artificial intelligence technology, the application of large-scale models is becoming increasingly widespread. Large-scale models are artificial intelligence models with a large number of parameters built by artificial intelligence networks. Examples include large language models (LLM), large-scale visual models, or multimodal large-scale models, as well as content generation models that generate content based on prompt words. Examples include models based on the Transformer architecture or models built based on attention mechanisms.

[0036] Current mainstream large-scale model inference service frameworks, while achieving efficient inference services from different perspectives, generally implement industry-leading inference optimization techniques. These techniques include, for example, flash attention, paged attention, dynamic batching, chunk prefill, and prefix caching. Among them, Flash-Attention technology is an attention algorithm that relies on block computation and high-speed cache optimization to reduce computational overhead by reducing frequent access to video memory; Paged-Attention technology is a video memory management scheme based on key-value cache (KV-Cache), which draws on the idea of ​​virtual memory paging in operating systems to avoid the video memory fragmentation problem in KV-Cache management; Dynamic-Batching technology can reduce the idle time of graphics processing unit (GPU) and improve hardware resource utilization by real-time collection of ready inference requests and dynamic merging of execution batches; Chunk-Prefill technology reduces single inference latency and supports long sequence inference by performing prefill computation in blocks of input sequence; Prefix-Cache technology reduces redundant computation and video memory consumption by caching and reusing shared sequence prefixes.

[0037] Among these techniques, Paged-Attention is an optimization built upon KV-Cache. KV-Cache is an optimization technique used in the autoregressive inference process of the Transformer architecture model. During autoregressive inference, the model generates the next token step by step based on the prompt provided by the user, with each step relying on previously generated tokens. In natural language processing, a token is the basic processing unit after text is segmented by a tokenizer. It can be a character, word, or sub-word fragment. A complete sentence is usually composed of multiple tokens and is the basic unit for the model to understand and generate language. In the model's self-attention mechanism, three vectors are calculated for each token: query (Q), key (K), and value (V). Each time a new token is generated, the model performs a dot product operation between the current query vector and the key vectors of all previous tokens to calculate an attention score, and then performs a weighted sum on the value vector accordingly. This calculation requires frequent access to previous token information. To avoid repeatedly calculating the key and value vectors of all historical lexics when generating new lexics, the inference system can store these already calculated key-value data. When generating the next lexicographical term, only the query, key, and value of the current lexicographical term need to be calculated, and then attention is performed between these values ​​and the cached historical key-value data. This approach significantly reduces the computational complexity of inference from O(N²) to O(N), greatly improving inference performance.

[0038] The KV-Cache storage strategy based on Paged-Attention technology uses "blocks" as the basic unit for fine-grained management on GPU memory (such as Video Random Access Memory, VRAM). In its implementation, the system first logically divides the Key and Value data generated by the Transformer layer from a single inference request into multiple logical blocks. The dimension format of a single logical block can be defined as [paged_block_size, head_dim], where head_dim represents the vector dimension of a single attention head in the model; paged_block_size is a configurable parameter. For example, if set to 128, it means that a single logical block can hold 128 KV-Cache data units (such as Key or Value data). Because the Transformer architecture uses a multi-head attention mechanism, each attention head needs to independently maintain its KV-Cache data. Therefore, the complete KV-Cache data of every 128 units is actually carried by multiple logical blocks, and the total number of these logical blocks is equal to the number of attention heads in the model (num_heads).

[0039] At the physical storage level, a single logical block corresponds to a contiguous physical storage region in the video memory space, and its capacity can accommodate the KV-Cache data of the aforementioned dimensions. Paged-Attention allows multiple contiguous physical storage regions corresponding to a requested KV-Cache data to be discretely distributed in the video memory space. The system can maintain a block table to record the mapping relationship between logical block numbers and physical storage region addresses.

[0040] Figure 1A This is a schematic diagram of storage space partitioning for KV-Cache storage.

[0041] For example, such as Figure 1AAs shown, the system pre-divides the available GPU memory space for storing KV-Cache into several physical storage regions at the block level, logically numbered as Paged Block 0, Paged Block 1, Paged Block 2, ..., Paged Block n. This allows for subsequent location and retrieval of KV-Cache data for a specific token via index logical numbers. When newly generated key and value data need to be stored during inference, available space can be dynamically requested from the free physical storage regions to complete the data storage. Currently, mainstream GPU memory architectures are arranged in a flat, compact form, meaning that the data within each logical block is address-contiguous, and adjacent logical blocks are also address-contiguous in the GPU memory space. For example, as... Figure 1A As shown, according to address continuity, first by row and then by column, the logical blocks are arranged in the physical storage as Paged Block 0, Paged Block 1, Paged Block 2, ..., Paged Block n, that is, the physical and logical arrangement order is consistent.

[0042] The aforementioned KV-Cache management method can achieve convenient indexing in mainstream GPU memory architectures (which adopt a flat, compact arrangement with consistent physical and logical layout). However, when faced with optimized new storage architectures, this continuity-based management method faces severe challenges, significantly increasing the complexity of data management and memory access indexing.

[0043] This disclosure provides at least one embodiment of a storage architecture and its corresponding storage organization method. Unlike traditional tiled compact arrangements, this architecture employs a unified memory architecture (UMA) or a non-unified memory architecture (NUMA) to improve data access efficiency. In a unified memory architecture, all memory is accessed using a unified address; in a non-unified memory architecture, memory partitions correspond to computing cores, which can improve data access efficiency. Furthermore, in this storage architecture (covering single-die or dual-die hardware designs), the continuity of physical addresses is not consistent with logical continuity. In addition, to optimize data access, special tensors are defined for data representation.

[0044] Specifically, for this special tensor, its data elements are divided into units of universal blocks (Ublocks). Data addresses within a single universal block are contiguous, but universal blocks follow specific arrangement rules of column major or row major. This mechanism results in a significant difference between the logical dimension of the data and the actual physical storage contiguousness; that is, logically adjacent (logically numbered adjacent) universal blocks are not physically contiguous in storage.

[0045] Figure 1B This is a schematic diagram of a general block partitioning method under a storage architecture and storage organization method provided in at least one embodiment of the present disclosure.

[0046] For example, such as Figure 1B As shown, taking the column-major arrangement rule (hereinafter also referred to as BLOCK_COL_MAJOR) between general blocks as an example, data is organized according to the address continuity principle of "column first, row second". This makes the actual arrangement order of general blocks in physical storage not linear Ublock 0, Ublock 1, Ublock 2, ..., Ublockm, but rather presents a distribution such as Ublock 0, Ublock 6, ..., Ublock 1, ..., Ublock 2, ..., Ublock5, ..., Ublock m. This misalignment between logical and physical mapping greatly increases the difficulty of data access and indexing, thus triggering a series of technical challenges in development practices.

[0047] Furthermore, each general block contains multiple sub-blocks, and the size of the sub-blocks and the data arrangement within the general block depend on the data type within the sub-blocks.

[0048] Figure 2A This is a schematic diagram of sub-block partitioning under a storage architecture and storage organization method provided in at least one embodiment of the present disclosure.

[0049] For example, such as Figure 2A As shown, each general block consists of four sub-blocks of the same size (Sub-Block 0 to Sub-Block 3) arranged along the column direction. It should be noted that... Figure 2A The number of sub-blocks in each general block shown is merely an example, and this disclosure does not limit the scope of the embodiments.

[0050] Figure 2B This is a schematic diagram of the sub-block data arrangement under the storage architecture and storage organization method provided in at least one embodiment of the present disclosure. Figure 2BThe arrows in the sub-block indicate the column-priority arrangement order of the data elements within the sub-block, that is, arranged sequentially from top to bottom along the column direction, and jumping to the top of the next column when the column is full.

[0051] For example, such as Figure 2B As shown, the size of a sub-block is defined by the number of data elements it can hold in both row and column dimensions. The number of data elements in the row direction is a configurable parameter, for example, it can be set to a fixed value of 32; while the number of data elements in the column direction is dynamically determined based on the data type, and can be calculated using the formula SUBBLOCK_H = 4 / sizeof(Dtype), where Dtype is the data type of the data within the sub-block, and sizeof() represents the operation to obtain the number of bytes occupied by that data type.

[0052] For example, when the data within a sub-block is of type INT8, SUBBLOCK_H = 4 / sizeof(Dtype) = 4 / 1 = 4, forming a structure of 4 rows and 32 columns. The data within a sub-block is arranged in column-major order, filling the current column with its four elements before moving to the next column. Each small block in the diagram represents a data element and occupies one byte.

[0053] For example, when the data within a sub-block is of FP16 data type, SUBBLOCK_H = 4 / sizeof(Dtype) = 4 / 2 = 2, forming a 2-row, 32-column structure. The sub-block is arranged in column-major order, with data filling the current column's two elements first, then moving to the next column. Each small block in the diagram represents a data element, occupying two bytes.

[0054] For example, when the data within a sub-block is of FP32 data type, SUBBLOCK_H = 4 / sizeof(Dtype) = 4 / 4 = 1, forming a 1-row, 32-column structure. The data within the sub-block is arranged in column-major order, but since there is only one row, the arrows within the sub-block indicate the row direction. Each small block in the diagram represents a data element, occupying four bytes.

[0055] Based on the above partitioning logic, the data capacity of the sub-block is set to a fixed 128 bytes, while the data capacity of the general block is a fixed 512 bytes. It should be noted that the data capacities of the sub-blocks and general blocks here are merely examples. In practical applications, those skilled in the art can adjust the above capacity configuration according to the actual storage architecture and specific needs, and this disclosure does not impose any limitations on this.

[0056] Because the general block uses the aforementioned complex data arrangement, the system cannot directly obtain specific data through a simple linear offset when locating it. This complexity of addressing logic further exacerbates the difficulty of data access and restricts inference efficiency.

[0057] This disclosure provides at least one embodiment of a data processing method, a data processing apparatus, an electronic device, and a storage medium.

[0058] The data processing method provided in at least one embodiment of this disclosure includes: receiving a data read / write request carrying logical block index information, wherein the logical block index information is used to indicate the target logical block to which the target data belongs; obtaining the physical address offset of the target logical block in the physical storage space through a data index interface based on the logical block index information; and performing reading or writing of the target data in the physical storage space based on the physical address offset, wherein the physical storage space is used to store data in at least one logical block, and multiple logical blocks with consecutive indexes are mapped to non-consecutive physical address regions in the physical storage space, wherein the data index interface is constructed based on the logical block data arrangement.

[0059] In at least one embodiment of the data processing method provided in this disclosure, a general and efficient indexing operation implementation scheme is proposed. By providing a unified data indexing interface, the underlying data arrangement is encapsulated, and an efficient logical block indexing mechanism is constructed. This supports the accurate retrieval of the physical address of the logical block corresponding to any logical block index identifier in any request, adapting to situations where the physical and logical arrangement orders are inconsistent under a specific storage architecture. Based on this fine-grained addressing capability, the system can flexibly execute efficient KV-Cache data access operations according to specific business needs, thereby significantly accelerating tasks such as the development of artificial intelligence processor operators and data transmission.

[0060] Furthermore, the data indexing interface provided in at least one embodiment of this disclosure also supports indexing of address-contiguous blocks, thereby facilitating quick access to storage space with contiguous addresses in the target logical block and improving data transmission efficiency.

[0061] Figure 3 This is a flowchart illustrating a data processing method provided in at least one embodiment of the present disclosure.

[0062] For example, such as Figure 3 As shown, at least one embodiment of the present disclosure provides a data processing method including the following steps S101 to S103.

[0063] Step S101: Receive a data read / write request carrying logical block index information, which is used to indicate the target logical block to which the target data belongs.

[0064] Step S102: Based on the logical block index information, obtain the physical address offset of the target logical block in the physical storage space through the data index interface.

[0065] Step S103: Based on the physical address offset, perform the reading or writing of the target data in the physical storage space.

[0066] In step S101, the data read / write request can be received from the host side (e.g., a central processing unit (CPU)). An example of a data read / write request could be an inference request for a large-scale model. Such requests not only involve matrix multiplication calculations but also involve frequent KV cache read / write operations, exhibiting significant data access characteristics, and are therefore essentially a data read / write request. The logical block index information is, for example, a logical block identifier (ID), which is the identifier of the logical block (target logical block) corresponding to the physical storage space that the data read / write request needs to access. Specifically, if the data read / write request is a read request, the logical block identifier is used to determine the storage location of the target data; if the data read / write request is a write request, the logical block identifier is used to determine the write location of the target data. For example, a data read / write request can carry multiple logical block index information, and each logical block index information carried by the data read / write request can be recorded in an index information table. The index information table is a data structure used to store the logical block index information carried by the current data read / write request. For example, dividing the final context length generated by a single inference request by paged_block_size will give you the number of logical blocks occupied by that inference request, and the logical block index information of each occupied logical block will be stored in the index information table.

[0067] For example, target data can include at least one of the following: voice data, image data, text data, video data, and biomedical data. For example, target data can be a tensor. A tensor typically refers to a multidimensional array capable of representing various data structures, including scalars (zero-dimensional tensors), vectors (one-dimensional tensors), matrices (two-dimensional tensors), and higher-dimensional arrays. A tensor consists of multiple elements. The specific position of these elements within the tensor can be represented by coordinates. For example, a two-dimensional tensor with a shape of 1×8190 indicates that the tensor has 1 row and 8190 columns. Any element can be accessed based on coordinates (i, j), where i is the row coordinate value and j is the column coordinate value. For example, rows can represent the batch dimension, and columns can represent the height dimension. For multidimensional tensors, the number and order of coordinates depend on the tensor's dimensions and shape.

[0068] For example, the target data can be key-value cache (KV cache) data, which is essentially a set of tensors consisting of key tensors and value tensors; the target data can also be only key tensors or only value tensors. The tensor shape of the key tensors and value tensors can be, for example, [num_tokens, num_heads, head_dim], where num_tokens represents the length of the current context sequence, i.e., the number of input or generated tokens, num_heads represents the number of attention heads, and head_dim represents the vector dimension of each attention head.

[0069] In step S102, the physical storage space is used to store data in at least one logical block, and multiple logical blocks with consecutive indexes are mapped to non-consecutive physical address regions in the physical storage space.

[0070] For example, physical storage space can be deployed on-chip or off-chip storage media in various artificial intelligence acceleration devices. Acceleration devices can include: Graphics Processing Units (GPUs), General-purpose Graphics Processing Units (GPGPUs), Tensor Processing Units (TPUs), Deep Learning Processing Units (DPUs), Accelerated Processing Units (APUs), Neural Network Processing Units (NPUs), etc. Storage media can include Video Random Access Memory (VRAM), High Bandwidth Memory (HBM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc.

[0071] For example, after the inference service framework starts, the system can allocate the available remaining storage resources in a specified proportion according to preset configuration parameters, as dedicated physical storage space for KV-Cache. For example, the configuration parameter can be set to 0.9, indicating that 90% of the remaining storage resources will be allocated to KV-Cache.

[0072] For example, physical storage space can be used to store data from multiple logical blocks. For instance, physical storage space can be organized as a multi-dimensional logical storage space, which is divided into multiple logical blocks with contiguous indexes. Specifically, physical storage space can be abstracted into a multi-dimensional tensor structure, i.e., logical storage space, adapted to the characteristics of deep learning operators or other uses (such as high-performance computing or distributed resource scheduling), through address mapping and data layout transformation. This logical storage space is divided into multiple logical blocks with contiguous indexes, numbered Paged Block 0, Paged Block 1, Paged Block 2, ..., Paged Block n, where the value of n depends on the size of the logical block and the size of the logical storage space.

[0073] In some examples, the physical storage space can be logically organized as a three-dimensional spatial structure [logic_N, logic_H, logic_W], where the triple defines the size of the logical storage space. The system can use the Paged-Attention mechanism described above to set (paged_block_H, paged_block_W) as the size of the logical block, and perform regular segmentation on the two-dimensional plane [logic_H, logic_W] in each batch (corresponding to logic_N), thereby generating a series of logical blocks of the same size. These blocks are then uniformly numbered according to the following order: first, traversing within a single batch from left to right and from top to bottom, and then traversing different batches sequentially. Here, paged_block_H is the size of the logical block in the height dimension, and paged_block_W is the size of the logical block in the width dimension, representing the number of data elements that the logical block can accommodate in the corresponding dimension.

[0074] The size of the logic block (paged_block_H, paged_block_W) and the size of the logical storage space (logic_N, logic_H, logic_W) are configurable. For example, the size of the logic block can be configured based on model characteristics (e.g., the vector dimension head_dim of each attention head) and storage organization; the size of the logical storage space can be configured based on the size of the logic block, for example, setting logic_H to an integer multiple of paged_block_H and logic_W to an integer multiple of paged_block_W.

[0075] It should be noted that the above-described three-dimensional logical storage space is merely an example, and the dimensions of the logical storage space are not limited to this. Depending on actual needs, physical storage space can be flexibly abstracted and organized into one-dimensional, two-dimensional, or higher-dimensional logical space structures, and this disclosure does not impose any limitations on this.

[0076] In the storage architecture and storage organization method provided in at least one embodiment of this disclosure, multiple logical blocks with consecutive indexes are mapped to non-consecutive physical address regions in the physical storage space. Specifically, for logically adjacent PagedBlock i and Paged Block i+1 (0 ≤ i < n), the physical storage regions of Paged Block i and Paged Block i+1 are not contiguous in the physical address space. This mapping relationship allows logically contiguous data blocks to be flexibly stored in any available location on the physical storage medium, thereby effectively utilizing fragmented storage space.

[0077] In step S102, the data indexing interface is constructed based on the logical block data arrangement method. The logical block data arrangement method defines the organization rules of logical blocks in the physical storage space, which may include the arrangement of data within a logical block in the physical storage space, or the distribution of multiple logical blocks in the physical storage space.

[0078] In step S102, even if the underlying storage medium's architecture is not arranged in a flat, compact manner, the data indexing interface can still provide a concise function interface to the upper-layer caller by encapsulating the underlying logical index-physical address translation logic. The caller only needs to pass in the logical block index information (such as the logical block ID), and the interface can automatically complete the translation from logical index to physical address. This design allows the upper-layer caller to be unaware of the physical architecture of the underlying storage medium, thus leveraging the space utilization advantages of non-contiguous storage while still using simple and intuitive operational semantics for data access.

[0079] It should be noted that "through the data index interface" mentioned in step S102 refers to the access operation of the target data by means of the interface from the perspective of the upper-level caller. It reflects the data location service based on logical index provided by the interface, rather than the specific underlying implementation details.

[0080] In step S103, based on the obtained physical address offset, the physical address corresponding to the target data can be calculated, so as to write the target data to the physical address or read the target data from the physical address.

[0081] In some examples, the physical address offset is used to represent the starting position of the target logical block in physical storage space and can be measured by the number of data elements. The physical address corresponding to the target data can be calculated using the following formula:

[0082] Physical address = Starting address of physical storage space + (Physical address offset × Number of bytes occupied by a single data element)

[0083] In the data processing method provided in at least one embodiment of this disclosure, a unified data indexing interface is provided to encapsulate the underlying data arrangement, constructing an efficient logical block indexing mechanism. This mechanism supports the accurate retrieval of the physical address of the logical block corresponding to any logical block index identifier in any request, adapting to situations where the physical and logical arrangement orders are inconsistent under a specific storage architecture. Based on this fine-grained addressing capability, the system can flexibly execute efficient KV-Cache data access operations according to specific business needs, thereby significantly accelerating tasks such as the development of artificial intelligence processor operators and data transmission.

[0084] In some examples, data within the same logical block is not distributed contiguously in physical storage space; that is, at least some logically adjacent data elements within the same logical block are not adjacent in physical storage space. In other words, a single logical block can be divided into multiple address-contiguous blocks, where data within the same address-contiguous block is distributed contiguously in physical storage space, and different address-contiguous blocks are mapped to non-contiguous physical address regions in physical storage space.

[0085] For example, each logical block can include multiple general-purpose blocks (Ublocks) as described above. The number of general-purpose blocks included in each logical block can be determined based on the pre-configured logical block size and general-purpose block size. If a single logical block covers multiple general-purpose blocks in the row direction, and the general-purpose block columns within the logical block constitute an address-contiguous block as described above, because the data within a general-purpose block column is stored contiguously in physical storage space, but different general-purpose block columns are not contiguous in physical address space.

[0086] Figure 4 This is a schematic diagram of a logical block data arrangement method provided in at least one embodiment of the present disclosure.

[0087] In this example, assume the stored data type is INT8, and the sub-block size (SUBBLOCK_H, SUBBLOCK_W) is configured as (4, 32). Each general block is set to include four sub-blocks, therefore the general block size (Ublock_H, Ublock_W) is (4×4, 32), which is also (16, 32). General blocks are arranged according to a column-major order.

[0088] Assume the size of the logical memory space (logic_N, logic_H, logic_W) is (1, 128×3, 128×4), and the size of the logical block (paged_block_H, paged_block_W) is set to (128, 128). In this case, paged_block_W is an integer multiple of Ublock_W (specifically 4), and paged_block_H is an integer multiple of Ublock_H (specifically 8).

[0089] For example, such as Figure 4 As shown, each logical block covers 4 general-purpose blocks in the row direction and 8 general-purpose blocks in the column direction, for a total of 32 general-purpose blocks, carrying 128×128 INT8 data. Taking Paged Block 0 as an example, since the general-purpose blocks follow a column-first arrangement rule, the physical storage area of ​​Paged Block 0 is not contiguous with the physical storage area of ​​the index-contiguous Paged Block 1 in the physical address space. Paged Block 0 includes 4 general-purpose block columns, each consisting of 8 general-purpose blocks. The data within a single general-purpose block column is stored contiguously in the physical storage space, but different general-purpose block columns are not contiguous in the physical address space.

[0090] In the above example, to simplify address calculation and mapping logic, the logical block size is set to an integer multiple of the general block size. That is, the logical block size in the height dimension is set to an integer multiple of the general block size in the height dimension, and the logical block size in the width dimension is set to an integer multiple of the general block size in the width dimension. It should be noted that the embodiments of this disclosure are not limited to this. Depending on the actual application scenario's requirements for storage granularity or processing precision, the logical block size can also be configured to a non-integer multiple of the general block size to achieve finer-grained partitioning and control.

[0091] In the example above, if described at the sub-block level, each logical block comprises multiple sub-blocks of the same size. Data within the same sub-block is stored contiguously in physical storage space using a column-major order, and the sub-block size is determined by the data type within the sub-block. This approach allows logical blocks to contain incomplete general blocks (e.g., containing three sub-blocks), enabling finer-grained data management and storage allocation.

[0092] Figure 5 Another flowchart of a data processing method provided for at least one embodiment of this disclosure.

[0093] An example of step S102 includes performing the following operations using a data indexing interface. For ease of description, these operations are referred to as steps S201 to S202, respectively. Figure 5 As shown.

[0094] It should be noted that in this example, "perform the following operations using the data indexing interface" refers to the specific implementation of the interface at the underlying level; that is, the following operations are encapsulated within the interface. In other words, the general data indexing interface encapsulates the actual indexing logic for a specific logical block data arrangement, including specific implementations such as coordinate calculation and address offset calculation.

[0095] Step S201: Obtain the first coordinates of the target logical block in the logical storage space based on the logical block index information.

[0096] For example, the first coordinate is a physical storage-independent logical coordinate used to represent the relative position of the target logical block in the logical storage space. In some examples, the first coordinate can be the starting coordinate of the target logical block (e.g., defined as the coordinate of the top-left vertex of the target logical block in the case of a two-dimensional logical block).

[0097] Since the logical storage space is divided into multiple logical blocks according to preset rules and numbered in a fixed order, the first coordinate of the target logical block in the logical storage space can be obtained by parsing the logical block index information through mapping algorithms or querying mapping tables.

[0098] For example, the mapping table can be a pre-built index table that records the mapping relationship between the starting coordinates of each logical block and the logical block index information (logical block identifier), so that the starting coordinates corresponding to a given logical block identifier can be obtained directly by querying the mapping table.

[0099] For example, the mapping algorithm can be based on the proportional relationship between the size of the logical storage space and the size of the logical block, transforming a one-dimensional logical block index into multi-dimensional logical coordinates through coordinate transformation. Correspondingly, an example of step S201 may include: obtaining the first coordinates of the target logical block in the logical storage space based on the logical block index information, combined with the size of the logical storage space and the size of the logical block.

[0100] Step S202: Based on the first coordinate and combined with the logical block data arrangement, obtain the physical address offset corresponding to the first coordinate, and use it as the physical address offset of the target logical block in the physical storage space.

[0101] The first coordinates obtained through step S201 are logical coordinates. Step S202 maps these logical coordinates to their actual locations in physical storage space. This process depends on the arrangement of data within the logical block in the physical storage space. When the first coordinate represents the starting coordinates of the target logical block, the physical address offset corresponding to the first coordinate represents the starting position of the target logical block in the physical storage space, which can be measured by the number of data elements.

[0102] For example, one example of step S201 may include steps S2011 to S2014.

[0103] Step S2011: Based on the size of the logical storage space and the size of the logical block, obtain the number of logical blocks in the first dimension and the second dimension of the logical storage space, respectively.

[0104] For example, in step S2011, the number of logical blocks in the first dimension of the logical storage space can be obtained based on the first dimension size of the logical storage space and the first dimension size of the logical block; and the number of logical blocks in the second dimension of the logical storage space can be obtained based on the second dimension size of the logical storage space and the second dimension size of the logical block.

[0105] For example, the number of logical blocks in the first dimension can be obtained by dividing the first dimension of the logical storage space by the first dimension of the logical block; the number of logical blocks in the second dimension can be obtained by dividing the second dimension of the logical storage space by the second dimension of the logical block.

[0106] For example, the first and second dimensions can be the two lowest (innermost) dimensions in a multidimensional space. Taking a three-dimensional logical storage space as an example, the size of this space is represented by (logic_N, logic_H, logic_W). In this example, the first dimension is defined as W (width direction), the second dimension as H (height direction), and the third dimension as N. The number of logical blocks w_blocks in the W dimension and the number of logical blocks h_blocks in the H dimension can be calculated using the following formulas:

[0107] w_blocks = logic_W / paged_block_W,

[0108] h_blocks = logic_H / paged_block_H,

[0109] Where logic_W represents the W-dimensional size of the logical storage space, logic_H represents the H-dimensional size of the logical storage space, paged_block_W is the W-dimensional size of the logical block, and paged_block_H is the H-dimensional size of the logical block.

[0110] It should be noted that the designation of the first, second, and third dimensions as W, H, and N dimensions respectively in this embodiment is merely illustrative and does not constitute a limitation on the technical solution of this embodiment. In other possible implementations, the first, second, and third dimensions may also be configured as any one of N, H, or W dimensions, or correspond to other types of dimensions, depending on actual needs or data arrangement rules.

[0111] Step S2012: Based on the number of logical blocks and logical block index information in the first and second dimensions, obtain the third dimension coordinates, the first dimension logical block index, and the second dimension logical block index of the target logical block.

[0112] For example, the first-dimensional logical block index represents the sequence number of the target logical block in the first dimension of the logical storage space, and the second-dimensional logical block index represents the sequence number of the target logical block in the second dimension of the logical storage space. Assume there are a1 logical blocks in the first dimension and b1 logical blocks in the second dimension. A first-dimensional logical block index of i indicates that the target logical block is the (i+1)th logical block in the first dimension, and a second-dimensional logical block index of j indicates that the target logical block is the (j+1)th logical block in the first dimension, where 0 ≤ i < a1 and 0 ≤ j < b1.

[0113] For example, one example of "obtaining the third-dimensional coordinates based on the number of logical blocks and logical block index information in the first and second dimensions" in step S2012 may include: using the logical block index information to perform an integer division operation on the product of the number of logical blocks in the first and second dimensions to obtain the third-dimensional coordinates.

[0114] For example, taking the three-dimensional logical storage space described above as an example, we define the first dimension as W, the second dimension as H, and the third dimension as N. The N-dimensional coordinates coord_n can be calculated using the following formula:

[0115] hw_blocks = h_blocks × w_blocks,

[0116] coord_n = page_block_id / hw_blocks,

[0117] Where w_blocks represents the number of logical blocks in the W dimension, h_blocks represents the number of logical blocks in the H dimension, paged_block_id represents the logical block identifier, and hw_blocks represents the product of the number of logical blocks in the W dimension and the number of logical blocks in the H dimension, which is the total number of logical blocks in the HW plane.

[0118] For example, one example of step S2012, "obtaining the first-dimensional logical block index and the second-dimensional logical block index of the target logical block based on the number of logical blocks and logical block index information under the first and second dimensions," may include the following steps S2012a to S2012c.

[0119] Step S2012a: Use the logical block index information to perform a modulo operation on the product of the number of logical blocks in the first dimension and the second dimension to obtain the first intermediate value.

[0120] Step S2012b: Use the first intermediate value to perform a modulo operation on the number of logical blocks in the first dimension to obtain the logical block index of the first dimension.

[0121] Step S2012c: Use the first intermediate value to perform an integer division operation on the number of logical blocks in the first dimension to obtain the logical block index in the second dimension.

[0122] For example, taking the three-dimensional logical storage space described above as an example, we define the first dimension as W, the second dimension as H, and the third dimension as N. The logical block index block_id_w of the W dimension and the logical block index block_id_h of the H dimension can be calculated using the following formulas:

[0123] block_id_w = (paged_block_id % hw_blocks) % w_blocks,

[0124] block_id_h = (paged_block_id % hw_blocks) / w_blocks,

[0125] Where w_blocks represents the number of logical blocks in the W dimension, h_blocks represents the number of logical blocks in the H dimension, paged_block_id represents the logical block identifier, and hw_blocks represents the product of the number of logical blocks in the W dimension and the number of logical blocks in the H dimension.

[0126] In step S2012a, one example of the first intermediate value is the calculation result of (paged_block_id % hw_blocks).

[0127] Step S2013: Based on the logical block size, the first-dimensional logical block index, and the second-dimensional logical block index, obtain the first-dimensional coordinates and the second-dimensional coordinates.

[0128] For example, in step S2013, the first dimension coordinates can be obtained based on the first dimension size and the first dimension logical block index of the logical block; and the second dimension coordinates can be obtained based on the second dimension size and the second dimension logical block index of the logical block.

[0129] For example, the first-dimensional coordinates can be obtained by calculating the product of the first-dimensional size and the first-dimensional logical block index; the second-dimensional coordinates can be obtained by calculating the product of the second-dimensional size and the second-dimensional logical block index.

[0130] For example, taking the three-dimensional logical storage space described above as an example, we define the first dimension as W, the second dimension as H, and the third dimension as N. The coordinates of the W dimension (coord_w) and the H dimension (coord_h) can be calculated using the following formulas:

[0131] coord_w = block_id_w × paged_block_W,

[0132] coord_h = block_id_h × paged_block_H,

[0133] Where block_id_w represents the logical block index in the W dimension, block_id_h represents the logical block index in the H dimension, paged_block_W is the W dimension size of the logical block, and paged_block_H is the H dimension size of the logical block.

[0134] Step S2014: Combine the first-dimensional coordinates, the second-dimensional coordinates, and the third-dimensional coordinates to obtain the first coordinate.

[0135] For example, after determining the first, second, and third dimension coordinates, the three coordinate components can be combined into a complete three-dimensional coordinate system according to the dimensional arrangement order of the logical storage space. Corresponding to the example above, the first coordinate can be represented as (coord_n, coord_h, coord_w).

[0136] For example, one example of step S202 may include steps S2021 to S2023.

[0137] Step S2021: Based on the first coordinates and the size of the logical storage space, obtain the first physical address offset.

[0138] For example, in step S2021, the first physical address offset can be obtained based on the third dimension coordinate in the first coordinate, the first dimension size and the second dimension size of the logical storage space.

[0139] For example, the first physical address offset can be obtained by multiplying the third-dimensional coordinate, the first-dimensional size of the logical storage space, and the second-dimensional size of the logical storage space.

[0140] For example, taking the three-dimensional logical storage space described above as an example, we define the first dimension as W, the second dimension as H, and the third dimension as N. The first physical address offset n_offset can be calculated using the following formula:

[0141] n_offset = logic_H × logic_W × coord_n,

[0142] Where coord_n is the N-dimensional coordinate, logic_H is the H-dimensional size of the logical storage space, and logic_W is the W-dimensional size of the logical storage space.

[0143] Step S2022: Based on the sub-block size and the first coordinate, and combined with the size of the logical storage space, obtain the second physical address offset.

[0144] For example, in step S2022, since the arrangement of data within the logic block in the physical storage space is known, as well as the distribution of multiple logic blocks in the physical storage space, the second physical address offset corresponding to the first coordinate can be determined at the granularity of the sub-blocks with a specific arrangement order within the logic block. That is, the address offset in the two-dimensional plane [logic_H, logic_W].

[0145] For example, one example of step S2022 may include steps S2022a to S2022c.

[0146] Step S2022a: Determine the first sub-address offset based on the first dimension coordinates in the first coordinate system, the second dimension size of the logical storage space, and the first dimension size of the sub-block.

[0147] For example, the first dimension coordinate can be used to divide the first dimension size of the sub-block to obtain the first intermediate result. Then, the product of the first intermediate result, the second dimension size of the logical storage space, and the first dimension size of the sub-block can be calculated to obtain the first sub-address offset.

[0148] Step S2022b: Determine the second sub-address offset based on the second dimension coordinate in the first coordinate, the first dimension size and the second dimension size of the sub-block.

[0149] For example, you can first use the second-dimensional coordinates to perform an integer division operation on the second-dimensional size of the sub-block to obtain the second intermediate result, and then calculate the product of the second intermediate result, the first-dimensional size of the sub-block, and the second-dimensional size of the sub-block to obtain the second sub-address offset.

[0150] Step S2022c: Obtain the second physical address offset based on the first sub-address offset and the second sub-address offset.

[0151] For example, the first sub-address offset and the second sub-address offset can be added together to obtain the second physical address offset.

[0152] Taking the three-dimensional logical storage space described above as an example, we define the first dimension as W, the second dimension as H, and the third dimension as N. The first sub-address offset_1, the second sub-address offset_2, and the second physical address offset_hw_offset can be calculated using the following formula:

[0153] offset_1 = (coord_w / SUBBLOCK_W) × (logic_H × SUBBLOCK_W),

[0154] offset_2 = (coord_h / SUBBLOCK_H) × SUBBLOCK_HW,

[0155] hw_offset = offset_1+offset_2,

[0156] Wherein, coord_w is the W-dimensional coordinate, coord_h is the H-dimensional coordinate, logic_H is the H-dimensional size of the logical storage space, SUBBLOCK_W is the W-dimensional size of the sub-block, SUBBLOCK_H is the H-dimensional size of the sub-block, and SUBBLOCK_HW is the product of the W-dimensional size and the H-dimensional size of the sub-block, which is also the number of data elements in a single sub-block.

[0157] In some examples, the logical block size is not an integer multiple of the sub-block size. Another example of step S2022 may include steps S2022a to S2022b and steps S2022d to S2022e as described above.

[0158] Step S2022d: Determine the third sub-address offset based on the first and second dimension coordinates in the first coordinate system, and the first and second dimension dimensions of the sub-block.

[0159] For example, the first intermediate result can be obtained by taking the first dimension of the sub-block as a modulo, and the third intermediate result can be obtained by taking the second dimension of the sub-block as a modulo, and the product of the second intermediate result and the second dimension of the sub-block can be calculated and summed with the third intermediate result to obtain the third sub-address offset.

[0160] Step S2022e: Obtain the second physical address offset based on the first sub-address offset, the second sub-address offset, and the third sub-address offset.

[0161] For example, the first sub-address offset, the second sub-address offset, and the third sub-address offset can be added together to obtain the second physical address offset.

[0162] Based on the above example, the third sub-address offset_3 and the second physical address offset_hw_offset can be calculated using the following formula:

[0163] offset_3 = (coord_w % SUBBLOCK_W) × SUBBLOCK_H + coord_h % SUBBLOCK_H,

[0164] hw_offset = offset_1+offset_2+offset_3,

[0165] Step S2023: Based on the first physical address offset and the second physical address offset, obtain the physical address offset corresponding to the first coordinate.

[0166] For example, the first physical address offset and the second physical address offset can be added together to obtain the physical address offset corresponding to the first coordinate.

[0167] The data processing method provided in at least one embodiment of this disclosure may further include step S104.

[0168] Step S104: Obtain at least one address contiguous block in the target logical block through the data index interface, wherein the data in the same address contiguous block is continuously distributed in the physical storage space, and different address contiguous blocks are mapped to non-contiguous physical address regions in the physical storage space.

[0169] In addition to obtaining the physical address offset of the target logical block in the physical storage space, the data indexing interface provided in at least one embodiment of this disclosure also supports directly obtaining address contiguous blocks in the target logical block, thereby facilitating fast access to address contiguous storage space in the target logical block. Address contiguous blocks have already been introduced above and will not be repeated here.

[0170] One example of step S104 includes performing the following operations using a data indexing interface. For ease of description, each operation will be referred to as steps S203 to S204.

[0171] Step S203: Determine the number of consecutive address blocks in the target logical block based on the sub-block size and the logical block size.

[0172] Step S204: Based on the sub-block size, logical block size, and logical storage space size, determine the physical address offset and length of at least one address contiguous block.

[0173] Based on the above description, if a single logical block covers multiple general blocks in the row direction, then each general block column in the logical block constitutes a contiguous block because the data inside a single general block column is stored contiguously in the physical storage space, but different general block columns are not contiguous in the physical address.

[0174] Since a general block is composed of sub-blocks, if we take sub-blocks as the granularity, each sub-block column in the logical block constitutes a contiguous address block. Therefore, in step S203, the number of contiguous address blocks in the target logical block can be determined based on the first dimension of the sub-blocks and the first dimension of the logical block. For example, the number of contiguous address blocks in the target logical block can be obtained by dividing the first dimension of the logical block by the first dimension of the sub-blocks.

[0175] In step S204, the physical address offset of at least one address contiguous block can be determined based on the second dimension of the logical storage space and the first dimension of the sub-block; the length of at least one address contiguous block, i.e. the number of data elements in a single address contiguous block, can be determined based on the second dimension of the logical block and the first dimension of the sub-block.

[0176] For example, the physical address offset of at least one address contiguous block can be determined based on the product of the second dimension of the logical storage space and the first dimension of the sub-block; the length of at least one address contiguous block can be determined based on the product of the second dimension of the logical block and the first dimension of the sub-block. For example, the physical address offset of the address contiguous block can be the offset of the starting address of the address contiguous block relative to the physical address of the top-left corner of the target logical block.

[0177] For example, the data indexing interface can return a queue of contiguous address blocks to the caller, where the k-th element of the queue is {the physical address offset of the contiguous address block k, the length of the contiguous address block k}, and the value of k is not greater than the number of contiguous address blocks in the target logical block.

[0178] In at least one embodiment of the data processing method provided in this disclosure, a unified data indexing interface is provided to index contiguous address blocks, thereby facilitating rapid access to contiguous storage space within the target logical block and improving data transmission efficiency. This approach avoids the additional addressing overhead caused by non-contiguous access, significantly improving the efficiency of spatial locality utilization during data transmission, and is particularly suitable for scenarios requiring batch reading of contiguous data blocks.

[0179] It should also be noted that the execution order of the various steps of the data processing method in the various embodiments of this disclosure is not limited. Although the execution process of each step has been described in a specific order above, this does not constitute a limitation on the embodiments of this disclosure. The various steps in the data processing method can be executed serially or in parallel, which can be determined according to actual needs.

[0180] For example, compared to the above description, the data processing method provided in at least one embodiment of this disclosure may include more or fewer steps, and the embodiments of this disclosure do not limit this.

[0181] The following is a pseudocode example of a data processing method provided in at least one embodiment of this disclosure, which is an example of step S201 described above:

[0182]

[0183] The following is another pseudocode example of the data processing method provided in at least one embodiment of this disclosure, which is an example of step S202 described above:

[0184]

[0185] The following is another pseudocode example of the data processing method provided in at least one embodiment of this disclosure, which is an example of steps S203 to S204 above:

[0186]

[0187] For the meaning of the variables in the pseudocode examples above, please refer to the description of the meaning of each variable in the formula in the above embodiment description; for the specific description of each pseudocode example, please refer to the description of each step of the data processing method above, which will not be repeated here.

[0188] It should be noted that the sub-block size in the above pseudocode is only an example. In practical applications, those skilled in the art can adjust the above sub-block size according to the actual storage architecture and specific requirements. This disclosure does not limit this.

[0189] The following describes a method for obtaining data using at least one embodiment of the data indexing interface provided in this disclosure. Figure 4 The example shows the physical address offset of the target logical block and an example of address contiguous block segmentation.

[0190] In this example, the dimensions of the logical storage space (logic_N, logic_H, logic_W) are (1, 128×3, 128×4), and the dimensions of the logical blocks (paged_block_H, paged_block_W) are (128, 128). Assume the logical block index information paged_block_id carried in the data read / write request is 9, meaning the target logical block is... Figure 4 Paged Block 9 in the middle.

[0191] In this example, the number of logical blocks in the W dimension, w_blocks = logic_W / paged_block_W = 512 / 128 = 4; the number of logical blocks in the H dimension, h_blocks = logic_H / paged_block_H = 384 / 128 = 3; the total number of logical blocks in the HW plane, hw_blocks = h_blocks × w_blocks = 3 × 4 = 12; the N-dimensional coordinates of the target logical block, coord_n = page_block_id / hw_blocks = 9 / 12 = 0; the H-dimensional logical block index of the target logical block, block_id_h = (paged_block_id % hw_blocks) / w_blocks = (9 % 12) / 4 = 2, meaning the target logical block is the 3rd logical block in the H dimension; the W-dimensional logical block index of the target logical block, block_id_w = (paged_block_id % hw_blocks) % w_blocks = (9 % 12) / 4 = 2. 12) % 4 = 1, meaning the target logical block is the second logical block in the W dimension; the H dimension coordinates of the target logical block are coord_h = block_id_h × paged_block_H = 2 × 128 = 256, and the W dimension coordinates are coord_w = block_id_w × paged_block_W = 1 × 128. Therefore, the starting coordinates of the target logical block Paged Block 9 are (0, 256, 128).

[0192] In this example, the stored data type is INT8, the sub-block size (SUBBLOCK_H, SUBBLOCK_W) is (4, 32), the number of data elements in a single sub-block is SUBBLOCK_HW = SUBBLOCK_W × SUBBLOCK_H = 4 × 32 = 128, the first physical address offset n_offset = logic_H × logic_W × coord_n = 0, the first sub-address offset offset_1 = (coord_w / SUBBLOCK_W) × (logic_H × SUBBLOCK_W) = (128 / 32) × (384 × 32) = 49152, which can also be understood as the address space occupied by the data elements included in Paged Blocks 0, 4, and 8; the second address offset offset_2 = (coord_h / SUBBLOCK_H) × SUBBLOCK_HW = (256 / 4) × 128 = 8192, the second physical address offset hw_offset = offset_1 + offset_2 = 49152 + 8192 = 57344, the physical address offset corresponding to the first coordinate offset = n_offset + hw_offset = 0 + 57344 = 57344.

[0193] In this example, the number of contiguous address blocks included in the target logical block is num_chunk = paged_block_W / SUBBLOCK_W = 128 / 32 = 4, the length of the contiguous address blocks is len_chunk = paged_block_H × SUBBLOCK_W = 128 × 32 = 4096, the physical address offset of contiguous address block 1 is 0, the physical address offset of contiguous address block 2 is 1 × logic_H × SUBBLOCK_W = 384 × 32 = 12288, the physical address offset of contiguous address block 3 is 2 × logic_H × SUBBLOCK_W = 2 × 384 × 32 = 24576, and the physical address offset of contiguous address block 4 is 3 × logic_H × SUBBLOCK_W = 3 × 384 × 32 = 36864. The address returned to the caller is in a contiguous block queue of ({0, 4096}, {12288, 4096}, {24576, 4096}, {36864, 4096}).

[0194] In the data processing method provided in at least one embodiment of this disclosure, an efficient logical block indexing mechanism and an indexing mechanism for continuous address partitioning within logical blocks are constructed by providing a unified data indexing interface. The system can flexibly execute efficient KV-Cache data access operations according to specific business needs.

[0195] For example, when performing kernel calculations, the physical storage location of the specified KV-Cache can be directly located based on the logical block identifier, enabling the computing core to directly perform efficient data read and write operations on the target storage area, thereby improving the data read and write efficiency during the attention mechanism calculation process.

[0196] For example, in scenarios where video memory resources are limited, when it is necessary to dump the existing KV Cache to CPU memory, the specific physical location of all data blocks corresponding to the specified request in video memory can be located based on the logical block identifier. Combined with the address contiguous block information within each logical block, the storage area with contiguous addresses can be identified. Then, efficient data copying and migration operations can be performed in units of contiguous address blocks, thereby improving dumping efficiency and reducing memory access overhead.

[0197] For example, the Prefill-Decode (PD) separation technology divides the inference process into two logically independent stages: the Prefill stage and the Decode stage. Based on their respective computational characteristics, resource scheduling and system optimization are performed separately, thereby improving overall inference efficiency. In distributed business scenarios with PD separation, the KV-Cache generated in the Prefill stage needs to be sent to other computing nodes. At this time, the specific physical location of all data blocks corresponding to a given request in the video memory can be located based on the logical block identifier. Combined with the address contiguous block information within each logical block, data transmission is performed, supporting optimization of the data packaging and unpacking parsing process.

[0198] Figure 6 This is a schematic block diagram of a data processing apparatus provided for at least one embodiment of the present disclosure.

[0199] The data processing device may be a processor or be disposed in a processor. The processor may include a graphics processor, a general-purpose graphics processor, a tensor processor, a deep learning processor, an accelerator processor, a neural network processor, etc. Of course, the embodiments of this disclosure are not limited to this, and the processor may also be any other type of processor.

[0200] For example, such as Figure 6 As shown, the task scheduling device 600 provided in at least one embodiment of this disclosure includes a receiving module 601, an acquisition module 602, and a read / write module 603.

[0201] For example, the receiving module 601 is configured to receive data read / write requests carrying logical block index information, which is used to indicate the target logical block to which the target data belongs.

[0202] For example, the acquisition module 602 is configured to obtain the physical address offset of the target logical block in the physical storage space through the data index interface based on the logical block index information.

[0203] For example, the read / write module 603 is configured to perform reading or writing of target data in physical storage space based on physical address offset.

[0204] For example, physical storage space is used to store data in at least one logical block. Multiple consecutive logical blocks are mapped to non-consecutive physical address regions in the physical storage space. The data indexing interface is built based on the logical block data arrangement.

[0205] In some examples, data within the same logical block is not distributed contiguously in the physical storage space.

[0206] In some examples, physical storage space is organized into multidimensional logical storage space, which is divided into multiple logical blocks with contiguous indexes.

[0207] In some examples, the acquisition module includes a first acquisition unit and a second acquisition unit. The first acquisition unit is configured to acquire the first coordinates of the target logical block in the logical storage space based on the logical block index information; the second acquisition unit is configured to acquire the physical address offset corresponding to the first coordinates, combined with the logical block data arrangement, as the physical address offset of the target logical block in the physical storage space.

[0208] In some examples, the first acquisition unit is further configured to: based on the logical block index information, and in combination with the size of the logical storage space and the size of the logical block, acquire the first coordinates of the target logical block in the logical storage space.

[0209] In some examples, the first acquisition unit is further configured to: acquire the number of logical blocks in the logical storage space in the first and second dimensions, respectively, based on the size of the logical storage space and the size of the logical blocks; acquire the third-dimensional coordinates, the first-dimensional logical block index, and the second-dimensional logical block index of the target logical block, based on the number of logical blocks in the first and second dimensions and the logical block index information, wherein the first-dimensional logical block index and the second-dimensional logical block index represent the arrangement sequence number of the target logical block in the first and second dimensions of the logical storage space, respectively; acquire the first-dimensional coordinates and the second-dimensional coordinates based on the logical block size, the first-dimensional logical block index, and the second-dimensional logical block index; and combine the first-dimensional coordinates, the second-dimensional coordinates, and the third-dimensional coordinates to obtain the first coordinates.

[0210] In some examples, each logical block comprises multiple sub-blocks of the same size, and the data in the same sub-block is stored contiguously in the physical storage space in column-major order. The size of the sub-block is determined according to the data type of the data in the sub-block.

[0211] In some examples, the second acquisition unit is further configured to: acquire a first physical address offset based on the first coordinate and the size of the logical storage space; acquire a second physical address offset based on the sub-block size and the first coordinate and the size of the logical storage space; and acquire the physical address offset corresponding to the first coordinate based on the first physical address offset and the second physical address offset.

[0212] In some examples, the second acquisition unit is further configured to acquire the first physical address offset based on the third-dimensional coordinate in the first coordinate, the first-dimensional size and the second-dimensional size of the logical storage space.

[0213] In some examples, the second acquisition unit is further configured to: determine a first sub-address offset based on the first dimension coordinates in the first coordinate system, the second dimension size of the logical storage space, and the first dimension size of the sub-block; determine a second sub-address offset based on the second dimension coordinates in the first coordinate system, the first dimension size of the sub-block, and the second dimension size of the sub-block; and acquire a second physical address offset based on the first sub-address offset and the second sub-address offset.

[0214] In some examples, the acquisition module is further configured to acquire at least one address contiguous block in the target logical block through a data indexing interface, wherein data in the same address contiguous block is continuously distributed in the physical storage space, and different address contiguous blocks are mapped to non-contiguous physical address regions in the physical storage space.

[0215] In some examples, the acquisition module also includes a third acquisition unit. The third acquisition unit is configured to determine the number of address contiguous blocks in the target logical block based on the sub-block size and the logical block size; and to determine the physical address offset and length of at least one address contiguous block based on the sub-block size, the logical block size, and the size of the logical storage space.

[0216] In some examples, the target data includes key-value cached data.

[0217] It should be noted that the above-mentioned modules can be implemented by software, hardware, firmware or any combination thereof. For example, the receiving module can be implemented as a receiving circuit, the acquisition module can be implemented as an acquisition circuit, and the read-write module can be implemented as a read-write circuit. The embodiments of this disclosure do not limit the specific implementation of these modules.

[0218] It should be understood that the data processing apparatus provided in at least one embodiment of this disclosure can be used to implement the aforementioned data processing method and can also achieve similar technical effects as the aforementioned data processing method, which will not be elaborated here.

[0219] It should be noted that in the embodiments of this disclosure, the data processing device may include more or fewer modules or units, and the connection relationship between the various modules or units is not limited and can be determined according to actual needs. The specific configuration of each module or unit is not limited and can be constructed from analog devices, digital chips, or other suitable methods according to circuit principles.

[0220] Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0221] For example, such as Figure 7 As shown, the electronic device 700 includes at least one processor 701 and at least one memory 702. The at least one memory 702 includes one or more computer program modules. These computer program modules are stored in the memory 702 and configured to be executed by the at least one processor 701. The one or more computer program modules include instructions for performing the data processing method described above. When executed by the at least one processor 701, they can perform one or more steps of the data processing method provided in at least one embodiment of this disclosure. The memory 702 and the processor 701 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0222] For example, processor 701 can be a central processing unit (CPU), digital signal processor (DSP), graphics processing unit (GPU), general-purpose graphics processing unit (GPGPU), artificial intelligence (AI) accelerator, or other form of processing unit with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA); for example, the central processing unit (CPU) can be an x86, ARM, or RISC-V architecture. Processor 701 can be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 700 to perform desired functions.

[0223] For example, memory 702 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0224] Figure 8 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0225] The electronic devices in at least one embodiment of this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, and fixed terminals such as digital TVs and desktop computers. Figure 8 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0226] The electronic device includes at least one processor and a memory. The processor may be referred to as processing device 801 as described below, and the memory may include at least one of ROM 802, RAM 803, and storage device 808 as described below. The memory is used to store programs for performing the methods described in the various method embodiments above; the processor is configured to execute the programs stored in the memory. The processor may include a central processing unit (CPU) or other forms of processing unit having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0227] like Figure 8 As shown, the electronic device 800 may include a processing unit 801 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in ROM 802 or a program loaded from storage device 808 into RAM 803. RAM 803 also stores various programs and data required for the operation of the electronic device 800. The processing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interfaces are also connected to bus 804.

[0228] Typically, the following devices can be connected to I / O interface 805: input devices 806 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 807 including, for example, displays, speakers, vibrators, etc.; storage devices 808 including, for example, magnetic tapes, hard disks, etc.; and communication devices 809. Communication device 809 allows electronic device 800 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 8 An electronic device 800 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0229] In particular, according to at least one embodiment of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, at least one embodiment of this disclosure includes a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device 809, or installed from a storage device 808, or installed from a ROM 802. When the computer program is executed by a processing device 801, it performs the functions defined in the methods of at least one embodiment of this disclosure.

[0230] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In at least one embodiment of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In at least one embodiment of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, radio frequency (RF), etc., or any suitable combination thereof.

[0231] The aforementioned computer-readable medium may be included in the aforementioned electronic device 800; or it may exist independently and not assembled into the electronic device 800.

[0232] Figure 9 This is a schematic block diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure.

[0233] For example, such as Figure 9 As shown, a non-transitory computer-readable storage medium 900 stores computer-readable instructions 901, which, when executed by at least one processor, perform one or more steps of the data processing method described above.

[0234] For example, the storage medium may include a memory card for a smartphone, a storage component for a tablet computer, a hard drive for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media. For example, the readable storage medium may also be... Figure 7 The memory 702 in the memory is described in the foregoing content and will not be repeated here.

[0235] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0236] The following points should be noted regarding this disclosure:

[0237] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0238] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0239] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0240] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A data processing method, characterized in that, The method includes: Receive a data read / write request carrying logical block index information, wherein the logical block index information is used to indicate the target logical block to which the target data belongs; Based on the logical block index information, the physical address offset of the target logical block in the physical storage space is obtained through the data index interface; Based on the physical address offset, the target data is read or written in the physical storage space. The physical storage space is used to store data in at least one logical block. The data indexing interface is constructed based on a logical block data arrangement method. This method indicates that multiple consecutive logical blocks are mapped to non-contiguous physical address regions in the physical storage space. Each logical block consists of multiple address-contiguous sub-blocks, where data within the same address-contiguous sub-block is continuously distributed in the physical storage space, while data from different address-contiguous sub-blocks is mapped to non-contiguous physical address regions. The physical storage space is organized into a multi-dimensional logical storage space, which is divided into multiple logical blocks with contiguous indexes. The step of obtaining the physical address offset of the target logical block in the physical storage space through the data index interface based on the logical block index information includes: Use the data indexing interface to perform the following operations: Based on the logical block index information, obtain the first coordinates of the target logical block in the logical storage space; Based on the first coordinate and the logical block data arrangement, the physical address offset corresponding to the first coordinate is obtained, which is used as the physical address offset of the target logical block in the physical storage space.

2. The data processing method according to claim 1, characterized in that, Data within the same logical block is not distributed contiguously in the physical storage space.

3. The data processing method according to claim 1, characterized in that, The plurality of logical blocks have the same size, and obtaining the first coordinates of the target logical block in the logical storage space based on the logical block index information includes: Based on the logical block index information, and combined with the size of the logical storage space and the logical block size, the first coordinates of the target logical block in the logical storage space are obtained.

4. The data processing method according to claim 3, characterized in that, The step of obtaining the first coordinates of the target logical block in the storage space based on the logical block index information, combined with the size of the logical storage space and the logical block size, includes: Based on the size of the logical storage space and the size of the logical block, the number of logical blocks in the logical storage space in the first dimension and the second dimension are obtained respectively. Based on the number of logical blocks in the first and second dimensions and the logical block index information, the third dimension coordinates, the first dimension logical block index and the second dimension logical block index of the target logical block are obtained, wherein the first dimension logical block index and the second dimension logical block index represent the arrangement sequence number of the target logical block in the first and second dimensions of the logical storage space, respectively. Based on the logical block size, the first-dimensional logical block index, and the second-dimensional logical block index, obtain the first-dimensional coordinates and the second-dimensional coordinates; The first coordinate is obtained by combining the first dimension coordinate, the second dimension coordinate, and the third dimension coordinate.

5. The data processing method according to claim 1, characterized in that, Each logical block comprises multiple sub-blocks of the same size. Data within the same sub-block is stored contiguously in the physical storage space in column-major order. The size of the sub-block is determined based on the data type of the data within it.

6. The data processing method according to claim 5, characterized in that, The step of obtaining the physical address offset corresponding to the first coordinate based on the first coordinate and in conjunction with the logical block data arrangement includes: Based on the first coordinates and the size of the logical storage space, the first physical address offset is obtained; Based on the sub-block size and the first coordinate, and combined with the size of the logical storage space, the second physical address offset is obtained; Based on the first physical address offset and the second physical address offset, obtain the physical address offset corresponding to the first coordinate.

7. The data processing method according to claim 6, characterized in that, The step of obtaining the first physical address offset based on the first coordinates and the size of the logical storage space includes: The first physical address offset is obtained based on the third dimension coordinate in the first coordinate system, the first dimension size and the second dimension size of the logical storage space.

8. The data processing method according to claim 6, characterized in that, The step of obtaining the second physical address offset based on the sub-block size and the first coordinate, combined with the size of the logical storage space, includes: Based on the first dimension coordinates in the first coordinate system, the second dimension size of the logical storage space, and the first dimension size of the sub-block, the first sub-address offset is determined. Based on the second-dimensional coordinates in the first coordinate system, the first-dimensional size and the second-dimensional size of the sub-block, determine the second sub-address offset; The second physical address offset is obtained based on the first sub-address offset and the second sub-address offset.

9. The data processing method according to claim 1, characterized in that, The method further includes: At least one address contiguous block in the target logical block is obtained through the data indexing interface.

10. The data processing method according to claim 9, characterized in that, The step of obtaining at least one address contiguous block in the target logical block through the data indexing interface includes: Use the data indexing interface to perform the following operations: The number of consecutive address blocks in the target logical block is determined based on the sub-block size and the logical block size. Based on the sub-block size, the logical block size, and the logical storage space size, the physical address offset and length of the at least one consecutive address block are determined.

11. The data processing method according to claim 1, characterized in that, The target data includes key-value cache data.

12. A data processing apparatus, comprising: The receiving module is configured to receive data read / write requests carrying logical block index information, wherein the logical block index information is used to indicate the target logical block to which the target data belongs; The acquisition module is configured to obtain the physical address offset of the target logical block in the physical storage space through the data index interface based on the logical block index information. The read / write module is configured to perform reading or writing of target data in the physical storage space based on the physical address offset. The physical storage space is used to store data in at least one logical block. The data indexing interface is constructed based on a logical block data arrangement method. This method indicates that multiple consecutive logical blocks are mapped to non-contiguous physical address regions in the physical storage space. Each logical block consists of multiple address-contiguous sub-blocks, where data within the same address-contiguous sub-block is continuously distributed in the physical storage space, while data from different address-contiguous sub-blocks is mapped to non-contiguous physical address regions. The physical storage space is organized into a multi-dimensional logical storage space, which is divided into multiple logical blocks with contiguous indexes. The acquisition module is further configured to perform the following operations using the data indexing interface: Based on the logical block index information, obtain the first coordinates of the target logical block in the logical storage space; Based on the first coordinate and the logical block data arrangement, the physical address offset corresponding to the first coordinate is obtained, which is used as the physical address offset of the target logical block in the physical storage space.

13. An electronic device, characterized in that, The electronic device includes: At least one processor; At least one memory, including one or more computer program modules; The one or more computer program modules are stored in the at least one memory and configured to be executed by the at least one processor, and the one or more computer program modules are used to implement the method according to any one of claims 1-11.

14. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer-readable instructions, wherein the computer-readable instructions, when executed by at least one processor, perform the method according to any one of claims 1-11.

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