Switching circuit and communication system

Abstract

The application discloses a switching circuit and a communication system. The switching circuit is electrically connected between a first device without a serial bus interface and a second device with a serial bus interface. The switching circuit comprises a controller, a data transceiver circuit and a bus communication circuit. The data transceiver circuit generates a second communication signal same as a first communication signal output by the controller in response to an enable signal output by the controller, and sends the second communication signal to the first device, or generates a fourth communication signal same as a third communication signal output by the first device in response to the third communication signal, and sends the fourth communication signal to the controller. The bus communication circuit establishes serial communication between the controller and the second device to realize data interaction between the controller and the second device. In this way, data interaction between the first device without a serial bus interface and the second device with a serial bus interface can be realized.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a switching circuit and communication system. Background Technology

[0002] In some application scenarios, data transmission between two devices is often required to achieve system functionality coordination and expansion. However, due to differences in device design or asynchronous technological iterations, devices may be unable to directly transmit data due to incompatible communication protocols or interfaces, thus affecting the overall system performance and compatibility. For example, in applications where a main unit with an inverter is connected in parallel with a battery pack, the following technical contradictions exist:

[0003] With the increasing electricity demand from users, expanding the capacity of energy storage systems by connecting multiple battery packs in parallel has become an urgent need. However, some inverter main units are not designed with reserved ports for parallel battery pack expansion, especially lacking an integrated CAN (Controller Area Network) communication interface, while the battery packs are equipped with CAN interfaces for real-time transmission of battery status. Because of its high reliability and real-time performance, the CAN bus is a commonly used communication protocol in battery management systems (BMS), but if the inverter main unit is not designed with a corresponding CAN interface, it cannot establish the necessary data exchange link with the battery packs. Summary of the Invention

[0004] This application provides a switching circuit and communication system that enables data interaction between a first device without a usable serial bus interface and a second device with a usable serial bus interface.

[0005] In a first aspect, embodiments of this application provide a switching circuit configured to be electrically connected between a first device without a usable serial bus interface and a second device with a usable serial bus interface. The switching circuit includes: a controller; a data transceiver circuit electrically connected between the controller and the first device, configured to: in response to an enable signal output by the controller, generate a second communication signal with the same logical state as a first communication signal output by the controller, and send the second communication signal to the first device; or, in response to a third communication signal output by the first device, generate a fourth communication signal with the same logical state as the third communication signal, and send the fourth communication signal to the controller; and a bus communication circuit electrically connected between the controller and the second device, configured to: establish communication between the controller and the second device. Serial communication is used to realize data interaction between the controller and the second device. The data transceiver circuit includes a tri-state gate and a first pull-up resistor. The enable pin of the tri-state gate is electrically connected to the pin of the controller that outputs the enable signal, the input pin of the tri-state gate is electrically connected to the pin of the controller that outputs the first communication signal, the output pin of the tri-state gate is electrically connected to the first device, the first end of the first pull-up resistor, and the pin of the controller that receives the fourth communication signal, and the second end of the first pull-up resistor is electrically connected to the first power supply. When the controller outputs the enable signal and the first communication signal, the enable signal is input to the enable pin of the tri-state gate, the first communication signal is input to the input pin of the tri-state gate, and the output pin of the tri-state gate outputs the second communication signal to the first device. When the first device outputs the third communication signal, the fourth communication signal is generated based on the first power supply at the first end of the first pull-up resistor.

[0006] In one or more embodiments, the switching circuit further includes a voltage divider circuit electrically connected to the data transceiver circuit at a first node, the first node being used to electrically connect to a first device; wherein, when the first node is not electrically connected to the first device, the voltage of the first node is a first voltage, and when the first node is electrically connected to the first device, the voltage of the first node is a second voltage, the first voltage and the second voltage being unequal.

[0007] In one or more embodiments, the switching circuit further includes a voltage detection circuit electrically connected to the first node and the controller; the voltage detection circuit is configured to generate a first detection signal to the controller based on the voltage of the first node; the controller is configured to determine the voltage of the first node based on the first detection signal, and determine whether the first node is electrically connected to the first device based on the voltage of the first node.

[0008] In one or more embodiments, the switching circuit further includes a wake-up circuit electrically connected to the controller and configured to electrically connect a first wake-up pin and a second wake-up pin of the second device; the wake-up circuit is configured to establish an electrical connection between the first wake-up pin and the second wake-up pin in response to a wake-up signal output by the controller, so as to wake up the second device.

[0009] In one or more embodiments, the switching circuit further includes a switching circuit and an output control circuit, the output control circuit being electrically connected to the controller and electrically connected to the switching circuit, the switching circuit being used to electrically connect the second device to the second node; the switching circuit is configured to be in an on state or an off state, wherein, when the switching circuit is in the off state, the voltage of the second node is a fourth voltage, and the second device stops operating; the output control circuit is configured to, when the switching circuit is in the on state, control the voltage of the second node to a third voltage in response to not receiving a control signal output by the controller, so that the second device determines that the switching circuit is electrically connected to the second device in response to receiving the third voltage, or, in response to receiving a control signal output by the controller, control the voltage of the second node to a fourth voltage, so that the second device stops operating.

[0010] In one or more embodiments, the data transceiver circuit further includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a first Schottky diode, a second Schottky diode, and a Zener diode; the first end of the first resistor is electrically connected to a first device, the second end of the first resistor is electrically connected to the first end of the first capacitor, the second end of the first capacitor is electrically connected to the output pin of the tri-state gate, the cathode of the first Schottky diode, the cathode of the Zener diode, and the cathode of the second Schottky diode, the anode of the first Schottky diode, the anode of the Zener diode, and the second end of the second capacitor are all grounded, the anode of the second Schottky diode is electrically connected to the first end of the fourth resistor, the second end of the fourth resistor is electrically connected to the first end of the second capacitor, the first end of the first pull-up resistor, and the pin of the controller that receives the first communication signal, the power supply pin of the tri-state gate is electrically connected to a second power supply, the ground pin of the tri-state gate is grounded, the enable pin of the tri-state gate is electrically connected to the pin of the controller that outputs the enable signal through the second resistor, and the input pin of the tri-state gate is electrically connected to the pin of the controller that outputs the first communication signal through the third resistor.

[0011] In one or more embodiments, the bus communication circuit includes a CAN transceiver; the transmit data input pin of the CAN transceiver is electrically connected to the serial data output pin of the controller, the receive data output pin of the CAN transceiver is electrically connected to the serial data input pin of the controller, the CAN high-order output pin of the CAN transceiver is electrically connected to the first differential pin of the second device, and the CAN low-order output pin of the CAN transceiver is electrically connected to the second differential pin of the second device.

[0012] In one or more embodiments, the voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor; a fifth voltage is input to a first terminal of the first voltage divider resistor, the second terminal of the first voltage divider resistor and the first terminal of the second voltage divider resistor are electrically connected to a first node, and the second terminal of the second voltage divider resistor is grounded.

[0013] In one or more embodiments, the voltage detection circuit includes an operational amplifier and a feedback resistor; the non-inverting input of the operational amplifier is electrically connected to a first node, the inverting input of the operational amplifier is electrically connected to the output of the operational amplifier through the feedback resistor, and the output of the operational amplifier is electrically connected to a controller.

[0014] In one or more embodiments, the wake-up circuit includes a first optocoupler and a first switching transistor;

[0015] The first terminal of the first switching transistor is electrically connected to the controller, the second terminal of the first switching transistor is grounded, the third terminal of the first switching transistor is electrically connected to the cathode of the light emitter of the first optocoupler, the anode of the light emitter of the first optocoupler is electrically connected to the second power supply, the first terminal of the light receiver of the first optocoupler is electrically connected to the first wake-up pin, and the second terminal of the light receiver of the first optocoupler is electrically connected to the second wake-up pin; wherein, in response to the wake-up signal output by the controller, the first switching transistor is turned on to turn on the first optocoupler and establish an electrical connection between the first wake-up pin and the second wake-up pin to wake up the second device.

[0016] In one or more embodiments, the switching circuit includes a toggle switch, and the output control circuit includes a second optocoupler, a second switching transistor, a third switching transistor, a first combined resistor, a second combined resistor, and a third combined resistor; the first terminal of the second switching transistor is electrically connected to a controller, the second terminal of the second switching transistor is grounded, the third terminal of the second switching transistor is electrically connected to the cathode of the light emitter of the second optocoupler, the anode of the light emitter of the second optocoupler is electrically connected to a second power supply, the first terminal of the light receiver of the second optocoupler is electrically connected to the first terminal of the first combined resistor, the first terminal of the second combined resistor, and the first terminal of the third switching transistor, the second terminal of the light receiver of the second optocoupler is electrically connected to the second terminal of the second combined resistor, the second terminal of the third switching transistor, and ground, the third terminal of the third switching transistor is electrically connected to the first terminal of the third combined resistor, the second terminal of the first combined resistor is electrically connected to the second terminal of the third combined resistor and the first terminal of the toggle switch, and the second terminal of the toggle switch is electrically connected to a second node.

[0017] Secondly, embodiments of this application provide a communication system, including a first device without a usable serial bus interface, a second device with a usable serial bus interface, and a switching circuit as described in the first aspect, the switching circuit being electrically connected between the first device and the second device.

[0018] In one or more embodiments, the first device includes a third voltage divider resistor and a fourth voltage divider resistor. A fifth voltage is input to a first terminal of the third voltage divider resistor, and a second terminal of the third voltage divider resistor is electrically connected to a first terminal of the fourth voltage divider resistor and a first node. The second terminal of the fourth voltage divider resistor is grounded. The first device is configured to: determine whether to supply power to the adapter circuit based on the voltage of the first node, wherein the first device supplies power to the adapter circuit when the voltage of the first node is a second voltage, and does not supply power to the adapter circuit when the voltage of the first node is a first voltage; after the first device supplies power to the adapter circuit, determine whether the first device and the adapter circuit are successfully connected based on the communication result between the first device and the adapter circuit, wherein the first device is determined to be successfully connected when the communication result is successful, and the first device is determined to be unsuccessfully connected when the communication result is unsuccessful; when the first device is determined to be successfully connected to the adapter circuit, the first device continues to supply power to the adapter circuit; when the first device is determined to be unsuccessfully connected to the adapter circuit, the first device stops supplying power to the adapter circuit.

[0019] In one or more embodiments, the second device includes a second pull-up resistor, a first end of which is input to the power supply voltage of the second device, and a second end of which is electrically connected to a second node; the second device is configured to: determine whether the second device supplies power to the transfer circuit based on the voltage of the second node, wherein the second device supplies power to the transfer circuit when the voltage of the second node is a third voltage, and the second device does not supply power to the transfer circuit when the voltage of the second node is a fourth voltage.

[0020] The beneficial effects of this application are as follows: The switching circuit in the embodiments of this application includes a controller, a data transceiver circuit, and a bus communication circuit. The data transceiver circuit is electrically connected between the controller and the first device, and the bus communication circuit is electrically connected between the controller and the second device. When the first device sends data and the second device receives data, the first device outputs a third communication signal. The data transceiver circuit generates a fourth communication signal with the same logical state as the third communication signal and sends the fourth communication signal to the controller. Simultaneously, the controller communicates with the second device through the bus communication circuit, and the controller can send the fourth communication signal to the second device. When the second device sends data and the first device receives data, the controller communicates with the second device through the bus communication circuit. The second device sends data to the controller. Simultaneously, the controller outputs an enable signal and uses the data sent by the second device as the first communication signal. The data transceiver circuit generates a second communication signal with the same logical state as the first communication signal and sends the second communication signal to the first device. Thus, data interaction is achieved between a first device without a usable serial bus interface and a second device with a usable serial bus interface. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are not intended to limit the embodiments, and elements having the same reference numerals in the drawings are designated as similar elements.

[0022] Figure 1 This is a schematic diagram of the adapter circuit provided in the embodiments of this application. Figure 1 ;

[0023] Figure 2 This is a schematic diagram of the adapter circuit provided in the embodiments of this application. Figure 2 ;

[0024] Figure 3 This is a schematic diagram of the adapter circuit provided in the embodiments of this application. Figure 3 ;

[0025] Figure 4 This is a schematic diagram of the adapter circuit provided in the embodiments of this application. Figure 4 ;

[0026] Figure 5 This is a schematic diagram of the adapter circuit provided in the embodiments of this application. Figure 5 ;

[0027] Figure 6 This is a schematic diagram of the adapter circuit provided in the embodiments of this application. Figure 6 ;

[0028] Figure 7 This is a schematic diagram of the circuit structure of the power supply circuit provided in the embodiment of this application;

[0029] Figure 8 This is a schematic diagram of a portion of the circuit structure in the adapter circuit and the first device provided in the embodiments of this application;

[0030] Figure 9 This is a schematic diagram of the circuit structure of the bus communication circuit provided in the embodiments of this application;

[0031] Figure 10 This is a schematic diagram of the circuit structure of the wake-up circuit provided in the embodiments of this application;

[0032] Figure 11 This is a schematic diagram of the circuit structure of the output control circuit provided in the embodiments of this application;

[0033] Figure 12 This is a schematic diagram of the communication system provided in the embodiments of this application. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be described clearly and in detail below with reference to the accompanying drawings. Obviously, the embodiments in this application are only some embodiments, not all embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0035] It should be noted that when an element is described as "connected" to another element, it can be directly connected to the other element, or there can be one or more intermediate elements between them.

[0036] Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0037] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the block diagram of the adapter circuit provided in an embodiment of this application. Figure 1 As shown, the adapter circuit 100 is configured to electrically connect a first device 200 that does not have a usable serial bus interface and a second device 300 that has a usable serial bus interface. The absence of a usable serial bus interface includes two scenarios: first, it physically does not exist, meaning the first device itself is neither designed nor equipped with a serial bus interface; second, it is functionally unusable, meaning that although the first device has the physical form of a serial bus interface, due to hardware damage, driver problems, disabled system settings, or firmware (such as BIOS) failure, the interface cannot be recognized or used normally by the operating system. Having a usable serial bus interface means that the first device not only possesses the physical conditions for serial communication but is also functionally capable of normal operation. A serial bus interface refers to an interface that transmits data bit by bit sequentially, such as a CAN bus interface. In a specific embodiment, the first device 200 is an inverter, and the second device 300 is a battery.

[0038] The switching circuit 100 includes a controller 110, a data transceiver circuit 120, and a bus communication circuit 130. The data transceiver circuit 120 is electrically connected between the controller 110 and the first device 200, and the bus communication circuit 130 is electrically connected between the controller 110 and the second device 300.

[0039] Specifically, the data transceiver circuit 120 is configured to: in response to an enable signal output by the controller 110, generate a second communication signal with the same logical state as the first communication signal output by the controller 110, and send the second communication signal to the first device 200; or, in response to a third communication signal output by the first device 200, generate a fourth communication signal with the same logical state as the third communication signal, and send the fourth communication signal to the controller 110. The bus communication circuit 130 is configured to: establish serial communication between the controller 110 and the second device 300 to realize data interaction between the controller 110 and the second device 300.

[0040] When the first device 200 sends data and the second device 300 receives data, the first device 200 outputs a third communication signal. The data transceiver circuit 120 generates a fourth communication signal with the same logic state as the third communication signal and sends the fourth communication signal to the controller 110. At the same time, the controller 110 realizes communication with the second device 300 through the bus communication circuit 130. The controller 110 can send the fourth communication signal to the second device 300.

[0041] When the second device 300 sends data and the first device 200 receives data, the controller 110 communicates with the second device 300 through the bus communication circuit 130. The second device 300 sends data to the controller 110. At the same time, the controller 110 outputs an enable signal and uses the data sent by the second device 300 as the first communication signal. The data transceiver circuit 120 generates a second communication signal with the same logic state as the first communication signal and sends the second communication signal to the first device 200.

[0042] In this way, data interaction can be achieved between a first device 200 that does not have a usable serial bus interface and a second device 300 that has a usable serial bus interface. Furthermore, data interaction between the first device 200 and the second device 300 can be achieved solely through the adapter circuit 100, without the need to add an additional interface to the first device 200, thus eliminating the need for additional costs.

[0043] In some embodiments, such as Figure 2 As shown, the adapter circuit 100 also includes a voltage divider circuit 140, which is electrically connected to the data transceiver circuit 120 at the first node P1. The first node P1 is used to electrically connect to the first device 200.

[0044] Specifically, when the first node P1 is not electrically connected to the first device 200, the voltage of the first node P1 is the first voltage, and when the first node P1 is electrically connected to the first device 200, the voltage of the first node P1 is the second voltage. The first voltage and the second voltage are not equal.

[0045] Thus, the switching circuit 100 can determine whether the first node P1 is electrically connected to the first device 200 based on the voltage of the first node P1, that is, whether the switching circuit 100 is electrically connected to the first device 200. Specifically, if the switching circuit 100 determines that the voltage of the first node P1 is a first voltage, it determines that the switching circuit 100 is electrically connected to the first device 200; if the switching circuit 100 determines that the voltage of the first node P1 is a second voltage, it determines that the switching circuit 100 is not electrically connected to the first device 200.

[0046] In some embodiments, such as Figure 3 As shown, the adapter circuit 100 also includes a voltage detection circuit 150, which is electrically connected to the first node P1 and the controller 110.

[0047] The voltage detection circuit 150 is configured to generate a first detection signal to the controller 110 based on the voltage of the first node P1. The controller 110 is configured to determine the voltage of the first node P1 based on the first detection signal, and to determine whether the first node P1 is electrically connected to the first device 200 based on the voltage of the first node P1.

[0048] Specifically, the voltage detection circuit 150 continuously monitors the voltage at a specific location (i.e., the first node P1). It then converts this analog voltage value into a first detection signal (which can be a digital signal or a specific voltage level) that the controller 110 can understand. The controller 110 receives the signal from the voltage detection circuit 150 and first reconstructs the actual voltage value of the first node. Then, based on this voltage value, the controller 110 uses preset logic to determine whether the first node P1 is connected to the first device 200. The preset logic is that when the voltage of the first node P1 is a second voltage, the controller 110 determines that the first node P1 is connected to the first device 200; when the voltage of the first node P1 is a first voltage, the controller 110 determines that the first node P1 is not connected to the first device 200.

[0049] In some embodiments, such as Figure 4 As shown, the switching circuit 100 also includes a wake-up circuit 160, which is electrically connected to the controller 110 and is used to electrically connect the first wake-up pin WAKE1 and the second wake-up pin WAKE2 of the second device 300.

[0050] The wake-up circuit 160 is configured to establish an electrical connection between the first wake-up pin WAKE1 and the second wake-up pin WAKE2 in response to a wake-up signal output by the controller 110, so as to wake up the second device 300.

[0051] Specifically, after the first device 200 is connected to the adapter circuit 100, the controller 110 can output a wake-up signal to the wake-up circuit 160 to establish an electrical connection between the first wake-up pin WAKE1 and the second wake-up pin WAKE2, so as to wake up the second device 300 and thus enable communication between the first device 200 and the second device 300.

[0052] In some embodiments, such as Figure 5 As shown, the adapter circuit 100 also includes an output control circuit 170 and a switch circuit 180. The output control circuit 170 is electrically connected to the controller 110 and electrically connected to the switch circuit 180. The switch circuit 180 is used to electrically connect the second device 300 to the second node P2.

[0053] The switching circuit 180 is configured to be in an on state or an off state, wherein when the switching circuit 180 is in the off state, the voltage of the second node P2 is the fourth voltage, and the second device 300 stops operating.

[0054] The output control circuit 170 is configured to: when the switching circuit 180 is in the on state, in response to not receiving a control signal output by the controller 110, control the voltage of the second node P2 to a third voltage so that the second device 300 determines that the transfer circuit 100 is electrically connected to the second device 300 in response to receiving the third voltage; or, in response to receiving a control signal output by the controller 110, control the voltage of the second node P2 to a fourth voltage so that the second device 300 stops operating.

[0055] Specifically, in scenarios where the second device 300 is allowed to operate (e.g., when the electrical connection between the first device 200 and the transfer circuit 100 is in a conducting state), the switching circuit 180 is in a conducting state and the controller 110 does not output a control signal. In this case, if the transfer circuit 100 is electrically connected to the second device 300, the output control circuit 170 can make the voltage of the second node P2 the third voltage. At the same time, the second device 300 can also determine that the transfer circuit 100 is electrically connected to the second device 300 based on the fact that the voltage of the second node P2 is the third voltage.

[0056] In scenarios where the second device 300 is not permitted to operate (e.g., when the electrical connection between the first device 200 and the transfer circuit 100 is disconnected), the switching circuit 180 is in the off state and / or the controller 110 outputs a control signal. In this case, the voltage at the second node P2 is the fourth voltage. If the transfer circuit 100 is electrically connected to the second device 300, the second device 300 stops operating based on the fact that the voltage at the second node P2 is the fourth voltage.

[0057] The cessation of operation of the second device 300 signifies the termination of its function; that is, the second device 300 stops performing external work or data processing. For example, in a specific embodiment, the second device 300 is a battery, and its cessation of operation means that the battery stops outputting power.

[0058] In some embodiments, such as Figure 6 As shown, the adapter circuit 100 also includes a power supply circuit 190. The power supply circuit 190 is electrically connected to each module in the adapter circuit 100 (including the controller 110, data transceiver circuit 120, bus communication circuit 130, voltage divider circuit 140, voltage detection circuit 150, wake-up circuit 160, output control circuit 170, and switch circuit 180). The power supply circuit 190 is also used to electrically connect the first device 200 and the second device 300 respectively.

[0059] The power supply circuit 190 is used to output a voltage that supplies power to each module in the adapter circuit 100 based on the power supply voltage output by the first device 200 or the second device 300.

[0060] Please refer to Figure 7 , Figure 7 A schematic diagram of the circuit structure of the power supply circuit 190 is shown as an example. Figure 7 As shown, the power supply circuit 190 includes a first diode D1, a second diode D2, and a voltage conversion circuit 191.

[0061] The anode of the first diode D1 is electrically connected to the first device 200, the cathode of the first diode D1 is electrically connected to the input terminal of the voltage conversion circuit 191 and the cathode of the second diode D2, the anode of the second diode D2 is electrically connected to the second device 300, and the voltage conversion circuit 191 is also electrically connected to each module (not shown in the figure) in the conversion circuit 100 to supply power to each module in the conversion circuit 100.

[0062] Voltage conversion circuit 191 is used to convert the voltage of the first device 200 or the second device 300 into a voltage that matches the respective modules in the adapter circuit 100, thereby powering the respective modules in the adapter circuit 100. Specifically, voltage conversion circuit 191 converts input electrical energy (voltage and current) into one or more different levels of output voltage and current to meet the specific power requirements of various electronic devices or circuits. For example, in a specific embodiment, when the voltages required by the respective modules in the adapter circuit 100 are 5V and 3.3V, voltage conversion circuit 191 includes a Buck (step-down) circuit and an LDO (linear regulator). The Buck (step-down) circuit is used to step down the voltage output by the first device 200 or the second device 300 to output a 5V voltage; the LDO is used to step down the 5V voltage to output a 3.3V voltage.

[0063] Please refer to Figure 8 , Figure 8 A schematic diagram of a portion of the circuit structure in the data transceiver circuit 120, the voltage divider circuit 140, the voltage detection circuit 150, and the first device 200 is shown as an example.

[0064] like Figure 8 As shown, the data transceiver circuit 120 includes a tri-state gate U1 and a first pull-up resistor RA1.

[0065] Specifically, the enable pin OE of the tri-state gate U1 is electrically connected to the EN pin of the controller 110 that outputs the enable signal; the input pin IN of the tri-state gate U1 is electrically connected to the U_TX pin of the controller 110 that outputs the first communication signal; the output pin OUT of the tri-state gate U1 is electrically connected to the first device 200, the first end of the first pull-up resistor RA1, and the U_RX pin of the controller 110 that receives the fourth communication signal; and the second end of the first pull-up resistor RA1 is electrically connected to the first power supply V1.

[0066] In some embodiments, the data transceiver circuit 120 further includes a first resistor RS1, a second resistor RS2, a third resistor RS3, a fourth resistor RS4, a first capacitor C1, a second capacitor C2, a first Schottky diode DA1, a second Schottky diode DA2, and a Zener diode DB1.

[0067] The first terminal of the first resistor RS1 is electrically connected to the first node P1. The second terminal of the first resistor RS1 is electrically connected to the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is electrically connected to the output pin OUT of the tri-state gate U1, the cathode of the first Schottky diode DA1, the cathode of the Zener diode DB1, and the cathode of the second Schottky diode DA2. The anodes of the first Schottky diode DA1, the anode of the Zener diode DB1, and the second terminal of the second capacitor C2 are all grounded to GND. The anode of the second Schottky diode DA2 is electrically connected to the first terminal of the fourth resistor RS4. The second terminal of the four resistors RS4 is electrically connected to the first terminal of the second capacitor C2, the first terminal of the first pull-up resistor RA1, and the controller 110 pin U_RX for receiving the fourth communication signal. The power supply pin VCC of the tri-state gate U1 is electrically connected to the second power supply V2. The ground pin G1 of the tri-state gate U1 is grounded to GND. The enable pin OE of the tri-state gate U1 is electrically connected to the controller 110 pin EN for outputting the enable signal through the second resistor RS2. The input pin IN of the tri-state gate U1 is electrically connected to the controller 110 pin U_TX for outputting the first communication signal through the third resistor RS3.

[0068] The first resistor RS1 is used for buffering and current limiting. The first capacitor C1 is an isolation capacitor. The second resistor RS2 and the third resistor RS3 are used for current limiting. The fourth resistor RS4 and the second capacitor C2 form a low-pass filter to filter out high-frequency interference caused by parasitic parameters of the components. The first Schottky diode DA1, the second Schottky diode DA2, and the Zener diode DB1 form a surge protection circuit.

[0069] In some embodiments, the voltage divider circuit 140 includes a first voltage divider resistor RB1 and a second voltage divider resistor RB2.

[0070] The first terminal of the first voltage divider resistor RB1 is input with the fifth voltage V5, the second terminal of the first voltage divider resistor RB1 and the first terminal of the second voltage divider resistor RB2 are electrically connected to the first node P1, and the second terminal of the second voltage divider resistor RB2 is grounded to GND.

[0071] In some embodiments, the first device 200 includes a third voltage divider resistor RB3 and a fourth voltage divider resistor RB4.

[0072] Among them, the first terminal of the third voltage divider resistor RB3 is input with the fifth voltage V5, the second terminal of the third voltage divider resistor RB3 is electrically connected to the first terminal of the fourth voltage divider resistor RB4 and the first node P1, and the second terminal of the fourth voltage divider resistor RB4 is grounded to GND.

[0073] Specifically, when the data transceiver circuit 120 is not connected to the first device 200, the voltage at the first node P1 is the first voltage (denoted as V1): V1 = RB2 / (RB1 + RB2) * V5. When the data transceiver circuit 120 is connected to the first device 200, both the controller 110 (through the voltage detection circuit 150) and the first device 200 can detect that the voltage at the first node P1 is the second voltage (denoted as VC2): VC2 = (RB2 / / RB4) / ((RB2 / / RB4) + (RB1 / / RB3)) * V5, where RB2 / / RB4 refers to the resistance value after the second voltage divider resistor RB2 and the fourth voltage divider resistor RB4 are connected in parallel, and RB1 / / RB3 refers to the resistance value after the first voltage divider resistor RB1 and the third voltage divider resistor RB3 are connected in parallel. In this way, based on the voltage at the first node P1, both the controller 110 and the first device 200 can identify whether the adapter circuit 100 is electrically connected to the first device 200.

[0074] In addition, by adjusting the resistance values ​​of the third voltage divider resistor RB3 and the fourth voltage divider resistor RB4, the voltage of the first node P1 after connection can be changed, thereby enabling the identification of different first devices 200.

[0075] The communication process between controller 110 and data transceiver circuit 120 is as follows:

[0076] When controller 110 outputs an enable signal and a first communication signal (a signal with a high level and / or a low level), the output pin OUT of tri-state gate U1 outputs a second communication signal, which is received by the first device 200. It can be understood that the second communication signal has the same logical state as the first communication signal, indicating that at a specific moment or within a certain time period, the second communication signal and the first communication signal are in the same state, for example, both are simultaneously high or simultaneously low. Furthermore, the logical high of the second communication signal is based on the voltage of the second power supply V2. Thus, the process of controller 110 outputting the first communication signal and data transceiver circuit 120 outputting the second communication signal to the first device 200 is realized.

[0077] Taking an example where the first device 200 outputs a power supply voltage of 10V, the second device 300 outputs a power supply voltage of 5V, the second power supply V2 is 5V, the first power supply V1 is 3.3V, and the forward voltage drop of the first Schottky diode DA1, the second Schottky diode DA2, and the Zener diode DB1 is 0.3V. Assuming that both the first device 200 and the second device 300 are electrically connected to the adapter circuit 100, the fifth voltage V5 is the 5V power supply voltage output by the second device 300. When the first device 200 outputs the third communication signal, the voltage at the first node P1 will experience a peak change of 5V. The initial level of the fourth communication signal is 3.3V. If the third communication signal has a falling edge, since the falling edge value is 5V and the initial level is 3.3V, the first node P1 will have a negative voltage. At this time, the first Schottky diode DA1 can clamp the pin U_TX of the first communication signal to approximately -0.3V. At this time, the second Schottky diode DA2 is turned on, and there is a 0.3V voltage drop on the second Schottky diode DA2. Therefore, a voltage of 0V appears on the pin U_TX of the first communication signal (that is, the fourth communication signal also has a falling edge and switches to a low level). Subsequently, if the third communication signal has a rising edge, the level of the first node P1 is raised to about 4.7V, the second Schottky diode DA2 is turned off, and the pin U_TX of the first communication signal is pulled up to 3.3V (that is, the fourth communication signal also has a rising edge and switches to a high level). In this way, the process of the first device 200 outputting the third communication signal and the data transceiver circuit 120 outputting the fourth communication signal to the controller 110 is realized.

[0078] In some embodiments, the voltage detection circuit 150 includes an operational amplifier U2 and a feedback resistor RT1.

[0079] The non-inverting input of operational amplifier U2 is electrically connected to the first node P1, the inverting input of operational amplifier U2 is electrically connected to the output of operational amplifier U2 through feedback resistor RT1, and the output of operational amplifier U2 is electrically connected to controller 110.

[0080] In some embodiments, the voltage detection circuit 150 further includes a fifth resistor RS5, a sixth resistor RS6, a seventh resistor RS7, and a third capacitor C3.

[0081] Among them, the fifth resistor RS5 is electrically connected between the first node P1 and the non-inverting input terminal of the operational amplifier U2, the sixth resistor RS6 is electrically connected between the non-inverting input terminal of the operational amplifier U2 and ground GND, the seventh resistor RS7 and the third capacitor C3 are connected in series between the output terminal of the operational amplifier U2 and ground GND, and the connection point between the seventh resistor RS7 and the third capacitor C3 is electrically connected to the controller 110.

[0082] Specifically, operational amplifier U2 and feedback resistor RT1 form a follower circuit for buffering. The fifth resistor RS5 and the sixth resistor RS6 are used for voltage division; by adding a follower circuit for buffering, the risk of sampling voltage deviation can be reduced. The seventh resistor RS7 and the third capacitor C3 form a low-pass filter.

[0083] Thus, the controller 110 can deduce the voltage of the first node P1 by using the voltage output from the voltage detection circuit 150 and the voltage division ratio of the fifth resistor RS5 and the sixth resistor RS6.

[0084] Please refer to Figure 9 , Figure 9 This is a schematic diagram of the circuit structure of the bus communication circuit 130 provided in an embodiment of this application. Figure 9 As shown, the bus communication circuit 130 includes a CAN transceiver U3.

[0085] The transmit data input pin TXD of CAN transceiver U3 (used to receive transmit data from controller 110) is electrically connected to the serial data output pin UCAN1 of controller 110. The receive data output pin RXD of CAN transceiver U3 (used to transmit received data to controller 110) is electrically connected to the serial data input pin UCAN2 of controller 110. The CAN high-order output pin CANH of CAN transceiver U3 is electrically connected to the first differential pin CAN1 of the second device 300. The CAN low-order output pin CANL of CAN transceiver U3 is electrically connected to the second differential pin CAN2 of the second device 300. The CAN high-order output pin CANH and the CAN low-order output pin CANL of CAN transceiver U3 are differential signal output terminals, where CANH is a high-level signal line and CANL is a low-level signal line.

[0086] In some embodiments, the bus communication circuit 130 further includes an eighth resistor RS8, a ninth resistor RS9, a tenth resistor RS10, an eleventh resistor RS11, a twelfth resistor RS12, a thirteenth resistor RS13, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a first transient voltage suppression diode TVS1, and a second transient voltage suppression diode TVS2.

[0087] The eighth resistor RS8 is electrically connected between the serial data output pin UCAN1 of the controller 110 and the transmit data input pin TXD of the CAN transceiver U3. The ninth resistor RS9 is electrically connected between the transmit data input pin TXD of the CAN transceiver U3 and ground GND. The tenth resistor RS10 is electrically connected between the first power supply V1 and the serial data input pin UCAN2 of the controller 110. The eleventh resistor RS11 is electrically connected between the serial data input pin UCAN2 of the controller 110 and the receive data output pin RXD of the CAN transceiver U3. The CAN high-order output pin CANH of the CAN transceiver U3 is electrically connected to the first terminal of the twelfth resistor RS12 and the first transient voltage suppressor diode TVS. The first terminal of 1, the first terminal of the fifth capacitor C5, and the first differential pin CAN1 of the second device 300 are electrically connected. The second terminal of the twelfth resistor RS12 is electrically connected to the first terminal of the thirteenth resistor RS13 and the first terminal of the fourth capacitor C4. The second terminal of the fourth capacitor C4 is grounded to GND. The CAN low-order output pin CANL of the CAN transceiver U3 is electrically connected to the second terminal of the thirteenth resistor RS13, the first terminal of the second transient voltage suppressor diode TVS2, the first terminal of the sixth capacitor C6, and the second differential pin CAN2 of the second device 300. The second terminal of the first transient voltage suppressor diode TVS1 is electrically connected to the second terminal of the second transient voltage suppressor diode TVS2, the second terminal of the fifth capacitor C5, and the second terminal of the sixth capacitor C6.

[0088] Specifically, the ninth resistor RS9 is a pull-down resistor, the tenth resistor RS10 is a pull-up resistor, and the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are filter capacitors. The first transient voltage suppressor diode TVS1 and the second transient voltage suppressor diode TVS2 are used to quickly conduct when voltage spikes (such as electrostatic discharge ESD or surges) occur on the bus, clamping the excessively high voltage to a safe level and protecting the downstream CAN transceiver U3 from damage.

[0089] When controller 110 sends data, the data is input to the transmit data input pin TXD of CAN transceiver U3 through the eighth resistor RS8. CAN transceiver U3 converts the logic level to the bus differential level and outputs it from the CANH and CANL pins to the first differential pin CAN1 and the second differential pin CAN2, and finally sends it to the second device 300.

[0090] When the second device 300 sends data, the data enters the CANH and CANL pins of the CAN transceiver U3. The CAN transceiver U3 converts the differential signal back to logic level and outputs it through the receive data output pin RXD of the CAN transceiver U3. The data is then transmitted through the eleventh resistor RS11 to the UCAN2 pin of the controller 110 for processing.

[0091] Please refer to Figure 10 , Figure 10 The circuit structure of the wake-up circuit provided in the embodiments of this application. For example... Figure 10 As shown, the wake-up circuit 160 includes a first optocoupler U4 and a first switching transistor Q1.

[0092] The first terminal of the first switch Q1 is electrically connected to the controller 110, the second terminal of the first switch Q1 is grounded (GND), the third terminal of the first switch Q1 is electrically connected to the cathode of the light emitter of the first optocoupler U4, the anode of the light emitter of the first optocoupler U4 is electrically connected to the second power supply V2, the first terminal of the light receiver of the first optocoupler U4 is electrically connected to the first wake-up pin WAKE1, and the second terminal of the light receiver of the first optocoupler U4 is electrically connected to the second wake-up pin WAKE2. In response to the wake-up signal output by the controller 110, the first switch Q1 is turned on, thereby turning on the first optocoupler U4 and establishing an electrical connection between the first wake-up pin WAKE1 and the second wake-up pin WAKE2 to wake up the second device 300.

[0093] In this embodiment, the first switching transistor Q1 is an NPN transistor. The base of the NPN transistor is the first terminal of the first switching transistor Q1, the emitter of the NPN transistor is the second terminal of the first switching transistor Q1, and the collector of the NPN transistor is the third terminal of the first switching transistor Q1.

[0094] In addition, the first switch Q1 can be any controllable switch, such as an insulated gate bipolar transistor (IGBT) device, an integrated gate commutated thyristor (IGCT) device, a gate turn-off thyristor (GTO) device, a silicon controlled rectifier (SCR) device, a junction gate field-effect transistor (JFET) device, a MOS controlled thyristor (MCT) device, etc.

[0095] In some embodiments, the wake-up circuit 160 further includes a fourteenth resistor RS14, a fifteenth resistor RS15, a sixteenth resistor RS16, and a seventeenth resistor RS17.

[0096] The fourteenth resistor RS14 is electrically connected between the controller 110 and the first terminal of the first switch transistor Q1. The fifteenth resistor RS15 is electrically connected between the first terminal of the first switch transistor Q1 and ground GND. The second terminal of the first switch transistor Q1 is grounded GND. The third terminal of the first switch transistor Q1 is electrically connected to the cathode of the light emitter of the first optocoupler U4. The sixteenth resistor RS16 is electrically connected between the second power supply V2 and the anode of the light emitter of the first optocoupler U4. The seventeenth resistor RS17 is electrically connected between the first terminal of the light receiver of the first optocoupler U4 and the first wake-up pin WAKE1.

[0097] Specifically, when the controller 110 outputs a wake-up signal (a high-level signal in this embodiment), the first switch Q1 is turned on, and the second power supply V2, the sixteenth resistor RS16, the light emitter of the first optocoupler U4 and the first switch Q1 form a circuit. The light emitter of the first optocoupler U4 is energized, the light receiver of the first optocoupler U4 is turned on, the electrical connection between the first wake-up pin WAKE1 and the second wake-up pin WAKE2 is established, and the second device 300 is woken up.

[0098] Please refer to Figure 11 , Figure 11 The circuit structure of the output control circuit and switching circuit provided in the embodiments of this application is shown. Figure 11 As shown, the output control circuit 170 includes a second optocoupler U5, a second switch Q2, a third switch Q3, a first combined resistor R1, a second combined resistor R2, and a third combined resistor R3, and the switching circuit 180 includes a toggle switch K1.

[0099] The first terminal of the second switch Q2 is electrically connected to the controller 110, the second terminal of the second switch Q2 is grounded to GND, the third terminal of the second switch Q2 is electrically connected to the cathode of the light emitter of the second optocoupler U5, the anode of the light emitter of the second optocoupler U5 is electrically connected to the second power supply V2, the first terminal of the light receiver of the second optocoupler U5 is electrically connected to the first terminal of the first combined resistor R1, the first terminal of the second combined resistor R2 and the first terminal of the third switch Q3, the second terminal of the light receiver of the second optocoupler U5 is electrically connected to the second terminal of the second combined resistor R2, the second terminal of the third switch Q3 and ground GND, the third terminal of the third switch Q3 is electrically connected to the first terminal of the third combined resistor R3, the second terminal of the first combined resistor R1 is electrically connected to the second terminal of the third combined resistor R3 and the first terminal of the toggle switch K1, and the second terminal of the toggle switch K1 is electrically connected to the second node P2.

[0100] Among them, the toggle switch K1 is a mechanical device that connects or disconnects the circuit by manually moving its handle (or lever), thereby realizing circuit switching.

[0101] In this embodiment, taking the second switch Q2 as an NPN transistor as an example, the base of the NPN transistor is the first terminal of the second switch Q2, the emitter of the NPN transistor is the second terminal of the second switch Q2, and the collector of the NPN transistor is the third terminal of the second switch Q2. Similarly, taking the third switch Q3 as an NMOS transistor as an example, the gate of the NMOS transistor is the first terminal of the third switch Q3, the source of the NMOS transistor is the second terminal of the third switch Q3, and the drain of the NMOS transistor is the third terminal of the third switch Q3.

[0102] In addition, the second switch Q2 and the third switch Q3 can be any controllable switch, such as an insulated gate bipolar transistor (IGBT) device, an integrated gate commutated thyristor (IGCT) device, a gate turn-off thyristor (GTO) device, a silicon controlled rectifier (SCR) device, a junction gate field-effect transistor (JFET) device, a MOS controlled thyristor (MCT) device, etc.

[0103] In some embodiments, the output control circuit 170 further includes an eighteenth resistor RS18, a nineteenth resistor RS19, and a twentieth resistor RS20.

[0104] The eighteenth resistor RS18 is electrically connected between the controller 110 and the first terminal of the second switch Q2. The nineteenth resistor RS19 is electrically connected between the first terminal of the second switch Q2 and ground GND. The twentieth resistor RS20 is electrically connected between the second power supply V2 and the anode of the light emitter of the second optocoupler U5.

[0105] In some embodiments, the second device 300 includes a second pull-up resistor RA2, the first end of which is input to the power supply voltage VB+ of the second device 300, and the second end of the second pull-up resistor RA2 is electrically connected to the second node P2.

[0106] Specifically, under the premise that the toggle switch K1 is closed by manual control (corresponding to the switch circuit 180 being in the conducting state), the following process is executed:

[0107] (1) When the controller 110 does not output a control signal, the controller 110 outputs a low-level signal to the first terminal of the second switch Q2, and the second switch Q2 remains off. The second optocoupler U5 also remains off. Since the toggle switch K1 is closed, the circuit containing the second pull-up resistor RA2, the first combined resistor R1, and the second combined resistor R2 is closed, and the current flows through the first combined resistor R1 and the second combined resistor R2 to turn on the third switch Q3. At this time, the voltage of the second node P2 is the third voltage (denoted as V3), which is approximately: V3=((R1+R2) / / R3) / (((R1+R2) / / R3)+RA2)*VB+, where (R1+R2) / / R3 is the resistance value of the first combined resistor R1 and the second combined resistor R2 connected in parallel with the third combined resistor R3. Thus, when the second device 300 determines that the voltage of the second node P2 is the third voltage V3, it can determine that the transfer circuit 100 has been electrically connected to the second device 300.

[0108] (2) When the controller 110 outputs a control signal, a high-level signal is output from the controller 110 to the first terminal of the second switch Q2, and the second switch Q2 is turned on. The second power supply V2, the twentieth resistor RS20, the light emitter of the second optocoupler U5 and the second switch Q2 form a circuit, the light emitter of the second optocoupler U5 is energized, the light receiver of the second optocoupler U5 is turned on, the second combined resistor R2 is short-circuited, and the third switch Q3 is turned off. At this time, the voltage of the second node P2 is the fourth voltage (denoted as V4): V4 = R1 / (R1+RA2)*VB+. Thus, when the second device 300 determines that the voltage of the second node P2 is the fourth voltage V4, the second device 300 stops operating. When the toggle switch K1 is manually turned off (corresponding to the switch circuit 180 being in the off state), the voltage of the second node P2 is the power supply voltage VB+ of the second device 300. Thus, when the second device 300 determines that the voltage of the second node P2 is the power supply voltage VB+ of the second device 300, the second device 300 stops operating.

[0109] This application also provides a communication system. For example... Figure 12 As shown, the communication system 1000 includes a first device 200 without a usable serial bus interface, a second device 300 with a usable serial bus interface, and a switching circuit 100 as in any embodiment of this application, the switching circuit 100 being electrically connected between the first device 200 and the second device 300.

[0110] In some embodiments, the first device 200 includes a third voltage divider resistor and a fourth voltage divider resistor. A fifth voltage is input to the first terminal of the third voltage divider resistor, the second terminal of the third voltage divider resistor is electrically connected to the first terminal and the first node of the fourth voltage divider resistor, and the second terminal of the fourth voltage divider resistor is grounded. Specifically, as follows... Figure 6As shown.

[0111] The first device 200 is configured to: determine whether to supply power to the transfer circuit 100 based on the voltage of the first node P1, wherein the first device 200 supplies power to the transfer circuit 100 when the voltage of the first node P1 is a second voltage, and does not supply power to the transfer circuit 100 when the voltage of the first node P1 is a first voltage; after the first device 200 supplies power to the transfer circuit 100, determine whether the first device 200 supplies power to the transfer circuit 100 based on the communication result between the first device 200 and the transfer circuit 100. Whether the adapter circuit 100 is successfully connected is determined as follows: if the communication result is successful, the first device 200 is determined to be successfully connected to the adapter circuit 100; if the communication result is unsuccessful, the first device 200 is determined to be unsuccessfully connected to the adapter circuit 100. When the first device 200 is determined to be successfully connected to the adapter circuit 100, the first device 200 continues to supply power to the adapter circuit 100. When the first device 200 is determined to be unsuccessfully connected to the adapter circuit 100, the first device 200 stops supplying power to the adapter circuit 100.

[0112] Specifically, firstly, the first device 200 starts up. When the first device 200 is electrically connected to the adapter circuit 100, the first device 200 can obtain the voltage of the first node P1 as the second voltage VC2, and VC2 = (RB2 / / RB4) / ((RB2 / / RB4) + (RB1 / / RB3)) * V5. The first device 200 supplies power to the adapter circuit 100. Afterwards, if the communication result between the first device 200 and the adapter circuit 100 is a communication failure, it is determined that the connection between the first device 200 and the adapter circuit 100 has failed, and at this time, the first device 200 stops supplying power to the adapter circuit 100; conversely, if the communication result between the first device 200 and the adapter circuit 100 is a communication success, it is determined that the connection between the first device 200 and the adapter circuit 100 has been successful, and at this time, the first device 200 continues to supply power to the adapter circuit 100. Subsequently, the controller 110 outputs a wake-up signal to turn on the first switch Q1, which in turn powers the light emitter of the first optocoupler U4 and turns on the light receiver of the first optocoupler U4. An electrical connection is established between the first wake-up pin WAKE1 and the second wake-up pin WAKE2, waking up the second device 300. Data interaction between the first device 200 and the second device 300 can then be realized.

[0113] In some embodiments, the second device 300 includes a second pull-up resistor, the first end of which is input to the power supply voltage of the second device, and the second end of which is electrically connected to a second node. Specifically, as shown below... Figure 9 As shown.

[0114] The second device 300 is configured to determine whether to supply power to the transfer circuit 100 based on the voltage of the second node P2, wherein the second device 300 supplies power to the transfer circuit 100 when the voltage of the second node P2 is the third voltage V3, and the second device 300 does not supply power to the transfer circuit 100 when the voltage of the second node P2 is the fourth voltage V4.

[0115] Specifically, first, the second device 300 starts up. When the second device 300 is electrically connected to the adapter circuit 100, the second device 300 can obtain the voltage of the second node P2 as the third voltage V3, and V3=((R1+R2) / / R3) / (((R1+R2) / / R3)+RA2)*VB+, and the second device 300 supplies power to the adapter circuit 100. Conversely, if the second device 300 is not electrically connected to the adapter circuit 100, the second device 300 can obtain the voltage of the second node P2 as the supply voltage of the second device 300, and the second device 300 does not supply power to the adapter circuit 100.

[0116] After the second device 300 supplies power to the transfer circuit 100, the voltage on the power connection line between the transfer circuit 100 and the first device 200 can reach the activation threshold of the first device 200, thereby activating the first device 200. Afterwards, data interaction between the first device 200 and the second device 300 can be realized.

[0117] The foregoing content describes two application scenarios for realizing data interaction between the first device 200 and the second device 300. One scenario is that the first device 200 starts first and then activates the second device 300 to realize data interaction between the first device 200 and the second device 300. The other scenario is that the second device 300 starts first and then activates the first device 200 to realize data interaction between the first device 200 and the second device 300.

[0118] After data interaction is established between the first device 200 and the second device 300, the following two situations may occur:

[0119] (1) The electrical connection between the first device 200 and the adapter circuit 100 is disconnected, and / or the communication between the first device 200 and the adapter circuit 100 is interrupted, and the first device 200 stops outputting power (including stopping supplying power to the adapter circuit 100). It can be understood that when the electrical connection between the first device 200 and the adapter circuit 100 is disconnected, the signal connection line (the signal connection line is used to transmit information, the purpose of which is to transmit logic state (0 or 1), analog voltage, frequency or data, etc.) can be set to disconnect before the power connection line (the power connection line is used to transmit energy, the purpose of which is to provide the electrical energy required for the operation of the device) is disconnected, so that the first device 200 has stopped outputting power before the power connection line between the first device 200 and the adapter circuit 100 is disconnected, thereby avoiding the hot-plugging of the first device 200 while it is powered on. Wherein, the electrical connection between the first device 200 and the adapter circuit 100 is disconnected means that the first device 200 detects that the voltage of the first node P1 is the first voltage V1, and V1=RB2 / (RB1+RB2)*V5.

[0120] Afterwards, controller 110 outputs a control signal to energize the emitter of the second optocoupler U5, turn on the receiver of the second optocoupler U5, and turn off the third switch Q3. At this time, if the toggle switch K1 has been manually opened, the voltage of the second node P2 is the power supply voltage VB+ of the second device 300; if the toggle switch K1 has not been manually opened, i.e., the toggle switch K1 remains closed, the voltage of the second node P2 is the fourth voltage V4: V4 = R1 / (R1+RA2)*VB+. Thus, when the second device 300 determines that the voltage of the second node P2 is the fourth voltage V4 or the power supply voltage VB+ of the second device 300, the second device 300 stops operating. Disconnecting the electrical connection between the second device 300 and the adapter circuit 100 afterwards helps to avoid hot-swapping the second device 300 while it is powered on.

[0121] (2) When the electrical connection between the second device 300 and the adapter circuit 100 is disconnected, the second device 300 will first detect that the voltage of the second node P2 is the power supply voltage VB+ of the second device 300. Then the second device 300 will determine that the electrical connection between the second device 300 and the adapter circuit 100 is disconnected, and the second device 300 will stop operating. Similarly, when the electrical connection between the second device 300 and the adapter circuit 100 is disconnected, the signal connection line can be set to disconnect before the power connection line of the second device 300 and the adapter circuit 100 is disconnected, so that the second device 300 has stopped operating before the power connection line of the second device 300 and the adapter circuit 100 is disconnected, thereby avoiding hot-plugging of the second device 300 while it is powered on.

[0122] Subsequently, the transfer circuit 100 sends data to the first device 200 via the data transceiver circuit 120 to inform the first device 200 to stop operating. Disconnecting the electrical connection between the first device 200 and the transfer circuit 100 afterward helps prevent hot-swapping of the first device 200 while it is powered on.

[0123] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

[0124] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A switching circuit, characterized in that, The adapter circuit, configured to electrically connect a first device without a usable serial bus interface to a second device with a usable serial bus interface, includes: Controller; A data transceiver circuit, electrically connected between the controller and the first device, is configured to: in response to an enable signal output by the controller, generate a second communication signal with the same logical state as a first communication signal output by the controller, and send the second communication signal to the first device; or, in response to a third communication signal output by the first device, generate a fourth communication signal with the same logical state as the third communication signal, and send the fourth communication signal to the controller. A bus communication circuit, electrically connected between the controller and the second device, is configured to: establish serial communication between the controller and the second device to realize data interaction between the controller and the second device; The data transceiver circuit includes a tri-state gate and a first pull-up resistor; The enable pin of the tri-state gate is electrically connected to the pin of the controller that outputs the enable signal, the input pin of the tri-state gate is electrically connected to the pin of the controller that outputs the first communication signal, the output pin of the tri-state gate is electrically connected to the first device, the first end of the first pull-up resistor and the pin of the controller that receives the fourth communication signal, and the second end of the first pull-up resistor is electrically connected to the first power supply. When the controller outputs an enable signal and the first communication signal, the enable signal is input to the enable pin of the tri-state gate, the first communication signal is input to the input pin of the tri-state gate, and the output pin of the tri-state gate outputs the second communication signal to the first device. When the first device outputs the third communication signal, the fourth communication signal is generated at the first end of the first pull-up resistor based on the first power supply. The data transceiver circuit further includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a first Schottky diode, a second Schottky diode, and a Zener diode; The first terminal of the first resistor is electrically connected to the first device. The second terminal of the first resistor is electrically connected to the first terminal of the first capacitor. The second terminal of the first capacitor is electrically connected to the output pin of the tri-state gate, the cathode of the first Schottky diode, the cathode of the Zener diode, and the cathode of the second Schottky diode. The anodes of the first Schottky diode, the anode of the Zener diode, and the second terminal of the second capacitor are all grounded. The anode of the second Schottky diode is electrically connected to the first terminal of the fourth resistor. The second terminal of the fourth resistor is electrically connected to the first terminal of the second capacitor, the first terminal of the first pull-up resistor, and the pin of the controller that receives the fourth communication signal. The power supply pin of the tri-state gate is electrically connected to the second power supply. The ground pin of the tri-state gate is grounded. The enable pin of the tri-state gate is electrically connected to the pin of the controller that outputs the enable signal through the second resistor. The input pin of the tri-state gate is electrically connected to the pin of the controller that outputs the first communication signal through the third resistor.

2. The adapter circuit according to claim 1, characterized in that, The adapter circuit further includes a voltage divider circuit, which is electrically connected to the data transceiver circuit at a first node, and the first node is used to electrically connect to the first device. Wherein, when the first node is not electrically connected to the first device, the voltage of the first node is a first voltage, and when the first node is electrically connected to the first device, the voltage of the first node is a second voltage, and the first voltage and the second voltage are not equal.

3. The adapter circuit according to claim 2, characterized in that, The switching circuit further includes a voltage detection circuit, which is electrically connected to the first node and the controller. The voltage detection circuit is configured to generate a first detection signal to the controller based on the voltage of the first node; The controller is configured to: determine the voltage of the first node based on the first detection signal, and determine whether the first node is electrically connected to the first device based on the voltage of the first node.

4. The adapter circuit according to claim 1, characterized in that, The switching circuit further includes a wake-up circuit, which is electrically connected to the controller and is used to electrically connect the first wake-up pin and the second wake-up pin of the second device. The wake-up circuit is configured to: in response to a wake-up signal output by the controller, establish an electrical connection between the first wake-up pin and the second wake-up pin to wake up the second device.

5. The adapter circuit according to claim 1, characterized in that, The adapter circuit further includes a switching circuit and an output control circuit. The output control circuit is electrically connected to the controller and to the switching circuit. The switching circuit is used to electrically connect the second device to the second node. The switching circuit is configured to be in an on state or an off state, wherein when the switching circuit is in the off state, the voltage of the second node is a fourth voltage, and the second device stops operating. The output control circuit is configured to: when the switching circuit is in the on state, in response to not receiving a control signal output by the controller, control the voltage of the second node to a third voltage so that the second device determines that the transfer circuit is electrically connected to the second device in response to receiving the third voltage; or, in response to receiving a control signal output by the controller, control the voltage of the second node to the fourth voltage so that the second device stops operating.

6. The adapter circuit according to claim 2, characterized in that, The voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor; The first terminal of the first voltage divider resistor is input with a fifth voltage, the second terminal of the first voltage divider resistor and the first terminal of the second voltage divider resistor are electrically connected to the first node, and the second terminal of the second voltage divider resistor is grounded.

7. The adapter circuit according to claim 3, characterized in that, The voltage detection circuit includes an operational amplifier and a feedback resistor; The non-inverting input of the operational amplifier is electrically connected to the first node, the inverting input of the operational amplifier is electrically connected to the output of the operational amplifier through the feedback resistor, and the output of the operational amplifier is electrically connected to the controller.

8. The adapter circuit according to claim 4, characterized in that, The wake-up circuit includes a first optocoupler and a first switching transistor; The first terminal of the first switching transistor is electrically connected to the controller, the second terminal of the first switching transistor is grounded, the third terminal of the first switching transistor is electrically connected to the cathode of the light emitter of the first optocoupler, the anode of the light emitter of the first optocoupler is electrically connected to the second power supply, the first terminal of the light receiver of the first optocoupler is electrically connected to the first wake-up pin, and the second terminal of the light receiver of the first optocoupler is electrically connected to the second wake-up pin. In response to the wake-up signal output by the controller, the first switch is turned on to turn on the first optocoupler and establish an electrical connection between the first wake-up pin and the second wake-up pin to wake up the second device.

9. The adapter circuit according to claim 5, characterized in that, The switching circuit includes a toggle switch, and the output control circuit includes a second optocoupler, a second switching transistor, a third switching transistor, a first combined resistor, a second combined resistor, and a third combined resistor. The first terminal of the second switch is electrically connected to the controller, the second terminal of the second switch is grounded, the third terminal of the second switch is electrically connected to the cathode of the light emitter of the second optocoupler, the anode of the light emitter of the second optocoupler is electrically connected to the second power supply, the first terminal of the light receiver of the second optocoupler is electrically connected to the first terminal of the first combined resistor, the first terminal of the second combined resistor and the first terminal of the third switch, the second terminal of the light receiver of the second optocoupler is electrically connected to the second terminal of the second combined resistor, the second terminal of the third switch and ground, the third terminal of the third switch is electrically connected to the first terminal of the third combined resistor, the second terminal of the first combined resistor is electrically connected to the second terminal of the third combined resistor and the first terminal of the toggle switch, and the second terminal of the toggle switch is electrically connected to the second node.

10. A communication system, characterized in that, It includes a first device without a usable serial bus interface, a second device with a usable serial bus interface, and a switching circuit as described in any one of claims 1-9, the switching circuit being electrically connected between the first device and the second device.

11. The communication system according to claim 10, characterized in that, The first device includes a third voltage divider resistor and a fourth voltage divider resistor. The first terminal of the third voltage divider resistor is input with a fifth voltage. The second terminal of the third voltage divider resistor is electrically connected to the first terminal of the fourth voltage divider resistor and a first node. The second terminal of the fourth voltage divider resistor is grounded. The first device is configured as follows: Based on the voltage of the first node, determine whether the first device supplies power to the adapter circuit, wherein the first device supplies power to the adapter circuit when the voltage of the first node is the second voltage, and the first device does not supply power to the adapter circuit when the voltage of the first node is the first voltage. After the first device supplies power to the adapter circuit, it is determined whether the first device and the adapter circuit are successfully connected based on the communication result between the first device and the adapter circuit. Specifically, if the communication result is successful, it is determined that the first device and the adapter circuit are successfully connected; if the communication result is unsuccessful, it is determined that the first device and the adapter circuit are unsuccessful. When it is determined that the first device is successfully connected to the adapter circuit, the first device continues to supply power to the adapter circuit; When it is determined that the first device has failed to connect to the adapter circuit, the first device stops supplying power to the adapter circuit.

12. The communication system according to claim 10, characterized in that, The second device includes a second pull-up resistor, the first end of which is input to the power supply voltage of the second device, and the second end of which is electrically connected to a second node; The second device is configured as follows: Based on the voltage of the second node, it is determined whether the second device supplies power to the transfer circuit. Specifically, the second device supplies power to the transfer circuit when the voltage of the second node is the third voltage, and the second device does not supply power to the transfer circuit when the voltage of the second node is the fourth voltage.

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