Interface protocol converters and electronic devices
By optimizing the interface protocol converter of the data path structure, the efficiency bottleneck in the collaborative operation of the AXI bus protocol and SRAM interface was solved, achieving higher bandwidth utilization and energy efficiency, and reducing hardware resource consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MOFFETT AI TECHNOLOGY SHENZHEN CO LTD
- Filing Date
- 2026-04-22
- Publication Date
- 2026-07-31
AI Technical Summary
In existing technologies, the collaborative operation of the AXI bus protocol and SRAM interface has significant efficiency bottlenecks. Traditional converters are complex to design, consume high hardware resources, have low bandwidth utilization, and perform poorly in high-frequency operation and power-sensitive applications.
By optimizing the data path structure, an interface protocol converter is designed, including a read conversion module and a write conversion module. Utilizing first-in-first-out memory and a request unpacking unit, the SRAM interface characteristics are optimized, simplifying the design and reducing latency and hardware resource consumption.
It significantly reduces conversion latency and hardware resource consumption, improves bandwidth utilization and energy efficiency, and achieves higher data transmission efficiency.
Smart Images
Figure CN122086821B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuits, and in particular to digital system design, interface protocol conversion technology, and especially to interface protocol converters and electronic devices. Background Technology
[0002] In existing digital system designs, the collaborative operation of the Advanced eXtensible Interface (AXI) bus protocol and the Static Random-Access Memory (SRAM) interface often faces significant efficiency bottlenecks. Traditional solutions often employ general-purpose AXI-to-SRAM converters, which are typically complex in design, integrating numerous state machines and multi-stage pipeline structures to handle the various transmission modes and burst lengths of the AXI protocol. Summary of the Invention
[0003] This disclosure provides an interface protocol converter and an electronic device.
[0004] According to one aspect of this disclosure, an interface protocol converter is provided, comprising: a read conversion module configured to convert the interface protocol of the read channel of an Advanced Scalable Interface (ASPI) into the interface protocol of a Static Random Access Memory (SRAM), wherein the read channel of the ASPI includes a read address channel and a read data channel; the read conversion module further comprising: a read address FIFO memory configured to store read address information obtained from the read address channel, wherein the read address information includes read identity information and read burst information; a read request expansion unit configured to generate multiple read requests one by one based on the read burst information and send the multiple read requests one by one to the SRAM; a read identity FIFO memory configured to store read identity information corresponding to the generated read request obtained from the read address FIFO memory when each of the multiple read requests is generated; and a read data control FIFO memory configured to store single-bit data when each of the multiple read requests is generated, to maintain consistency with the depth of the read identity FIFO memory; and a write conversion module configured to convert the interface protocol of the write channel of the ASPI into the interface protocol of the SRAM.
[0005] In some embodiments, the read request expansion unit is further configured to control whether to continue generating subsequent read requests based on the read burst information and whether to send the currently generated read request to the static random access memory, based on the memory status information returned by the read identity first-in-first-out memory and the back pressure signal returned by the static random access memory, whenever a read request is generated based on the read burst information.
[0006] In some embodiments, the read conversion module further includes a read data buffer unit configured to store read data returned from static random access memory and to send the read data to the read data channel.
[0007] In some embodiments, the read data buffer unit is a first-in-first-out memory structure or a bypass structure.
[0008] In some embodiments, when the read data buffer unit is a first-in-first-out (FIFO) memory structure, the depth of the read data buffer unit is consistent with that of the read data control FIFO memory and the read identity FIFO memory.
[0009] In some embodiments, generating multiple read requests one by one based on read burst information includes: expanding the read burst information using a calculator and an adder to generate multiple read requests one by one.
[0010] In some embodiments, the write channel of the advanced extensible interface includes a write address channel and a write data channel. The write conversion module includes: a write address FIFO memory configured to store write address information obtained from the write address channel, wherein the write address information includes write identity information and write burst information; a write request expansion unit configured to generate multiple write requests one by one based on the write burst information and send the multiple write requests one by one to a static random access memory; a write identity FIFO memory configured to store write identity information corresponding to the generated write request obtained from the write address FIFO memory when each of the multiple write requests is generated; and a write data FIFO memory configured to store write data passed from the write data channel and send the write data to the static random access memory when the write request expansion unit sends the multiple write requests one by one.
[0011] In some embodiments, the write request expansion unit is configured to control whether to continue generating subsequent write requests based on the write burst information and whether to send the currently generated write request to the static random access memory, based on the memory status information returned by the write data first-in-first-out memory, the backpressure signal returned by the static random access memory, and the memory status information returned by the write identity first-in-first-out memory, whenever a write request is generated based on the write burst information.
[0012] In some embodiments, the depths of the write address FIFO memory, the write identity FIFO memory, and the write data FIFO memory are different.
[0013] According to another aspect of this disclosure, an electronic device is provided, including an interface protocol converter as provided above.
[0014] According to one or more embodiments of this disclosure, by optimizing the data path structure, deep optimization of the SRAM interface characteristics can be achieved, which can significantly reduce conversion latency and hardware resource consumption, while achieving higher bandwidth utilization and energy efficiency.
[0015] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description
[0016] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.
[0017] Figure 1 This is a block diagram illustrating an interface protocol converter according to an exemplary embodiment.
[0018] Figure 2 This is a block diagram illustrating the write conversion module of an interface protocol converter according to an exemplary embodiment.
[0019] Figure 3 This is a schematic diagram illustrating a specific read conversion module of an interface protocol converter according to an exemplary embodiment.
[0020] Figure 4 This is a schematic diagram illustrating the write conversion module of an interface protocol converter according to an exemplary embodiment. Detailed Implementation
[0021] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.
[0022] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.
[0023] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.
[0024] In existing digital system designs, the collaborative operation of the AXI bus protocol and SRAM memory interface often faces significant efficiency bottlenecks. Traditional solutions mostly employ general-purpose AXI-to-SRAM converters. These converters are typically complex in design, integrating numerous state machines and multi-stage pipeline structures to handle the various transmission modes and burst lengths of the AXI protocol. However, this general-purpose design incurs significant timing overhead and area costs, especially performing poorly in high-frequency operations or power-sensitive applications. Furthermore, existing converters often lack in-depth optimization for SRAM interface characteristics, such as failing to effectively utilize SRAM byte enable signals or address auto-incrementing features, resulting in low actual bandwidth utilization.
[0025] Existing technologies also utilize standardized IP cores provided by Field Programmable Gate Array (FPGA) vendors. However, these IP cores are designed to be overly bulky to accommodate various application scenarios. They have numerous configurable parameters but limited practical optimization, and timing convergence issues exist at certain process nodes. More importantly, existing solutions often employ conservative data path designs when dealing with unaligned accesses or partial write operations, requiring multiple accesses or complex data reassembly logic to complete the operation. This not only increases latency but also results in unnecessary power consumption.
[0026] The embodiments of this disclosure provide an interface protocol converter that optimizes the data path structure to achieve deep optimization of SRAM interface characteristics, which can significantly reduce conversion latency and hardware resource consumption, while achieving higher bandwidth utilization and energy efficiency.
[0027] Figure 1 This is a block diagram illustrating an interface protocol converter 100 according to an exemplary embodiment.
[0028] like Figure 1As shown, this disclosure proposes an interface protocol converter 100, including: a read conversion module 110 configured to convert the interface protocol of an AXI read channel to an SRAM interface protocol, wherein the AXI read channel includes a read address (AR) channel and a read data (R) channel, and the read conversion module 110 includes: a read address first-in-first-out (FIFO) memory 112 configured to store read address information obtained from the AR channel, wherein the read address information includes read identity information and read burst information; and a read request expansion unit 114 configured to generate multiple read requests one by one based on the read burst information. The system requests multiple read requests to SRAM one by one; a read identity FIFO memory 116 is configured to store read identity information corresponding to the generated read request obtained from read address FIFO memory 112 when each read request is generated; a read data control FIFO memory 118 is configured to store single-bit data when each read request is generated to maintain consistency with the depth of read identity FIFO memory 116; and a write conversion module 120 is configured to convert the AXI write channel interface protocol to the SRAM interface protocol.
[0029] In the example, reading burst information can include the address of the read address (araddr), the length of the read address (arlen), etc., and reading identity information can be represented as arid.
[0030] Therefore, by pushing the read identity information into the read identity FIFO memory, the read requests received by the interface of the subsequent SRAM do not contain the read identity information. The SRAM only needs to process a single read request and does not need to process the read identity information. In addition, the empty / full status of the read identity FIFO memory or the read data control FIFO memory can fully reflect the empty / full status of the subsequent SRAM, which simplifies the design while achieving correct back pressure.
[0031] In some embodiments, the read request expansion unit 114 is further configured to control whether to continue generating subsequent read requests based on the read burst information and whether to send the currently generated read request to the SRAM, based on the memory status information returned by the read identity first-in-first-out memory 116 and the back pressure signal returned by the SRAM, whenever a read request is generated based on the read burst information.
[0032] In the example, the memory status information returned by the read identity FIFO memory 116 can include Almost Full, Full, Empty, etc., and the backpressure signal returned by the SRAM can be represented as i_sram_gnt (on the read side, i_sram_gnt = 1 indicates no backpressure, and 0 indicates backpressure), which can indicate whether backpressure is applied or not. For example, when the memory status information is Empty and i_sram_gnt = 1, it means that the read identity FIFO memory 116 is empty (all data has been taken), and the backpressure signal is invalid. In this case, the read request expansion unit 114 can continue to generate subsequent read requests based on the read burst information and can send the currently generated read request to the SRAM. When the memory status information is Almost Full and i_sram_gnt = 0, it means that the read identity FIFO memory 116 is almost full, and the backpressure signal is valid. In this case, the read request expansion unit 114 cannot continue to generate subsequent read requests based on the read burst information or send the currently generated read request to the SRAM.
[0033] In some embodiments, the read conversion module 110 further includes a read data buffer unit configured to store read data returned from SRAM and send the read data to the R channel.
[0034] In the example, the read conversion module 110 also includes a read data buffer unit for interface protocol conversion of the R channel.
[0035] In some embodiments, the read data buffer unit is a first-in-first-out (FIFO) memory structure or a bypass structure.
[0036] In the example, the read data buffer unit can be a physically existing data FIFO, or it can be configured as a bypass structure to save resources.
[0037] When the read data buffer unit is a bypass structure (signaled as EN_DATA_FIFO == 0), the data returned by the subsequent SRAM interface directly enters the AXI master device's data FIFO without the need for interface protocol converter buffering. The AXI master device's data FIFO, read identity FIFO 116, and read data control FIFO 118 need to be synchronized when pushing out data to maintain consistent depth, thereby ensuring normal reverse pressure. If the SRAM interface has a step-by-step reverse pressure structure, the AXI master device's data FIFO can have its depth set independently, and it is not mandatory for it to have the same depth as the read identity FIFO 116 and read data control FIFO 118.
[0038] In some embodiments, when the read data buffer unit is a first-in-first-out (FIFO) memory structure, the depth of the read data buffer unit needs to be consistent with the depth of the read data control FIFO memory 118 and the read identity FIFO memory 116.
[0039] In the example, when the read data buffer unit is a first-in-first-out (FIFO) memory structure (signaled as EN_DATA_FIFO != 0), since the interface protocol converter has an internal data FIFO (i.e., read data buffer unit), the data needs to be buffered by the interface protocol converter before being sent to the AXI master device. Therefore, in the absence of step-by-step reverse pressure on the SRAM interface, the read data buffer unit, the read identity FIFO memory 116, and the read data control FIFO memory 118 need to be synchronized when pushing out data to maintain consistent depth, thereby ensuring normal reverse pressure. If the SRAM interface has a step-by-step reverse pressure structure, the data FIFO, which serves as the read data buffer unit, can have its depth set independently and is not required to have the same depth as the read identity FIFO memory 116 and the read data control FIFO memory 118.
[0040] In some embodiments, generating multiple read requests one by one based on read burst information may include expanding the read burst information using a timer and an adder to generate multiple read requests one by one.
[0041] In the example, the read request expansion unit 114 can expand the read burst information based on the memory status information returned by the first-in-first-out memory 116 based on the read identity and the back pressure signal i_sram_gnt returned by the SRAM (e.g., generated through logic gates). The specific expansion process includes inputting the read address timing signal arcnt generated by the timer and the address araddr of the read address into the adder to obtain the read request.
[0042] Figure 2 This is a block diagram illustrating the write conversion module 120 of an interface protocol converter 100 according to an exemplary embodiment.
[0043] In some embodiments, the AXI write channel includes a write address (AW) channel and a write data (W) channel. The write conversion module 120 includes: a write address first-in-first-out memory 122, configured to store write address information obtained from the AW channel, wherein the write address information includes write identity information and write burst information; a write request expansion unit 124, configured to generate multiple write requests one by one based on the write burst information, and send the multiple write requests one by one to SRAM; a write identity first-in-first-out memory 126, configured to store write identity information obtained from the write address first-in-first-out memory 122 corresponding to the generated write request when each of the multiple write requests is generated; and a write data first-in-first-out memory 128, configured to store write data received from the W channel, and send the write data to SRAM when the write request expansion unit sends the multiple write requests one by one.
[0044] In the example, writing burst information can include the address wraddr of the write address, the length wrlen of the read address, etc., and reading identity information can be represented as wid.
[0045] Therefore, by pushing the write identity information into the write identity first-in-first-out memory, the write requests received by the interface of the subsequent SRAM do not contain the write identity information. Only a single write request needs to be processed, and the write identity information does not need to be processed. In addition, the empty or full state of the write identity first-in-first-out memory can completely reflect the empty or full state information of the subsequent SRAM, which simplifies the design while achieving correct backpressure.
[0046] In some embodiments, the write request expansion unit 124 is configured to control whether to continue generating subsequent write requests based on the write burst information and whether to send the currently generated write request to the SRAM, based on the memory status information returned by the write data first-in-first-out memory 128, the back pressure signal returned by the SRAM, and the memory status information returned by the write identity first-in-first-out memory 126, whenever a write request is generated based on the write burst information.
[0047] In the example, the memory status information returned by the write data first-in-first-out memory 128 and the write identity first-in-first-out memory 126 may include Almost Full, Full, Empty, etc., and the back pressure signal returned by the SRAM can be represented as i_sram_gnt, which can indicate back pressure or no back pressure. The write data FIFO memory 128 and the write request expansion unit 124 can jointly provide data and write request information to the subsequent SRAM when there is no backpressure. For example, when the write data FIFO memory 128 is not Empty and the memory status information returned by the write identity FIFO memory 126 is not full and i_sram_gnt=1 (on the write side, i_sram_gnt is 1 when there is no backpressure, and 0 when there is backpressure), it means that the write data FIFO memory 128 has data to send to the subsequent SRAM and the write identity FIFO memory 126 can store the write identity information. The backpressure signal is invalid. Then, the write data FIFO memory 128 can send the write data to the subsequent SRAM, and the write request expansion unit 124 can continue to generate subsequent write requests based on the write burst information and can send the currently generated write request to the SRAM. When the memory status information returned by both the write data FIFO memory 128 and the write identity FIFO memory 126 is Almost, When the SRAM is full and i_sram_gnt=0, it means that the write data first-in-first-out memory 128 and the write identity first-in-first-out memory 126 are almost full. The back pressure signal is valid. Therefore, the write request expansion unit 124 cannot continue to generate subsequent write requests based on the write burst information or send the currently generated write request to the SRAM.
[0048] Therefore, by using the write data first-in-first-out memory 128, the write identity first-in-first-out memory 126, and the signals returned by the SRAM to control the write request expansion unit 124 to expand the write burst information, the design is simplified while achieving correct back pressure.
[0049] In the example, the depths of the write address first-in-first-out memory 122, the write identity first-in-first-out memory 126, and the write data first-in-first-out memory 128 can be different.
[0050] In the example, since write address operations and write data operations can be asynchronous, the push operations of the three write address FIFO memory 122, write identity FIFO memory 126, and write data FIFO memory 128 can be asynchronous, and their depth settings can be different.
[0051] Figure 3 This is a schematic diagram illustrating the read conversion module 320 of the interface protocol converter 100 according to an exemplary embodiment.
[0052] refer to Figure 3 The working principle of the read conversion module 320 is explained below: The AXI master device 310 may include a master device read request generator 311, a master device controller 312, a master device data buffer 313, and an AXI interface 314.
[0053] The read conversion module 320 includes a read address first-in-first-out memory 321, a read identity first-in-first-out memory 322, a read data control first-in-first-out memory 323, a read request expansion unit 324, and a read data buffer unit 325.
[0054] The read address FIFO memory 321 of the read conversion module 320 obtains and stores read identity information and read burst information (generated by the master device read request generator 311) from the read address channel 315 of the AXI interface 314 of the AXI master device 310; the read request expansion unit 324 obtains the read identity information and read burst information pushed out from the read address FIFO memory 321, and generates multiple read requests one by one based on the read burst information, and sends the multiple read requests one by one to the SRAM interface 330 for read address operation; the read identity FIFO memory 322 can store the read identity information obtained from the read address FIFO memory 321 corresponding to the generated read request when each of the multiple read requests is generated; the read data control FIFO memory 323 is configured to store single-bit data when each of the multiple read requests is generated, so as to keep the depth consistent with the read identity FIFO memory 322.
[0055] The read request expansion unit 324 can also control whether to continue generating subsequent read requests based on the read burst information and whether to send the currently generated read request to the SRAM, based on the memory status information returned by the read data control first-in-first-out memory 323 and the back pressure signal returned by the SRAM interface 330, after each read request is generated based on the read burst information.
[0056] The read conversion module 320 also includes a read data buffer unit 325, which can be configured to store SRAM read data 321 returned from SRAM and send the SRAM read data 321 to the read data channel 316 of the AXI master device 310.
[0057] The read data buffer unit 325 can be a first-in-first-out memory structure or a bypass structure.
[0058] When the read data buffer unit 325 is a bypass structure, the SRAM read data 321 is directly transmitted to the master device data buffer 313 through the read conversion module 320 via line 317.
[0059] When the read data buffer unit 325 is a first-in-first-out (FIFO) memory structure, the depth of the read data buffer unit 325 is consistent with that of the read data control FIFO memory 323 and the read identity FIFO memory 322.
[0060] The read request expansion unit 324 can expand the read burst information based on the memory status information returned by the read data control first-in-first-out memory 321 and the reverse pressure signal i_sram_gnt returned by the SRAM interface 330 (e.g., generated through logic gates). The specific expansion process includes inputting the read address timing signal arcnt generated by the timer and the read address address araddr into the adder to obtain the read request.
[0061] Figure 4 This is a schematic diagram illustrating the write conversion module 420 of the interface protocol converter 100 according to an exemplary embodiment.
[0062] refer to Figure 4 The working principle of the write conversion module 420 is explained below: The AXI 410 includes a write address channel 411, a write response channel 413, and a write data channel 412.
[0063] The write conversion module 420 includes a write address first-in-first-out memory 421, a write request expansion unit 424, a write identity first-in-first-out memory 422, and a write data first-in-first-out memory 423.
[0064] The write address FIFO memory 421 is configured to store write address information obtained from the write address channel 411, wherein the write address information includes write identity information and write burst information; the write request expansion unit 424 is configured to generate multiple write requests one by one based on the write burst information, and send the multiple write requests one by one to the SRAM interface 430 for write address operation; the write identity FIFO memory 422 is configured to store the write identity information corresponding to the generated write request obtained from the write address FIFO memory 421 when each of the multiple write requests is generated, wherein the write identity information can be returned to AXI as the write response information of the subsequent write response channel 413. 410 (The write request reaches its destination at the write conversion module, and after the write response channel 413 of the AXI410 master device is ready, an early response can be returned sequentially)); and the write data first-in-first-out memory 423 is configured to store the write data 425 passed from the write data channel 412, and when the write request expansion unit sends multiple write requests one by one, it sends the write data 425 and the write strobe data 426 to the SRAM interface 430.
[0065] The write request expansion unit 424 is configured to control whether to continue generating subsequent write requests based on the write burst information and whether to send the currently generated write request to the SRAM interface 430 after each write request is generated based on the memory status information returned by the write data first-in-first-out memory 423 (e.g., an empty signal), the back pressure signal returned by the SRAM interface 430, and the memory status information returned by the write identity first-in-first-out memory 422.
[0066] Since write address operations and write data operations can be asynchronous, the depths of write address first-in-first-out memory 421, write identity first-in-first-out memory 422, and write data first-in-first-out memory 423 can be different.
[0067] It should be understood that, Figure 3 and Figure 4 These are all examples for illustrative purposes, not for limiting purposes. For instance, the structure of the read conversion module and the write conversion module of the interface protocol converter does not have to be... Figure 3 and Figure 4 The structure of the example in the text.
[0068] According to one aspect of this disclosure, an electronic device is also provided, including the interface protocol converter of any of the embodiments described above.
[0069] The various features and processes described above can be used independently or combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Furthermore, certain method or process blocks may be omitted in some embodiments. The methods and processes described herein are not limited to any particular order, and associated blocks or states may be executed in other suitable orders. For example, described blocks or states may be executed in a non-specifically disclosed order, or multiple blocks or states may be combined in a single block or state. Exemplary blocks or states may be executed serially, in parallel, or otherwise. Blocks or states may be added to or removed from the disclosed exemplary embodiments. The exemplary systems and components described herein may be configured differently from those described. For example, elements may be added, removed, or rearranged compared to the disclosed exemplary embodiments.
[0070] The various operations of the exemplary methods described herein can be performed at least in part by an algorithm. An algorithm may consist of program code or instructions stored in memory (such as the non-transitory computer-readable storage medium described above). Such an algorithm may include a machine learning algorithm. In some embodiments, the machine learning algorithm may not be explicitly programmed into the computer to perform the function, but may learn from training data to obtain a predictive model for performing that function.
[0071] The various operations of the exemplary methods described herein can be performed at least in part by one or more processors, which are temporarily configured (e.g., by software) or permanently configured to perform the relevant operations. Whether temporarily or permanently configured, such processors can constitute the engine of a processor implementation whose operation is to perform one or more of the operations or functions described herein.
[0072] Similarly, the methods described herein can be implemented at least partially by a processor, where a specific processor or one or more processors are examples of hardware. For example, at least some operations of the methods can be performed by one or more processors or an engine implemented by a processor. Furthermore, one or more processors can also run in a “cloud computing” environment or as “Software as a Service” (SaaS) to support the execution of the relevant operations. For example, at least some operations can be performed by a group of computers (as an example of a machine including processors), which can be accessed via a network (e.g., the Internet) and through one or more appropriate interfaces (e.g., application programming interfaces (APIs)).
[0073] The performance of certain operations can be distributed across processors, not just residing within a single machine, but deployed across many machines. In some exemplary embodiments, the processor or the processor-implemented engine may reside in a single geographic location (e.g., in a home environment, office environment, or server farm). In other exemplary embodiments, the processor or the processor-implemented engine may be distributed across many geographic locations.
[0074] In this specification, multiple instances may implement components, operations, or structures described as a single instance. Although individual operations of one or more methods are described and illustrated as independent operations, one or more individual operations may be performed concurrently, and these operations are not required to be performed in the order shown. Structures and functionalities presented as independent components in the example configuration may be implemented as combined structures or components. Similarly, structures and functionalities presented as individual components may be implemented as independent components. These and other variations, modifications, additions, and improvements are all within the scope of this document.
[0075] As used herein, “or” is inclusive rather than exclusive unless explicitly stated or indicated by context. Furthermore, “and” is both common and individual unless explicitly stated or indicated by context. Moreover, multiple instances may be provided for the resources, operations, or structures described herein as a single example. Furthermore, the boundaries between various resources, operations, engines, and data stores are somewhat arbitrary, and specific operations are illustrated within the context of a particular illustrative configuration. The allocation of other functionalities is conceivable and may fall within the scope of various embodiments of this disclosure. Generally, structures and functionalities presented as independent resources in example configurations may be implemented as combined structures or resources. Similarly, structures and functionalities presented as individual resources may be implemented as independent resources. These and other variations, modifications, additions, and improvements are all within the scope of embodiments of this disclosure. Therefore, this specification and accompanying drawings should be viewed in an illustrative rather than restrictive sense.
[0076] The terms “comprising” or “including” are used to indicate the presence of a subsequently stated feature, but do not preclude the addition of other features. Conditional language, in particular, such as “may,” “can,” or “may,” unless specifically stated or otherwise understood in the context of use, is generally intended to express that certain embodiments include certain features, elements, and / or steps, while other embodiments do not. Therefore, such conditional language generally does not imply that a feature, element, and / or step is necessary in any way for one or more embodiments, or that one or more embodiments must include logic that, with or without user input or prompting, determines whether such features, elements, and / or steps are included in any particular embodiment, or whether they are to be performed in any particular embodiment.
Claims
1. An interface protocol converter, characterized in that, The interface protocol converter includes: A read conversion module is configured to convert the interface protocol of the read channel of an Advanced Scalable Interface (ASPI) into the interface protocol of a Static Random Access Memory (SRAM), wherein the read channel of the ASPI includes a read address channel and a read data channel, and the read conversion module includes: The read address first-in-first-out memory is configured to store read address information obtained from the read address channel, wherein the read address information includes read identity information and read burst information; The read request expansion unit is configured to generate multiple read requests one by one based on the read burst information, and send the multiple read requests one by one to the static random access memory; A read identity first-in-first-out (FIFO) memory is configured to store read identity information corresponding to the generated read request, obtained from the read address FIFO memory, when each of the plurality of read requests is generated; and The read data control first-in-first-out (FIFO) memory is configured to store a single bit of data at the time of each of the plurality of read requests, to maintain consistency with the depth of the read identity FIFO memory. The write conversion module is configured to convert the interface protocol of the write channel of the Advanced Extensible Interface (ALE) into the interface protocol of the Static Random Access Memory (SRAM), and The read request expansion unit is further configured to control whether to continue generating subsequent read requests based on the read burst information and whether to send the currently generated read request to the static random access memory, based on the memory status information returned by the read identity first-in-first-out memory and the back pressure signal returned by the static random access memory, whenever a read request is generated based on the read burst information.
2. The interface protocol converter according to claim 1, characterized in that, The read conversion module also includes: A read data buffer unit is configured to store read data returned from the static random access memory and to send the read data to the read data channel.
3. The interface protocol converter according to claim 2, characterized in that, The read data buffer unit is a first-in-first-out memory structure or a bypass structure.
4. The interface protocol converter according to claim 3, characterized in that, When the read data buffer unit is a first-in-first-out (FIFO) memory structure, the depth of the read data buffer unit is consistent with that of the read data control FIFO memory and the read identity FIFO memory.
5. The interface protocol converter according to claim 1, characterized in that, Based on the read burst information, multiple read requests are generated one by one, including: The read burst information is expanded using a calculator and an adder to generate the multiple read requests one by one.
6. The interface protocol converter according to any one of claims 1 to 5, characterized in that, The write channel of the advanced extensible interface includes a write address channel and a write data channel, and the write conversion module includes: The write address first-in-first-out memory is configured to store write address information obtained from the write address channel, wherein the write address information includes write identity information and write burst information; The write request expansion unit is configured to generate multiple write requests one by one based on the write burst information, and send the multiple write requests one by one to the static random access memory. A write identity first-in-first-out (FIFO) memory is configured to store write identity information corresponding to the generated write request, obtained from the write address FIFO memory, when each of the plurality of write requests is generated; and The write data first-in-first-out memory is configured to store write data received from the write data channel, and to send the write data to the static random access memory when the write request expansion unit sends the plurality of write requests one by one.
7. The interface protocol converter according to claim 6, characterized in that, The write request expansion unit is configured to, whenever a write request is generated based on the write burst information, control whether the write request expansion unit continues to generate subsequent write requests based on the write burst information and whether to send the currently generated write request to the static random access memory, based on the memory status information returned by the write data first-in-first-out memory, the backpressure signal returned by the static random access memory, and the memory status information returned by the write identity first-in-first-out memory.
8. The interface protocol converter according to claim 7, characterized in that, The depths of the write address FIFO memory, the write identity FIFO memory, and the write data FIFO memory are different.
9. An electronic device, characterized in that, Includes the interface protocol converter as described in any one of claims 1 to 8.