Inter-nuclear communication systems, control methods, devices, equipment, media, and chip circuits

Abstract

This disclosure relates to the field of processor communication technology, specifically to an inter-core communication system, control method, apparatus, device, medium, and chip circuit. The inter-core communication system includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module is connected to each processor core in the subsystem via the subsystem bus, and the subsystem message queue module is connected to the on-chip system message queue module. This solution can shorten the message transmission path length for inter-subsystem core communication and achieve physical isolation and traffic splitting between inter-subsystem core communication and cross-subsystem core communication, avoiding contention for the on-chip system bus between inter-subsystem core communication and cross-subsystem core communication, thereby reducing inter-core communication latency and improving inter-core communication efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of processor communication technology, specifically to an inter-core communication system, control method, device, equipment, medium, and chip circuit. Background Technology

[0002] In recent years, with the advancement of semiconductor technology, researchers have discovered that the higher the processor frequency, the more exponentially the processor's power consumption and heat generation increase, leading to overheating and unstable operation. Therefore, the approach of continuously increasing the clock frequency to improve the performance of a single processor has encountered bottlenecks such as high power consumption and difficulty in heat dissipation. Integrating multiple processor cores (including homogeneous Central Processing Unit (CPU) cores, heterogeneous CPU cores, Graphics Processing Unit (GPU) cores, Digital Signal Processor (DSP) cores, Neural Processing Unit (NPU) cores, etc.) onto a single chip to form a multi-core processor system has become the current technological development trend.

[0003] A multi-core processor system can include multiple subsystems, and processor cores in different subsystems can share resources such as cache, external storage, and network controllers. While sharing these resources, different processor cores also engage in frequent communication. If effective inter-core communication is not possible, the overall performance of the multi-core processor system will inevitably be affected. In related technologies, different processor cores can communicate with each other within the same subsystem and with each other across different subsystems via a bus.

[0004] However, in the above scheme, when the number of processor cores in a multi-core processor system is large, communication between processor cores in the same subsystem is prone to competing for bus resources with communication between processor cores in different subsystems, thereby increasing communication latency and power consumption of the multi-core processor system, resulting in low efficiency of inter-core communication. Summary of the Invention

[0005] To address the problems in related technologies, embodiments of this disclosure provide an inter-core communication system, control method, apparatus, device, medium, and chip circuit.

[0006] In a first aspect, this disclosure provides an inter-core communication system, which includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module in the subsystem is connected to each processor core in the subsystem through the subsystem bus, and the subsystem message queue module in the subsystem is connected to the on-chip system message queue module.

[0007] Any one of the multiple processor cores is configured as follows: Send messages to the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem where any processor core is located; The subsystem message queue module in the first subsystem is configured as follows: Retrieve messages sent by any processor core; If the target processor core of the message is determined to be the first processor core in the first subsystem, then the message will be scheduled to the first processor core. The first processor core is configured as follows: Messages scheduled by the subsystem message queue module in the first subsystem are obtained through the subsystem bus in the first subsystem. The subsystem message queue module in the first subsystem is also configured as follows: If the target processor core of the message is determined to be the second processor core of the second subsystem in multiple subsystems, then the message will be scheduled to the on-chip system message queue module. The on-chip system message queue module is configured as follows: Obtain messages scheduled by the subsystem message queue module in the first subsystem, and schedule the messages to the subsystem message queue module in the second subsystem; The subsystem message queue module in the second subsystem is configured as follows: Obtain messages scheduled by the on-chip system message queue module and schedule the messages to the second processor core; The second processor core is configured as follows: Messages are obtained through the subsystem bus in the second subsystem.

[0008] In one embodiment of this disclosure, sending a message to a subsystem message queue module in the first subsystem via a subsystem bus in the first subsystem containing any processor core includes: In the first subsystem, the subsystem message queue module configures a core message sending channel for any processor core, and determines the target core message sending channel corresponding to the priority in the message. If the target core message sending channel is idle, a message is sent to the target core message sending channel through the subsystem bus in the first subsystem.

[0009] In one embodiment of this disclosure, before acquiring a message sent by any processor core, the subsystem message queue module in the first subsystem is further configured to: Obtain the core weight corresponding to any processor core; Based on the core weight corresponding to any processor core, determine the maximum number of first data packets that any processor core can transmit in a single core communication cycle, wherein the core weight of any processor core is positively correlated with the number of first data packets of any processor core. Retrieve messages sent by any processor core, including: Within at least one core communication cycle, based on the first data packet number corresponding to any processor core, the message sent by any processor core is obtained from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem.

[0010] In one embodiment of this disclosure, obtaining a message sent by any processor core from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem includes: If the subsystem message queue module in the first subsystem includes at least one priority core message sending channel with currently available messages in the core message sending channel configured for any processor core, then the highest priority target priority core message sending channel is determined from the at least one priority core message sending channel with currently available messages, and the message sent by any processor core is obtained from the target priority core message sending channel. If the core message sending channel configured for any processor core in the subsystem message queue module of the first subsystem does not include at least one priority core message sending channel with currently available messages, and the core message sending channel configured for any processor core in the subsystem message queue module of the first subsystem includes at least one weighted fair core message sending channel with currently available messages, then the core message sending channel weight of each weighted fair core message sending channel in the at least one weighted fair core message sending channel with currently available messages is obtained, wherein the core message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair core message sending channel; Based on the message length of the message in each weighted fair core message sending channel in at least one currently available weighted fair core message sending channel and the corresponding core message sending channel weight, obtain the message transmission duration corresponding to each weighted fair core message sending channel in at least one currently available weighted fair core message sending channel, and determine the target weighted fair core message sending channel with the shortest message transmission duration in at least one currently available weighted fair core message sending channel. Obtain messages sent by any processor core from the target weighted fair core message sending channel.

[0011] In one embodiment of this disclosure, scheduling a message to a first processor core includes: In the core message receiving channel configured for the first processor core by the subsystem message queue module in the first subsystem, the first core message receiving channel corresponding to the priority in the message is determined; The message is scheduled to the first core message receiving channel, and the first interrupt notification is sent to the first processor core; Messages scheduled by the subsystem message queue module in the first subsystem are obtained through the subsystem bus in the first subsystem, including: In response to the first interrupt notification, the current process of the first processor core is interrupted; The message scheduled by the subsystem message queue module in the first subsystem is obtained from the first core message receiving channel through the subsystem bus in the first subsystem. Scheduling messages to the second processor core includes: In the core message receiving channel configured for the second processor core by the subsystem message queue module in the second subsystem, the second core message receiving channel corresponding to the priority in the message is determined. The message is scheduled to the second core message receiving channel, and a second interrupt notification is sent to the second processor core. Messages are obtained via the subsystem bus in the second subsystem, including: In response to the second interrupt notification, the current process of the second processor core is interrupted; Messages are obtained from the second core message receiving channel via the subsystem bus in the second subsystem.

[0012] In one embodiment of this disclosure, the inter-core communication system further includes a message interconnection network module, which is connected to the on-chip system message queue module and the subsystem message queue module in each of the multiple subsystems. Retrieve messages scheduled by the subsystem message queue module in the first subsystem, including: The message interconnection network module obtains messages scheduled by the subsystem message queue module in the first subsystem. Retrieve messages scheduled by the on-chip system message queue module, including: The message interconnection network module obtains messages scheduled by the on-chip system message queue module.

[0013] In one embodiment of this disclosure, scheduling a message to an on-chip system message queue module includes: In the subsystem message sending channel configured for the first subsystem by the on-chip system message queue module, determine the first subsystem message sending channel corresponding to the priority in the message; If the first subsystem message sending channel is idle, the message will be scheduled to the first subsystem message sending channel in the on-chip system message queue module.

[0014] In one embodiment of this disclosure, before obtaining the message scheduled by the subsystem message queue module in the first subsystem, the on-chip system message queue module is further configured as follows: Obtain the subsystem weight corresponding to any subsystem; Based on the subsystem weight corresponding to any subsystem, determine the maximum number of second data packets that any subsystem can transmit within a single subsystem communication cycle, wherein the subsystem weight of any subsystem is positively correlated with the number of second data packets of any subsystem. Retrieve messages scheduled by the subsystem message queue module in the first subsystem, including: Within at least one subsystem communication cycle, based on the second data packet number corresponding to the first subsystem, messages scheduled by the subsystem message queue module in the first subsystem are obtained from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem.

[0015] In one embodiment of this disclosure, obtaining messages scheduled by the subsystem message queue module in the first subsystem from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem includes: If the on-chip system message queue module configures at least one priority subsystem message sending channel with currently available messages in the subsystem message sending channel of the first subsystem, then the target priority subsystem message sending channel with the highest priority is determined from the at least one priority subsystem message sending channel with currently available messages, and the message scheduled by the subsystem message queue module in the first subsystem is obtained from the target priority subsystem message sending channel. If the on-chip system message queue module configures at least one priority subsystem message sending channel with currently available messages in the subsystem message sending channels of the first subsystem, and the on-chip system message queue module configures at least one weighted fair subsystem message sending channel with currently available messages in the subsystem message sending channels of the first subsystem, then the subsystem message sending channel weight of each weighted fair subsystem message sending channel in the at least one weighted fair subsystem message sending channel with currently available messages is obtained, wherein the subsystem message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair subsystem message sending channel; Based on the message length of the message in each of the at least one currently available weighted fair subsystem message sending channels and the corresponding subsystem message sending channel weight, obtain the message transmission duration corresponding to each of the at least one currently available weighted fair subsystem message sending channels, and determine the target weighted fair subsystem message sending channel with the shortest message transmission duration in the at least one currently available weighted fair subsystem message sending channels; Obtain messages scheduled by the subsystem message queue module in the first subsystem from the message sending channel of the target weighted fairness subsystem.

[0016] Secondly, this disclosure provides a control method for an inter-core communication system. The inter-core communication system includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module in the subsystem is connected to each processor core in the subsystem through the subsystem bus in the subsystem, and the subsystem message queue module in the subsystem is connected to the on-chip system message queue module. Inter-nuclear communication system control methods include: Control any one of the multiple processor cores and send messages to the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem where the processor core is located; Control the subsystem message queue module in the first subsystem to obtain messages sent by any processor core. If it is determined that the target processor core of the message is the first processor core in the first subsystem, then schedule the message to the first processor core. Control the first processor core and obtain messages scheduled by the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem; The subsystem message queue module in the first subsystem controls the message to the on-chip system message queue module when it determines that the target processor core of the message is the second processor core of the second subsystem in the multiple subsystems. Control the on-chip system message queue module to obtain messages scheduled by the subsystem message queue module in the first subsystem, and schedule the messages to the subsystem message queue module in the second subsystem; Control the subsystem message queue module in the second subsystem, obtain messages scheduled by the on-chip system message queue module, and schedule the messages to the second processor core; It controls the second processor core and obtains messages through the subsystem bus in the second subsystem.

[0017] In one embodiment of this disclosure, sending a message to a subsystem message queue module in the first subsystem via a subsystem bus in the first subsystem containing any processor core includes: In the first subsystem, the subsystem message queue module configures a core message sending channel for any processor core, and determines the target core message sending channel corresponding to the priority in the message. If the target core message sending channel is idle, a message is sent to the target core message sending channel through the subsystem bus in the first subsystem.

[0018] In one embodiment of this disclosure, the method further includes: The subsystem message queue module in the first control subsystem obtains the core weight corresponding to any processor core before obtaining the message sent by any processor core. Based on the core weight corresponding to any processor core, it determines the maximum number of first data packets that any processor core can transmit in a single core communication cycle. The core weight of any processor core is positively correlated with the number of first data packets of any processor core. Retrieve messages sent by any processor core, including: Within at least one core communication cycle, based on the first data packet number corresponding to any processor core, the message sent by any processor core is obtained from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem.

[0019] In one embodiment of this disclosure, obtaining a message sent by any processor core from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem includes: If the subsystem message queue module in the first subsystem includes at least one priority core message sending channel with currently available messages in the core message sending channel configured for any processor core, then the highest priority target priority core message sending channel is determined from the at least one priority core message sending channel with currently available messages, and the message sent by any processor core is obtained from the target priority core message sending channel. If the core message sending channel configured for any processor core in the subsystem message queue module of the first subsystem does not include at least one priority core message sending channel with currently available messages, and the core message sending channel configured for any processor core in the subsystem message queue module of the first subsystem includes at least one weighted fair core message sending channel with currently available messages, then the core message sending channel weight of each weighted fair core message sending channel in the at least one weighted fair core message sending channel with currently available messages is obtained, wherein the core message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair core message sending channel; Based on the message length of the message in each weighted fair core message sending channel in at least one currently available weighted fair core message sending channel and the corresponding core message sending channel weight, obtain the message transmission duration corresponding to each weighted fair core message sending channel in at least one currently available weighted fair core message sending channel, and determine the target weighted fair core message sending channel with the shortest message transmission duration in at least one currently available weighted fair core message sending channel. Obtain messages sent by any processor core from the target weighted fair core message sending channel.

[0020] In one embodiment of this disclosure, scheduling a message to a first processor core includes: In the core message receiving channel configured for the first processor core by the subsystem message queue module in the first subsystem, the first core message receiving channel corresponding to the priority in the message is determined; The message is scheduled to the first core message receiving channel, and the first interrupt notification is sent to the first processor core; Messages scheduled by the subsystem message queue module in the first subsystem are obtained through the subsystem bus in the first subsystem, including: In response to the first interrupt notification, the current process of the first processor core is interrupted; The message scheduled by the subsystem message queue module in the first subsystem is obtained from the first core message receiving channel through the subsystem bus in the first subsystem. Scheduling messages to the second processor core includes: In the core message receiving channel configured for the second processor core by the subsystem message queue module in the second subsystem, the second core message receiving channel corresponding to the priority in the message is determined. The message is scheduled to the second core message receiving channel, and a second interrupt notification is sent to the second processor core. Messages are obtained via the subsystem bus in the second subsystem, including: In response to the second interrupt notification, the current process of the second processor core is interrupted; Messages are obtained from the second core message receiving channel via the subsystem bus in the second subsystem.

[0021] In one embodiment of this disclosure, the inter-core communication system further includes a message interconnection network module, which is connected to the on-chip system message queue module and the subsystem message queue module in each of the multiple subsystems. Retrieve messages scheduled by the subsystem message queue module in the first subsystem, including: The message interconnection network module obtains messages scheduled by the subsystem message queue module in the first subsystem. Retrieve messages scheduled by the on-chip system message queue module, including: The message interconnection network module obtains messages scheduled by the on-chip system message queue module.

[0022] In one embodiment of this disclosure, scheduling a message to an on-chip system message queue module includes: In the subsystem message sending channel configured for the first subsystem by the on-chip system message queue module, determine the first subsystem message sending channel corresponding to the priority in the message; If the first subsystem message sending channel is idle, the message will be scheduled to the first subsystem message sending channel in the on-chip system message queue module.

[0023] In one embodiment of this disclosure, the method further includes: Before acquiring messages scheduled by the subsystem message queue module in the first subsystem, the control on-chip system message queue module acquires the subsystem weight corresponding to any subsystem. Based on the subsystem weight corresponding to any subsystem, it determines the maximum number of second data packets that any subsystem can transmit within a single subsystem communication cycle. The subsystem weight of any subsystem is positively correlated with the number of second data packets of any subsystem. Retrieve messages scheduled by the subsystem message queue module in the first subsystem, including: Within at least one subsystem communication cycle, based on the second data packet number corresponding to the first subsystem, messages scheduled by the subsystem message queue module in the first subsystem are obtained from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem.

[0024] In one embodiment of this disclosure, obtaining messages scheduled by the subsystem message queue module in the first subsystem from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem includes: If the on-chip system message queue module configures at least one priority subsystem message sending channel with currently available messages in the subsystem message sending channel of the first subsystem, then the target priority subsystem message sending channel with the highest priority is determined from the at least one priority subsystem message sending channel with currently available messages, and the message scheduled by the subsystem message queue module in the first subsystem is obtained from the target priority subsystem message sending channel. If the on-chip system message queue module configures at least one priority subsystem message sending channel with currently available messages in the subsystem message sending channels of the first subsystem, and the on-chip system message queue module configures at least one weighted fair subsystem message sending channel with currently available messages in the subsystem message sending channels of the first subsystem, then the subsystem message sending channel weight of each weighted fair subsystem message sending channel in the at least one weighted fair subsystem message sending channel with currently available messages is obtained, wherein the subsystem message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair subsystem message sending channel; Based on the message length of the message in each of the at least one currently available weighted fair subsystem message sending channels and the corresponding subsystem message sending channel weight, obtain the message transmission duration corresponding to each of the at least one currently available weighted fair subsystem message sending channels, and determine the target weighted fair subsystem message sending channel with the shortest message transmission duration in the at least one currently available weighted fair subsystem message sending channels; Obtain messages scheduled by the subsystem message queue module in the first subsystem from the message sending channel of the target weighted fairness subsystem.

[0025] Thirdly, this disclosure provides an inter-core communication system control device. The inter-core communication system includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module in the subsystem is connected to each processor core in the subsystem through the subsystem bus in the subsystem, and the subsystem message queue module in the subsystem is connected to the on-chip system message queue module. Internuclear communication system control device, including: The first core control module is configured to control any one of the multiple processor cores and send messages to the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem where the processor core is located. The first queue control module is configured to control the subsystem message queue module in the first subsystem to obtain messages sent by any processor core. If it is determined that the target processor core of the message is the first processor core in the first subsystem, the message will be scheduled to the first processor core. The second core control module is configured to control the first processor core and obtain messages scheduled by the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem. The second queue control module is configured to control the subsystem message queue module in the first subsystem. When it is determined that the target processor core of the message is the second processor core of the second subsystem in the multiple subsystems, the message will be scheduled to the on-chip system message queue module. The third queue control module is configured to control the on-chip system message queue module, obtain messages scheduled by the subsystem message queue module in the first subsystem, and schedule the messages to the subsystem message queue module in the second subsystem. The fourth queue control module is configured to control the subsystem message queue module in the second subsystem, obtain messages scheduled by the on-chip system message queue module, and schedule the messages to the second processor core. The third core control module is configured to control the second processor core and obtain messages through the subsystem bus in the second subsystem.

[0026] Fourthly, embodiments of this disclosure provide an electronic device including a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method as described in any one of the second aspects.

[0027] Fifthly, this disclosure provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the method as described in any one of the second aspects.

[0028] In a sixth aspect, this disclosure provides a chip circuit including any of the inter-core communication systems in the first aspect.

[0029] In a seventh aspect, an electronic device is provided in this disclosure, including the chip circuit described in the sixth aspect.

[0030] According to the technical solution provided in this disclosure, the inter-core communication system includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module is connected to each processor core in the subsystem via the subsystem bus, and is also connected to the on-chip system message queue module. Any processor core among the multiple processor cores is configured to send a message to the subsystem message queue module in the first subsystem via the subsystem bus of the first subsystem where that processor core resides. The subsystem message queue module in the first subsystem is configured to: acquire the message sent by any processor core; and if the target processor core of the message is determined to be the first processor core in the first subsystem, then forward the message to the first processor core in the first subsystem. Processor core scheduling; a first processor core is configured to: acquire messages scheduled by the subsystem message queue module in the first subsystem via the subsystem bus in the first subsystem; the subsystem message queue module in the first subsystem is further configured to: if the target processor core of the message is determined to be the second processor core in the second subsystem of multiple subsystems, then schedule the message to the on-chip system message queue module; the on-chip system message queue module is configured to: acquire messages scheduled by the subsystem message queue module in the first subsystem and schedule the messages to the subsystem message queue module in the second subsystem; the subsystem message queue module in the second subsystem is configured to: acquire messages scheduled by the on-chip system message queue module and schedule the messages to the second processor core; the second processor core is configured to: acquire messages via the subsystem bus in the second subsystem.

[0031] In the above scheme, by configuring a subsystem message queue module in each subsystem of the inter-core communication system and connecting the subsystem message queue module to all processor cores in the corresponding subsystem through the subsystem bus, the processor cores in the same subsystem can communicate with the subsystem message queue module through the subsystem bus within the subsystem without having to go through the on-chip system bus. This not only shortens the length of the message transmission path between different processor cores in the same subsystem, but also avoids the competition for the on-chip system bus between inter-core communication between different processor cores in the same subsystem and inter-core communication across subsystems. By configuring an on-chip system message queue module in the inter-core communication system and connecting the subsystem message queue modules of each subsystem to the on-chip system message queue module, when processor cores in different subsystems are communicating with each other, the subsystem message queue module in the subsystem containing the source processor core transmitting the message will transmit the message to the on-chip system message queue module, and then to the subsystem message queue module in the subsystem containing the target processor core. The target processor core's message queue module will then transmit the message to the target processor core. This achieves physical isolation and traffic splitting between inter-subsystem core communication and cross-subsystem core communication, avoiding contention for the on-chip system bus. In summary, the above scheme can shorten the message transmission path length for inter-subsystem core communication and achieve physical isolation and traffic splitting between inter-subsystem core communication and cross-subsystem core communication, avoiding contention for the on-chip system bus. Therefore, this scheme can reduce inter-core communication latency and improve inter-core communication efficiency.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0033] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings: Figure 1 A structural diagram of an inter-core communication system according to an embodiment of the present disclosure is shown.

[0034] Figure 2 A structural diagram of another inter-core communication system according to an embodiment of the present disclosure is shown.

[0035] Figure 3 A structural diagram of another inter-core communication system according to an embodiment of the present disclosure is shown.

[0036] Figure 4 A flowchart illustrating a control method for an inter-core communication system according to an embodiment of the present disclosure is shown.

[0037] Figure 5A structural block diagram of an inter-nuclear communication system control device according to an embodiment of the present disclosure is shown.

[0038] Figure 6 A structural diagram of a subsystem message queue module according to an embodiment of the present disclosure is shown.

[0039] Figure 7 A structural diagram of a system-on-chip message queue module according to an embodiment of the present disclosure is shown.

[0040] Figure 8 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0041] Figure 9 A schematic diagram of the structure of a computer system suitable for implementing the method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0042] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings to enable those skilled in the art to readily implement them. Furthermore, for clarity, portions unrelated to the description of exemplary embodiments have been omitted from the drawings.

[0043] In this disclosure, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, behaviors, components, parts or combinations thereof.

[0044] It should also be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0045] In this disclosure, any operation involving the acquisition of user information or user data, or the display of user information or user data to others, is an operation authorized or confirmed by the user, or actively selected by the user.

[0046] In related technologies, different processor cores can communicate between processor cores within the same subsystem and between processor cores in different subsystems via a bus. However, in the above scheme, when the number of processor cores in a multi-core processor system is large, communication between processor cores within the same subsystem can easily compete with communication between processor cores in different subsystems for bus resources, thereby increasing communication latency and power consumption of the multi-core processor system, resulting in low efficiency of inter-core communication.

[0047] To address the aforementioned issues, this disclosure provides an inter-core communication system, a chip circuit, and an electronic device.

[0048] According to the technical solution provided in this disclosure, the inter-core communication system includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module is connected to each processor core in the subsystem via the subsystem bus, and is also connected to the on-chip system message queue module. Any processor core among the multiple processor cores is configured to send a message to the subsystem message queue module in the first subsystem via the subsystem bus of the first subsystem where that processor core resides. The subsystem message queue module in the first subsystem is configured to: acquire the message sent by any processor core; and if the target processor core of the message is determined to be the first processor core in the first subsystem, then forward the message to the first processor core in the first subsystem. Processor core scheduling; a first processor core is configured to: acquire messages scheduled by the subsystem message queue module in the first subsystem via the subsystem bus in the first subsystem; the subsystem message queue module in the first subsystem is further configured to: if the target processor core of the message is determined to be the second processor core in the second subsystem of multiple subsystems, then schedule the message to the on-chip system message queue module; the on-chip system message queue module is configured to: acquire messages scheduled by the subsystem message queue module in the first subsystem and schedule the messages to the subsystem message queue module in the second subsystem; the subsystem message queue module in the second subsystem is configured to: acquire messages scheduled by the on-chip system message queue module and schedule the messages to the second processor core; the second processor core is configured to: acquire messages via the subsystem bus in the second subsystem.

[0049] In the above scheme, by configuring a subsystem message queue module in each subsystem of the inter-core communication system and connecting the subsystem message queue module to all processor cores in the corresponding subsystem through the subsystem bus, the processor cores in the same subsystem can communicate with the subsystem message queue module through the subsystem bus within the subsystem without having to go through the on-chip system bus. This not only shortens the length of the message transmission path between different processor cores in the same subsystem, but also avoids the competition for the on-chip system bus between inter-core communication between different processor cores in the same subsystem and inter-core communication across subsystems. By configuring an on-chip system message queue module in the inter-core communication system and connecting the subsystem message queue modules of each subsystem to the on-chip system message queue module, when processor cores in different subsystems are communicating with each other, the subsystem message queue module in the subsystem containing the source processor core transmitting the message will transmit the message to the on-chip system message queue module, and then to the subsystem message queue module in the subsystem containing the target processor core. The target processor core's message queue module will then transmit the message to the target processor core. This achieves physical isolation and traffic splitting between inter-subsystem core communication and cross-subsystem core communication, avoiding contention for the on-chip system bus. In summary, the above scheme can shorten the message transmission path length for inter-subsystem core communication and achieve physical isolation and traffic splitting between inter-subsystem core communication and cross-subsystem core communication, avoiding contention for the on-chip system bus. Therefore, this scheme can reduce inter-core communication latency and improve inter-core communication efficiency.

[0050] This disclosure provides an inter-core communication system, which includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module is connected to each processor core in the subsystem via the subsystem bus, and the subsystem message queue module is connected to the on-chip system message queue module. Any one of the multiple processor cores is configured as follows: Send messages to the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem where any processor core is located; The subsystem message queue module in the first subsystem is configured as follows: Retrieve messages sent by any processor core; If the target processor core of the message is determined to be the first processor core in the first subsystem, then the message will be scheduled to the first processor core. The first processor core is configured as follows: Messages scheduled by the subsystem message queue module in the first subsystem are obtained through the subsystem bus in the first subsystem. The subsystem message queue module in the first subsystem is also configured as follows: If the target processor core of the message is determined to be the second processor core of the second subsystem in multiple subsystems, then the message will be scheduled to the on-chip system message queue module. The on-chip system message queue module is configured as follows: Obtain messages scheduled by the subsystem message queue module in the first subsystem, and schedule the messages to the subsystem message queue module in the second subsystem; The subsystem message queue module in the second subsystem is configured as follows: Obtain messages scheduled by the on-chip system message queue module and schedule the messages to the second processor core; The second processor core is configured as follows: Messages are obtained through the subsystem bus in the second subsystem.

[0051] The inter-core communication system provided in this embodiment is described using an example where the system includes two subsystems, each containing four processor cores. Figure 1 A structural diagram of an inter-core communication system according to an embodiment of the present disclosure is shown. Figure 1 As shown, the inter-core communication system 100 includes an on-chip system message queue module 200, a subsystem 300, and a subsystem 400.

[0052] The subsystem 300 includes processor core 301, processor core 302, processor core 303, processor core 304, subsystem bus 305, and subsystem message queue module 306. The subsystem message queue module 306 is connected to processor core 301, processor core 302, processor core 303, and processor core 304 through the subsystem bus 305, and is connected to the on-chip system message queue module 200.

[0053] Subsystem 400 includes processor core 401, processor core 402, processor core 403, processor core 404, subsystem bus 405, and subsystem message queue module 406. Subsystem message queue module 406 is connected to processor core 401, processor core 402, processor core 403, and processor core 404 through subsystem bus 405, and subsystem message queue module 406 is connected to on-chip system message queue module 200.

[0054] In this process, processor core 301 sends a message to subsystem message queue module 306 within subsystem 300 via subsystem bus 305. Subsystem message queue module 306 receives the message from processor core 301. If subsystem message queue module 306 determines that the target processor core of the message is processor core 302, meaning that processor core 301 and processor core 302 in subsystem 300 are communicating between subsystem kernels, then the message is scheduled to processor core 302. Processor core 302 receives the message scheduled by subsystem message queue module 306 via subsystem bus 305. Subsystem 300 can be considered the first subsystem, and processor core 302 can be considered the first processor core.

[0055] If the subsystem message queue module 306 determines that the target processor core of the message is processor core 401 in subsystem 400, that is, processor core 301 and processor core 401 are communicating across subsystem cores, subsystem 400 can be regarded as a second subsystem, and processor core 401 can be regarded as a second processor core, then the message is scheduled to the on-chip system message queue module 200; the on-chip system message queue module 200 obtains the message scheduled by the subsystem message queue module 306 and schedules the message to the subsystem message queue module 406 in subsystem 400; the subsystem message queue module 406 obtains the message scheduled by the on-chip system message queue module 200 and schedules the message to processor core 401; processor core 401 obtains the message through the subsystem bus 405 in subsystem 400.

[0056] In one embodiment of this disclosure, a processor core can be understood as the smallest hardware computing unit capable of independently reading instructions, decoding and executing operations, and handling data storage and interaction requests. The processor core may integrate computing components such as an arithmetic logic unit, a register set, an instruction decoder, and a cache.

[0057] In this inter-core communication system, each subsystem contains multiple processor cores. The processor cores in different subsystems can be classified as homogeneous or heterogeneous combinations based on the subsystem's function. A homogeneous combination means that the processor cores in multiple subsystems are of the same type, with identical core architectures and instruction sets, suitable for parallel processing of similar tasks. A heterogeneous combination means that the processor cores in different subsystems are of different types, with different core architectures and instruction sets, used to handle different types of tasks.

[0058] For example, the multiple subsystems of the inter-core communication system may consist only of a central processing unit (CPU) subsystem, which is a homogeneous combination, meaning that each CPU subsystem includes multiple CPU cores of the same type. Alternatively, the multiple subsystems of the inter-core communication system may include at least one CPU subsystem and at least one artificial intelligence accelerator subsystem, which is a heterogeneous combination, wherein the CPU cores in the CPU subsystem are of a different type than the neural network processor cores in the artificial intelligence accelerator subsystem.

[0059] In one embodiment of this disclosure, when the source processor core sends a message, a unified identification field can be encapsulated in the message header. This identification field includes information such as the source processor core ID, the target processor core ID, priority, and message length.

[0060] Both the target processor core ID and the source processor core ID can employ a hierarchical encoding design. For example, if both the target processor core ID and the source processor core ID are 32 bits, then the first 16 bits of the target processor core ID represent the subsystem ID of the target subsystem where the target processor core resides, and the last 16 bits indicate the ID of the target processor core within the target subsystem. Similarly, the first 16 bits of the source processor core ID represent the subsystem ID of the source processor core resides, and the last 16 bits represent the core ID of the local processor core within the subsystem where the source processor core resides.

[0061] In one embodiment of this disclosure, the inter-core communication system further includes an on-chip system bus, which is connected to the on-chip system message queue module and the subsystem bus of each of the multiple subsystems.

[0062] Retrieve messages scheduled by the subsystem message queue module in the first subsystem, including: The messages scheduled by the subsystem message queue module in the first subsystem are obtained through the subsystem bus and the on-chip system bus in the first subsystem. Retrieve messages scheduled by the on-chip system message queue module, including: Messages scheduled by the on-chip system message queue module are obtained through the subsystem bus and on-chip system bus in the second subsystem. For example, Figure 2 A structural diagram of another inter-core communication system according to an embodiment of the present disclosure is shown. (As follows) Figure 2 As shown, the inter-core communication system 100 also includes an on-chip system bus 500, which is connected to the subsystem bus 305 of subsystem 300, the subsystem bus 405 of subsystem 400 and the on-chip system message queue module 200.

[0063] The on-chip system message queue module 200 can obtain messages scheduled by the subsystem message queue module 306 through the subsystem bus 305 and the on-chip system bus 500, and the subsystem message queue module 406 can obtain messages scheduled by the on-chip system message queue module 200 through the subsystem bus 405 and the on-chip system bus 500.

[0064] Alternatively, the inter-core communication system may also include a message interconnection network module, which is connected to the on-chip system message queue module and the subsystem message queue module in each of the multiple subsystems. Retrieve messages scheduled by the subsystem message queue module in the first subsystem, including: The message interconnection network module obtains messages scheduled by the subsystem message queue module in the first subsystem. Retrieve messages scheduled by the on-chip system message queue module, including: The message interconnection network module obtains messages scheduled by the on-chip system message queue module.

[0065] For example, Figure 3 A structural diagram of another inter-core communication system according to an embodiment of the present disclosure is shown. Figure 3 As shown, the inter-core communication system 100 also includes a message interconnection network module 600, which is connected to the subsystem message queue module 306 of subsystem 300, the subsystem message queue module 406 of subsystem 400 and the on-chip system message queue module 200, respectively.

[0066] The on-chip system message queue module 200 can obtain messages scheduled by the subsystem message queue module 306 through the message interconnection network module 600; the subsystem message queue module 406 can obtain messages scheduled by the on-chip system message queue module 200 through the message interconnection network module 600.

[0067] In one embodiment of this disclosure, the on-chip system message queue module pre-stores a globally unified ID mapping table, which indicates the correspondence between subsystem IDs and subsystem physical identifiers. After receiving a message from a subsystem message queue module within any subsystem, the on-chip system message queue module can determine the subsystem to which the target processor core belongs based on the identifier field encapsulated in the message header and the pre-stored ID mapping table, thereby scheduling the message to the subsystem message queue module within that subsystem.

[0068] According to the technical solution provided in the embodiments of this disclosure, by configuring a subsystem message queue module in each subsystem of the inter-core communication system and connecting the subsystem message queue module to all processor cores in the corresponding subsystem through the subsystem bus, the processor cores in the same subsystem can communicate with the subsystem message queue module through the subsystem bus within the subsystem without having to go around the on-chip system bus. This not only shortens the length of the message transmission path between different processor cores in the same subsystem, but also avoids the competition for the on-chip system bus between inter-core communication between different processor cores in the same subsystem and inter-core communication across subsystems. Alternatively, by configuring an on-chip system message queue module in the inter-core communication system and connecting the subsystem message queue modules of each subsystem to the on-chip system message queue module, when processor cores in different subsystems are communicating with each other, the subsystem message queue module in the subsystem containing the source processor core forwards the message to the on-chip system message queue module, and then transmits it to the subsystem message queue module in the subsystem containing the target processor core. This subsystem message queue module then forwards the message to the target processor core, thus achieving physical isolation and traffic splitting between inter-subsystem core communication and cross-subsystem core communication, avoiding contention for the on-chip system bus. In summary, the above scheme can shorten the message transmission path length for inter-subsystem core communication and achieve physical isolation and traffic splitting between inter-subsystem core communication and cross-subsystem core communication, avoiding contention for the on-chip system bus. Therefore, this scheme can reduce inter-core communication latency and improve inter-core communication efficiency.

[0069] In one embodiment of this disclosure, sending a message to a subsystem message queue module in the first subsystem via a subsystem bus in the first subsystem containing any processor core includes: In the first subsystem, the subsystem message queue module configures a core message sending channel for any processor core, and determines the target core message sending channel corresponding to the priority in the message. If the target core message sending channel is idle, a message is sent to the target core message sending channel through the subsystem bus in the first subsystem.

[0070] In one embodiment of this disclosure, before acquiring a message sent by any processor core, the subsystem message queue module in the first subsystem is further configured to: Obtain the core weight corresponding to any processor core; Based on the core weight corresponding to any processor core, determine the maximum number of first data packets that any processor core can transmit in a single core communication cycle, wherein the core weight of any processor core is positively correlated with the number of first data packets of any processor core. Retrieve messages sent by any processor core, including: Within at least one core communication cycle, based on the first data packet number corresponding to any processor core, the message sent by any processor core is obtained from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem.

[0071] In one implementation of this disclosure, obtaining the core weight corresponding to any processor core can be achieved by: pre-assigning a core weight to each core based on the task importance, communication requirements, etc. of each processor core in the subsystem. The core weight can be stored in the register of the subsystem message queue module, and the core weight in the register can be dynamically modified.

[0072] In one implementation of this disclosure, the number of first data packets that any processor core can transmit in a single core communication cycle is determined based on the core weight corresponding to any processor core. This can be achieved by substituting the core weight corresponding to any processor core into a pre-acquired algorithm to calculate the number of first data packets that any processor core can transmit in a single core communication cycle.

[0073] For example, based on the subsystem bus bandwidth and the duration of the core communication cycle, the maximum number of total data packets that can be transmitted by all processor cores in the first subsystem where any processor core resides within a single core communication cycle can be calculated. Then, based on the formula: the maximum number of first data packets that can be transmitted by any processor core within a single core communication cycle = (core weight corresponding to any processor core / sum of core weights of all processor cores in the first subsystem) × total number of data packets transmitted by the subsystem, the maximum number of first data packets that can be transmitted by any processor core within a single core communication cycle can be calculated.

[0074] In one implementation of this disclosure, within at least one core communication cycle, based on the first data packet number corresponding to any processor core, the message sent by any processor core is obtained from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem. This can be understood as: In each core communication cycle within at least one core communication cycle, messages sent by any processor core are retrieved from the core message sending channel configured for that processor core by the subsystem message queue module in the first subsystem. If the number of data packets retrieved from the core message sending channel configured for that processor core by the subsystem message queue module in the first subsystem during the current core communication cycle equals the first number of data packets, then retrieving messages from the core message sending channel configured for that processor core by the subsystem message queue module in the first subsystem is paused. In the next core communication cycle, retrieving messages from the core message sending channel configured for that processor core by the subsystem message queue module in the first subsystem continues. This process is repeated until all messages from the processor core have been retrieved.

[0075] In the above technical solution, by obtaining the core message transmission status and corresponding core weight of each processor core in any subsystem, and then quantizing and allocating the bus bandwidth of each core communication cycle to each processor core according to the principle that the core weight is positively correlated with the number of data packets, it ensures that processor cores with higher weights, i.e., higher priority and higher communication needs, obtain sufficient bandwidth resources, and avoids communication blockage of low-priority processor cores caused by a single processor core monopolizing the subsystem bus. Thus, while meeting the communication needs of different processor cores within the subsystem, it improves the stability of communication between subsystem cores.

[0076] In one embodiment of this disclosure, obtaining a message sent by any processor core from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem includes: If the subsystem message queue module in the first subsystem includes at least one priority core message sending channel with currently available messages in the core message sending channel configured for any processor core, then the highest priority target priority core message sending channel is determined from the at least one priority core message sending channel with currently available messages, and the message sent by any processor core is obtained from the target priority core message sending channel. If the core message sending channel configured for any processor core in the subsystem message queue module of the first subsystem does not include at least one priority core message sending channel with currently available messages, and the core message sending channel configured for any processor core in the subsystem message queue module of the first subsystem includes at least one weighted fair core message sending channel with currently available messages, then the core message sending channel weight of each weighted fair core message sending channel in the at least one weighted fair core message sending channel with currently available messages is obtained, wherein the core message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair core message sending channel; Based on the message length of the message in each weighted fair core message sending channel in at least one currently available weighted fair core message sending channel and the corresponding core message sending channel weight, obtain the message transmission duration corresponding to each weighted fair core message sending channel in at least one currently available weighted fair core message sending channel, and determine the target weighted fair core message sending channel with the shortest message transmission duration in at least one currently available weighted fair core message sending channel. Obtain messages sent by any processor core from the target weighted fair core message sending channel.

[0077] In one implementation of this disclosure, the subsystem message queue module can pre-configure multiple core message sending channels for different processor cores. These multiple core message sending channels may include priority core message sending channels and weighted fair core message sending channels. The priority of the priority core message sending channels and the weight of the weighted fair core message sending channels are configured. The priority core message sending channels can be used to schedule real-time control messages, and the weighted fair core message sending channels can be used to schedule batch data. The subsystem message queue module can read the preset channel configuration parameters for different processor cores and, based on these parameters, determine which core message sending channels for different processor cores belong to the priority core message sending channels and which belong to the weighted fair core message sending channels.

[0078] In one implementation of this disclosure, the subsystem message queue module can monitor the status of the weighted fair core message sending channels corresponding to different processor cores in the subsystem in real time, thereby determining whether there are messages to be transmitted in each weighted fair core message sending channel. If there are messages to be transmitted, the message length of the message in the weighted fair core message sending channel can be obtained.

[0079] In the above technical solution, during the process of obtaining messages sent by any processor core from the core message sending channels configured for any processor core by the subsystem message queue module in the first subsystem, priority core message sending channels with current messages are identified first, and the highest priority target priority core message sending channel is selected first to obtain messages sent by any processor core. This ensures that high-priority messages sensitive to latency, such as real-time control and interrupt response, do not need to wait for low-priority messages and can directly obtain core message sending channel resources, achieving low-latency and non-blocking transmission of critical messages. However, when the core message sending channels configured for any processor core by the subsystem message queue module in the first subsystem do not include at least one priority core message sending channel with current messages, and the core message sending channels configured for any processor core by the subsystem message queue module in the first subsystem include at least one weighted fair core message sending channel with current messages, by using at least one... The algorithm identifies the message length and corresponding core message sending channel weight in each of the currently active weighted fair core message sending channels. It then obtains the message transmission duration for each of at least one of these channels and determines the target weighted fair core message sending channel with the shortest transmission duration. By retrieving messages sent by any processor core from this target channel, the algorithm ensures that weighted fair core message sending channels with higher core message sending channel weights receive more bandwidth while preventing a single channel from monopolizing bandwidth and causing congestion in other channels with lower core message sending channel weights. This achieves fair bandwidth allocation for low-priority messages, thus improving the utilization rate of core message sending channel resources and message transmission efficiency.

[0080] In one embodiment of this disclosure, scheduling a message to a first processor core includes: In the core message receiving channel configured for the first processor core by the subsystem message queue module in the first subsystem, the first core message receiving channel corresponding to the priority in the message is determined; The message is scheduled to the first core message receiving channel, and the first interrupt notification is sent to the first processor core; Messages scheduled by the subsystem message queue module in the first subsystem are obtained through the subsystem bus in the first subsystem, including: In response to the first interrupt notification, the current process of the first processor core is interrupted; The message scheduled by the subsystem message queue module in the first subsystem is obtained from the first core message receiving channel through the subsystem bus in the first subsystem. Scheduling messages to the second processor core includes: In the core message receiving channel configured for the second processor core by the subsystem message queue module in the second subsystem, the second core message receiving channel corresponding to the priority in the message is determined. The message is scheduled to the second core message receiving channel, and a second interrupt notification is sent to the second processor core. Messages are obtained via the subsystem bus in the second subsystem, including: In response to the second interrupt notification, the current process of the second processor core is interrupted; Messages are obtained from the second core message receiving channel via the subsystem bus in the second subsystem.

[0081] In one implementation of this disclosure, the subsystem message queue module can pre-configure multiple core message receiving channels for different processor cores, wherein each of these multiple core message receiving channels can correspond to a different priority. The subsystem message queue module can obtain the processor core ID and priority of the target processor core from the priority field of the corresponding message header. Based on the processor core ID, it can determine to schedule the message to the message receiving channel corresponding to the processor core ID, and based on the priority, it can determine to schedule the message to the message receiving channel corresponding to the priority.

[0082] In the above technical solution, the subsystem message queue module in the first subsystem determines the first core message receiving channel corresponding to the priority in the message from the core message receiving channels configured for the first processor core in the subsystem message queue module of the first subsystem, schedules the message to the first core message receiving channel, and sends a first interrupt notification to the first processor core. The first processor core responds to the first interrupt notification, interrupting its current process, and retrieves the message scheduled by the subsystem message queue module of the first subsystem from the first core message receiving channel via the subsystem bus of the first subsystem. Similarly, the subsystem message queue module in the second subsystem determines the second core message receiving channel corresponding to the priority in the message from the core message receiving channels configured for the second processor core in the subsystem message queue module of the second subsystem, sends the message to the second core message receiving channel, and sends a second interrupt notification to the second processor core. The second processor core responds to the second interrupt notification, interrupting its current process, and retrieves the message from the second core message receiving channel via the subsystem bus of the second subsystem. The above scheme can ensure that high-priority messages can be scheduled through the core message receiving channel that matches their priority, avoiding the blocking caused by low-priority messages preempting high-priority core message receiving channels or high-priority messages being scheduled through low-priority core message receiving channels. While ensuring message transmission efficiency, it improves the utilization rate of core message receiving channels within the subsystem and the stability of message communication between subsystem kernels.

[0083] In one embodiment of this disclosure, before obtaining the message scheduled by the subsystem message queue module in the first subsystem, the on-chip system message queue module is further configured as follows: Obtain the subsystem weight corresponding to any subsystem; Based on the subsystem weight corresponding to any subsystem, determine the maximum number of second data packets that any subsystem can transmit within a single subsystem communication cycle, wherein the subsystem weight of any subsystem is positively correlated with the number of second data packets of any subsystem. Retrieve messages scheduled by the subsystem message queue module in the first subsystem, including: Within at least one subsystem communication cycle, based on the second data packet number corresponding to the first subsystem, messages scheduled by the subsystem message queue module in the first subsystem are obtained from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem.

[0084] In one implementation of this disclosure, obtaining the subsystem weight corresponding to any subsystem can be achieved by the on-chip system message queue module reading the subsystem weights of each subsystem within the inter-core communication system from the registers. Specifically, a unique subsystem weight can be pre-assigned to each subsystem based on its task importance and communication requirements within the inter-core communication system, and stored in the registers of the on-chip system message queue module. The subsystem weights stored in the registers of the on-chip system message queue module can be dynamically modified.

[0085] In one implementation of this disclosure, the maximum number of second data packets that any subsystem can transmit within a single subsystem communication cycle is determined based on the subsystem weight corresponding to any subsystem. This can be achieved by substituting the subsystem weight corresponding to any subsystem into a pre-acquired algorithm to calculate the maximum number of second data packets that any subsystem can transmit within a single subsystem communication cycle.

[0086] For example, based on the subsystem bus bandwidth and the duration of the subsystem communication cycle, the maximum number of total data packets that can be transmitted by all subsystems in a single subsystem communication cycle within the inter-core communication system can be calculated. Then, based on the maximum number of second data packets that any subsystem can transmit in a single subsystem communication cycle = (the subsystem weight corresponding to any subsystem / the sum of the subsystem weights of all subsystems) × the total number of data packets transmitted by the subsystem, the maximum number of second data packets that any subsystem can transmit in a single subsystem communication cycle can be calculated to obtain the maximum number of second data packets that any subsystem can transmit in a single subsystem communication cycle.

[0087] In one implementation of this disclosure, during at least one subsystem communication cycle, based on the second data packet number corresponding to the first subsystem, messages scheduled by the subsystem message queue module in the first subsystem are obtained from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem. This can be understood as: In each subsystem communication cycle within at least one subsystem communication cycle, messages scheduled by the subsystem message queue module of the first subsystem are retrieved from the subsystem message transmission channel configured by the on-chip system message queue module for the first subsystem. If the number of data packets retrieved from the subsystem message transmission channel configured by the on-chip system message queue module for the first subsystem in the current subsystem communication cycle equals the maximum total number of data packets that the first subsystem can transmit in a single subsystem communication cycle, then the retrieval of messages scheduled by the subsystem message queue module of the first subsystem from the subsystem message transmission channel configured by the on-chip system message queue module for the first subsystem is paused. In the next subsystem communication cycle, the retrieval of messages scheduled by the subsystem message queue module of the first subsystem continues from the subsystem message transmission channel configured by the on-chip system message queue module for the first subsystem. This process is repeated until all messages scheduled by the subsystem message queue module of the first subsystem are retrieved.

[0088] In the above technical solution, by obtaining the subsystem weight corresponding to each subsystem in multiple subsystems, and then according to the principle that the subsystem weight is positively correlated with the number of transmitted data packets, the bus bandwidth of each subsystem communication cycle is quantitatively allocated to each system. This ensures that subsystems with higher weights, i.e., higher priority and higher communication needs, receive sufficient bandwidth resources, while avoiding communication blockage of low-priority subsystems caused by a single subsystem monopolizing transmission resources. Thus, the stability of communication between different subsystems is improved while meeting the communication needs of different subsystems.

[0089] In one embodiment of this disclosure, obtaining messages scheduled by the subsystem message queue module in the first subsystem from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem includes: If the on-chip system message queue module configures at least one priority subsystem message sending channel with currently available messages in the subsystem message sending channel of the first subsystem, then the target priority subsystem message sending channel with the highest priority is determined from the at least one priority subsystem message sending channel with currently available messages, and the message scheduled by the subsystem message queue module in the first subsystem is obtained from the target priority subsystem message sending channel. If the on-chip system message queue module configures at least one priority subsystem message sending channel with currently available messages in the subsystem message sending channels of the first subsystem, and the on-chip system message queue module configures at least one weighted fair subsystem message sending channel with currently available messages in the subsystem message sending channels of the first subsystem, then the subsystem message sending channel weight of each weighted fair subsystem message sending channel in the at least one weighted fair subsystem message sending channel with currently available messages is obtained, wherein the subsystem message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair subsystem message sending channel; Based on the message length of the message in each of the at least one currently available weighted fair subsystem message sending channels and the corresponding subsystem message sending channel weight, obtain the message transmission duration corresponding to each of the at least one currently available weighted fair subsystem message sending channels, and determine the target weighted fair subsystem message sending channel with the shortest message transmission duration in the at least one currently available weighted fair subsystem message sending channels; Obtain messages scheduled by the subsystem message queue module in the first subsystem from the message sending channel of the target weighted fairness subsystem.

[0090] In one implementation of this disclosure, the on-chip system message queue module can pre-configure multiple subsystem message sending channels for different subsystems. These multiple subsystem message sending channels may include priority subsystem message sending channels and weighted fair subsystem message sending channels. The priority of the priority subsystem message sending channels and the weight of the weighted fair subsystem message sending channels are configured. The priority subsystem message sending channels can be used to schedule real-time control messages, while the weighted fair subsystem message sending channels can be used to schedule batch data. The on-chip system message queue module can read the preset channel configuration parameters for different subsystems and, based on these parameters, determine which subsystem message sending channels belong to the priority subsystem message sending channels and which belong to the weighted fair subsystem message sending channels.

[0091] In one implementation of this disclosure, the on-chip system message queue module can monitor the status of the weighted fair subsystem message sending channels corresponding to different subsystems in real time, thereby determining whether there are messages to be transmitted in each weighted fair subsystem message sending channel. If there are messages to be transmitted, the message length of the message in the weighted fair subsystem message sending channel can be obtained.

[0092] In the above technical solution, by prioritizing the highest priority subsystem message sending channel to obtain messages scheduled by the subsystem message queue module through the on-chip system message queue module, it can be ensured that high-priority messages sensitive to latency, such as real-time control and interrupt response, do not need to wait for low-priority messages and can directly obtain subsystem message sending channel resources, achieving low-latency and non-blocking transmission of critical messages. However, if the subsystem message sending channels configured by the on-chip system message queue module for the first subsystem do not include at least one priority subsystem message sending channel with currently available messages, and the subsystem message sending channels configured by the on-chip system message queue module for the first subsystem include at least one weighted fair subsystem message sending channel with currently available messages, then the subsystem message sending channel weight of each weighted fair subsystem message sending channel in the at least one weighted fair subsystem message sending channel with currently available messages is obtained, and based on each weighted fair subsystem message sending channel in the at least one weighted fair subsystem message sending channel with currently available messages... The algorithm identifies the message length and corresponding weight of messages in the fair subsystem message sending channel, obtains the message transmission duration of each weighted fair subsystem message sending channel in at least one currently active message-containing weighted fair subsystem message sending channel, and determines the target weighted fair subsystem message sending channel with the shortest message transmission duration among these channels. It then retrieves messages scheduled by the subsystem message queue module in the first subsystem from the target weighted fair subsystem message sending channel. This approach ensures that weighted fair subsystem message sending channels with higher weights receive more bandwidth resources while preventing a single weighted fair subsystem message sending channel from monopolizing bandwidth and causing blockages in other weighted fair subsystem message sending channels with lower weights. This achieves fair bandwidth allocation for low-priority messages, thus improving the utilization rate and message transmission efficiency of subsystem message sending channel resources.

[0093] Figure 4 A flowchart illustrating a control method for an inter-core communication system according to an embodiment of the present disclosure is shown. The inter-core communication system includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module is connected to each processor core in the subsystem via the subsystem bus, and the subsystem message queue module is connected to the on-chip system message queue module. like Figure 4 As shown, the inter-nuclear communication system control method includes the following steps S101-S105: In step S101, any one of the multiple processor cores is controlled to send a message to the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem where the processor core is located.

[0094] In step S102, the subsystem message queue module in the first subsystem is controlled to obtain a message sent by any processor core. If it is determined that the target processor core of the message is the first processor core in the first subsystem, the message is scheduled to the first processor core.

[0095] In step S103, the first processor core is controlled to obtain messages scheduled by the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem.

[0096] In step S104, the subsystem message queue module in the first subsystem is controlled to schedule the message to the on-chip system message queue module when it is determined that the target processor core of the message is the second processor core of the second subsystem in the multiple subsystems.

[0097] In step S105, the on-chip system message queue module is controlled to obtain the message scheduled by the subsystem message queue module in the first subsystem and schedule the message to the subsystem message queue module in the second subsystem.

[0098] In step S106, the subsystem message queue module in the second subsystem is controlled to obtain the message scheduled by the on-chip system message queue module and schedule the message to the second processor core.

[0099] In step S107, the second processor core is controlled to obtain messages through the subsystem bus in the second subsystem.

[0100] In one embodiment of this disclosure, sending a message to a subsystem message queue module in the first subsystem via a subsystem bus in the first subsystem containing any processor core includes: In the first subsystem, the subsystem message queue module configures a core message sending channel for any processor core, and determines the target core message sending channel corresponding to the priority in the message. If the target core message sending channel is idle, a message is sent to the target core message sending channel through the subsystem bus in the first subsystem.

[0101] In one embodiment of this disclosure, the method further includes: The subsystem message queue module in the first control subsystem obtains the core weight corresponding to any processor core before obtaining the message sent by any processor core. Based on the core weight corresponding to any processor core, it determines the maximum number of first data packets that any processor core can transmit in a single core communication cycle. The core weight of any processor core is positively correlated with the number of first data packets of any processor core. Retrieve messages sent by any processor core, including: Within at least one core communication cycle, based on the first data packet number corresponding to any processor core, the message sent by any processor core is obtained from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem.

[0102] In one embodiment of this disclosure, obtaining a message sent by any processor core from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem includes: If the subsystem message queue module in the first subsystem includes at least one priority core message sending channel with currently available messages in the core message sending channel configured for any processor core, then the highest priority target priority core message sending channel is determined from the at least one priority core message sending channel with currently available messages, and the message sent by any processor core is obtained from the target priority core message sending channel. If the core message sending channel configured for any processor core in the subsystem message queue module of the first subsystem does not include at least one priority core message sending channel with currently available messages, and the core message sending channel configured for any processor core in the subsystem message queue module of the first subsystem includes at least one weighted fair core message sending channel with currently available messages, then the core message sending channel weight of each weighted fair core message sending channel in the at least one weighted fair core message sending channel with currently available messages is obtained, wherein the core message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair core message sending channel; Based on the message length of the message in each weighted fair core message sending channel in at least one currently available weighted fair core message sending channel and the corresponding core message sending channel weight, obtain the message transmission duration corresponding to each weighted fair core message sending channel in at least one currently available weighted fair core message sending channel, and determine the target weighted fair core message sending channel with the shortest message transmission duration in at least one currently available weighted fair core message sending channel. Obtain messages sent by any processor core from the target weighted fair core message sending channel.

[0103] In one embodiment of this disclosure, scheduling a message to a first processor core includes: In the core message receiving channel configured for the first processor core by the subsystem message queue module in the first subsystem, the first core message receiving channel corresponding to the priority in the message is determined; The message is scheduled to the first core message receiving channel, and the first interrupt notification is sent to the first processor core; Messages scheduled by the subsystem message queue module in the first subsystem are obtained through the subsystem bus in the first subsystem, including: In response to the first interrupt notification, the current process of the first processor core is interrupted; The message scheduled by the subsystem message queue module in the first subsystem is obtained from the first core message receiving channel through the subsystem bus in the first subsystem. Scheduling messages to the second processor core includes: In the core message receiving channel configured for the second processor core by the subsystem message queue module in the second subsystem, the second core message receiving channel corresponding to the priority in the message is determined. The message is scheduled to the second core message receiving channel, and a second interrupt notification is sent to the second processor core. Messages are obtained via the subsystem bus in the second subsystem, including: In response to the second interrupt notification, the current process of the second processor core is interrupted; Messages are obtained from the second core message receiving channel via the subsystem bus in the second subsystem.

[0104] In one embodiment of this disclosure, the inter-core communication system further includes a message interconnection network module, which is connected to the on-chip system message queue module and the subsystem message queue module in each of the multiple subsystems. Retrieve messages scheduled by the subsystem message queue module in the first subsystem, including: The message interconnection network module obtains messages scheduled by the subsystem message queue module in the first subsystem. Retrieve messages scheduled by the on-chip system message queue module, including: The message interconnection network module obtains messages scheduled by the on-chip system message queue module.

[0105] In one embodiment of this disclosure, scheduling a message to an on-chip system message queue module includes: In the subsystem message sending channel configured for the first subsystem by the on-chip system message queue module, determine the first subsystem message sending channel corresponding to the priority in the message; If the first subsystem message sending channel is idle, the message will be scheduled to the first subsystem message sending channel in the on-chip system message queue module.

[0106] In one embodiment of this disclosure, the method further includes: Before acquiring messages scheduled by the subsystem message queue module in the first subsystem, the control on-chip system message queue module acquires the subsystem weight corresponding to any subsystem. Based on the subsystem weight corresponding to any subsystem, it determines the maximum number of second data packets that any subsystem can transmit within a single subsystem communication cycle. The subsystem weight of any subsystem is positively correlated with the number of second data packets of any subsystem. Retrieve messages scheduled by the subsystem message queue module in the first subsystem, including: Within at least one subsystem communication cycle, based on the second data packet number corresponding to the first subsystem, messages scheduled by the subsystem message queue module in the first subsystem are obtained from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem.

[0107] In one embodiment of this disclosure, obtaining messages scheduled by the subsystem message queue module in the first subsystem from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem includes: If the on-chip system message queue module configures at least one priority subsystem message sending channel with currently available messages in the subsystem message sending channel of the first subsystem, then the target priority subsystem message sending channel with the highest priority is determined from the at least one priority subsystem message sending channel with currently available messages, and the message scheduled by the subsystem message queue module in the first subsystem is obtained from the target priority subsystem message sending channel. If the on-chip system message queue module configures at least one priority subsystem message sending channel with currently available messages in the subsystem message sending channels of the first subsystem, and the on-chip system message queue module configures at least one weighted fair subsystem message sending channel with currently available messages in the subsystem message sending channels of the first subsystem, then the subsystem message sending channel weight of each weighted fair subsystem message sending channel in the at least one weighted fair subsystem message sending channel with currently available messages is obtained, wherein the subsystem message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair subsystem message sending channel; Based on the message length of the message in each of the at least one currently available weighted fair subsystem message sending channels and the corresponding subsystem message sending channel weight, obtain the message transmission duration corresponding to each of the at least one currently available weighted fair subsystem message sending channels, and determine the target weighted fair subsystem message sending channel with the shortest message transmission duration in the at least one currently available weighted fair subsystem message sending channels; Obtain messages scheduled by the subsystem message queue module in the first subsystem from the message sending channel of the target weighted fairness subsystem.

[0108] In the above scheme, by configuring a subsystem message queue module in each subsystem of the inter-core communication system and connecting the subsystem message queue module to all processor cores in the corresponding subsystem through the subsystem bus, the processor cores in the same subsystem can communicate with the subsystem message queue module through the subsystem bus within the subsystem without having to go through the on-chip system bus. This not only shortens the length of the message transmission path between different processor cores in the same subsystem, but also avoids the competition for the on-chip system bus between inter-core communication between different processor cores in the same subsystem and inter-core communication across subsystems. By configuring an on-chip system message queue module in the inter-core communication system and connecting the subsystem message queue modules of each subsystem to the on-chip system message queue module, when processor cores in different subsystems are communicating with each other, the subsystem message queue module in the subsystem containing the source processor core transmitting the message will transmit the message to the on-chip system message queue module, and then to the subsystem message queue module in the subsystem containing the target processor core. The target processor core's message queue module will then transmit the message to the target processor core. This achieves physical isolation and traffic splitting between inter-subsystem core communication and cross-subsystem core communication, avoiding contention for the on-chip system bus. In summary, the above scheme can shorten the message transmission path length for inter-subsystem core communication and achieve physical isolation and traffic splitting between inter-subsystem core communication and cross-subsystem core communication, avoiding contention for the on-chip system bus. Therefore, this scheme can reduce inter-core communication latency and improve inter-core communication efficiency.

[0109] Figure 5 This diagram illustrates a structural block diagram of an inter-core communication system control device according to an embodiment of the present disclosure. The device can be implemented as part or all of an electronic device through software, hardware, or a combination of both.

[0110] The inter-core communication system includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module in each subsystem is connected to each processor core in the subsystem through the subsystem bus, and the subsystem message queue module in each subsystem is connected to the on-chip system message queue module.

[0111] like Figure 5 As shown, the inter-nuclear communication system control device includes: The first core control module 501 is configured to control any one of the multiple processor cores to send messages to the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem where the processor core is located. The first queue control module 502 is configured to control the subsystem message queue module in the first subsystem to obtain messages sent by any processor core. If it is determined that the target processor core of the message is the first processor core in the first subsystem, the message will be scheduled to the first processor core. The second core control module 503 is configured to control the first processor core and obtain messages scheduled by the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem. The second queue control module 504 is configured to control the subsystem message queue module in the first subsystem, and when it is determined that the target processor core of the message is the second processor core of the second subsystem in the multiple subsystems, the message will be scheduled to the on-chip system message queue module. The third queue control module 505 is configured to control the on-chip system message queue module, obtain messages scheduled by the subsystem message queue module in the first subsystem, and schedule the messages to the subsystem message queue module in the second subsystem. The fourth queue control module 506 is configured to control the subsystem message queue module in the second subsystem, obtain messages scheduled by the on-chip system message queue module, and schedule the messages to the second processor core. The third core control module 507 is configured to control the second processor core and obtain messages through the subsystem bus in the second subsystem.

[0112] In the above scheme, by configuring a subsystem message queue module in each subsystem of the inter-core communication system and connecting the subsystem message queue module to all processor cores in the corresponding subsystem through the subsystem bus, the processor cores in the same subsystem can communicate with the subsystem message queue module through the subsystem bus within the subsystem without having to go through the on-chip system bus. This not only shortens the length of the message transmission path between different processor cores in the same subsystem, but also avoids the competition for the on-chip system bus between inter-core communication between different processor cores in the same subsystem and inter-core communication across subsystems. By configuring an on-chip system message queue module in the inter-core communication system and connecting the subsystem message queue modules of each subsystem to the on-chip system message queue module, when processor cores in different subsystems are communicating with each other, the subsystem message queue module in the subsystem containing the source processor core transmitting the message will transmit the message to the on-chip system message queue module, and then to the subsystem message queue module in the subsystem containing the target processor core. The target processor core's message queue module will then transmit the message to the target processor core. This achieves physical isolation and traffic splitting between inter-subsystem core communication and cross-subsystem core communication, avoiding contention for the on-chip system bus. In summary, the above scheme can shorten the message transmission path length for inter-subsystem core communication and achieve physical isolation and traffic splitting between inter-subsystem core communication and cross-subsystem core communication, avoiding contention for the on-chip system bus. Therefore, this scheme can reduce inter-core communication latency and improve inter-core communication efficiency.

[0113] Figure 6 A structural diagram of a subsystem message queue module according to an embodiment of the present disclosure is shown. Figure 6 As shown, the subsystem message queue module includes a subsystem bus interface, a subsystem configuration and status register group, a subsystem transmit channel management unit, a subsystem receive channel management unit, a subsystem interrupt management unit, a subsystem scheduling unit, a subsystem routing unit, and a subsystem monitoring unit.

[0114] The subsystem bus interface is used to establish a hardware interaction link between the processor core and the subsystem message queue module. It supports the processor core in configuring the module parameters of the subsystem message queue module and receives message sending requests initiated by the processor core, ensuring that messages flow efficiently within the subsystem bus.

[0115] The subsystem configuration and status register group has an independent register address range and is used to store various key parameters required for the operation of the subsystem message queue module. It supports preset configuration of the priority of the priority core message sending channel and the priority of the core message receiving channel, as well as the weight of the weighted fair core message sending channel. It also allows querying the real-time status of each channel (such as empty / full, message inventory). Independent enqueue and dequeue ports are allocated to each processor core to ensure that message scheduling operations of different cores do not interfere with each other.

[0116] The subsystem sending channel management unit is used to manage and control the core message sending channel resources in the shared cache of the subsystem message queue module. It allocates free addresses in the shared cache to messages, writes messages to the corresponding addresses according to categories to complete enqueueing, and tracks the enqueue pointer position of each core message sending channel in real time. When a message is scheduled, it promptly reclaims the free address and updates the channel status.

[0117] The subsystem receive channel management unit is used to manage and control the core message receive channel resources in the shared buffer of the subsystem message queue module. It allocates dedicated buffer addresses to messages, stores messages in order into the buffers of the corresponding core message receive channels, and maintains the dequeue pointers for each core message receive channel. When a message is scheduled, it performs a dequeue operation and reclaims the corresponding free buffer address to prevent core message receive channel buffer overflow.

[0118] The subsystem interrupt management unit is used to monitor the status changes of the core message receiving channel of each processor in real time. When the core message receiving channel receives a new message or the message inventory reaches a preset threshold, it sends an interrupt notification directly to the corresponding processor core through a hardware signal, notifying the processor core to read the message from the core message receiving channel in a timely manner.

[0119] The subsystem scheduling unit is used to prioritize filtering and forwarding real-time information streams and high-priority control messages based on the preset core weights of processor cores, the priorities of priority core message sending channels, and the weights of weighted fair core message sending channels. It supports independent configuration of bandwidth ratios for each core message sending channel, ensuring low-latency transmission of high-priority messages while allocating fair bandwidth for low-priority messages.

[0120] The subsystem routing unit is used to parse the processor core ID in the message header and determine whether the target processor core of the message is located in this subsystem: if it is the local processor core, the message is directly routed to the core message receiving channel of the corresponding processor core; if it is the core of another subsystem, the message is forwarded to the on-chip system message queue module according to the routing table.

[0121] The subsystem monitoring unit is used to collect real-time operational data of each core message sending / receiving channel, including key information such as channel traffic, busy / idle status, and message inventory. It continuously tracks load changes in each core message sending / receiving channel. When a core message sending / receiving channel is detected to be in an overloaded state for an extended period, a dynamic adjustment mechanism is automatically triggered to modify the weight configuration of that channel, optimize bandwidth allocation, and prevent congestion from affecting overall communication efficiency.

[0122] Figure 7 A structural diagram of a system-on-chip message queue module according to an embodiment of the present disclosure is shown. Figure 7 As shown, the on-chip system message queue module includes an on-chip system bus interface, an on-chip system configuration and status register group, an on-chip system channel management unit, an on-chip system scheduling unit, an on-chip system routing unit, and an on-chip system monitoring unit.

[0123] The on-chip system bus interface is used to connect to the on-chip system bus. It supports the system firmware in writing global scheduling parameters such as subsystem weights, priority of priority subsystem message sending channels, weight of weighted fair subsystem message sending channels, and bandwidth ratio of each channel to the on-chip system message queue module. It also allows querying the real-time running status of the on-chip system message queue module. On the other hand, it connects to the subsystem message queue modules of each subsystem to realize bidirectional transmission of messages across subsystems.

[0124] The on-chip system configuration and status register group is used to allocate an independent register address range for the on-chip system message queue module. It is specifically used to store the parameters required for cross-subsystem communication scheduling, including subsystem weights, priority of priority subsystem message sending channels, weight of weighted fair subsystem message sending channels, and bandwidth ratio of each channel. It also supports real-time querying of information such as the status and message inventory of each channel, and allocates independent enqueue / dequeue ports for each subsystem to ensure that cross-subsystem message transmission between different subsystems does not interfere with each other.

[0125] The on-chip system channel management unit is used to allocate dedicated cache addresses for messages, store messages in order into the buffer of the corresponding subsystem's sending channel, and maintain the dequeue pointer of each subsystem's sending channel to track the message storage location in real time. When the scheduling unit initiates message scheduling, it quickly locates and extracts the target message. After the message is scheduled and forwarded, it performs a dequeue operation and releases the cache free address to avoid buffer overflow of the subsystem's sending channel.

[0126] The on-chip system scheduling unit is used to prioritize and forward high-priority cross-subsystem messages (such as real-time control instructions) based on the subsystem weights, priorities of priority subsystem message transmission channels, weighted fair subsystem message transmission channel weights, and bandwidth proportions of each channel, as preset in the configuration register. At the same time, it allocates the bus bandwidth of each communication cycle to each subsystem to be transmitted according to the subsystem weight proportions. It supports independent configuration of bandwidth proportions for each subsystem message transmission channel to avoid a single subsystem monopolizing the communication link and to balance the priority and fairness of message transmission.

[0127] The on-chip system routing unit is used to parse the target subsystem ID in the message header, match the corresponding subsystem communication link information in the routing table, and push the message with the identified target to the sending channel management unit. Then, it is forwarded to the subsystem message queue module of the target subsystem through the bus interface to ensure the accuracy of the message path.

[0128] The on-chip system monitoring unit (SMU) is used to collect real-time operational data from each message sending / receiving channel, including key information such as channel traffic, message transmission rate, and link congestion. It continuously tracks load changes in each message sending / receiving channel, and automatically triggers a dynamic adjustment mechanism when a channel is detected to be chronically overloaded. This mechanism modifies the bandwidth allocation of the corresponding channel, optimizes resource allocation strategies, and prevents link congestion from impacting overall communication efficiency.

[0129] This disclosure also discloses an electronic device. Figure 8 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0130] like Figure 8 As shown, the electronic device includes a memory and a processor, wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method according to embodiments of the present disclosure.

[0131] This disclosure provides a control method for an inter-core communication system. The inter-core communication system includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module in each subsystem is connected to each processor core in the subsystem through the subsystem bus, and the subsystem message queue module in each subsystem is connected to the on-chip system message queue module. Inter-nuclear communication system control methods include: Control any one of the multiple processor cores and send messages to the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem where the processor core is located; Control the subsystem message queue module in the first subsystem to obtain messages sent by any processor core. If it is determined that the target processor core of the message is the first processor core in the first subsystem, then schedule the message to the first processor core. Control the first processor core and obtain messages scheduled by the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem; The subsystem message queue module in the first subsystem controls the message to the on-chip system message queue module when it determines that the target processor core of the message is the second processor core of the second subsystem in the multiple subsystems. Control the on-chip system message queue module to obtain messages scheduled by the subsystem message queue module in the first subsystem, and schedule the messages to the subsystem message queue module in the second subsystem; Control the subsystem message queue module in the second subsystem, obtain messages scheduled by the on-chip system message queue module, and schedule the messages to the second processor core; It controls the second processor core and obtains messages through the subsystem bus in the second subsystem.

[0132] In one embodiment of this disclosure, sending a message to a subsystem message queue module in the first subsystem via a subsystem bus in the first subsystem containing any processor core includes: In the first subsystem, the subsystem message queue module configures a core message sending channel for any processor core, and determines the target core message sending channel corresponding to the priority in the message. If the target core message sending channel is idle, a message is sent to the target core message sending channel through the subsystem bus in the first subsystem.

[0133] In one embodiment of this disclosure, the method further includes: The subsystem message queue module in the first control subsystem obtains the core weight corresponding to any processor core before obtaining the message sent by any processor core. Based on the core weight corresponding to any processor core, it determines the maximum number of first data packets that any processor core can transmit in a single core communication cycle. The core weight of any processor core is positively correlated with the number of first data packets of any processor core. Retrieve messages sent by any processor core, including: Within at least one core communication cycle, based on the first data packet number corresponding to any processor core, the message sent by any processor core is obtained from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem.

[0134] In one embodiment of this disclosure, obtaining a message sent by any processor core from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem includes: If the subsystem message queue module in the first subsystem includes at least one priority core message sending channel with currently available messages in the core message sending channel configured for any processor core, then the highest priority target priority core message sending channel is determined from the at least one priority core message sending channel with currently available messages, and the message sent by any processor core is obtained from the target priority core message sending channel. If the core message sending channel configured for any processor core in the subsystem message queue module of the first subsystem does not include at least one priority core message sending channel with currently available messages, and the core message sending channel configured for any processor core in the subsystem message queue module of the first subsystem includes at least one weighted fair core message sending channel with currently available messages, then the core message sending channel weight of each weighted fair core message sending channel in the at least one weighted fair core message sending channel with currently available messages is obtained, wherein the core message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair core message sending channel; Based on the message length of the message in each weighted fair core message sending channel in at least one currently available weighted fair core message sending channel and the corresponding core message sending channel weight, obtain the message transmission duration corresponding to each weighted fair core message sending channel in at least one currently available weighted fair core message sending channel, and determine the target weighted fair core message sending channel with the shortest message transmission duration in at least one currently available weighted fair core message sending channel. Obtain messages sent by any processor core from the target weighted fair core message sending channel.

[0135] In one embodiment of this disclosure, scheduling a message to a first processor core includes: In the core message receiving channel configured for the first processor core by the subsystem message queue module in the first subsystem, the first core message receiving channel corresponding to the priority in the message is determined; The message is scheduled to the first core message receiving channel, and the first interrupt notification is sent to the first processor core; Messages scheduled by the subsystem message queue module in the first subsystem are obtained through the subsystem bus in the first subsystem, including: In response to the first interrupt notification, the current process of the first processor core is interrupted; The message scheduled by the subsystem message queue module in the first subsystem is obtained from the first core message receiving channel through the subsystem bus in the first subsystem. Scheduling messages to the second processor core includes: In the core message receiving channel configured for the second processor core by the subsystem message queue module in the second subsystem, the second core message receiving channel corresponding to the priority in the message is determined. The message is scheduled to the second core message receiving channel, and a second interrupt notification is sent to the second processor core. Messages are obtained via the subsystem bus in the second subsystem, including: In response to the second interrupt notification, the current process of the second processor core is interrupted; Messages are obtained from the second core message receiving channel via the subsystem bus in the second subsystem.

[0136] In one embodiment of this disclosure, the inter-core communication system further includes a message interconnection network module, which is connected to the on-chip system message queue module and the subsystem message queue module in each of the multiple subsystems. Retrieve messages scheduled by the subsystem message queue module in the first subsystem, including: The message interconnection network module obtains messages scheduled by the subsystem message queue module in the first subsystem. Retrieve messages scheduled by the on-chip system message queue module, including: The message interconnection network module obtains messages scheduled by the on-chip system message queue module.

[0137] In one embodiment of this disclosure, scheduling a message to an on-chip system message queue module includes: In the subsystem message sending channel configured for the first subsystem by the on-chip system message queue module, determine the first subsystem message sending channel corresponding to the priority in the message; If the first subsystem message sending channel is idle, the message will be scheduled to the first subsystem message sending channel in the on-chip system message queue module.

[0138] In one embodiment of this disclosure, the method further includes: Before acquiring messages scheduled by the subsystem message queue module in the first subsystem, the control on-chip system message queue module acquires the subsystem weight corresponding to any subsystem. Based on the subsystem weight corresponding to any subsystem, it determines the maximum number of second data packets that any subsystem can transmit within a single subsystem communication cycle. The subsystem weight of any subsystem is positively correlated with the number of second data packets of any subsystem. Retrieve messages scheduled by the subsystem message queue module in the first subsystem, including: Within at least one subsystem communication cycle, based on the second data packet number corresponding to the first subsystem, messages scheduled by the subsystem message queue module in the first subsystem are obtained from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem.

[0139] In one embodiment of this disclosure, obtaining messages scheduled by the subsystem message queue module in the first subsystem from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem includes: If the on-chip system message queue module configures at least one priority subsystem message sending channel with currently available messages in the subsystem message sending channel of the first subsystem, then the target priority subsystem message sending channel with the highest priority is determined from the at least one priority subsystem message sending channel with currently available messages, and the message scheduled by the subsystem message queue module in the first subsystem is obtained from the target priority subsystem message sending channel. If the on-chip system message queue module configures at least one priority subsystem message sending channel with currently available messages in the subsystem message sending channels of the first subsystem, and the on-chip system message queue module configures at least one weighted fair subsystem message sending channel with currently available messages in the subsystem message sending channels of the first subsystem, then the subsystem message sending channel weight of each weighted fair subsystem message sending channel in the at least one weighted fair subsystem message sending channel with currently available messages is obtained, wherein the subsystem message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair subsystem message sending channel; Based on the message length of the message in each of the at least one currently available weighted fair subsystem message sending channels and the corresponding subsystem message sending channel weight, obtain the message transmission duration corresponding to each of the at least one currently available weighted fair subsystem message sending channels, and determine the target weighted fair subsystem message sending channel with the shortest message transmission duration in the at least one currently available weighted fair subsystem message sending channels; Obtain messages scheduled by the subsystem message queue module in the first subsystem from the message sending channel of the target weighted fairness subsystem.

[0140] Figure 9 A schematic diagram of the structure of a computer system suitable for implementing the method according to an embodiment of the present disclosure is shown.

[0141] like Figure 9As shown, the computer system includes a processing unit that can execute various methods described above based on a program stored in a read-only memory (ROM) or a program loaded from a storage portion into a random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer system. The processing unit, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0142] The following components are connected to the I / O interface: input sections including keyboards, mice, etc.; output sections including cathode ray tubes (CRTs), liquid crystal displays (LCDs), and speakers; storage sections including hard disks; and communication sections including network interface cards such as LAN cards and modems. The communication section performs communication processes via a network such as the Internet. Drives are also connected to the I / O interface as needed. Removable media, such as disks, optical disks, magneto-optical disks, semiconductor memories, etc., are installed on the drive as needed so that computer programs read from them can be installed into the storage section as required. The processing unit can be implemented as a CPU, GPU, TPU, FPGA, NPU, etc.

[0143] In particular, according to embodiments of this disclosure, the methods described above can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program tangibly embodied on a machine-readable medium, the computer program containing program code for performing the methods described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium.

[0144] This disclosure also discloses a chip circuit, including any of the inter-core communication systems provided in the embodiments of this disclosure.

[0145] This disclosure also discloses an electronic device including a chip circuit provided in embodiments of this disclosure.

[0146] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0147] The units or modules described in the embodiments of this disclosure can be implemented in software or programmable hardware. The described units or modules can also be located in a processor, and the names of these units or modules do not necessarily constitute a limitation on the unit or module itself.

[0148] In another aspect, this disclosure also provides a computer-readable storage medium, which may be a computer-readable storage medium included in the electronic device or computer system described above; or it may be a standalone computer-readable storage medium not assembled into a device. The computer-readable storage medium stores one or more programs, which are used by one or more processors to perform the methods described in this disclosure.

[0149] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. An inter-nuclear communication system, characterized in that, The inter-core communication system includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module in each subsystem is connected to each processor core in the subsystem through the subsystem bus, and the subsystem message queue module in each subsystem is connected to the on-chip system message queue module. Any one of the plurality of processor cores is configured as follows: Messages are sent to the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem where any of the processor cores are located; The subsystem message queue module in the first subsystem is configured as follows: Obtain the message sent by any of the processor cores; If the target processor core of the message is determined to be the first processor core in the first subsystem, then the message is scheduled to the first processor core. The first processor core is configured as follows: Messages scheduled by the subsystem message queue module in the first subsystem are obtained through the subsystem bus in the first subsystem. The subsystem message queue module in the first subsystem is also configured as follows: If the target processor core of the message is determined to be the second processor core of the second subsystem of the plurality of subsystems, then the message is scheduled to the on-chip system message queue module; The on-chip system message queue module is configured as follows: Obtain the message scheduled by the subsystem message queue module in the first subsystem, and schedule the message to the subsystem message queue module in the second subsystem; The subsystem message queue module in the second subsystem is configured as follows: Obtain the message scheduled by the on-chip system message queue module, and schedule the message to the second processor core; The second processor core is configured as follows: The message is obtained through the subsystem bus in the second subsystem.

2. The inter-nuclear communication system according to claim 1, characterized in that, Sending a message to the subsystem message queue module in the first subsystem via the subsystem bus of the first subsystem where any of the processor cores resides includes: In the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem, a target core message sending channel corresponding to the priority in the message is determined; If the target core message sending channel is idle, the message is sent to the target core message sending channel through the subsystem bus in the first subsystem.

3. The inter-nuclear communication system according to claim 1, characterized in that, Before acquiring the message sent by any of the processor cores, the subsystem message queue module in the first subsystem is further configured as follows: Obtain the core weight corresponding to any of the processor cores; Based on the core weight corresponding to any processor core, determine the maximum number of first data packets that any processor core can transmit in a single core communication cycle, wherein the core weight of any processor core is positively correlated with the number of first data packets of any processor core; The step of obtaining the message sent by any of the processor cores includes: Within at least one core communication cycle, based on the first data packet number corresponding to any processor core, the message sent by any processor core is obtained from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem.

4. The inter-nuclear communication system according to claim 3, characterized in that, The step of obtaining the message sent by any processor core from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem includes: If the subsystem message queue module in the first subsystem includes at least one priority core message sending channel with currently received messages in the core message sending channel configured for any processor core, then the target priority core message sending channel with the highest priority is determined from the at least one priority core message sending channel with currently received messages, and the message sent by any processor core is obtained from the target priority core message sending channel. If the subsystem message queue module in the first subsystem does not include at least one priority core message sending channel with currently received messages in the core message sending channels configured for any processor core, and the subsystem message queue module in the first subsystem includes at least one weighted fair core message sending channel with currently received messages in the core message sending channels configured for any processor core, then the core message sending channel weight of each weighted fair core message sending channel in the at least one weighted fair core message sending channel with currently received messages is obtained, wherein the core message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair core message sending channel; Based on the message length of the message in each of the at least one currently active weighted fair core message sending channels and the corresponding core message sending channel weight, the message transmission duration corresponding to each of the at least one currently active weighted fair core message sending channels is obtained, and the target weighted fair core message sending channel with the shortest message transmission duration is determined in the at least one currently active weighted fair core message sending channels. The message sent by any of the processor cores is obtained from the target weighted fair core message sending channel.

5. The inter-nuclear communication system according to claim 1, characterized in that, The step of scheduling the message to the first processor core includes: In the core message receiving channel configured for the first processor core by the subsystem message queue module in the first subsystem, a first core message receiving channel corresponding to the priority in the message is determined; The message is scheduled to the first core message receiving channel, and a first interrupt notification is sent to the first processor core. The step of obtaining messages scheduled by the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem includes: In response to the first interrupt notification, the current process of the first processor core is interrupted; The message scheduled by the subsystem message queue module in the first subsystem is obtained from the first core message receiving channel through the subsystem bus in the first subsystem. The step of scheduling the message to the second processor core includes: In the core message receiving channel configured for the second processor core by the subsystem message queue module in the second subsystem, a second core message receiving channel corresponding to the priority in the message is determined; The message is scheduled to the second core message receiving channel, and a second interrupt notification is sent to the second processor core; The step of obtaining the message through the subsystem bus in the second subsystem includes: In response to the second interrupt notification, the current process of the second processor core is interrupted; The message is obtained from the second core message receiving channel via the subsystem bus in the second subsystem.

6. The inter-nuclear communication system according to claim 1, characterized in that, The inter-core communication system further includes a message interconnection network module, which is connected to the on-chip system message queue module and the subsystem message queue module in each of the multiple subsystems. The step of obtaining the message scheduled by the subsystem message queue module in the first subsystem includes: The message interconnection network module obtains the message scheduled by the subsystem message queue module in the first subsystem; The step of obtaining the message scheduled by the on-chip system message queue module includes: The message interconnection network module obtains messages scheduled by the on-chip system message queue module.

7. The inter-nuclear communication system according to claim 1, characterized in that, The step of scheduling the message to the on-chip system message queue module includes: In the subsystem message sending channels configured by the on-chip system message queue module for the first subsystem, the first subsystem message sending channel corresponding to the priority in the message is determined; If the first subsystem message sending channel is idle, the message will be scheduled to the first subsystem message sending channel in the on-chip system message queue module.

8. The inter-nuclear communication system according to claim 1, characterized in that, Before obtaining the message scheduled by the subsystem message queue module in the first subsystem, the on-chip system message queue module is further configured as follows: Obtain the subsystem weight corresponding to any of the subsystems; Based on the subsystem weight corresponding to any subsystem, determine the maximum number of second data packets that any subsystem can transmit within a single subsystem communication cycle, wherein the subsystem weight of any subsystem is positively correlated with the number of second data packets of any subsystem; The step of obtaining the message scheduled by the subsystem message queue module in the first subsystem includes: Within at least one subsystem communication cycle, based on the second data packet number corresponding to the first subsystem, the message scheduled by the subsystem message queue module in the first subsystem is obtained from the subsystem message sending channel configured by the on-chip system message queue module for the first subsystem.

9. The inter-nuclear communication system according to claim 8, characterized in that, The step of obtaining the message scheduled by the subsystem message queue module in the first subsystem from the subsystem message sending channel configured for the first subsystem by the on-chip system message queue module includes: If the on-chip system message queue module is configured with at least one priority subsystem message sending channel that currently has messages in the subsystem message sending channel of the first subsystem, then the target priority subsystem message sending channel with the highest priority is determined from the at least one priority subsystem message sending channel that currently has messages, and the message scheduled by the subsystem message queue module in the first subsystem is obtained from the target priority subsystem message sending channel. If the on-chip system message queue module does not include at least one priority subsystem message sending channel with currently received messages in the subsystem message sending channels configured for the first subsystem, and the on-chip system message queue module includes at least one weighted fair subsystem message sending channel with currently received messages in the subsystem message sending channels configured for the first subsystem, then the subsystem message sending channel weight of each weighted fair subsystem message sending channel in the at least one weighted fair subsystem message sending channel with currently received messages is obtained, wherein the subsystem message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair subsystem message sending channel; Based on the message length of the message in each of the at least one currently message-containing weighted fair subsystem message sending channels and the corresponding subsystem message sending channel weight, the message transmission duration corresponding to each of the at least one currently message-containing weighted fair subsystem message sending channels is obtained, and the target weighted fair subsystem message sending channel with the shortest message transmission duration is determined in the at least one currently message-containing weighted fair subsystem message sending channels. The message scheduled by the subsystem message queue module in the first subsystem is obtained from the message sending channel of the target weighted fairness subsystem.

10. A control method for an inter-nuclear communication system, characterized in that, The inter-core communication system includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module in each subsystem is connected to each processor core in the subsystem through the subsystem bus, and the subsystem message queue module in each subsystem is connected to the on-chip system message queue module. The inter-nuclear communication system control method includes: Control any one of the plurality of processor cores to send a message to the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem where the processor core is located; The subsystem message queue module in the first subsystem is controlled to obtain messages sent by any of the processor cores. If it is determined that the target processor core of the message is the first processor core in the first subsystem, the message is scheduled to the first processor core. Control the first processor core to obtain messages scheduled by the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem; The subsystem message queue module in the first subsystem controls the message to be scheduled to the on-chip system message queue module when it is determined that the target processor core of the message is the second processor core of the second subsystem in the plurality of subsystems. The system-on-chip message queue module is controlled to obtain the message scheduled by the subsystem message queue module in the first subsystem and to schedule the message to the subsystem message queue module in the second subsystem. Control the subsystem message queue module in the second subsystem to obtain the message scheduled by the on-chip system message queue module and schedule the message to the second processor core; The second processor core is controlled to obtain the message through the subsystem bus in the second subsystem.

11. The control method for an inter-nuclear communication system according to claim 10, characterized in that, Sending a message to the subsystem message queue module in the first subsystem via the subsystem bus of the first subsystem where any of the processor cores resides includes: In the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem, a target core message sending channel corresponding to the priority in the message is determined; If the target core message sending channel is idle, the message is sent to the target core message sending channel through the subsystem bus in the first subsystem.

12. The control method for an inter-nuclear communication system according to claim 10, characterized in that, The method further includes: The subsystem message queue module in the first control subsystem obtains the core weight corresponding to any processor core before obtaining the message sent by any processor core. Based on the core weight corresponding to any processor core, it determines the maximum number of first data packets that any processor core can transmit in a single core communication cycle, wherein the core weight of any processor core is positively correlated with the number of first data packets of any processor core. The step of obtaining the message sent by any of the processor cores includes: Within at least one core communication cycle, based on the first data packet number corresponding to any processor core, the message sent by any processor core is obtained from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem.

13. The control method for an inter-nuclear communication system according to claim 12, characterized in that, The step of obtaining the message sent by any processor core from the core message sending channel configured for any processor core by the subsystem message queue module in the first subsystem includes: If the subsystem message queue module in the first subsystem includes at least one priority core message sending channel with currently received messages in the core message sending channel configured for any processor core, then the target priority core message sending channel with the highest priority is determined from the at least one priority core message sending channel with currently received messages, and the message sent by any processor core is obtained from the target priority core message sending channel. If the subsystem message queue module in the first subsystem does not include at least one priority core message sending channel with currently received messages in the core message sending channels configured for any processor core, and the subsystem message queue module in the first subsystem includes at least one weighted fair core message sending channel with currently received messages in the core message sending channels configured for any processor core, then the core message sending channel weight of each weighted fair core message sending channel in the at least one weighted fair core message sending channel with currently received messages is obtained, wherein the core message sending channel weight is positively correlated with the bandwidth of the corresponding weighted fair core message sending channel; Based on the message length of the message in each of the at least one currently active weighted fair core message sending channels and the corresponding core message sending channel weight, the message transmission duration corresponding to each of the at least one currently active weighted fair core message sending channels is obtained, and the target weighted fair core message sending channel with the shortest message transmission duration is determined in the at least one currently active weighted fair core message sending channels. The message sent by any of the processor cores is obtained from the target weighted fair core message sending channel.

14. The inter-nuclear communication system control method according to claim 10, characterized in that, The step of scheduling the message to the first processor core includes: In the core message receiving channel configured for the first processor core by the subsystem message queue module in the first subsystem, a first core message receiving channel corresponding to the priority in the message is determined; The message is scheduled to the first core message receiving channel, and a first interrupt notification is sent to the first processor core. The step of obtaining messages scheduled by the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem includes: In response to the first interrupt notification, the current process of the first processor core is interrupted; The message scheduled by the subsystem message queue module in the first subsystem is obtained from the first core message receiving channel through the subsystem bus in the first subsystem. The step of scheduling the message to the second processor core includes: In the core message receiving channel configured for the second processor core by the subsystem message queue module in the second subsystem, a second core message receiving channel corresponding to the priority in the message is determined; The message is scheduled to the second core message receiving channel, and a second interrupt notification is sent to the second processor core; The step of obtaining the message through the subsystem bus in the second subsystem includes: In response to the second interrupt notification, the current process of the second processor core is interrupted; The message is obtained from the second core message receiving channel via the subsystem bus in the second subsystem.

15. The control method for an inter-nuclear communication system according to claim 10, characterized in that, The inter-core communication system further includes a message interconnection network module, which is connected to the on-chip system message queue module and the subsystem message queue module in each of the multiple subsystems. The step of obtaining the message scheduled by the subsystem message queue module in the first subsystem includes: The message interconnection network module obtains the message scheduled by the subsystem message queue module in the first subsystem; The step of obtaining the message scheduled by the on-chip system message queue module includes: The message interconnection network module obtains messages scheduled by the on-chip system message queue module.

16. A control device for an inter-nuclear communication system, characterized in that, The inter-core communication system includes an on-chip system message queue module and multiple subsystems. Each subsystem includes a subsystem bus, a subsystem message queue module, and multiple processor cores. The subsystem message queue module in each subsystem is connected to each processor core in the subsystem through the subsystem bus, and the subsystem message queue module in each subsystem is connected to the on-chip system message queue module. The inter-nuclear communication system control device includes: The first core control module is configured to control any one of the plurality of processor cores to send messages to the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem where the processor core is located. The first queue control module is configured to control the subsystem message queue module in the first subsystem to obtain messages sent by any processor core. If it is determined that the target processor core of the message is the first processor core in the first subsystem, the message is scheduled to the first processor core. The second core control module is configured to control the first processor core and obtain messages scheduled by the subsystem message queue module in the first subsystem through the subsystem bus in the first subsystem. The second queue control module is configured to control the subsystem message queue module in the first subsystem, and when it is determined that the target processor core of the message is the second processor core of the second subsystem in the plurality of subsystems, the message is scheduled to the on-chip system message queue module. The third queue control module is configured to control the on-chip system message queue module to obtain the message scheduled by the subsystem message queue module in the first subsystem and to schedule the message to the subsystem message queue module in the second subsystem. The fourth queue control module is configured to control the subsystem message queue module in the second subsystem, obtain the message scheduled by the on-chip system message queue module, and schedule the message to the second processor core; The third core control module is configured to control the second processor core and obtain the message through the subsystem bus in the second subsystem.

17. An electronic device, characterized in that, The method includes a memory and a processor; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method of any one of claims 10-15.

18. A computer-readable storage medium storing computer instructions thereon, characterized in that, When executed by a processor, the computer instructions implement the method described in any one of claims 10-15.

19. A chip circuit, characterized in that, The system includes the inter-nuclear communication system according to any one of claims 1 to 9.

20. An electronic device, characterized in that, Includes the chip circuit described in claim 19.

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