Near memory computing chip architecture and method

Abstract

The invention relates to the technical field of chip design, in particular to a near-memory computing chip architecture and method. The system comprises a calculation module, the calculation module comprises a plurality of calculation cores, and each calculation core comprises a register, an arithmetic logic unit and a first-level cache; a second level cache, wherein the second level cache is connected with the calculation module; the high-bandwidth memory comprises a plurality of high-bandwidth memory bare chips, and each high-bandwidth memory bare chip is connected with the second-level cache; the first-level cache, the second-level cache and each high-bandwidth memory bare chip respectively comprise a plurality of near memory calculation groups, each near memory calculation group comprises an arithmetic logic unit, an interconnection module and a plurality of memory banks, and the memory banks in each near memory calculation group are connected with the arithmetic logic unit in the near memory calculation group through the interconnection module. The problem of a storage wall can be relieved, and the computing power of a chip is improved.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a near-memory computing chip architecture and method. Background Technology

[0002] Modern processor design faces the memory wall problem, specifically referring to the limitation of memory bandwidth on further development of chip computing power. Even if the number of processors inside the chip increases, the speed at which data is supplied from outside the chip to inside the chip cannot keep up with the speed at which the processors inside the chip process data. The processors inside the chip can only wait, and therefore, the chip's computing power cannot be further improved. Summary of the Invention

[0003] The purpose of this invention is to provide a near-memory computing chip architecture and method to alleviate the memory wall problem and improve chip computing power.

[0004] According to a first aspect of the present invention, a near-memory computing chip architecture is provided, the chip architecture comprising: The computing module includes several computing cores, each of which includes a register, an arithmetic logic unit, and a level 1 cache.

[0005] A second-level cache, which is connected to the computing module.

[0006] High-bandwidth memory, comprising a plurality of high-bandwidth memory dies, each high-bandwidth memory die being connected to the secondary cache.

[0007] The L1 cache, L2 cache, and each high-bandwidth memory die each include several near-memory computing groups. Each near-memory computing group contains an arithmetic logic unit, an interconnect module, and several memory banks. The memory banks in each near-memory computing group are connected to the arithmetic logic unit in that near-memory computing group through the interconnect module.

[0008] Furthermore, each computing core also includes shared memory, which comprises several near-memory computing groups.

[0009] According to a second aspect of the present invention, a near-memory computing method based on the above-described chip architecture is provided, the method comprising the following steps: S010, obtain the address of the first data (addr0) and the address of the second data (addr1).

[0010] S020, if addr0 and addr1 are in the same near-memory computation group of a high-bandwidth memory die, then the computation logic of the data of addr0 and addr1 is placed in the arithmetic logic unit in the near-memory computation group where addr0 and addr1 are located, and the arithmetic logic unit in the near-memory computation group where addr0 and addr1 are located is used to perform the computation on the data of addr0 and addr1, and the computation result is written back to the target address.

[0011] Furthermore, S020 also includes: if addr0 and addr1 are in different near-memory computation groups of a high-bandwidth memory die, or if addr0 and addr1 are in near-memory computation groups of different high-bandwidth memory dies, then proceed to S030.

[0012] S030, load the data of addr0 and addr1 into the first L2 cache address L2addr0 and the second L2 cache address L2addr1 respectively. If L2addr0 and L2addr1 are in the same near-memory computation group of the L2 cache, then put the computation logic of the data of L2addr0 and L2addr1 into the arithmetic logic unit in the near-memory computation group where L2addr0 and L2addr1 are located, and use the arithmetic logic unit in the near-memory computation group where L2addr0 and L2addr1 are located to perform computation on the data of L2addr0 and L2addr1, and write the computation result back to the target address.

[0013] Furthermore, S030 also includes: if L2addr0 and L2addr1 are in different near-memory computation groups of the L2 cache, then proceed to S040.

[0014] S040, load the data of L2addr0 and L2addr1 into the first L1 cache address L1addr0 and the second L1 cache address L1addr1 of the target computing core, respectively. If L1addr0 and L1addr1 are in the same near-memory computing group of the L1 cache, then place the calculation logic of the data of L1addr0 and L1addr1 into the arithmetic logic unit in the near-memory computing group where L1addr0 and L1addr1 are located, and use the arithmetic logic unit in the near-memory computing group where L1addr0 and L1addr1 are located to calculate the data of L1addr0 and L1addr1, and write the calculation result back to the target address; the target computing core is the computing core that performs the calculation of the first data and the second data.

[0015] According to a third aspect of the present invention, a near-memory computing method based on the above-described chip architecture is provided, the method comprising the following steps: S100, obtain the address of the first data addr0 and the address of the second data addr1.

[0016] S200, if addr0 and addr1 are in the same near-memory computing group in the shared memory of the target computing core, then the calculation logic of the data of addr0 and addr1 is placed in the arithmetic logic unit in the near-memory computing group where addr0 and addr1 are located, and the arithmetic logic unit in the near-memory computing group where addr0 and addr1 are located is used to calculate the data of addr0 and addr1, and the calculation result is written back to the target address; the target computing core is the computing core that performs the calculation of the first data and the second data.

[0017] Furthermore, S200 also includes: if addr0 is in a near-memory computation group of a high-bandwidth memory die and addr1 is in a near-memory computation group of a shared cache, then proceed to S300.

[0018] S300: After loading the data of addr0 into the first level cache address L1addr0 of the target computing core, the data of L1addr0 is then loaded into the shared cache address addr' of the target computing core. If addr' and addr1 are in the same near-memory computing group of the shared memory of the target computing core, the calculation logic of the data of addr' and addr1 is placed in the arithmetic logic unit in the near-memory computing group where addr' and addr1 are located, and the arithmetic logic unit in the near-memory computing group where addr' and addr1 are located is used to calculate the data of addr' and addr1, and the calculation result is written back to the target address.

[0019] Furthermore, S300 also includes: if addr' and addr1 are in different near-memory computing groups in the shared memory of the target computing core, then proceed to S400.

[0020] S400 loads the data of addr' and addr1 into the first register r0 and the second register r1 of the target computing core, respectively, and uses the arithmetic logic unit included in the target computing core to perform calculations on the data of r0 and r1, and writes the calculation results back to the target address.

[0021] Furthermore, S200 also includes: if addr0 and addr1 are in different near-memory computation groups of a high-bandwidth memory die or addr0 and addr1 are in near-memory computation groups of different high-bandwidth memory dies, then proceed to S500.

[0022] S500: Load the data of addr0 and addr1 into the first L2 cache address L2addr0 and the second L2 cache address L2addr1 respectively. If L2addr0 and L2addr1 are in different near-memory calculation groups of the L2 cache, then proceed to S510.

[0023] S510: Load the data of L2addr0 and L2addr1 into the first level cache address L1addr0 and the second level cache address L1addr1 of the target computing core, respectively. If L1addr0 and L1addr1 are in different near-memory computing groups of the first level cache, then proceed to S520.

[0024] S520 loads the data of L1addr0 into the shared cache address addr' of the target computing core, and loads the data of L1addr1 into another shared cache address addr'' of the target computing core. If addr' and addr'' are in the same near-memory computing group of the shared memory of the target computing core, the calculation logic of the data of addr' and addr'' is placed in the arithmetic logic unit in the near-memory computing group where addr' and addr'' are located, and the arithmetic logic unit in the near-memory computing group where addr' and addr'' are located is used to calculate the data of addr' and addr'', and the calculation result is written back to the target address.

[0025] Compared with the prior art, the present invention has at least the following beneficial effects: In this invention, the L1 cache, L2 cache, and each high-bandwidth memory die include several near-memory computation groups. Each near-memory computation group contains an arithmetic logic unit, an interconnect module, and several memory banks. The memory banks in each near-memory computation group are connected to the arithmetic logic unit in that near-memory computation group via the interconnect module. Compared to existing technologies, this invention can utilize the arithmetic logic unit in the near-memory computation group to perform calculations on the data in the memory banks of that near-memory computation group, eliminating the need to load all data into the registers in the computation core for calculation. This saves memory bandwidth, alleviates the memory wall problem, and improves chip computing power. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the near-memory computing chip architecture provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the near-memory computing chip architecture provided in Embodiment 2 of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] It should be noted that the terms "first," "second," etc., in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0030] Example 1: According to this embodiment, a near-memory computing chip architecture is provided, such as... Figure 1 As shown, the chip architecture includes: The computing module includes several computing cores, each of which includes a register, an arithmetic logic unit, and a level 1 cache. Figure 1 In the process, the computing module includes N+1 computing cores, namely core0, core1, ..., coreN, and each computing core also includes control logic.

[0031] The second-level cache is connected to the computing module. Specifically, the second-level cache (L2 cache) is connected to the first-level cache (L1 cache) of each computing core.

[0032] High-bandwidth memory, comprising a plurality of high-bandwidth memory dies, each high-bandwidth memory die being connected to the secondary cache. Figure 1 In this context, high-bandwidth memory (HBM) includes at least two high-bandwidth memory dies (HBM Die), namely HBM Die0, HBM Die1, and so on.

[0033] The L1 cache, L2 cache, and each high-bandwidth memory die each include several near-memory computing groups. Each near-memory computing group contains an arithmetic logic unit, an interconnect module, and several memory banks. The memory banks in each near-memory computing group are connected to the arithmetic logic unit in that near-memory computing group through the interconnect module. Figure 1 In this embodiment, every four memory banks, interconnect modules, and arithmetic logic units (ALUs) in HBM Die0 and HBM Die1 constitute one near-memory compute group (CNM group), and every two memory banks, interconnect modules, and ALUs in the L2 cache constitute one CNM group. It should be understood that this is only an example; the number of banks in the L1 cache, L2 cache, and the near-memory compute group included in each high-bandwidth memory die are not mutually restrictive and can be arbitrarily set. Furthermore, Figure 1Only a portion of the CNM groups included in the Level 1 cache are shown, and the Level 1 cache may also include multiple CNM groups. Optionally, the interconnect module is a crossbar switch.

[0034] In this embodiment, the L1 cache, L2 cache, and each high-bandwidth memory die include several near-memory computation groups. Each near-memory computation group contains an arithmetic logic unit, an interconnect module, and several memory banks. The memory banks in each near-memory computation group are connected to the arithmetic logic unit in that near-memory computation group through the interconnect module. Compared to existing technologies, this embodiment can utilize the arithmetic logic unit in the near-memory computation group to perform calculations on the data in the memory banks of the near-memory computation group to which the arithmetic logic unit belongs. This eliminates the need to load all data into the registers in the computation core for calculation, saving memory bandwidth, alleviating the memory wall problem, and improving chip computing power.

[0035] In this embodiment, the near-memory computing method based on the above-described chip architecture includes the following steps: S010, obtain the address of the first data (addr0) and the address of the second data (addr1).

[0036] In this embodiment, the first data and the second data are two data sets to be calculated.

[0037] S020, if addr0 and addr1 are in the same near-memory computation group of a high-bandwidth memory die, then the computation logic of the data of addr0 and addr1 is placed in the arithmetic logic unit in the near-memory computation group where addr0 and addr1 are located, and the arithmetic logic unit in the near-memory computation group where addr0 and addr1 are located is used to perform the computation on the data of addr0 and addr1, and the computation result is written back to the target address.

[0038] As a specific implementation, if the target address and addr0 and addr1 are in the same near-memory computation group on the same high-bandwidth memory die, the computation result can be directly written back to the memory within the same near-memory computation group. If the target address and addr0 and addr1 are in different near-memory computation groups on the same high-bandwidth memory die, the result can be written back according to the transmission path (if any) between the different near-memory computation groups, or the computation result can be transferred to the L2 cache first and then written back. If the target address and addr0 and addr1 are in near-memory computation groups on different high-bandwidth memory dies, the result can be written back according to the transmission path (if any) between the different high-bandwidth memory dies, or the computation result can be transferred to the L2 cache first and then written back.

[0039] In one specific implementation, each CNM group also includes a judgment module to determine whether the addresses of the two data items to be calculated are within the group. If the judgment result is yes, no more data is reported, and a completion signal is returned upwards; if the judgment result is no, the data is uploaded in response to the data loading instruction sent by the superior. For example, if addr0 and addr1 are in the same near-memory computation group of a high-bandwidth memory die, and the judgment module of the near-memory computation group determines whether the addresses of the two data items to be calculated are within the group, then the near-memory computation group will no longer report data, but the arithmetic logic unit within the group will perform the calculation, and return a completion signal after the calculation is completed.

[0040] As a specific implementation, S020 further includes: if addr0 and addr1 are in different near-memory computing groups of a high-bandwidth memory die, or if addr0 and addr1 are in near-memory computing groups of different high-bandwidth memory dies, then proceed to S030.

[0041] S030, load the data of addr0 and addr1 into the first L2 cache address L2addr0 and the second L2 cache address L2addr1 respectively. If L2addr0 and L2addr1 are in the same near-memory computation group of the L2 cache, then put the computation logic of the data of L2addr0 and L2addr1 into the arithmetic logic unit in the near-memory computation group where L2addr0 and L2addr1 are located, and use the arithmetic logic unit in the near-memory computation group where L2addr0 and L2addr1 are located to perform computation on the data of L2addr0 and L2addr1, and write the computation result back to the target address.

[0042] As a specific implementation, if L2addr0 and L2addr1 are in the same near-memory computation group in the L2 cache, and the target address is an address in a high-bandwidth memory die, then the path for writing the computation result back to the target address is from the near-memory computation group to the high-bandwidth memory die.

[0043] As a specific implementation, S030 further includes: if L2addr0 and L2addr1 are in different near-memory computation groups of the L2 cache, then proceed to S040.

[0044] S040, load the data of L2addr0 and L2addr1 into the first L1 cache address L1addr0 and the second L1 cache address L1addr1 of the target computing core, respectively. If L1addr0 and L1addr1 are in the same near-memory computing group of the L1 cache, then place the calculation logic of the data of L1addr0 and L1addr1 into the arithmetic logic unit in the near-memory computing group where L1addr0 and L1addr1 are located, and use the arithmetic logic unit in the near-memory computing group where L1addr0 and L1addr1 are located to calculate the data of L1addr0 and L1addr1, and write the calculation result back to the target address; the target computing core is the computing core that performs the calculation of the first data and the second data.

[0045] As a specific implementation, if L2addr0 and L2addr1 are in the same near-memory computation group in the L1 cache, and the target address is an address in a high-bandwidth memory die, then the path for writing the computation result back to the target address is from the near-memory computation group to the L2 cache to the high-bandwidth memory die.

[0046] As a specific implementation, S040 further includes: if L1addr0 and L1addr1 are in different near-memory computation groups of the L1 cache, then proceed to S050.

[0047] S050, load the data of L1addr0 and L1addr1 into the first register r0 and the second register r1 of the target computing core, respectively, and the arithmetic logic unit included in the target computing core performs calculations on the data of r0 and r1, and writes the calculation results back to the target address.

[0048] As a specific implementation, if L1addr0 and L1addr1 are in different near-memory computation groups of the L1 cache, and the target address is an address in a high-bandwidth memory die, then the path for writing the computation result back to the target address is from the arithmetic logic unit of the target computation core to the L1 cache to the L2 cache to the high-bandwidth memory die.

[0049] Based on S010-S050, by judging step by step from the lowest level storage (HBM die) - L2 cache - L1 cache - top level core (register), the calculation is completed first at the storage level where the data is located, thereby reducing cross-level data movement from the source. Compared with the existing technology that requires loading data into registers for calculation, the method of this embodiment minimizes the amount of cross-level data movement by calculating nearby, reducing bandwidth occupation and power consumption, and improving chip computing power.

[0050] Example 2: Compared to Embodiment 1, each computing core in this embodiment also includes shared memory, which comprises several near-memory computing groups, such as... Figure 2 As shown. Figure 2 Only a portion of the CNM groups included in the L1 cache are shown, and shared memory may also include multiple CNM groups. In this embodiment, the number of shared memory, L1 cache, L2 cache, and the number of banks included in the near-memory computing group of each high-bandwidth memory die are not mutually restrictive and can be arbitrarily set.

[0051] In this embodiment, the near-memory computing method based on the above-described chip architecture includes the following steps: S100, obtain the address of the first data addr0 and the address of the second data addr1.

[0052] S200, if addr0 and addr1 are in the same near-memory computing group in the shared memory of the target computing core, then the calculation logic of the data of addr0 and addr1 is placed in the arithmetic logic unit in the near-memory computing group where addr0 and addr1 are located, and the arithmetic logic unit in the near-memory computing group where addr0 and addr1 are located is used to calculate the data of addr0 and addr1, and the calculation result is written back to the target address; the target computing core is the computing core that performs the calculation of the first data and the second data.

[0053] As a specific implementation, if addr0 and addr1 are in the same near-memory computing group in the shared memory of the target computing core, and the target address is an address in a high-bandwidth memory die, then the path for writing the calculation result back to the target address is from the near-memory computing group to the L1 cache to the L2 cache to the high-bandwidth memory die.

[0054] As a specific implementation, each CNM group of shared memory also includes a judgment module to determine whether the addresses of the two data to be calculated are within the same group. If the judgment result is yes, no more data is reported, and a completion signal is returned upwards; if the judgment result is no, a data loading instruction sent by the superior is responded to, and the data is uploaded.

[0055] In one specific implementation, S200 further includes: if addr0 is in a near-memory computation group of a high-bandwidth memory die and addr1 is in a near-memory computation group of a shared cache, then proceed to S300.

[0056] S300: After loading the data of addr0 into the first level cache address L1addr0 of the target computing core, the data of L1addr0 is then loaded into the shared cache address addr' of the target computing core. If addr' and addr1 are in the same near-memory computing group of the shared memory of the target computing core, the calculation logic of the data of addr' and addr1 is placed in the arithmetic logic unit in the near-memory computing group where addr' and addr1 are located, and the arithmetic logic unit in the near-memory computing group where addr' and addr1 are located is used to calculate the data of addr' and addr1, and the calculation result is written back to the target address.

[0057] It should be understood that the process of loading the data of addr0 into the first level cache address L1addr0 of the target computing core is the same as the loading process in Embodiment 1, including: first loading the data of addr0 into the first level cache address L2addr0, and then loading the data of L2addr0 into the first level cache address L1addr0 of the target computing core.

[0058] As a specific implementation, S300 further includes: if addr' and addr1 are in different near-memory computing groups of the shared memory of the target computing core, then proceed to S400.

[0059] S400 loads the data of addr' and addr1 into the first register r0 and the second register r1 of the target computing core, respectively, and uses the arithmetic logic unit included in the target computing core to perform calculations on the data of r0 and r1, and writes the calculation results back to the target address.

[0060] As a specific implementation, if addr' and addr1 are in different near-memory computing groups of the shared memory of the target computing core, and the target address is an address in a high-bandwidth memory die, then the path for writing the calculation result back to the target address is from the arithmetic logic unit of the target computing core to the shared memory to the L1 cache to the L2 cache to the high-bandwidth memory die.

[0061] As a specific implementation, S200 further includes: if addr0 and addr1 are in the same near-memory computation group of a high-bandwidth memory die, then the computation logic of the data of addr0 and addr1 is placed in the arithmetic logic unit in the near-memory computation group where addr0 and addr1 are located, and the arithmetic logic unit in the near-memory computation group where addr0 and addr1 are located is used to perform computation on the data of addr0 and addr1, and the computation result is written back to the target address.

[0062] As a specific implementation, if addr0 and addr1 are in different near-memory computation groups of the same high-bandwidth memory die, or addr0 and addr1 are in near-memory computation groups of different high-bandwidth memory dies, or L2addr0 and L2addr1 are in different near-memory computation groups of the L2 cache, then the processing shall be carried out in accordance with the method of Embodiment 1, which will not be repeated here.

[0063] As a specific implementation, S200 further includes: if addr0 and addr1 are in different near-memory computing groups of a high-bandwidth memory die or addr0 and addr1 are in near-memory computing groups of different high-bandwidth memory dies, then proceed to S500.

[0064] S500: Load the data of addr0 and addr1 into the first L2 cache address L2addr0 and the second L2 cache address L2addr1 respectively. If L2addr0 and L2addr1 are in different near-memory calculation groups of the L2 cache, then proceed to S510.

[0065] S510: Load the data of L2addr0 and L2addr1 into the first level cache address L1addr0 and the second level cache address L1addr1 of the target computing core, respectively. If L1addr0 and L1addr1 are in different near-memory computing groups of the first level cache, then proceed to S520.

[0066] S520 loads the data of L1addr0 into the shared cache address addr' of the target computing core, and loads the data of L1addr1 into another shared cache address addr'' of the target computing core. If addr' and addr'' are in the same near-memory computing group of the shared memory of the target computing core, the calculation logic of the data of addr' and addr'' is placed in the arithmetic logic unit in the near-memory computing group where addr' and addr'' are located, and the arithmetic logic unit in the near-memory computing group where addr' and addr'' are located is used to calculate the data of addr' and addr'', and the calculation result is written back to the target address.

[0067] As a specific implementation, if addr' and addr'' are in different near-memory computation groups of the shared memory of the target computing core, then the data of addr' is loaded into the first register r0 of the target computing core, the data of addr'' is loaded into the second register r1 of the target computing core, and the arithmetic logic unit included in the target computing core is used to perform calculations on the data of r0 and r1, and the calculation results are written back to the target address.

[0068] Based on Embodiment 1, each computing core in this embodiment also includes shared memory. Accordingly, by judging step by step from the lowest level storage (HBM die) - L2 cache - L1 cache - shared memory - top-level core (register), or by judging step by step from shared memory - top-level core (register), the calculation is preferentially completed at the storage level where the data is located, thereby reducing cross-level data movement from the source. Compared with the existing technology, which requires loading data into registers for calculation, the method of this embodiment minimizes the amount of cross-level data movement by calculating nearby, reducing bandwidth occupation and power consumption, and improving chip computing power.

[0069] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. It should also be understood that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A near-memory computing chip architecture, characterized in that, The chip architecture includes: The computing module includes several computing cores, each computing core including a register, an arithmetic logic unit and a level 1 cache; A second-level cache, which is connected to the computing module; High-bandwidth memory, wherein the high-bandwidth memory comprises a plurality of high-bandwidth memory dies, each high-bandwidth memory die being connected to the secondary cache; The L1 cache, L2 cache, and each high-bandwidth memory die each include several near-memory computing groups. Each near-memory computing group contains an arithmetic logic unit, an interconnect module, and several memory banks. The memory banks in each near-memory computing group are connected to the arithmetic logic unit in that near-memory computing group through the interconnect module.

2. The near-memory computing chip architecture according to claim 1, characterized in that, Each computing core also includes shared memory, which comprises several near-memory computing groups.

3. A near-memory computing method based on the chip architecture described in claim 1 or 2, characterized in that, The method includes the following steps: S010, obtain the address of the first data (addr0) and the address of the second data (addr1); S020, if addr0 and addr1 are in the same near-memory computation group of a high-bandwidth memory die, then the computation logic of the data of addr0 and addr1 is placed in the arithmetic logic unit in the near-memory computation group where addr0 and addr1 are located, and the arithmetic logic unit in the near-memory computation group where addr0 and addr1 are located is used to perform the computation on the data of addr0 and addr1, and the computation result is written back to the target address.

4. The near-memory computation method according to claim 3, characterized in that, S020 also includes: if addr0 and addr1 are in different near-memory computation groups of a high-bandwidth memory die, or if addr0 and addr1 are in near-memory computation groups of different high-bandwidth memory dies, then proceed to S030; S030, load the data of addr0 and addr1 into the first L2 cache address L2addr0 and the second L2 cache address L2addr1 respectively. If L2addr0 and L2addr1 are in the same near-memory computation group of the L2 cache, then put the computation logic of the data of L2addr0 and L2addr1 into the arithmetic logic unit in the near-memory computation group where L2addr0 and L2addr1 are located, and use the arithmetic logic unit in the near-memory computation group where L2addr0 and L2addr1 are located to perform computation on the data of L2addr0 and L2addr1, and write the computation result back to the target address.

5. The near-memory calculation method according to claim 4, characterized in that, S030 also includes: if L2addr0 and L2addr1 are in different near-memory computation groups of the L2 cache, then proceed to S040; S040, load the data of L2addr0 and L2addr1 into the first L1 cache address L1addr0 and the second L1 cache address L1addr1 of the target computing core, respectively. If L1addr0 and L1addr1 are in the same near-memory computing group of the L1 cache, then place the calculation logic of the data of L1addr0 and L1addr1 into the arithmetic logic unit in the near-memory computing group where L1addr0 and L1addr1 are located, and use the arithmetic logic unit in the near-memory computing group where L1addr0 and L1addr1 are located to calculate the data of L1addr0 and L1addr1, and write the calculation result back to the target address; the target computing core is the computing core that performs the calculation of the first data and the second data.

6. A near-memory computing method based on the chip architecture of claim 2, characterized in that, The method includes the following steps: S100, obtain the address of the first data (addr0) and the address of the second data (addr1); S200, if addr0 and addr1 are in the same near-memory computing group in the shared memory of the target computing core, then the calculation logic of the data of addr0 and addr1 is placed in the arithmetic logic unit in the near-memory computing group where addr0 and addr1 are located, and the arithmetic logic unit in the near-memory computing group where addr0 and addr1 are located is used to calculate the data of addr0 and addr1, and the calculation result is written back to the target address; the target computing core is the computing core that performs the calculation of the first data and the second data.

7. The near-memory computation method according to claim 6, characterized in that, S200 also includes: if addr0 is in a near-memory compute group of a high-bandwidth memory die and addr1 is in a near-memory compute group of a shared cache, then proceed to S300; S300: After loading the data of addr0 into the first level cache address L1addr0 of the target computing core, the data of L1addr0 is then loaded into the shared cache address addr' of the target computing core. If addr' and addr1 are in the same near-memory computing group of the shared memory of the target computing core, the calculation logic of the data of addr' and addr1 is placed in the arithmetic logic unit in the near-memory computing group where addr' and addr1 are located, and the arithmetic logic unit in the near-memory computing group where addr' and addr1 are located is used to calculate the data of addr' and addr1, and the calculation result is written back to the target address.

8. The near-memory computation method according to claim 7, characterized in that, S300 also includes: if addr' and addr1 are in different near-memory computing groups in the shared memory of the target computing core, then proceed to S400; S400 loads the data of addr' and addr1 into the first register r0 and the second register r1 of the target computing core, respectively, and uses the arithmetic logic unit included in the target computing core to perform calculations on the data of r0 and r1, and writes the calculation results back to the target address.

9. The near-memory computation method according to claim 6, characterized in that, S200 also includes: if addr0 and addr1 are in different near-memory computation groups of a high-bandwidth memory die or addr0 and addr1 are in near-memory computation groups of different high-bandwidth memory dies, then proceed to S500; S500: Load the data of addr0 and addr1 into the first L2 cache address L2addr0 and the second L2 cache address L2addr1 respectively. If L2addr0 and L2addr1 are in different near memory calculation groups of the L2 cache, then proceed to S510. S510: Load the data of L2addr0 and L2addr1 into the first level cache address L1addr0 and the second level cache address L1addr1 of the target computing core, respectively. If L1addr0 and L1addr1 are in different near-memory computing groups of the first level cache, then proceed to S520. S520 loads the data of L1addr0 into the shared cache address addr' of the target computing core, and loads the data of L1addr1 into another shared cache address addr'' of the target computing core. If addr' and addr'' are in the same near-memory computing group of the shared memory of the target computing core, the calculation logic of the data of addr' and addr'' is placed in the arithmetic logic unit in the near-memory computing group where addr' and addr'' are located, and the arithmetic logic unit in the near-memory computing group where addr' and addr'' are located is used to calculate the data of addr' and addr'', and the calculation result is written back to the target address.

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