A multi-source decision and partition self-healing anti-radiation SRAM computing method and system

Abstract

This application relates to the fields of integrated circuit design and artificial intelligence hardware optimization technology, and discloses a radiation-resistant SRAM in-memory computing method and system with multi-source decision-making and partition self-healing. The method includes: steps for cross-layer benchmark archiving and pre-susceptibility topology initialization; steps for multi-source data acquisition and feature quantization processing in runtime; steps for semantic attribution and nonlinear weighted analysis of runtime fields; steps for spatiotemporal multidimensional state machine decision-making based on large model stage perception and thermodynamic constraints; steps for bit-plane decoupling mapping and asymmetric compression migration for large model features; and steps for multi-physics closed-loop self-healing and heterogeneous degradation reconstruction. The system corresponds to this method. This application solves the technical problems of difficulty in quantifying the performance degradation of in-memory computing chips under extreme radiation, difficulty in identifying fault mechanisms, and difficulty in controlling online self-healing.

Description

Technical Field

[0001] This application relates to the fields of integrated circuit design and artificial intelligence hardware optimization technology, specifically a radiation-resistant SRAM storage method and system with multi-source decision-making and partition self-healing. Background Technology

[0002] Currently, when SRAM-based compute-in-memory (CIM) chips perform long-term tasks under extreme environments such as space radiation and high-energy particle impacts, their reliability is not only affected by random disturbances such as transient single-event upsets (SEUs) or transient pulses (SETs), but also faces long-term degradation issues such as physical aging of devices and threshold voltage drift caused by cumulative radiation dose. Existing reliability management solutions mostly rely on static bit error rate statistics or simple checksum mechanisms, which are insufficient to isolate process / voltage / temperature (PVT) noise interference in real time during chip operation. They also cannot accurately distinguish between physical device damage and transient computational errors at the logic level, making it difficult to achieve targeted fault isolation, resource remapping, or physical self-healing while ensuring the continuity of computational tasks. Furthermore, for critical data such as KV cache in large-scale model applications, there is a lack of strong consistency guarantees and low-overhead protection mechanisms during dynamic migration.

[0003] Therefore, the question is how to construct a control technology that realizes multi-source decision-making closed loop under the high radiation environment of SRAM in-memory computing chips without interrupting normal computing tasks, and further realize the progressive self-healing of damaged physical units under closed-loop monitoring, so as to solve the technical problems of difficult quantification of in-memory computing performance degradation, difficult identification of fault mechanisms, and difficult control of online self-healing of in-memory computing chips under extreme radiation. Summary of the Invention

[0004] The purpose of this application is to provide a radiation-resistant SRAM memory computing method and system with multi-source decision-making and partition self-healing, so as to solve the technical problems in the prior art of difficult quantification of memory computing performance degradation, difficult identification of fault mechanisms, and difficult control of online self-healing of memory computing chips under extreme radiation.

[0005] To achieve the above objectives, this application provides a radiation-resistant SRAM computing method with multi-source decision-making and partitioned self-healing, comprising: The steps for establishing cross-layer soft and hard benchmarks and initializing pre-susceptibility topology; based on these steps, a dynamic benchmark system with pre-prediction capabilities is constructed; The steps for multi-source data acquisition and feature quantization processing in runtime; based on these steps, multi-source monitoring data is output, which is used to characterize the physical health status of the SRAM array, calculate runtime verification status, and KV block access statistics; The steps for runtime field semantic attribution and nonlinear weighted analysis; based on these steps, the field semantic attribution value is output, which is used to quantify the overall threat of all semantic errors to SRAM computation in the current runtime cycle; The steps for spatiotemporal multidimensional state machine decision-making based on large model stage perception and thermodynamic constraints; based on this step, combined with multi-source monitoring data and field semantic attribution values, at least output state variables to characterize the health status of the SRAM array and policy matrices to characterize hardware and software cooperative action instructions. Steps for bit-plane decoupling mapping and asymmetric compression migration for large model features; atomic switching based on these steps to complete data migration; The steps of multiphysics closed-loop self-healing and heterogeneous transformation reconstruction; based on these steps, SRAM array partition self-healing and device function reconstruction are performed.

[0006] To achieve the above objectives, this application also provides a radiation-resistant SRAM memory system with multi-source decision-making and partition self-healing, which applies the multi-source decision-making and partition self-healing radiation-resistant SRAM memory method described above, including: The dynamic benchmark construction module is used for cross-layer benchmark archiving and pre-susceptibility topology initialization; a dynamic benchmark system with pre-prediction capability is built based on this dynamic benchmark construction module. The multi-source data processing module is used for multi-source data acquisition and feature quantization processing in runtime. Based on the multi-source data processing module, multi-source monitoring data is output, which is used to characterize the physical health status of the SRAM array, the calculation and verification status, and the KV block access statistics. The field semantic analysis module is used for the steps of runtime field semantic attribution and nonlinear weighted analysis; based on the field semantic analysis module, the field semantic attribution value is output, which is used to quantify the overall threat of all semantic errors to SRAM computing in the current runtime cycle; A multi-dimensional state decision module is used to make spatiotemporal multi-dimensional state machine decisions based on large model stage perception and thermodynamic constraints. Based on this multi-dimensional state decision module, combined with multi-source monitoring data and field semantic attribution values, at least the state variables used to characterize the health status of the SRAM array and the policy matrix used to characterize the software and hardware cooperative action instructions are output. The decoupled data migration module is used for bit-plane decoupling mapping and asymmetric compression migration steps for large model features; atomic switching is performed based on this decoupled data migration module to complete the data migration. A closed-loop self-healing reconfiguration module is used for multi-physics closed-loop self-healing and heterogeneous transformation reconfiguration; based on this closed-loop self-healing reconfiguration module, SRAM array partition self-healing and device function reconfiguration are performed.

[0007] Beneficial Effects: This application's multi-source decision-making and partition self-healing radiation-resistant SRAM in-memory computing method and system, by constructing a closed-loop system integrating hardware and software, dynamically monitors the long-term health status of the chip. During runtime verification, it incorporates short-term operational errors and adjusts the chip's computing mode, memory cell mapping, verification strategy, and task scheduling in real time to ensure the system maintains good computing performance and reliability even under radiation damage. It can more comprehensively and accurately reflect the performance degradation and reliability of in-memory computing chips under radiation or disturbance environments. It enables refined and quantitative evaluation of the radiation resistance performance of in-memory computing chips without interrupting normal chip operation; thus, it can more realistically reflect the reliability performance of in-memory computing chips in practical applications, especially suitable for fields with extremely high requirements for chip radiation resistance, such as space missions and military communications, promoting the application and development of in-memory computing chips in extreme environments. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A flowchart illustrating the radiation-resistant SRAM storage method with multi-source decision-making and partitioned self-healing provided in this application embodiment; Figure 2 The simulation effect comparison diagram provided for the embodiments of this application; in the figure: (a) is a comparison of the evolution of chip health under radiation environment; (b) is a comparison of the throughput of bit plane decoupling and pooling strategy; Figure 3 This is a structural block diagram of a radiation-resistant SRAM computing system with multi-source decision-making and partition self-healing provided in an embodiment of this application.

[0010] The implementation, functional features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0011] The technical solutions in the embodiments of this application will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0012] In this document, the term "comprising" is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0013] Existing SRAM in-memory computing chip reliability management technologies mainly rely on traditional error correction codes (ECC) or static redundancy backup mechanisms. While the former can correct a small number of memory bit flips (SEUs), it only protects against storage-related issues and cannot detect or address physical degradation problems in analog computing links caused by cumulative radiation dose (TID), such as transistor threshold voltage drift and increased leakage current. As a result, when chips are exposed to long-term space radiation, they cannot distinguish between transient soft errors and permanent device aging damage. Often, computing units are prematurely discarded due to misjudgment before the physical damage reaches a critical level, or they are forced to run even when the device has severely degraded, leading to unreliable calculation results. This severely impacts the chip's on-orbit lifespan and mission reliability.

[0014] On the other hand, existing reliability assessment schemes typically lack decoupling capabilities from environmental interference and proactive physical layer repair methods. In actual operation, signal drift caused by temperature fluctuations (T) and power supply noise (V) can easily mask the true physical health fingerprint, leading to false alarms or missed alarms in the monitoring system. Furthermore, faced with confirmed hardware damage, existing technologies usually only employ passive isolation-discard strategies, lacking self-healing mechanisms similar to physical annealing to restore the performance of damaged units. Moreover, in large-scale model applications, existing task migration schemes struggle to guarantee strong consistency of critical state data such as KV caches during dynamic scheduling, easily leading to context loss or inference interruptions.

[0015] In summary, existing technologies generally suffer from several technical shortcomings, including a single dimension for reliability monitoring, inability to decouple PVT environmental noise from physical damage, lack of proactive physical self-healing capabilities, and difficulty in ensuring data consistency during dynamic task migrations. These problems are particularly pronounced when in-memory computing chips are applied in high-reliability aerospace, military communications, and nuclear industries, limiting their ability to maintain long-term performance and intelligent survivability under extreme environments.

[0016] To address the aforementioned technical deficiencies, this embodiment discloses a radiation-resistant SRAM in-memory computing method and system based on multi-source decision-making and partitioned self-healing. This method is applicable to in-memory computing (CIM) chips operating in space radiation environments, high-energy particle radiation, or other strong radiation application scenarios. Specifically, it addresses the potential physical degradation and operational failures that CIM chips may face during long-term operation in radiation environments by proposing a real-time, comprehensive, and reliable multi-source evidence closed-loop control mechanism. In summary, this embodiment constructs a closed-loop system integrating hardware modules and software control systems to dynamically monitor the chip's long-term health status (e.g., long-term drift, aging slope), and during operational verification, it incorporates short-term operational errors (e.g., single-event upsets, transient current disturbances) to adjust the chip's computing mode, memory cell mapping, verification strategy, and task scheduling in real time, ensuring good computing performance and reliability even under radiation damage. Unlike existing technologies, this embodiment not only relies on simple bit error statistics (e.g., single-event upsets, SEUs) as evaluation indicators but also introduces a multi-source joint decision-making mechanism based on computational result consistency, current transient characteristic analysis, and weighted readback results. This mechanism can more comprehensively and accurately reflect the performance degradation and reliability of in-memory computing chips under radiation or disturbance environments. Through this method, this embodiment can perform a refined and quantitative evaluation of the radiation resistance performance of in-memory computing chips without interrupting the normal operation of the chip. This allows for a more realistic reflection of the reliability performance of in-memory computing chips in practical applications, and is particularly suitable for fields with extremely high requirements for chip radiation resistance, such as space missions and military communications, thus promoting the application and development of in-memory computing chips in extreme environments.

[0017] The known technical content that forms the basis of this embodiment and helps to understand this embodiment will now be described.

[0018] SRAM Compute-in-Memory (CIM) and its sensitivity to analog characteristics. SRAM CIM technology utilizes the analog circuit characteristics of SRAM cells (such as superimposing currents on bit lines using Kirchhoff's current law) to directly perform matrix multiplication and addition (MAC) operations within the memory array, breaking through the memory wall bottleneck of the traditional von Neumann architecture. Its core principle is that the memory cell is not only a container for data but also an executor of analog computation. However, because CIM relies on analog signals (voltage / current amplitude) to express computation results, it is more sensitive to transistor threshold voltage drift, power supply noise, and temperature changes compared to pure digital logic. This makes it extremely difficult to distinguish between soft errors and hard damage in radiated environments.

[0019] Multidimensional Failure Mechanisms in Space Radiation Environments. In aerospace or high-energy physics applications, the radiation effects faced by chips can be mainly divided into two categories, with drastically different impacts on CIM chips: Single-Event Effects (SEE): As mentioned earlier, this includes static memory bit flips caused by single-event upsets (SEUs) and transient pulses in the analog computing link caused by single-event transients (SETs). These failures are usually transient and can be recovered by rewriting or resetting. Cumulative Radiation Effects (TID / DD): Total Ionizing Dose Effect (TID) and Displacement Damage (DD) can cause the gate oxide layer of transistors to trap charges or lattice defects, resulting in permanent threshold voltage drift and increased leakage current. For SRAM CIMs, this manifests as long-term degradation of computational accuracy (i.e., aging or drift). This physical damage cannot be repaired by simple resetting and is a major cause of chip end-of-life.

[0020] Thermal annealing is a self-healing physical mechanism. Semiconductor physics research shows that high-temperature environments can accelerate the release of trapped charges and the recombination of lattice defects. Heating (annealing) damaged semiconductor devices at specific temperatures can effectively restore parameter drift caused by thermal runaway (TID), reduce leakage current, and restore device performance. This physical mechanism is the theoretical basis for realizing online "self-healing" of chips, but how to precisely control the heating area to avoid thermal runaway is a challenge in engineering implementation.

[0021] Key-Value Cache (KV Cache) in Large Language Models. In Transformer architectures and large language model inference processes, to avoid redundant computations, the key-value matrix of historical tokens is typically cached, known as a KV Cache. KV Cache not only consumes a large amount of storage space but also grows with the sequence length. More importantly, KV Cache is state data, and its consistency directly determines the correctness of the contextual logic for subsequent inference. In in-memory computing architectures, ensuring strong consistency of the KV Cache during migration without blocking the pipeline when a computing unit (tile) fails is a recognized technical challenge.

[0022] The relevant technical terms involved in this embodiment are explained below.

[0023] PVT Decoupling: PVT refers to Process, Voltage, and Temperature. In this embodiment, PVT decoupling specifically refers to a physical health sensing algorithm and circuit mechanism. By performing differential operations on "physical fingerprint data" that is sensitive to aging and "pseudo-sensing reference data" that is only sensitive to temperature drift / power supply noise, the interference of ambient temperature fluctuations and power supply voltage disturbances on the monitoring results is eliminated in real time, thereby accurately extracting the "long-term health drift" caused only by radiation damage or device aging.

[0024] Shadow Write: In this embodiment, it specifically refers to a data synchronization mechanism applied during the dynamic migration of a large model key-value cache (KVCache). During the migration of data from the source tile to the target tile, the system activates shadow write mode, simultaneously routing and writing all write operations to the mirror address of the target tile. This mechanism, combined with background copying, ensures that the data on the target end is completely consistent with the data on the source end the instant the migration is completed, achieving task switching with zero downtime and zero data loss.

[0025] Hysteresis State Machine: The core control logic of the collaborative decision engine in this embodiment. Unlike ordinary state machines that instantly flip over a single threshold, this state machine introduces a hysteresis interval (containing both high and low thresholds) in the transition determination of health states (such as healthy, deteriorating, and critical). A state change is only triggered when the monitored indicator (such as drift or bit error rate) exceeds the hysteresis boundary, effectively preventing frequent oscillations between different states (Ping-pong effect) caused by sensor transient noise or single particle disturbances, thus ensuring the stability of the scheduling strategy.

[0026] Partitioned Micro-heating Self-healing: This embodiment proposes an active physical repair technology. It refers to applying a controlled pulsed thermal field (thermal annealing) to specific sub-array (tile) regions identified as degraded using a micro-heater array integrated within the chip. This process accelerates the escape of trapped charges and the recombination of lattice defects through high temperature, thereby eliminating or mitigating transistor threshold drift caused by the total ionization dose (TID) effect, achieving physical recovery of device performance.

[0027] Dummy Leakage Slope: In the self-healing closed-loop control of this embodiment, it refers to the rate of change of leakage current of dummy (pseudo / idle) cells distributed within the heating area over time, which is collected in real time. This physical quantity serves as a proxy feedback signal for thermal load and annealing process, used to determine whether heating has reached a safe limit or effective range. When the slope exceeds a preset threshold or enters a stable region, the system automatically triggers "closed-loop termination" to prevent permanent thermal damage to the chip due to overheating.

[0028] Root of Reliability (RoR): This refers to the hardware core responsible for executing verification logic (such as remainder generation and consistency comparison), and is the starting point of the trust chain. The unique self-checking mechanism in this embodiment requires a fail-safe check of the hardware core itself before outputting the verification result. This prevents the output of erroneous safety signals due to radiation damage to the verification circuit itself, ensuring the reliability of the monitor itself.

[0029] KV Consistency Migration: A special protection process for KV Cache data in the Transformer architecture. Unlike ordinary memory copying, this process includes rigorous steps such as target selection, incremental logging, shadow write synchronization, version convergence determination, and atomic pointer switching. It aims to ensure that when a storage unit needs to be replaced due to aging or failure, the context state of the inference task can be transferred to the new unit without loss and smoothly, thus guaranteeing the logical continuity of long sequence generation.

[0030] Secondary Drift Slope: This refers to the rate of change of the physical fingerprint of a damaged tile within a subsequent operating window after thermal annealing and self-healing. This metric reflects the stability of the self-healing effect (whether degradation rebound occurs). In this embodiment, this slope is used as a key input to predict the remaining lifetime (RUL) of the device through a regression model, and based on this, a decision is made on whether to degrade the tile or permanently isolate it.

[0031] Physical Fingerprint Data: In this embodiment, this specifically refers to time-series data collected by the physical fingerprint sensing array inside the chip. This data is not user-stored logical information, but rather reflects the response characteristics of the SRAM memory cells and surrounding analog circuits under current physical conditions (such as threshold voltage drift and leakage current levels). By comparing it with the factory reference fingerprint, this data is used to calculate the amount of fingerprint drift, which is the core basis for determining whether the chip has undergone physical aging or radiation damage.

[0032] Field Semantic Label: This refers to the attribute identifier assigned to each binary bit of a neural network weight or activation value during the compilation phase on the host computer. Label types include Sign, Exponent, Mantissa, and Most Significant Bit (MSB). This embodiment utilizes this label to perform attribution weighting on verification failure events at runtime. For example, the error weight of the exponent bit is much higher than that of the mantissa bit, thereby achieving differentiated fault response based on data importance.

[0033] Redundant Residue Number System (RRNS): An enhanced runtime data integrity verification mechanism. When a conventional single modulus check (Mod M) detects a potential anomaly or insufficient confidence, the system activates an additional set of redundant moduli through the redundancy modulus management module. By calculating multiple remainders in parallel, this mechanism significantly reduces the aliasing rate and improves the detection coverage for multi-bit flips or specific pattern errors.

[0034] Atomic Switch: In this embodiment, during resource mapping and data migration, it specifically refers to an indivisible pointer update operation. Whether it's a mapped pointer to computing resources or a key-value pointer to data, the switching process must be completed within a single clock cycle or a protected transaction. This ensures that the system state is either at the old address or the new address, and never remains in an intermediate state, thus preventing data access errors or loss during task migration.

[0035] Cross-timescale trend cross-validation: One of the core algorithms of the collaborative decision engine in this embodiment. This algorithm jointly analyzes changes in long-term physical drift (reflecting device aging, which changes slowly) and changes in short-term operational evidence (reflecting computational errors, which change rapidly). Its purpose is to distinguish between gradual computational degradation caused by device aging and sudden computational errors caused by single-event upsets, thereby guiding the system to choose whether to perform physical self-healing or simply recalculate the data.

[0036] Throughput Compensation Scheduling: A resource scheduling strategy executed by a dynamic capacity compensation unit when computing power decreases due to partial tile degradation or the implementation of degradation strategies (such as reducing frequency or parallelism). This strategy introduces a compensation coefficient by dynamically adjusting task priorities, enabling redundant computing units, or changing pipeline depth to forcibly boost the overall processing capacity of the system, ensuring that the output throughput of critical tasks still meets real-time requirements even in the event of hardware failure.

[0037] The radiation-resistant SRAM storage method with multi-source decision-making and partitioned self-healing in this embodiment will now be described in detail.

[0038] This embodiment discloses a radiation-resistant SRAM computing method with multi-source decision-making and partitioned self-healing, including: The steps for establishing cross-layer soft and hard benchmarks and initializing pre-susceptibility topology; based on these steps, a dynamic benchmark system with pre-prediction capabilities is constructed; The steps for multi-source data acquisition and feature quantization processing in runtime; based on these steps, multi-source monitoring data is output, which is used to characterize the physical health status of the SRAM array, calculate runtime verification status, and KV block access statistics; The steps for runtime field semantic attribution and nonlinear weighted analysis; based on these steps, the field semantic attribution value is output, which is used to quantify the overall threat of all semantic errors to SRAM computation in the current runtime cycle; The steps for spatiotemporal multidimensional state machine decision-making based on large model stage perception and thermodynamic constraints; based on this step, combined with multi-source monitoring data and field semantic attribution values, at least output state variables to characterize the health status of the SRAM array and policy matrices to characterize hardware and software cooperative action instructions. Steps for bit-plane decoupling mapping and asymmetric compression migration for large model features; atomic switching based on these steps to complete data migration; The steps of multiphysics closed-loop self-healing and heterogeneous transformation reconstruction; based on these steps, SRAM array partition self-healing and device function reconstruction are performed.

[0039] Reference Figure 1 , Figure 1 A flowchart illustrating the radiation-resistant SRAM storage method with multi-source decision-making and partitioned self-healing provided in this application embodiment.

[0040] like Figure 1 As shown, this embodiment discloses a radiation-resistant SRAM computing method with multi-source decision-making and partitioned self-healing, including: S10: Soft and hard cross-layer benchmark filing and pre-susceptibility topology initialization.

[0041] In the multi-source decision-making and partitioned self-healing radiation-resistant SRAM computing method of this embodiment, the startup phase first executes a software and hardware cross-layer initialization process. Unlike existing technologies that passively record only logical addresses and static physical characteristics, thus failing to detect fault risks in advance, this embodiment deeply integrates semiconductor manufacturing process variation (PV), array physical susceptibility topology, and the algorithmic semantic tolerance of the Large Language Model (LLM) during the initialization phase, constructing a dynamic benchmark system with pre-predictive capabilities. The specific execution logic is as follows: S101: Archive of storage array hierarchical structure and radiation susceptibility topology.

[0042] In the application scenario of this embodiment, SRAM computing adopts a hierarchical structure with cross-layer mapping between software and hardware, and its physical resources are divided into: complete computing array (Array) → computing block (Tile) → storage partition (Partition) → data block (Block).

[0043] To support the bit-plane decoupling residual utilization mechanism in the subsequent S50, a physical bit-plane topology mapping is established when reading the array structure configuration table, and the following initial logical mapping table is fixed: Calculate the mapping table It is used to record the mapping relationship between logical computation tasks and storage blocks (Tile); Partition Mapping Table It is used to record the addressing relationship between a storage tile and its internal storage partition.

[0044] Due to unavoidable process variations (PV) in the chip fabrication process, different regions on the same chip inherently possess varying radiation resistance. During factory testing, extreme voltage and frequency stress test vectors are injected into the entire array to extract the leakage variance and threshold drift extreme values ​​of each physical unit. The data for each memory tile is recorded. Leakage current variance under secondary stress test and threshold voltage drift The innate susceptibility coefficient is calculated according to the following formula, and the on-chip radiation susceptibility topology matrix is ​​generated and stored. : in: This indicates that the input variables are linearly normalized based on the maximum and minimum values ​​of the array statistics. Its specific mathematical expression is as follows: Here, Represents the current specific The calculated value of the unnormalized innate susceptibility coefficient, i.e. , and These are the global maximum and minimum values ​​of the calculated value measured during the factory calibration test of the entire array, thus strictly mapping its value range to... . and This is a process sensitivity weighting parameter, which can be calibrated offline based on historical irradiation test data. On-chip radiation susceptibility topology matrix. The coordinates of physical regions in the array that are inherently weak in radiation resistance are precisely marked. These coordinates will be used as core parameters to flow into S103 to participate in the fault tolerance margin calculation and guide critical computing tasks to avoid high-risk physical regions during operation.

[0045] S102: Initialization of hybrid baseline fingerprint and asymmetric canary decoupled network.

[0046] To accurately assess the true degradation of SRAM arrays under complex radiation and temperature drift environments, a health baseline fingerprint vector is generated and written to the non-volatile memory area using on-chip automated testing equipment. This health baseline fingerprint vector Parameters such as the output voltage distribution of the sensing amplifier and the initial threshold voltage are used by S20 to calculate the physical drift.

[0047] To address the technical shortcomings of conventional pseudo-sensing units, which suffer from hysteresis, this embodiment activates a specific asymmetric canary decoupling network during the initialization phase. The SRAM cells in this network are intentionally designed with asymmetry in their physical layout, featuring thinner gate oxide layers or shorter channel lengths, thus exponentially amplifying their physical sensitivity to total ionization dose effects.

[0048] Record the front-end sensing benchmark of the network in S102. This front-end sensing reference This will be transmitted to S20 to ensure that a time difference warning signal can be captured and ambient temperature drift (PVT) noise is filtered out before the core in-memory computing logic unit actually experiences radiation failure. Simultaneously, during this initialization phase, the global threshold configuration package is synchronously loaded and solidified from the host computer. This global threshold configuration package Including the spatiotemporal fault propagation decision threshold Semantic lethal defense threshold Hysteresis state machine basic trigger threshold With lower limit recovery threshold The self-healing energy safety threshold that S60 will subsequently utilize. With respect to the chip's safe temperature threshold for preventing burn-out And the KV cache migration threshold that S50 will subsequently call. and And the device lifetime grading thresholds that will be called by S604 subsequently. and In this embodiment, the global threshold configuration package This will serve as the benchmark for judging subsequent state machine evolution and repair games.

[0049] S103: Semantic tag loading and cross-layer fault tolerance margin model construction.

[0050] Load the field semantic label table specific to the large model from the deployment configuration package generated by the host computer. and the corresponding set of basic field weights The basic weight set of this field Follow a strict order of physical destructive forces: .in, For the weight of the symbol field, The weights of the index field, The weight of the last digit segment.

[0051] At the same time, the underlying hardware agent is enabled, including activating the outlier counter and the attention memory access counter, to prepare a hardware-level sparsity monitoring interface for S30.

[0052] To quantify the robustness of the hardware-software co-process during the initialization phase, the on-chip radiation susceptibility topology matrix generated by S101 is invoked. For each logical data block mapped in the array Constructing a cross-layer fault tolerance margin index The corresponding mathematical expression is: in: The semantic labels for the specific fields mapped to this data block, such as the sign bit, exponent bit, etc. This represents the maximum allowable numerical drift limit for this specific semantic field in neural network quantization, i.e., the algorithm tolerance. This is the inherent vulnerability coefficient of the physical location of the data block, i.e., physical fragility. Sensitivity factor for large model network layers. Cross-layer fault tolerance margin index. This couples the process vulnerability in microelectronics manufacturing with the algorithm tolerance and semantic lethality in artificial intelligence. The smaller the value, the higher the risk level of the data block, indicating that it is in a dual high-risk state of being both physically extremely fragile and semantically absolutely fatal. The calculation result is solidified in this step and directly passed to step S40, serving as the initial decision threshold benchmark for the S50 state machine to trigger emergency resource remapping.

[0053] S104: Semantic binding structure and KV block index establishment.

[0054] To ensure accurate spatiotemporal tracing of large model logic data with SRAM physical storage units, this embodiment establishes two data tracing structures: Dynamic mapping table between data address and field semantics This is used to record the strong binding relationship between the underlying physical address and the semantics of higher-level fields. When S20 outputs the underlying physical error address... At that time, the table will support the S30 to accurately invert the logical semantics of the damaged bit, such as determining whether it is an exponent bit or a mantissa bit.

[0055] KV block temporal locality index table This is specifically designed for large model generation tasks, i.e., establishing block-level tracing of the historical context key-value cache in Decode. It records the partition number of each KV block in the array, which serves as the basis for subsequent S20 computational heat. And the absolute routing basis for S50 to perform consistent shadow write withdrawal.

[0056] S105: Multiphysics sensing environment interface activated.

[0057] To support cross-timescale state machine decision-making and burn-out Pareto constraints in S40, the on-chip power management IC and distributed thermistor array are woken up during the initialization phase, and the following environmental monitoring variable real-time acquisition interfaces are established: large model inference phase identifier interface. Used to obtain the current LLM workload in real time, either prefilled or decoded; system global remaining energy budget interface. On-chip global thermal mapping interface ,in, Indicates the global thermal distribution map Extract The local temperature value of the corresponding area.

[0058] S106: Unified definition and reset of the variable system for cross-temporal and spatiotemporal reliability assessment.

[0059] After completing the mapping and mounting of all underlying physical benchmarks and upper-level large model logic, register the full lifecycle operation monitoring variable system in the protected security register area and assign it absolute initial values: This indicates that the drift matrix of each physical partition will be dynamically updated in S20; This represents the error intensity matrix for each partition, which will be dynamically updated in S20; This indicates that the semantic attribution matrix of each partition field will be dynamically updated in S30; , representing the KV block heat statistics vector, will be dynamically updated in S20; This indicates that the cross-temporal and spatial fusion reliability index matrix of each partition will be dynamically updated in S40; , represents an independent indicator variable array for each partition state machine, defining the initial state of all storage blocks (Tile) as standard healthy.

[0060] S107: Triggering closed-loop monitoring of on-orbit operation.

[0061] Through the initialization of S101 to S106 above, the control bus releases the initialization lock signal, officially enters the running state, and continuously pumps real-time physical noise and running error event streams to the running state multi-source data acquisition in the subsequent step S20 without interrupting the normal storage and computing tasks.

[0062] S20: Multi-source data acquisition and feature quantization processing in runtime.

[0063] After completing the initialization and operational baseline establishment in S10, this embodiment enters the operational monitoring phase. During this phase, while performing SRAM in-memory computation tasks, multi-source operational status data is continuously collected to form the multi-dimensional monitoring information required for subsequent reliability assessment.

[0064] In this specific application, the data obtained from runtime monitoring mainly includes three types of information: SRAM array physical health status data, computational runtime verification information, and KV block access statistics. By uniformly collecting and processing the above multi-source data, runtime reliability assessment variables are generated, including physical drift. runtime error intensity and KV block heat index And simultaneously extract the error data address The operational reliability assessment variables will be used as strictly closed-loop input parameters. Among them: and The flow will proceed to the next step S30 to perform field semantic attribution analysis; and Steps S40 and S50 are used as the basis for multi-source reliability decisions and dynamic resource remapping. The specific execution logic is as follows: S201: SRAM array operation fingerprint generation and PVT decoupled quantization.

[0065] In this embodiment, in order to dynamically assess the true physical health status of the SRAM array under irradiation, radiation aging characteristics must be extracted from complex environmental noise. Unlike existing technologies that only collect static leakage current data, which is susceptible to temperature and voltage (PVT) interference, this embodiment introduces a differential decoupling acquisition mechanism.

[0066] The differential decoupling acquisition mechanism performs the following operations periodically during operation: Array monitoring collects electrical characteristic parameters of the SRAM array currently performing in-memory computing tasks, including the output voltage distribution of the sense amplifier and the threshold voltage drift characteristics of the memory cells; thus forming the original operational fingerprint vector. .

[0067] Synchronously collect the current state of the asymmetric canary network established in S102 in real time. And retrieve the front-end sensing reference stored in S102. Because the network possesses asymmetric sensitivity to the amplification of total ionizing dose, an asymmetric amplification scaling factor is introduced during layout design. For the original running fingerprint Perform precise decoupling of environmental noise (PVT) to generate the current purification operation fingerprint vector. The corresponding mathematical expression is: Current purification operation fingerprint vector By using the lead drift of the canary network to effectively replace the ambient noise, the hardware can achieve real-time purification without the need for complex nonlinear fitting circuits.

[0068] Retrieve the factory baseline fingerprint vector established in step S102 Using a tile as the granularity, the drift matrix of each physical partition on the chip is quantized by calculating the normalized Euclidean distance between the cleaned fingerprint and the reference fingerprint. The corresponding mathematical expression is: in: This represents the total number of units participating in fingerprint sampling within a single tile. (Drift matrix) The cumulative physical degradation of each array partition under irradiation is characterized in this step and is dynamically updated. It serves as the input variable for subsequent S40 multi-source reliability comprehensive decision-making, i.e., spatiotemporal fault propagation gradient prediction and physical self-healing determination.

[0069] Simultaneously, the physical drift of adjacent monitoring windows is extracted, and the long-term aging drift slope of each physical zone is calculated in real time. The corresponding mathematical expression is: in, This represents the time interval between adjacent monitoring windows.

[0070] Based on this, the matrix and slope It is dynamically updated in this step and flows into subsequent steps.

[0071] S202: Collection of runtime error statistics based on non-linear penalty.

[0072] During in-memory computation tasks, real-time verification of the computation results is performed to detect errors and accurately identify their severity. In one specific application of this embodiment, the verification process employs a checksum consistency verification mechanism, such as parity check codes or extended Hamming codes, to perform real-time verification of the in-memory computation results. Checksums are generated and stored concurrently when data is written to the SRAM array. During computation output, a new checksum is generated and compared with the original stored checksum for consistency.

[0073] When inconsistent calculation results are detected, two operations are performed: First: Record the physical address of the data where the error occurred. Simultaneously extract the erroneous polarity of the data reversal. For example, 0 flipped to 1 is recorded as +1, and 1 flipped to 0 is recorded as -1. The data will be directly transmitted to step S30 for extracting semantic tags, while It will be directly stored in the reliability log to support the targeted electrothermal de-trapping operation in the subsequent step S602.

[0074] Second: Update runtime error statistics. Unlike existing technologies that rely solely on linear bit error rate statistics, making it difficult to identify severe sudden faults caused by high-energy particles, this embodiment uses the following two key parameters for statistics: This indicates that within the current monitoring period, a specific physical partition is being monitored. The cumulative number of verification failures detected; Indicates that The number of consecutive verification failures within a given area. Based on this statistical parameter, calculate the regional runtime error intensity matrix independently per tile. The corresponding mathematical expression is: in: Basic error weights; and This represents the continuous error exponential penalty coefficient. Regional operational error intensity matrix. The innovation lies in the fact that when radiation induces isolated soft errors (SEUs), the error intensity increases linearly and gradually; however, when single-event multiple-batch flips (MBUs) or latch-up effects (SELs) occur, they lead to continuous errors. When increasing, This will amplify exponentially, thereby ensuring that task isolation and migration strategies can be triggered quickly and forcefully in subsequent S40 decisions. It is updated in this step and flows into step S30 to participate in semantic attribution weighting.

[0075] S203: Time decay-based KV block heat statistics collection.

[0076] To support the key-value cache (KV Cache) critical data protection mechanism in large model inference, this embodiment performs time-based access statistics on the KV cache data generated during model execution. This is based on the KV block index structure loaded in step S104. Block-level management is performed on the key-value data in the SRAM array. Because large-scale model inference exhibits significant temporal locality—that is, the probability of referencing older tokens gradually decreases—this embodiment abandons the traditional absolute accumulation counting method. In the current monitoring period... within, no. The actual number of accesses to each KV block is: An exponential moving average (EMA) time decay model is used to dynamically calculate and update the corresponding KV block heat index. The corresponding mathematical expression is: in: It is the heat attenuation factor; This represents the historical heat value from the previous monitoring period.

[0077] This popularity index, which incorporates a time-forgetting mechanism, is used for calculation. It can accurately reflect the actual access activity and importance of the data block at the current moment. Each KV block... This is continuously updated in this step and serves as the sorting criterion for prioritizing healthy Tile resources and triggering shadow write consistency migration during the resource remapping process in subsequent step S50.

[0078] S204: Multi-source monitoring data output.

[0079] Through the data acquisition and feature quantization processes from S201 to S203, this embodiment completes the unified acquisition of multi-source data from the underlying physical state to the upper-level algorithm logic, and updates and outputs the following key runtime variable system: the runtime error intensity output to S30. and error data address Physical drift amount output to S40 and long-term aging drift slope KV block heat index output to S40 and S50 The aforementioned key operational variables establish a closed loop from the generation end to the consumption end, providing quantitative data support for subsequent field semantic attribution, cross-timescale decision-making, and partition self-healing.

[0080] S30: Runtime field semantic attribution and nonlinear weighted analysis.

[0081] In this embodiment, after completing the multi-source operational data acquisition in S20, the operational error intensity within the current monitoring period has been obtained. and including Set of events for failed verification of the erroneous address Traditional in-memory computing systems' ECC (Electronic Code Correction) mechanisms often treat all bit flips indiscriminately, failing to perceive the actual destructive impact of erroneous data on upper-level large-scale model algorithms. To identify the culpability of error sources and significantly reduce redundant energy consumption in radiation-hardened systems, this step introduces a hardware-software co-attribution mechanism, jointly mapping the underlying physical bit plane mapping, activation sparsity, and attention context mechanisms to the algorithm's semantic dimension. The specific execution logic is as follows: S301: Error address resolution and dual localization using physical-semantic features.

[0082] When a discrete verification failure event is detected within the running window, extract the physical address of the data corresponding to each error. , Perform dual-location parsing: logical semantic location and physical topology location.

[0083] For logical semantic location, the data address and field semantic binding mapping structure established in S10 is invoked. The table lookup and parsing outputs the semantic type of the corresponding field. In the floating-point storage task of this embodiment, the output type enumeration includes a sign field, an exponent field, and a mantissa field.

[0084] For physical topology positioning, the field / bit plane slice access interface inside the in-memory array is called to... The process involves reverse mapping to the underlying physical geometry and topology to determine whether a damaged physical bit line belongs to a high-order data region. Based on this, a topology severity factor is output. For example, when a high-energy particle breaks through the physical bit plane containing the most significant bit (MSB), Assign the maximum value, otherwise assign the base value of 1.

[0085] S302: Dynamic weight mapping based on attention perception and sparsity masking.

[0086] After determining the semantic type of each erroneous data, the field weight set initialized in step S10 is used. Retrieving basic weight parameters Its original principle A strict hierarchy.

[0087] Unlike the static table lookup of existing technologies, this embodiment combines the inference characteristics of large models to construct a dynamic joint weight. The corresponding mathematical expression is: Two hardware-level mask variables were introduced: the activation sparsity mask and the... and attention context factors .

[0088] Targeting activation sparsity masks This is provided in real-time by the activation outlier / pruning agent count. If the data corresponding to the error address is multiplied by a zero activation value (such as one set to zero by the ReLU function) within the current MAC (multiply-accumulate) operation cycle, then... This mechanism implements low-level filtering of silent errors, preventing the system from overreacting.

[0089] Attention context factors The KV block heat index is continuously updated and transmitted from step S203. Mapping generation. Through a normalization function. The key-value (KV) popularity is mapped to the attention weight factor of the large model, and the specific calculation formula is as follows: In one embodiment, the normalization function may be adopted. or This is to ensure the absolute convergence of the weight mapping.

[0090] S303: Non-linear aggregation calculation of field semantic attribution values.

[0091] To comprehensively quantify the overall threat posed by all semantic errors to SRAM storage during the current runtime cycle, the runtime error intensity transmitted in step S20 will be... The error dynamic weights obtained in this step are then nonlinearly aggregated. This embodiment introduces a nonlinear sensitivity penalty factor. It is obtained by mapping the semantic type of the field, and the corresponding mathematical expression is: in: This is the preset base magnification factor; For field sensitivity mapping functions, in one embodiment, , , Based on this, this embodiment constructs a novel field semantic attribution value based on physical partitioning. The aggregation model, and its corresponding mathematical expression, is: in: This is a critical semantic indicator function that returns 1 if the error falls in a highly sensitive region (such as the most significant bit of the sign bit or the exponent bit Exp), and 0 otherwise. In one embodiment, the set of key semantic fields is... .

[0092] Field semantic attribution value The innovation and technical effectiveness of the aggregation model lie in its ability to achieve [the desired effect]. The zero-mask property can silently filter out a large number of invalid soft errors that have no impact on the final calculation result, greatly saving the overhead of dynamic capacity compensation; however, once an error breaks through the sparsity defense line and falls on a high attention weight ( The exponent term is located at the sign or exponent position of the highest (extremely high) exponent. It is activated instantaneously. This nonlinear expansion mechanism provides a quantitative basis for subsequent steps S40 to directly trigger emergency physical self-healing or consistent resource migration.

[0093] S304: Attribution Variable Output and Closed-Loop Transmission.

[0094] After completing the above calculations, the previously homogenized underlying hardware was successfully corrected and reported as faulty. After multiple filtering and weighting based on sparsity, attention heat, physical bit plane, and logical semantics, it is transformed into a field semantic attribution value with extremely high perceptual sensitivity of large model algorithms. The variable This step completes the closed-loop update and serves as the core output parameter, along with the physical drift amount flowing in from step S20. KV block heat index and runtime error strength The convergence of these sources serves as absolute input parameters, which are then passed to the multi-source reliability comprehensive decision-making process in subsequent step S40 to drive the hysteresis state machine to perform system-level scheduling under multi-objective constraints.

[0095] S40: Spatiotemporal multidimensional state machine decision-making based on large model stage perception and thermodynamic constraints.

[0096] After completing the preliminary multi-source data extraction and attribution in the operational state, this embodiment has already collected the absolute input variables, namely the physical drift amount, transmitted from S20 and S30 in the current monitoring cycle. KV block heat index and field semantic attribution values .

[0097] Unlike existing technologies that employ static, one-dimensional, and passive threshold scheduling that ignores the overall physical environment of the chip, this embodiment introduces large-model inference stage perception, spatiotemporal fault propagation prediction, and thermodynamic Pareto constraint mechanisms in S40, constructing a hysteretic state machine with active defense capabilities. The specific execution logic is as follows: S401: Introducing cross-timescale reliability fusion with large model stage awareness.

[0098] In real-world large language model inference, computing power and data sensitivity are not constant but dynamically alternate with each inference stage. The current large model inference stage identifier is obtained in real-time from the on-chip instruction scheduler. .

[0099] To break down the dimensional separation between long-term physical degradation (TID) and instantaneous algorithmic soft errors (SEE), a reliability index matrix spanning multiple time scales is constructed using physical memory blocks as the granularity. The corresponding mathematical expression is: in, This is the dynamic time-scale balance factor, and its specific values ​​are as follows: when The pre-filling stage is a computationally intensive task, highly susceptible to system failures due to underlying physical hardware deviations. Automatic adjustment is necessary. Value, assigning physical drift amount Greater decision-making weight; when During the decoding phase, which is a memory-intensive task, the time limit should be reduced. The value causes the decision focus to shift towards semantically incorrect key-value cached data. tilt.

[0100] This formula utilizes the natural logarithm. The semantic index term that surged in S30 was smoothly pulled back to the linear space, and the weights of the underlying soft and hard faults were combined with the upper-level large model. The timing workload binding enables dynamic hardware tolerance adjustment driven by algorithm load.

[0101] S402: Predictive over-level determination based on spatiotemporal fault gradient.

[0102] During high-energy particle-induced single-event latch-up (SEL), errors spread in a ripple-like pattern across the chip's physical layout. To achieve early fault interception, the drift slope passed in step S201 is invoked. Spatial distribution, calculations for specific physics Spatiotemporal fault propagation gradient The corresponding mathematical expression is: in, Characterizing the rate of time degradation, the latter term Characterize the Spatial diffusion gradient of physical damage with adjacent physical regions Indicates on the physical map and A set of adjacent tiles that share a boundary or are located within 1 Manhattan distance.

[0103] Real-time monitoring With the transient semantic peak of this partition If detected (This indicates that the fault is spreading at the physical level) or (This indicates that the core semantic defense line has been breached), ignoring the evolution flow of the conventional state machine, directly and predictively cutting off the power supply to that area in advance, and forcing the state machine to jump to a critical damage state. ).in, and All are configured by the threshold configuration package in S102. Unified loading and distribution.

[0104] S403: Smooth evolution of hysteresis state machine to eliminate ping-pong effect.

[0105] Within a normal cycle that does not trigger predictive cascading failures, the reliability index will be... The input is fed into a multi-level hysteresis state machine to independently determine the state variables of each physical partition. The corresponding mathematical expression is: Unlike existing technologies that use a single fixed threshold, which are prone to frequent false triggering, this embodiment employs a dual threshold mechanism, including an upper trigger threshold. and lower limit recovery threshold ,and The corresponding triggering logic is as follows: In response to the triggered degradation, the cross-layer fault tolerance margin initialized by S103 is invoked. And extract the minimum fault tolerance margin among all logical data blocks currently mapped to this tile. (i.e., following the weakest link effect), the basic threshold of the hysteresis state machine Dynamic modulation is performed to generate a unique trigger threshold for this physical tile; the corresponding mathematical expression is: Only when the previous cycle And currently hour, Talent leap to become .

[0106] For confirmed recovery, only when the status is... And after adaptive repair Only then was it permitted to restore to State. This mechanism utilizes tolerance banding to absorb sensor quantization noise, ensuring the stability of the underlying scheduling.

[0107] S404: Strategy matrix generation under multi-objective constraints of energy and thermodynamics.

[0108] Traversing the state variables of each physical partition It begins to generate a strategy matrix for multi-objective collaborative resource management. Given the extremely limited heat dissipation and energy conditions in aerospace or extremely enclosed environments, this step introduces a system residual energy budget. and on-chip global thermal distribution map (It is provided in real time by the on-chip power management IC and distributed thermistors) as a Pareto constraint: like Then, a "silent inspection strategy" is generated for the region, maintaining the current running mapping and using the computing power of idle periods for low-power background parity checking.

[0109] like Then, a "soft-level fault tolerance and remapping strategy" is generated for this region. At this time, the KV block heat index passed in step S20 is invoked. The remaining healthy tile resources in the array will be strictly distributed according to... The data is allocated in descending order of size to ensure the lossless operation of high-frequency key data.

[0110] like This triggers a physical repair game. When facing core damage requiring the initiation of step S60's partitioned micro-heating self-healing, a thermodynamic safety game must be played, including: Hardware self-healing access, specifically, if Sufficient, and the localized heat corresponding to the fault area. Below the safety critical temperature Then in Write hardware closed-loop thermal annealing self-healing instructions into it; Thermal runaway avoidance specifically involves rejecting heating requests to prevent chip burnout if the chip is already overheated or running out of energy, and instead... The KV consistency shadow write cross-region migration instruction is written into the system, and the core tasks and data are forcibly removed from the disaster area through pure software means, delaying physical self-healing until the thermal environment is safe.

[0111] S405: Decision-making closed loop and core variable output.

[0112] Thus far, step S40, through a computational chain involving stage-based perception fusion, gradient prediction, hysteresis evolution, and thermodynamic game theory, transforms the underlying multi-source monitoring data into absolutely secure hardware-software coordinated action commands. The state variables generated in this step... and resource management strategy matrix As the core control word, along with the KV block heat index with address tags... Together with the fault target region identifier, it is used as an unambiguous input parameter and passed in parallel to the subsequent KV consistency migration and task remapping steps S50 based on shadow write and the controlled partition progressive annealing self-healing step S60, thereby driving the subsequent execution units.

[0113] S50: Bit-plane decoupling mapping and asymmetric compression migration mechanism for large model features.

[0114] Upon receiving the state variable passed in step S40 Resource management strategy matrix Fault target area identification and KV block heat index Afterwards, if a judgment is made In a downgrade (i.e.) ) or critical damage (i.e. If the status is reached, the lossless remapping and critical data protection process will be triggered in step S50.

[0115] Unlike existing technologies that rely on discarding all bad blocks and performing lossless blind copying during system shutdown, this embodiment employs a bit-plane decoupling residual utilization and shadow write consistency migration mechanism tailored to the inference characteristics of large language models. The specific execution logic is as follows: S501: Fault-targeted locking and bit-plane decoupling residual utilization.

[0116] Parse the fault target region identifier passed in step S40 to locate the physical set of faults. And scan the remaining resources inside the array to establish a healthy candidate pool. .

[0117] Traditional in-memory computing arrays typically discard the entire array upon detecting a tile failure, leading to a precipitous drop in computing power. This embodiment, based on the topological characteristics of an in-memory computing physical array, introduces a bit-plane decoupling mapping mechanism: Retrieve the initial computation task mapping table established in step S10 Breaking away from traditional tile-level hard binding, for The internal computational logic involves physical decomposition of high and low bits. In the SRAM storage array, the large model weight matrix is ​​stored in a bit-slice structure, based on bit-plane indices. The mathematical expression for identifying data bit weights is: Modify the mapping rules to force Most significant bit (MSB) bit plane stripping, migration to an absolutely safe location The least significant bit (LSB) bit plane, which has extremely high fault tolerance, will be retained in the middle; Residual value calculation is performed in the process. This is the bit-plane boundary threshold used to distinguish between semantically sensitive MSBs and semantically insensitive LSBs.

[0118] Through the above decoupling operations across the physical and logical layers, a new version of the computing power task mapping table is generated and updated. This mechanism can prevent the generation of fatal semantic errors with almost no additional consumption of healthy physical resources, thereby achieving efficient utilization of hardware computing power.

[0119] S502: Attention-Sink driven asymmetric lossy emergency transfer.

[0120] During the parallel cycle of the computing power decoupling mapping, the data stored in... The historical context data (KV Cache) of large models directly threatened by physical failure is safely removed. To cope with the short migration time window during the radiation outbreak, this embodiment abandons the traditional full lossless copy and introduces an asymmetric lossy compression migration mechanism based on Attention-Sink.

[0121] Call the KV block heat index continuously updated from step S20. And combined with the threshold parameter loaded in step S102 ( The system dynamically tiers the KV data within the disaster area and generates corresponding transmission bus configuration commands, including: Core sedimentation area, i.e. If a key Attention-Sink (such as a sentence-initial token or core subject) is identified as a key inference feature of a large model, it is assigned the highest priority and a full-precision lossless shadow write migration channel is enabled.

[0122] Secondary context area, i.e. It was determined to be an intermediate state characteristic, and was transmitted via the on-chip bus to... When transmitting this type of data, the hardware truncation gate logic at the transmitting end is activated directly to perform hardware-level quantization truncation lossy migration (for example, truncate the mantissa from FP16 precision to INT8 precision during bus transmission).

[0123] The forgetting area, i.e. If a historical feature is deemed invalid, it will be silently discarded.

[0124] The aforementioned asymmetric data compression mechanism can reduce the bus transmission load under disaster conditions and greatly shorten the migration time of critical data.

[0125] S503: NoC congestion-aware cycle-stealing flow control and consistent atomic switching.

[0126] For critical data that triggered the migration mechanism in S502, to ensure zero downtime for large model inference tasks, a shadow write mode is enabled at the hardware routing layer. This means that while asynchronously copying data in the background, newly generated write requests from the model are doubly routed to the source address. and target health address .

[0127] To prevent shadow writes from instantly overloading the on-chip network (NoC) and causing a global deadlock, this embodiment uses a congestion-aware cycle-stealing flow control model and a consistency convergence determination formula, including: For cycle-stealing flow control, the backpressure performance counter of the on-chip network router is read in real time to obtain the current NoC congestion index. By constructing a dynamic Sigmoid decay function, the bus bandwidth injection rate of shadow writes can be controlled in real time. The calculation formula is as follows: in: Maximum allowed bus bandwidth; This is the critical threshold for bus safety congestion. This is the congestion sensitivity adjustment coefficient.

[0128] When NoC experiences severe congestion during the intensive memory access phase of large model decoding... It exhibits non-linear exponential contraction and automatically switches to a covert cycle-stealing mode, that is, it only uses the Stall intervals when the arithmetic unit is waiting for data to move data; when the bus is idle, it resumes full-speed migration.

[0129] To address consistency convergence and atomic switching, a data consistency convergence index is constructed during the parallel processing of background copying and shadow writing. The difference between the hardware read / write version numbers of the source and target ends is non-linearly evaluated using the exponential decay characteristic. The corresponding mathematical expression is: in: This represents the number of high-frequency KV blocks in the current migration batch. and The latest shadow write version numbers received at the source address and the destination address are respectively; This is the convergence sensitivity coefficient.

[0130] When the background copy catches up with the historical data differences, it makes hour, It strictly converges to the maximum value 1. At this moment, an atomic switch is triggered within a single clock cycle, switching all logical access pointers of the large model to the safe area, thus completely completing the migration of critical data.

[0131] S504: Variable update and physical self-healing handshake closed loop.

[0132] After the atomic switch is completed, the fault area The core computing tasks and critical data within the system have been completely cleared, achieving secure clearance of the physical space. The following closed-loop handshake operation will then be performed: Solidify and output the new version of the computing power task mapping table. and the latest KV block storage location mapping table ; Broadcast core status signal to the system's underlying hardware monitoring bus: Disaster area clearing complete. And at that instant, the hardware snapshot register is triggered, recording the specific faulty area. The current physical drift is locked at the single-unit baseline. This serves as the absolute time benchmark for subsequent S60 assessment of physical self-healing recovery rate.

[0133] At this point, the three absolute variables generated in step S50 will serve as unambiguous prerequisite unlocking conditions, directly passed to and triggering step S60 of the final partition progressive annealing self-healing. The signal output provides a safe physical range for S60 to perform high-energy-consuming and high-risk hardware-level thermal annealing repair without the risk of data loss.

[0134] S60: Multiphysics closed-loop self-healing and heterogeneous metamorphic reconstruction mechanism.

[0135] After completing the resource remapping and critical data migration in step S50, a deep, low-level physical self-healing operation is performed on the damaged SRAM array region in step S60. Unlike existing technologies that rely on blind global heating lacking safety control or the crude approach of permanently scrapping severely damaged devices, this embodiment employs a soft-hard cross-layer reconstruction mechanism that combines electrothermal synergy, waste heat parasitism, and the transformation of entropy sources sampled from a large model. The specific execution logic is as follows: S601: Hardware Interlock Confirmation and Thermodynamic Energy Dispatch.

[0136] Receive the physical set of faults from step S50 And the crucial signal that the disaster area has been cleared. .

[0137] To prevent thermal stress generated during the physical self-healing process from causing secondary damage to in-memory computing tasks, a hardware state interlock mechanism is introduced, which only locks the state when a fault is detected. Self-healing permissions are only granted when it is certain that the key KV data and computing power mapping of the large model in the area have been safely removed via shadow write.

[0138] Retrieve the current system's remaining energy budget The thermodynamic repair strategies were determined, including parasitic annealing and active electrothermal synergy.

[0139] For parasitic annealing, if (i.e., energy is critical), instead of using dedicated micro-heaters, the scheduler deliberately distributes high-density non-critical computing tasks (such as background matrix parity checking) densely to [the relevant area]. In the adjacent healthy area, the waste heat generated by the high-frequency switching of surrounding transistors is used to parasitically bake the damaged area, achieving annealing with zero additional energy consumption.

[0140] For active electrothermal synergy, if Then the on-chip microheater is activated for precise targeted annealing.

[0141] S602: Electrothermal Co-targeting Detrapping and Dummy Closed-Loop Control Based on Error Polarity.

[0142] To address the accumulation of trapped charge in the oxide layer caused by ionizing radiation, relying solely on heat release is extremely inefficient. This embodiment introduces an electrothermal synergistic stress recovery mechanism.

[0143] Before applying the thermal field, based on the fault area Internal historical operational error statistics, extracting the majority polarity characteristics of soft errors. It is the historical record within that tile. The majority statistical result (e.g., over 80% of errors in this region are represented by a 0 flipping to a 1). Based on this, a global reverse volume bias voltage is generated for the entire physical region, and the corresponding mathematical expression is: in, It is a symbolic function; This is the preset body bias recovery voltage amplitude. A bulk bias voltage is applied to the entire bottom well region, providing a uniform, strong electric field-directed traction force for the vast majority of charges trapped in the oxide layer, enabling them to rapidly and collaboratively detach at lower temperatures. During the annealing heating process, the leakage current of the dummy cells within this region is sampled at high frequency. Calculate its recovery gradient A dual-source annealing power closed-loop control model was constructed, and the corresponding mathematical expression is: in: The required annealing power for the base; The preset proportional gain coefficient; The waste heat equivalent of computing power is obtained by reading and... Dynamic computing load rate of adjacent healthy tiles The thermodynamic closed loop is estimated by multiplying the clock flip rate by the preset thermal resistance conversion coefficient, so that no additional high-precision temperature sensor is needed to achieve the thermodynamic closed loop. The recovery gradient is calculated by sampling the leakage current of the pseudo-sensing unit during the annealing heating process; For the global temperature burn-out safety indication function, when the current chip target area temperature is fed back by the on-chip global thermal distribution map interface established in step S105... Returns 1 if the condition is met, otherwise returns zero. This represents the annealing convergence limit threshold. The dual-source annealing power closed-loop control model utilizes a computational waste heat offsetting active heating energy reuse mechanism. Simultaneously, when the leakage current recovery gradient... Approaching the convergence limit At that time, active heating power It will automatically approach zero and cut off, thus preventing overheating and burnout.

[0144] S603: Post-healing physical fingerprint resampling and nonlinear lifetime (RUL) reassessment.

[0145] After thermal annealing, the array monitoring is triggered to re-acquire the electrical characteristics of the area and generate a post-healing fingerprint vector. Calculate the current post-healing physical drift. And retrieve the information from step S504 (issuing the signal that the disaster area has been cleared). (At the instant) the amount of fault drift before annealing locked by a hardware snapshot The physical self-healing recovery rate is calculated using the following formula. The combined physical self-healing recovery rate and the drift degradation slope of the unit's history. A nonlinear remaining useful life prediction model is established, and the corresponding mathematical expression is: in: The long-term drift slope average value, which is continuously calculated for step S201 and stored in the system reliability log, represents the historical aging and degradation rate of the unit. The physical breakdown limit threshold for SRAM cells; The recovery efficiency mapping function, used to represent the self-healing effect's correction to the remaining lifespan, can be implemented in one specific embodiment as follows: It should be noted that if the recovery rate is extremely low, it indicates that irreversible displacement damage has occurred. It will drop sharply.

[0146] S604: Heterogeneous metamorphosis and reconstruction and physical resource pool closed loop.

[0147] This embodiment breaks away from the existing technology where parts are scrapped if they cannot be repaired, based on the calculated... Value, pair Performing highly intelligent heterogeneous resource pool reorganization based on large-scale model algorithms, including: Returning to the healthy computing power pool, i.e. At this point, the device is in excellent physical condition, and its address is released back to the system. In this context, it is permitted to undertake the computation of the most significant bit (MSB) or the most popular key-value matrix for large models that are extremely sensitive. Degradation-tolerant computing pool, i.e. At this time, the device has a minor hidden defect, and it is classified as... It also shakes hands with the bit plane decoupling mapping mechanism in step S50, and will only be allowed to carry the least significant bit (LSB) mantissa calculation task of large models in the future. Physical true random entropy source metamorphosis pool, i.e. When a device is severely damaged and its threshold voltage is in a metastable state, its readout will exhibit extremely strong random physical oscillations between 0 and 1. This embodiment does not discard this behavior; instead, it modifies the hardware routing label and includes it in the large model physical entropy source pool. When the large model enters the Decode stage, these severely damaged SRAM arrays are directly used as Physical True Random Number Generators (TRNGs). Specifically, the metastability caused by the severely degraded thresholds of the damaged SRAM cells is used to perform high-frequency blind reads on the isolated array. The read-out physical oscillation bitstream is processed by on-chip lightweight XOR post-processing logic to eliminate bias, generating an absolutely random seed (entropy seed) conforming to a uniform distribution. This seed is directly fed into the LLM's Top-p / Top-k sampling module, providing natural cosmic radiation noise computing power for large model generation. This transforms the fatal physical damage to the underlying hardware into a usable entropy source for the top-level algorithm. In one embodiment, the system uses an exponential moving average (EMA) strategy to dynamically update the usable seed state of the physical entropy source pool to ensure the throughput of large model sampling.

[0148] After completing the above physical pooling and underlying mapping table ( After the update, the state variable in step S40 is updated via the interrupt controller. Forced reset to a healthy state ( ).

[0149] The technical effects of the multi-source decision-making and partitioned self-healing radiation-resistant SRAM storage method in this embodiment will now be explained based on simulation results.

[0150] Reference Figure 2 , Figure 2 The simulation effect comparison diagram provided for the embodiments of this application; in the figure: (a) is a comparison of the evolution of chip health under radiation environment; (b) is a comparison of the throughput of bit plane decoupling and pooling strategy.

[0151] like Figure 2 As shown in the figure, (a) illustrates the chip's normalized health under radiation conditions (i.e., 1- The evolution of the chip health under the monitoring window t in step S20 is compared. The blue curve with square markers represents the existing technology, i.e., the passive attenuation mechanism. With increasing radiation exposure time, the chip health exhibits a continuous decline due to cumulative damage caused by the total ionizing dose (TID) effect, and rapidly collapses after reaching the 0.4 failure threshold (dashed line). In contrast, the black solid line with triangle markers represents this embodiment, i.e., the multi-scale annealing self-healing mechanism, exhibiting a significant sawtooth-shaped recovery characteristic. This indicates that during the running multi-source data acquisition and feature quantization processing (S20), when the physical drift is monitored in real time... The deterioration caused the system state machine to transition to a critical damage state. In this embodiment, the multiphysics closed-loop self-healing and heterogeneous degradation reconstruction mechanism (S60) was successfully triggered. By applying controlled electrothermal synergistic targeted annealing, the trapped charge was successfully released, significantly improving the physical health of the transistor. Although the slope of subsequent drift degradation due to irreversible displacement damage gradually steepens with the increase of self-healing cycles (corresponding to the remaining lifetime reassessment in S603), this embodiment significantly extends the on-orbit operating lifetime of the chip above the failure threshold through multiple safe closed-loop self-healing operations.

[0152] like Figure 2As shown in Figure (b), the effective normalized throughput changes with the physical defect rate of the Tile array, deeply verifying the bit-plane decoupling and pooling strategy of this embodiment. The gray "×" dashed line represents the existing technology (fixed mapping collapse), whose throughput drops sharply and precipitously with increasing physical defect rate, indicating that it collapses completely once an error occurs, lacking the ability to dynamically schedule damaged resources. The black "○" dashed line represents the comparative scheme of this embodiment using only "redundancy exhaustion linear decline," where performance rapidly declines linearly after exhausting the first 15% of redundant resources. The black "◊" solid line represents the complete dynamic compensation scheme of this embodiment, which maintains good effective throughput even in the extremely high defect rate range. Specifically, the evolution of this curve corresponds to the heterogeneous resource pool closed-loop reorganization logic in step S604: in the low defect rate range of 0~15% (redundancy compensation region), devices in excellent condition are reassigned to... Near-lossless throughput was maintained through conventional remapping; in the higher defect rate range of 15-40% (bit plane degradation compensation region), the curve remained stable at a high level, which is because devices with slight dark defects were included in the degradation tolerance calculation pool. This triggers the bit-plane decoupling residual value utilization mechanism in S501. Only the highly sensitive most significant bit (MSB) is moved out, while the least significant bit (LSB), which has extremely high fault tolerance, remains in the fault tile for residual value calculation, achieving ultimate optimization of hardware computing power. In the extremely high defect rate range (metamorphosis zone) of greater than 40%, the curve shows a reasonable secondary decrease. This is because when the device is severely damaged and the threshold voltage is in a metastable state, it is no longer forced to perform multiply-accumulate calculations, but instead is allocated to the large model physical entropy source pool. This approach directly transforms severely damaged SRAM arrays into physical true random number generators (TRNGs), providing pure, natural cosmic radiation noise computing power (entropy seeds) for the Top-p / Top-k sampling modules of Large Language Models (LLMs). This heterogeneous transformation and reconstruction not only explains the logical decrease in throughput but also perfectly realizes the cross-boundary transformation of extremely damaged hardware into a usable entropy source for top-level algorithms, ensuring overall high availability under extremely harsh radiation environments.

[0153] In summary, this embodiment focuses on hardware-in-the-loop (HIL) operational sensing and multi-level verification closed-loop. By introducing physical fingerprint sensing and PVT decoupling mechanisms, it utilizes differential decoupling technology to eliminate temperature drift and power supply disturbances in real time, accurately extracting long-term physical fingerprints reflecting the true aging of the device. During the chip's actual task execution, this embodiment integrates multi-source evidence, including consistency of calculation results, transient current characteristics, and weighted readback, achieving decoupled judgment and independent characterization of transient soft errors (SEU / SET) and long-term physical damage (Aging / TID). Compared to traditional static testing (which cannot detect aging trends) and single logic verification (susceptible to analog noise interference), this embodiment significantly reduces the misjudgment rate caused by environmental noise, solving the problem of accurately quantifying the dual failure mechanisms of "storage" and "computing" in in-memory computing chips under complex radiation environments. Simultaneously, this embodiment creates a zoned micro-heating progressive self-healing and closed-loop termination mechanism, using an on-chip micro-heater array to anneal and repair damaged areas, and utilizing dummy leakage slope feedback to monitor thermal effects in real time, preventing overheating damage. This mechanism overcomes the limitations of traditional technologies that can only passively isolate or completely discard chips, endowing them with the ability to actively repair physical damage under extreme radiation environments. Combined with post-healing secondary drift assessment and RUL prediction, it achieves health pool management throughout the chip's entire lifecycle, significantly extending the chip's on-orbit lifespan. Furthermore, for large-scale model applications, this embodiment designs a KV consistency migration and shadow write management mechanism. Through background copying and shadow write operations, it ensures zero data loss and strong consistency of key-value cache (KV Cache) data during dynamic task migration, guaranteeing the continuity of long-sequence inference tasks. In addition, combined with dynamic capacity compensation and task degradation strategies, the system can automatically adjust computational precision, number system, or throughput when hardware degrades or resources are limited, achieving stable degradation and high availability under extreme environments, providing a robust hardware layer guarantee for high-reliability aerospace and nuclear industry tasks.

[0154] Reference Figure 3 , Figure 3 The diagram shows the structure of a radiation-resistant SRAM storage system with multi-source decision-making and partition self-healing provided in this application embodiment; in the diagram: 10, dynamic benchmark construction module; 20, multi-source data processing module; 30, field semantic analysis module; 40, multi-dimensional state decision-making module; 50, decoupled data migration module; 60, closed-loop self-healing reconstruction module.

[0155] like Figure 3 As shown, this embodiment also discloses a radiation-resistant SRAM memory system with multi-source decision-making and partition self-healing, which applies the multi-source decision-making and partition self-healing radiation-resistant SRAM memory method described above, including: The dynamic benchmark construction module 10 is used for cross-layer soft and hard benchmark archiving and pre-susceptibility topology initialization; a dynamic benchmark system with pre-prediction capability is constructed based on the dynamic benchmark construction module 10. The multi-source data processing module 20 is used for multi-source data acquisition and feature quantization processing in runtime. Based on the multi-source data processing module 20, multi-source monitoring data is output, which is used to characterize the physical health status of the SRAM array, calculate the runtime verification status, and KV block access statistics. The field semantic analysis module 30 is used for the steps of runtime field semantic attribution and nonlinear weighted analysis; based on the field semantic analysis module 30, the field semantic attribution value is output, which is used to quantify the overall threat of all semantic errors to SRAM computing in the current runtime cycle; The multi-dimensional state decision module 40 is used to make spatiotemporal multi-dimensional state machine decisions based on large model stage perception and thermodynamic constraints. Based on the multi-dimensional state decision module 40, combined with multi-source monitoring data and field semantic attribution values, at least the state variables used to characterize the health status of the SRAM array and the strategy matrix used to characterize the software and hardware cooperative action instructions are output. The decoupled data migration module 50 is used for bit-plane decoupling mapping and asymmetric compression migration for large model features; atomic switching is performed based on the decoupled data migration module 50 to complete the data migration. The closed-loop self-healing reconfiguration module 60 is used for multi-physics closed-loop self-healing and heterogeneous transformation reconfiguration; based on the closed-loop self-healing reconfiguration module 60, the SRAM array is partitioned for self-healing and the device functions are reconfigured.

[0156] It should be noted that the multi-source decision-making and partition self-healing radiation-resistant SRAM memory system of this embodiment corresponds to the aforementioned multi-source decision-making and partition self-healing radiation-resistant SRAM memory method. Therefore, any content not specifically described in the multi-source decision-making and partition self-healing radiation-resistant SRAM memory system of this embodiment, including but not limited to functional definitions, working principles, and technical effects, can be referred to the description in the aforementioned multi-source decision-making and partition self-healing radiation-resistant SRAM memory method, and will not be repeated here.

[0157] In the embodiments provided in this application, it should be understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, code, or any suitable combination thereof. For hardware implementation, the processor may be implemented in one or more of the following: application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, other electronic units designed to implement the functions described herein, or combinations thereof. For software implementation, some or all of the processes of the embodiments may be performed by a computer program instructing the associated hardware. During implementation, the program may be stored in a computer-readable storage medium or transmitted as one or more instructions or code on a computer-readable storage medium. Computer-readable storage media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of a computer program from one place to another. Storage media may be any available medium accessible to a computer. Computer-readable storage media may include, but are not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code having the form of instructions or data structures and accessible to a computer.

[0158] Finally, it should be noted that the above description is only a preferred embodiment of this application and is not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A multi-source decision and partition self-healing anti-radiation SRAM computing method, characterized in that, include: S10: Cross-layer benchmark establishment and pre-susceptibility topology initialization, including: generating an on-chip radiation susceptibility topology matrix that labels the physical coordinates of the SRAM array’s inherently weak radiation resistance; constructing a cross-layer fault tolerance margin model that couples process vulnerability, algorithm tolerance, and semantic lethality; and building a dynamic benchmark system with pre-prediction capabilities based on S10. S20: Multi-source data acquisition and feature quantization processing in operation mode, including: performing PVT decoupling quantization on the SRAM array operation fingerprint to generate multi-source monitoring data that includes at least a drift matrix characterizing cumulative physical degradation and a long-term aging drift slope; outputting multi-source monitoring data based on S20, which is used to characterize the physical health status of the SRAM array, calculate the operation verification status, and KV Cache access statistics; S30: Runtime field semantic attribution and nonlinear weighted analysis, including: physical-semantic dual localization of error addresses, construction of dynamic joint weights by combining activation sparsity mask and attention context factor, and completion of nonlinear aggregation calculation of field semantic attribution value; output field semantic attribution value based on S30, which is used to quantify the overall threat of all semantic errors to SRAM storage in the current runtime cycle; S40: Spatiotemporal multidimensional state machine decision-making based on large model stage perception and thermodynamic constraints, including: introducing cross-timescale reliability fusion of large model inference stage perception, generating a policy matrix under energy and thermodynamic multi-objective constraints, and completing the decision-making closed loop and core variable output; based on S40, combined with multi-source monitoring data and field semantic attribution values, at least outputting state variables to characterize the health status of the SRAM array and a policy matrix to characterize software and hardware cooperative action instructions; S50: Bit-plane decoupling mapping and asymmetric compression migration for large model features, including: utilization of bit-plane decoupling residuals, asymmetric compression migration driven by attention sedimentation and NoC congestion-aware cycle-stealing flow control mechanism; atomic switching based on S50 to complete data migration; S60: Multiphysics closed-loop self-healing and heterogeneous transformation reconstruction, including: electrothermal coordinated targeted de-trapping based on applying reverse body bias voltage with incorrect polarity, heating using a dual-source annealing power closed-loop control model, and functional reconstruction based on the results of nonlinear lifetime re-estimation after heating; partitioned self-healing of SRAM array based on S60, and reconstruction of device functions.

2. The multi-source decision and partition self-healing radiation-hardened SRAM-in- compute method of claim 1, wherein, The steps for establishing the soft and hard cross-layer benchmark and initializing the pre-susceptibility topology are as follows: S101: In-memory array hierarchical structure and radiation susceptibility topology documentation; Based on S101, an on-chip radiation susceptibility topology matrix is ​​generated and stored, which marks the physical coordinates of the SRAM array that are inherently weak in radiation resistance. S102: Initialization of the hybrid baseline fingerprint and asymmetric canary decoupling network; Based on S102: Generate a health baseline fingerprint vector; Activate the asymmetric canary decoupling network to exponentially amplify the physical sensitivity to the total ionization dose effect, and record the pre-sensing baseline of the asymmetric canary decoupling network; Load and solidify the global threshold configuration package for the decision of the evolution and repair game. S103: Semantic tag loading and cross-layer fault tolerance margin model construction; based on S103, a cross-layer fault tolerance margin index is constructed for coupling process vulnerability, algorithm tolerance, and semantic fatalness The corresponding mathematical expression is: in: To map to data blocks Specific field semantic tags; This represents the maximum allowable numerical drift limit for the semantic label of this specific field in neural network quantization; For data blocks The innate susceptibility coefficient of physical location; For large model network layer sensitivity factors; S104: Semantic binding structure and KV Cache index establishment; Spatiotemporal tracing between large model logical data and SRAM array is completed based on S104; S105: Multiphysics environment sensing interface activated; Real-time acquisition of environmental monitoring variables is completed based on S105; S106: Unified definition and reset of the cross-temporal and spatiotemporal reliability assessment variable system; S107: Triggering closed-loop monitoring of on-orbit operation.

3. The radiation-resistant SRAM storage method with multi-source decision-making and partitioned self-healing as described in claim 1, characterized in that, The steps for the operational multi-source data acquisition and feature quantization processing are as follows: S201: SRAM array operation fingerprint generation and PVT decoupling quantization; based on the S201 output, the drift matrix characterizes the cumulative physical degradation of each SRAM array partition under irradiation and the long-term aging drift slope of each SRAM array partition. S202: Statistical collection of runtime errors based on nonlinear penalty; Based on S202, when it is determined that the calculation result does not meet the preset consistency requirements, the physical address of the data where the error occurred is recorded and the statistical information of the runtime error is updated; wherein, the statistical information includes the data for a storage block within the current monitoring period. Total number of detected verification failures and in the storage block Number of consecutive check failures Based on this statistical information, the regional operational error intensity matrix is ​​obtained. The corresponding mathematical expression is: wherein: is a base error weight; and is a continuous error exponent penalty coefficient; S203: Time decay-based KV Cache hotness statistics collection; based on S203, dynamically calculate and update the corresponding hotness index of KV Cache The corresponding mathematical expression is: wherein: is the actual access count of the th KV Cache; is the hotness decay factor; is the historical hotness value of the last monitoring period; S204: Multi-source monitoring data output; Based on S204, multi-source monitoring data is output, which includes operational error intensity, error data address, physical drift amount, long-term aging drift slope, and heat index.

4. The multi-source decision and partition self-healing radiation-hardened SRAM computing method of claim 1, wherein, The steps of the semantic attribution and nonlinear weighted analysis of the running-state fields are as follows: S301: Error address resolution and dual location based on physical-semantic features; based on S301, the semantic type of the field is output for semantic location, and the topology severity factor is output for physical location. S302: Dynamic weight mapping based on attention perception and sparsity mask; Based on S302, dynamic joint weights are constructed by combining preset basic weight parameters, activation sparsity mask, attention context factor and topological severity factor. S303: Nonlinear aggregation calculation of field semantic attribution value; based on S303, output the quantification of the overall threat of all semantic errors to the storage and computing block in the current running period of the field semantic attribution value The corresponding mathematical expression is: in: For storage blocks runtime error conditions; Indicates dynamic joint weights; This is a non-linear sensitivity penalty factor determined based on field sensitivity. For key semantic indicator functions, when an error occurs... Returns 1 if the value falls within a preset highly sensitive region, otherwise returns 0. This is a pre-defined set of key semantic fields; S304: Attribution variable output and closed-loop transfer; data transfer based on S304.

5. The multi-source decision and partition self-healing radiation-hardened SRAM-in- compute method of claim 1, wherein, The steps for spatiotemporal multidimensional state machine decision-making based on large model stage perception and thermodynamic constraints are as follows: S401: Introduce cross-time scale reliability fusion perceived in the large model stage; based on S401, build a storage and calculation block At the moment of the reliability index matrix The corresponding mathematical expression is: in, The dynamic timescale balance factor is determined based on the current large model inference phase. In order to be in storage blocks at time The physical drift amount obtained based on multi-source monitoring data, In order to be in storage blocks at time The semantic attribution value of the field; S402: Predictive over-level determination based on spatiotemporal fault gradient; Based on S402, calculate the calculation for the stored-block... Spatiotemporal fault propagation gradient The corresponding mathematical expression is: in: For storage blocks The long-term aging drift slope, obtained from multi-source monitoring data, is used to characterize the performance of the memory block. The deterioration of time, the latter item Characterizing this storage block Spatial diffusion gradient of physical damage with adjacent physical regions Indicates on the physical map and A set of adjacent storage blocks that share a boundary or are located within a Manhattan distance of 1; early interception of faults based on spatiotemporal fault propagation gradients; S403: Smooth evolution of the hysteresis state machine to eliminate the ping-pong effect; based on S403, a preset dual-threshold mechanism is implemented for the storage block. The determination of the state variable is expressed by the following mathematical expression: in, correspond ; S404: Strategy matrix generation under multi-objective constraints of energy and thermodynamics; Based on S404 and combined with S403, corresponding preset strategy matrices are generated for different state variables; S405: Decision-making closed loop and core variable output; Based on S405, combined with S401 to S404, through the computational link of stage perception fusion, gradient prediction, hysteresis evolution and thermodynamic game, the underlying multi-source monitoring data is transformed into software and hardware collaborative action instructions.

6. The multi-source decision and partition self-healing radiation-hardened SRAM-in- compute method of claim 1, wherein, The steps of bit-plane decoupling mapping and asymmetric compression transfer for large model features are as follows: S501: Fault-targeted locking and bit-plane decoupling residual utilization; Based on S501, complete the decoupling operation across physical and logical layers, and generate and update the new version of the computing power task mapping table; S502: Attention-delayed asymmetric lossy emergency migration; Based on S502, combined with the preset KV cache migration threshold and the asymmetric lossy compression migration mechanism based on attention accumulation, the KV data in the disaster area is dynamically divided into echelons, and corresponding transmission bus configuration instructions are generated. S503: NoC congestion-aware cycle-stealing flow control and consistent atomic switching; Based on S503, using a preset congestion-aware cycle-stealing flow control model and consistency convergence determination formula, while asynchronously copying data in the background, newly generated write requests are dual-routed to the source address and the target healthy address. Specifically: based on the difference between the real-time acquired on-chip network congestion index and the preset safety threshold, the bus bandwidth injection rate of the dual-route is dynamically adjusted in a non-linear decay manner to perform cycle-stealing flow control; a data consistency convergence index is constructed based on the difference in write version numbers received at the source address and the target address, and an atomic switch is triggered when the version number difference approaches zero and the convergence index meets the preset conditions. S504: Variable update and physical self-healing handshake closed loop; Based on S504, solidify and output the new version of the computing power task mapping table and the latest KV Cache storage location mapping table, broadcast the disaster area clearing completion signal to the underlying hardware monitoring bus, and trigger hardware snapshot to obtain the current physical drift amount of the fault area.

7. The multi-source decision and partition self-healing radiation-hardened SRAM-in- compute method of claim 1, wherein, The steps of the multiphysics closed-loop self-healing and heterogeneous metamorphic reconstruction are as follows: S601: Hardware interlock confirmation and thermodynamic energy scheduling; Based on S601 and combined with the remaining energy budget at the current moment, determine the thermodynamic repair strategy, including parasitic annealing and active electrothermal synergy. S602: Electrothermal Co-targeting De-trapping and Dummy Closed-Loop Control Based on Error Polarity; Based on S602, the majority polarity characteristics of historical operational errors in the fault region of the SRAM array are extracted, and the bias polarity is dynamically determined in a way that shows the opposite pull to the majority polarity characteristics. Combined with the preset recovery voltage amplitude, the bias is directed towards the fault region. A global reverse body bias voltage is applied to the bottom well region as a whole; and during the annealing heating process, based on the pre-constructed dual-source annealing power closed-loop control model, the energy reuse of active heating is achieved by offsetting the waste heat of computing power. S603: Post-healing physical fingerprint resampling and nonlinear lifetime re-estimation; Based on S603, after thermal annealing, nonlinear lifetime re-estimation is performed using physical self-healing recovery rate, long-term aging drift slope, physical breakdown limit threshold and post-healing physical drift amount; Among them, physical self-healing recovery rate is determined based on post-healing physical drift amount and pre-healing physical drift amount. S604: Heterogeneous metamorphic reconstruction and physical resource pool closed loop; Based on S604, combined with the nonlinear lifetime re-estimation results obtained from S603, the device function is reconstructed.

8. The radiation-resistant SRAM storage method with multi-source decision-making and partitioned self-healing as described in claim 7, characterized in that, The mathematical expression corresponding to the dual-source annealing power closed-loop control model is: in: The required annealing power for the base; The preset proportional gain coefficient; The waste heat equivalent of computing power is obtained by reading the data from the fault area. Dynamic computing load rate of adjacent healthy storage blocks It is estimated by multiplying the clock toggle rate by a preset thermal resistance conversion factor; The recovery gradient is calculated by sampling the leakage current of the pseudo-sensing unit during the annealing heating process; This is a global temperature-based burn-out safety indication function, used when the current target area temperature of the chip... Less than the preset safe temperature threshold for chip burnout Returns 1 if the condition is met, otherwise returns zero. This is the preset annealing convergence limit threshold.

9. The multi-source decision and partition self-healing radiation-hardened SRAM-in- compute method of claim 7, wherein, The reconfiguration of device functions specifically includes: When the result of nonlinear lifetime re-estimation is greater than or equal to the preset upper limit of device lifetime classification threshold, the device is allowed to undertake the calculation task of the most significant bit or high-heat KV matrix again. When the result of nonlinear lifetime re-estimation is greater than or equal to the preset lower limit of device lifetime classification threshold and less than the upper limit of device lifetime classification threshold, the device function is reconfigured to only be allowed to carry the least significant bit mantissa calculation task. When the result of the nonlinear lifetime re-estimation is less than the lower limit of the device lifetime grading threshold, the device function is reconfigured by changing the hardware routing label so that the device can generate an absolutely random seed that conforms to a uniform distribution.

10. A radiation-resistant SRAM storage system with multi-source decision-making and partition self-healing, employing the radiation-resistant SRAM storage method with multi-source decision-making and partition self-healing as described in any one of claims 1 to 9, characterized in that, include: The dynamic benchmark construction module is used for cross-layer benchmark archiving and pre-susceptibility topology initialization; Based on this dynamic benchmark construction module, a dynamic benchmark system with forward prediction capabilities is constructed. The multi-source data processing module is used for runtime multi-source data acquisition and feature quantization processing; Based on the multi-source data processing module, multi-source monitoring data is output, which is used to characterize the physical health status of the SRAM array, the calculation operation verification status, and the KV Cache access statistics. The field semantic analysis module is used for the steps of runtime field semantic attribution and nonlinear weighted analysis. Based on the semantic analysis module of this field, the semantic attribution value of the field is output. This semantic attribution value is used to quantify the overall threat of all semantic errors to SRAM computing in the current running cycle. A multi-dimensional state decision module is used to make spatiotemporal multi-dimensional state machine decisions based on large model stage perception and thermodynamic constraints. Based on this multi-dimensional state decision module, combined with multi-source monitoring data and field semantic attribution values, at least the state variables used to characterize the health status of the SRAM array and the policy matrix used to characterize the software and hardware cooperative action instructions are output. The decoupled data migration module is used for bit-plane decoupling mapping and asymmetric compression migration steps for large model features; atomic switching is performed based on this decoupled data migration module to complete the data migration. A closed-loop self-healing reconstruction module is used for multi-physics closed-loop self-healing and heterogeneous transformation reconstruction. Based on this closed-loop self-healing reconfiguration module, the SRAM array is partitioned for self-healing, and the device functions are reconfigured.

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