Quantum bit global feedback control system and method

Abstract

This invention provides a global feedback control system and method for qubits, applicable to the field of quantum computing measurement and control. The global feedback control system for qubits includes: multiple measurement and control chassis, each chassis including a readout module and a control module; a feedback module configured to receive state information of first qubits sent by the readout modules of each measurement and control chassis, perform correlation mapping processing on the state information of multiple first qubits based on preset feedback configuration information, generate feedback strategies for second qubits measured and controlled by each measurement and control chassis, and distribute each feedback strategy to the readout module of the corresponding measurement and control chassis; the readout module is further configured to receive feedback strategies sent by the feedback modules and forward the feedback strategies to the corresponding control module within the same measurement and control chassis, so that the control module generates a control waveform matching the feedback strategy.

Description

Technical Field

[0001] This invention relates to the field of quantum computing measurement and control, and specifically to a global feedback control system and method for qubits. Background Technology

[0002] With the development of quantum computing technology, qubit feedback control has become a core technology for improving the efficiency of quantum computing experiments and supporting the experimental architecture of quantum error correction. In related technologies, qubit feedback typically employs a one-to-one connection method, achieving fundamental correction of the qubit state by responding to and controlling its state.

[0003] In the process of realizing the concept of this invention, it was found that the related technologies have at least the following problems: the one-to-one connection method lacks global collaborative scheduling capability, making it difficult to adapt to complex collaborative control scenarios with multiple qubits and multiple measurement and control chassis, resulting in insufficient flexibility and accuracy of feedback control, and making it difficult to meet the needs of high-performance quantum computing experiments. Summary of the Invention

[0004] In view of the above problems, the present invention provides a global feedback control system and method for qubits.

[0005] According to a first aspect of the present invention, a global feedback control system for qubits is provided, comprising: a plurality of measurement and control chassis, each of the measurement and control chassis including a readout module and a control module, wherein the readout module is configured to acquire state information of a first qubit, and the control module is configured to output a control waveform to a second qubit to change the state of the second qubit; a feedback module is configured to receive the state information of the first qubit sent by the readout module of each of the measurement and control chassis, perform correlation mapping processing on the state information of the plurality of first qubits based on preset feedback configuration information, generate a feedback strategy for the second qubit measured and controlled by each of the measurement and control chassis, and distribute each of the feedback strategies to the readout module of the corresponding measurement and control chassis; the readout module is further configured to receive the feedback strategy sent by the feedback module and forward the feedback strategy to the corresponding control module within the same measurement and control chassis, so that the control module generates a control waveform matching the feedback strategy.

[0006] According to an embodiment of the present invention, the feedback module includes: an instruction control unit configured to parse a preset instruction set and issue corresponding control instructions to the feedback execution unit; the feedback execution unit configured to, in response to the received control instructions, perform association mapping processing on the state information of multiple first qubits according to the mapping rules in the preset feedback configuration information; wherein the mapping rules include: a one-to-one mapping rule for determining the feedback strategy for a single second qubit based on the state information of a single first qubit, a multiple-to-one mapping rule for jointly determining the feedback strategy for a single second qubit based on the state information of multiple first qubits, a one-to-many mapping rule for jointly determining the feedback strategy for multiple second qubits based on the state information of a single first qubit, and a multiple-to-many mapping rule for jointly determining the feedback strategy for multiple second qubits based on the state information of multiple first qubits.

[0007] According to an embodiment of the present invention, when the mapping rule is the many-to-one mapping rule or the many-to-many mapping rule, the feedback execution unit is further configured to: respond to the control instruction, call and execute the preset strategy generation algorithm according to the preset feedback configuration information, perform joint operation on the received state information of the multiple first qubits, and generate a feedback strategy for the second qubit based on the operation result.

[0008] According to an embodiment of the present invention, the above-mentioned instruction control unit is further configured to: acquire preset feedback configuration information and preset number of cycles corresponding to the target loop body; execute the target loop body based on the preset number of cycles to control the feedback execution unit to repeatedly execute the following operations, and update the current loop count value after each execution until the current loop count value reaches the preset number of cycles; perform association mapping processing on the received state information of the multiple first qubits based on the preset feedback configuration information to generate feedback strategies corresponding to the second qubits measured and controlled by each of the above-mentioned measurement and control boxes, and output the generated multiple feedback strategies.

[0009] According to an embodiment of the present invention, the feedback module further includes a communication control unit and a block random access memory; the communication control unit is configured to receive the preset instruction set and multiple different preset feedback configuration information issued by the host computer, and forward them to the instruction control unit; the instruction control unit is further configured to: store the received multiple different preset feedback configuration information in corresponding independent storage areas of the block random access memory; parse the preset instruction set to determine a target configuration identifier, and read the corresponding preset feedback configuration information from the block random access memory according to the target configuration identifier, and provide it to the feedback execution unit.

[0010] According to an embodiment of the present invention, the feedback module further includes: an identifier register configured to assign a corresponding state identifier bit to each of the second qubits, wherein the state identifier bit is a first state indicating that the feedback strategy for the corresponding second qubit has been generated, or a second state indicating that the feedback strategy for the corresponding second qubit has not been generated; the feedback execution unit is further configured to: in response to generating a feedback strategy for a single second qubit, update the state identifier bit in the identifier register corresponding to the second qubit from the second state to the first state.

[0011] According to an embodiment of the present invention, the instruction control unit is further configured to: read the state flag bits corresponding to each of the second qubits in the flag register, and monitor the total duration of generating multiple feedback strategies based on the clock cycle; in response to the multiple state flag bits being in the first state, or the total duration reaching a preset duration, issue an output instruction to the feedback execution unit so that the feedback execution unit outputs the multiple feedback strategies generated.

[0012] According to an embodiment of the present invention, the above-mentioned feedback execution unit is further configured to: in response to an identifier reset instruction issued by the above-mentioned instruction control unit, reset the state identifier bit corresponding to each of the above-mentioned second qubits in the above-mentioned identifier register from the above-mentioned first state to the above-mentioned second state; wherein, the above-mentioned identifier reset instruction is issued by the above-mentioned instruction control unit before each round of execution.

[0013] According to an embodiment of the present invention, the feedback module further includes: an information input unit configured to receive and aggregate the state information of the plurality of first qubits according to the hardware connection order of each of the above-mentioned readout modules; and an information output unit configured to distribute the feedback strategy generated by the association mapping process to the corresponding readout module based on the hardware output order of the control and measurement chassis to which each of the above-mentioned second qubits belongs.

[0014] A second aspect of the present invention provides a global feedback control method for qubits, comprising: acquiring state information of multiple first qubits through multiple readout modules distributed in different measurement and control chassis, and sending the state information to a feedback module; performing association mapping processing on the multiple state information based on preset feedback configuration information through the feedback module to generate a feedback strategy for the second qubits measured and controlled by each of the measurement and control chassis, and distributing the generated feedback strategies to the readout modules of the corresponding measurement and control chassis; forwarding the received feedback strategies to a control module within the same measurement and control chassis through each of the readout modules; and generating a corresponding control waveform according to the received feedback strategy through each of the control modules, and outputting the control waveform to the corresponding second qubit.

[0015] According to an embodiment of the present invention, through the coordinated operation of multiple measurement and control chassis, each chassis includes a readout module and a control module. The readout module can accurately acquire the state information of the first qubit, while the control module is responsible for outputting a control waveform to the second qubit, thereby changing its state. Based on this, a feedback module, acting as a core hub, receives the first qubit state information from the readout modules of each measurement and control chassis, performs correlation mapping processing on this state information according to preset feedback configuration information, generates feedback strategies for the second qubit measured and controlled by each measurement and control chassis, and accurately distributes these strategies to the readout modules of the corresponding measurement and control chassis. The readout module further receives the feedback strategies and forwards them to the control module within the same measurement and control chassis, enabling the control module to generate a control waveform matching the feedback strategy, achieving efficient and precise control of the qubit state, and improving the stability and accuracy of the quantum computing system. Attached Figure Description

[0016] The above-mentioned contents, as well as other objects, features and advantages of the present invention, will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings.

[0017] Figure 1 A schematic diagram of a global feedback control system for qubits according to an embodiment of the present invention is shown.

[0018] Figure 2 A flowchart illustrating the cyclic feedback process of a global feedback control system for qubits according to an embodiment of the present invention is shown.

[0019] Figure 3 A schematic diagram of module interaction of a global feedback control system for qubits according to an embodiment of the present invention is shown.

[0020] Figure 4 A flowchart illustrating the feedback output of a global feedback control system for qubits according to an embodiment of the present invention is shown.

[0021] Figure 5 A schematic diagram of the global interaction of a quantum bit global feedback control system according to an embodiment of the present invention is shown.

[0022] Figure 6 A flowchart of a global feedback control method for qubits according to an embodiment of the present invention is shown. Detailed Implementation

[0023] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0026] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0027] In the technical solution of this invention, the data involved (including but not limited to data used for analysis, data stored, data displayed, etc.) are all information and data authorized by the user or fully authorized by all parties. The collection, storage, use, processing, transmission, provision, disclosure and application of related data all comply with relevant laws, regulations and standards, necessary confidentiality measures have been taken, and they do not violate public order and good morals. Corresponding operation entry points are provided for users to choose to authorize or refuse.

[0028] In quantum computing experiments, feedback control scenarios can be categorized into local feedback and global feedback based on the scale of the qubit readout modules involved. The most common example, measurement-based active qubit initialization, falls under the category of local feedback. It determines whether to perform a specific feedback operation on a qubit based on its measurement state. Global feedback, on the other hand, involves information exchange between multiple readout modules. After comprehensively analyzing and processing all readout results, it achieves individual control of multiple modules.

[0029] In related technologies, electronic feedback systems can control arbitrary waveform generators to output different feedback waveforms based on the state of qubits, and have been successfully demonstrated in active qubit initialization experiments. In addition, there is a feedback electronics system based on radio frequency switches, which achieves different feedback waveform outputs by controlling the on / off state of the radio frequency switches.

[0030] However, the aforementioned feedback methods all connect the qubit readout system and the control system via cables or traces on a printed circuit board (PCB). This means the state of the qubit resolved by the readout system can only be transmitted to a specific control system. This fixed hardware structure significantly reduces the flexibility of this feedback method, making it unsuitable for feedback control between arbitrary qubits. In particular, existing quantum computing measurement and control systems are mostly presented in a chassis form, with the readout module and control module connected by internal wiring within a single chassis. If the readout module and control module for a single qubit are distributed across different chassis, the aforementioned localized feedback experiment will also be impossible.

[0031] Furthermore, quantum error correction is the cornerstone of realizing universal quantum computing. It requires continuously collecting the state of all qubits during quantum experiments, decoding and analyzing it, and then dynamically adjusting subsequent quantum gate operations. This also requires a global feedback loop for quantum computing.

[0032] In view of this, embodiments of the present invention provide a global feedback control system for qubits. The system includes: multiple measurement and control cabinets, each including a readout module and a control module. The readout module is configured to acquire the state information of a first qubit, and the control module is configured to output a control waveform to a second qubit to change the state of the second qubit. A feedback module is configured to receive the state information of the first qubit sent by the readout modules of each measurement and control cabinet, perform correlation mapping processing on the state information of multiple first qubits based on preset feedback configuration information, generate a feedback strategy for the second qubit measured and controlled by each measurement and control cabinet, and distribute each feedback strategy to the readout module of the corresponding measurement and control cabinet. The readout module is further configured to receive the feedback strategy sent by the feedback module and forward the feedback strategy to the corresponding control module within the same measurement and control cabinet, so that the control module generates a control waveform that matches the feedback strategy.

[0033] Figure 1 A schematic diagram of a global feedback control system for qubits according to an embodiment of the present invention is shown.

[0034] According to an embodiment of the present invention, a global feedback control system for qubits includes: multiple measurement and control chassis, each measurement and control chassis including a readout module and a control module, wherein the readout module is configured to acquire the state information of a first qubit, and the control module is configured to output a control waveform to a second qubit to change the state of the second qubit; a feedback module is configured to receive the state information of the first qubit sent by the readout module of each measurement and control chassis, perform correlation mapping processing on the state information of multiple first qubits based on preset feedback configuration information, generate a feedback strategy for the second qubit measured and controlled by each measurement and control chassis, and distribute each feedback strategy to the readout module of the corresponding measurement and control chassis; the readout module is further configured to receive the feedback strategy sent by the feedback module and forward the feedback strategy to the corresponding control module in the same measurement and control chassis, so that the control module generates a control waveform that matches the feedback strategy.

[0035] like Figure 1 As shown, the feedback module is sequentially connected to readout module 1, ..., in control chassis 1, and readout module m in control chassis m. Readout module 1 is connected to control modules 1-1, 1-2, ..., 1-n via wiring within the chassis. Similarly, readout module m is also connected to control modules m-1, m-2, ..., mn via wiring within the chassis.

[0036] The measurement and control chassis adopts a standardized rack-mount design. Each chassis integrates an independent readout module and control module. Furthermore, each measurement and control chassis is connected to an external interface module via a high-speed backplane bus, supporting parallel expansion and synchronous collaboration of multiple measurement and control chassis.

[0037] The readout module outputs the excitation waveform to the qubit readout cavity via a high-sampling-rate digital-to-analog converter. After the qubit information is coupled with the excitation waveform, it is then acquired by the high-sampling-rate analog-to-digital converter. Subsequently, through demodulation and state determination algorithms, the state information of the qubit is finally obtained.

[0038] For example, the hardware input interface of the feedback module is connected to readout module one, readout module two, and readout module three in sequence. Readout module one is responsible for reading qubits 1 to 8, readout module two is responsible for reading qubits 9 to 16, and readout module three is responsible for reading qubits 17 to 24. So the order of the input qubits is [qubits 1 to 8, qubits 9 to 16, qubits 17 to 24].

[0039] The control module is equipped with a waveform generator, a high-precision digital-to-analog converter, and a power amplifier unit. The waveform generator supports programmable generation of arbitrary waveforms and can generate corresponding baseband control signals according to the received feedback strategy. After being converted into analog signals, the signal gain is adjusted by the power amplifier unit, and finally, a control waveform that meets the control requirements of the qubit is output. This control waveform can be transmitted to the control port of the second qubit through a dedicated quantum control channel to achieve precise control of the state of the second qubit.

[0040] The feedback module adopts a centralized server architecture or a distributed processing unit cluster deployment. Its hardware core includes a high-performance processor (such as a Field Programmable Gate Array, FPGA), a large-capacity cache unit, and a high-speed communication interface. The feedback module establishes a communication connection with the readout module of each measurement and control chassis through a multi-channel data receiving interface.

[0041] The preset feedback configuration information is stored in the local database or configurable register of the feedback module. This preset feedback configuration information contains the mapping rules between qubits. The correlation mapping process is implemented by running a preset instruction set. Specifically, by executing instructions in the preset instruction set, the state information of multiple first qubits is calculated according to the relationships between the qubits, and the calculation results are obtained. Based on the calculation results, a feedback strategy is generated for each second qubit measured and controlled by the measurement and control chassis. The feedback module distributes the feedback strategy to the readout module of the corresponding measurement and control chassis. After receiving the feedback strategy, the readout module forwards the feedback strategy to the corresponding control module through the backplane bus inside the measurement and control chassis.

[0042] For example, the hardware output interface of the feedback module is sequentially connected to readout module one, readout module two, and readout module three. Readout module one is connected to control modules 1-1, 1-2, ..., 1-8 via internal wiring, and is responsible for controlling qubits 24-17 respectively; readout module two is connected to control modules 2-1, 2-2, ..., 2-8 via internal wiring, and is responsible for controlling qubits 16-9 respectively; readout module three is connected to control modules 3-1, 3-2, ..., 3-8 via internal wiring, and is responsible for controlling qubits 8-1 respectively. Therefore, the output qubit sequence is mapped as [qubits 24-17, qubits 16-9, qubits 8-1].

[0043] After receiving the feedback strategy, the waveform generator generates the control waveform in real time according to the parameters configured in the feedback strategy. If the feedback strategy includes timing synchronization requirements, the control module will receive the global synchronization clock signal sent by the feedback module through the synchronization signal interface to ensure that the output timing of the control waveform is synchronized with the control actions of other measurement and control chassis. Finally, the control waveform matching the feedback strategy is precisely applied to the second qubit through the control channel to achieve dynamic adjustment of the state of the second qubit and realize global feedback control of the qubit.

[0044] Through the coordinated operation of multiple measurement and control chassis, each chassis contains a readout module and a control module. The readout module accurately acquires the state information of the first qubit, while the control module is responsible for outputting control waveforms to the second qubit, thereby changing its state. Based on this, a feedback module, acting as the core hub, receives the first qubit state information from the readout modules of each chassis. According to preset feedback configuration information, it performs correlation mapping on this state information to generate feedback strategies for the second qubits measured and controlled by each chassis, and accurately distributes these strategies to the corresponding readout modules. The readout modules further receive the feedback strategies and forward them to the control modules within the same chassis, enabling the control modules to generate control waveforms that match the feedback strategies. This achieves efficient and precise control of the qubit state, improving the stability and accuracy of the quantum computing system.

[0045] According to an embodiment of the present invention, the feedback module includes: an instruction control unit configured to parse a preset instruction set and issue corresponding control instructions to the feedback execution unit; and a feedback execution unit configured to, in response to the received control instructions, perform association mapping processing on the state information of multiple first qubits according to the mapping rules in the preset feedback configuration information; wherein the mapping rules include: a one-to-one mapping rule for determining the feedback strategy for a single second qubit based on the state information of a single first qubit, a multiple-to-one mapping rule for jointly determining the feedback strategy for a single second qubit based on the state information of multiple first qubits, a one-to-many mapping rule for jointly determining the feedback strategy for multiple second qubits based on the state information of a single first qubit, and a multiple-to-many mapping rule for jointly determining the feedback strategy for multiple second qubits based on the state information of multiple first qubits.

[0046] The instruction control unit uses an FPGA chip as its core hardware platform, coupled with a high-speed cache and instruction decoding circuit, to achieve efficient parsing of the preset instruction set and accurate issuance of control instructions. The preset instruction set is stored in the unit's built-in non-volatile memory, and the instruction format adopts a standardized structure. The preset instruction set is shown in Table 1.

[0047] Table 1:

[0048]

[0049] As shown in Table 1, LUI (Load Upper Immediate) is the instruction to load the upper half of an immediate value. This instruction loads an immediate value into the upper half of a register and is often used to construct large constant values. JAL (Jump and Link) is the instruction to jump and link. This instruction is used to implement program jump operations and save the return address to the specified register for subsequent return operations. ADDI (Add Immediate) is the instruction to add an immediate value. This instruction adds an immediate value to the value in a register and stores the result in the destination register. ADD (Add, ADD) is the instruction to add the values ​​in two registers and store the result in the destination register. BNE (Branch if Not Equal) is the instruction to branch if not equal. This instruction determines whether the values ​​in two registers are not equal, and if not, jumps to the specified address to continue program execution. EXEC (Execute, EXEC) is the instruction to execute. This is a custom instruction for quantum feedback circuits, used to trigger specific operations or processes in the quantum feedback circuit. DLY (Delay, DLY) is a delay instruction. This is a quantum feedback circuit customization instruction used to insert delays into the quantum feedback circuit to meet specific timing requirements or adjust the order of operations. By combining these instructions, the feedback module can complete a specified operation at a specified time point.

[0050] After the instruction control unit is started, it sequentially captures instructions from the preset instruction set and sends the corresponding control instructions to the feedback execution unit through the high-speed serial bus. At the same time, it attaches an instruction execution timing identifier to ensure that the control instructions and the status information processing flow of the feedback execution unit are accurately synchronized.

[0051] The feedback execution unit responds to the control commands from the command control unit and completes the association mapping processing of multi-qubit state information based on the mapping rules in the preset feedback configuration information. At the hardware level, the feedback execution unit receives the state information of the first qubit uploaded by the readout module in each measurement and control chassis through a multi-channel data interface, providing data input for the association mapping processing.

[0052] For the four mapping rules, the feedback execution unit integrates corresponding dedicated processing logic: For the one-to-one mapping rule, a one-to-one mapping table is established between the first qubit and the second qubit, and the feedback strategy for the corresponding single second qubit is quickly generated based on the state information of the single first qubit. For the one-to-many mapping rule, a one-to-one mapping table is established between the first qubit and multiple second qubits, and the feedback strategy for the corresponding multiple second qubits is quickly generated based on the state information of the single first qubit.

[0053] Many-to-single mapping rules and many-to-many mapping rules can employ decoding algorithms such as association matching and belief propagation algorithms to determine the feedback strategy for one or more second qubits based on the state information of multiple first qubits, so as to ensure that the feedback strategy can achieve global optimization and control of the multi-qubit system.

[0054] The instruction control unit of the feedback module parses the preset instruction set and issues control instructions. The feedback execution unit processes the state information of the qubit according to the mapping rules, realizing multiple mapping methods, accurately generating feedback strategies, and improving the flexibility and adaptability of qubit control.

[0055] According to an embodiment of the present invention, when the mapping rule is a many-to-single mapping rule or a many-to-many mapping rule, the feedback execution unit is further configured to: respond to a control command, call and execute a preset strategy generation algorithm according to preset feedback configuration information, perform joint operations on the state information of the received multiple first qubits, and generate a feedback strategy for the second qubit based on the operation result.

[0056] In scenarios where the mapping rule is a many-to-one or many-to-many mapping rule, the feedback execution unit first responds to the control command issued by the instruction control unit, reads the preset feedback configuration information, determines the association relationship between multiple first qubits and their corresponding single or multiple second qubits, and then calls and executes the preset strategy generation algorithm to perform joint operations on the state information of multiple first qubits, and generates a feedback strategy for the second qubits based on the operation results. The preset strategy generation algorithm can be a decoding algorithm such as association matching or belief propagation.

[0057] In addition, for scenarios involving many-to-single mapping rules and many-to-many mapping rules, simple logical operations (such as AND / OR / XOR) can be used to perform joint logical operations on the state information of multiple first qubits to generate a feedback strategy for the second qubit.

[0058] After the calculation is completed, the generated feedback strategy is transmitted to the output buffer module of the feedback execution unit, awaiting subsequent distribution to the control module of the corresponding measurement and control chassis. Under the many-to-single or many-to-many mapping rule, the feedback execution unit performs joint calculations on the received state information of multiple first qubits according to the control instructions and preset feedback configuration information, and generates a feedback strategy based on the calculation results, which enhances the complexity and accuracy of qubit control.

[0059] According to an embodiment of the present invention, the instruction control unit is further configured to: acquire preset feedback configuration information and preset number of cycles corresponding to the target loop body; execute the target loop body based on the preset number of cycles to control the feedback execution unit to repeatedly execute the following operations, and update the current loop count value after each execution until the current loop count value reaches the preset number of cycles; perform association mapping processing on the state information of the received multiple first qubits based on the preset feedback configuration information to generate feedback strategies corresponding to the second qubits measured and controlled by each measurement and control chassis, and output the generated multiple feedback strategies.

[0060] The instruction control unit locates the storage partition corresponding to the target loop body by executing memory read and write instructions, and extracts the preset feedback configuration information and preset loop count from the storage module.

[0061] The preset feedback configuration information includes mapping rules associated with the target loop body. Simultaneously, the instruction control unit executes parameter reading instructions to read auxiliary parameters such as loop start trigger conditions and loop interval timing, completing the basic information preparation before loop execution.

[0062] During the initialization phase of loop execution, the instruction control unit clears the current loop count value using its built-in counter module and loads the preset loop count into the comparator module's base value register to establish the basis for loop termination. Subsequently, the instruction control unit executes the loop start control command to drive the target loop body to run repeatedly according to the preset loop count.

[0063] At the start of each cycle, the feedback execution unit receives the state information of multiple first qubits uploaded by each measurement and control chassis, completes the association mapping process according to the mapping rules in the preset feedback configuration information, generates corresponding feedback strategies for different second qubits, and forwards the generated feedback strategies to the distribution channels of each corresponding measurement and control chassis.

[0064] After each round of feedback strategy output is completed, the instruction control unit triggers the counter module to increment the current loop count. The counter module uses synchronous counting to ensure precise synchronization between the count update and the loop execution steps. After the count is updated, the comparator module immediately compares the current loop count with the preset number of loops in real time. If the current count is less than the preset number of loops, the instruction control unit maintains the loop state and triggers the synchronous trigger signal for the next loop after a preset loop interval. If the current count reaches the preset number of loops, the comparator module outputs a loop termination signal, and the instruction control unit then executes the loop stop command, simultaneously resetting the current loop count to zero, completing the full loop execution of the target loop. Subsequent iterations can be triggered based on new instructions to start the next loop task or switch to other operating modes.

[0065] Throughout the entire loop execution process, the built-in status monitoring module of the instruction control unit monitors the loop counter value update status in real time. If an abnormal counter value, execution timeout, or strategy output error occurs, the abnormal interruption mechanism will be triggered immediately to suspend loop execution, record fault information, and report an abnormal alarm to the system master control module, ensuring the reliability and safety of loop control.

[0066] By acquiring the preset feedback configuration information and loop count of the target loop body through the instruction control unit, the system can control the feedback execution unit to repeatedly execute the association mapping processing of the state information according to the preset loop count, generate the feedback strategy and output it, and update the loop count value after each execution until the preset number of times is reached. This achieves efficient, repeated generation and updating of the quantum bit feedback strategy, improving the automation and accuracy of quantum bit control.

[0067] Figure 2 A flowchart illustrating the cyclic feedback process of a global feedback control system for qubits according to an embodiment of the present invention is shown.

[0068] like Figure 2 As shown, this embodiment includes operations S201 to S205.

[0069] In operation S201, the preset feedback configuration information and preset number of cycles corresponding to the first loop body and the second loop body are obtained respectively.

[0070] In operation S202, the first loop body is executed based on the preset number of loops of the first loop body, and the current loop count value corresponding to the first loop body is updated.

[0071] In operation S203, it is determined whether the current loop counter value has reached the preset number of loops corresponding to the first loop body. If yes, operation S204 is executed; otherwise, operation S202 is executed.

[0072] In operation S204, the second loop body is executed based on the preset number of iterations of the second loop body, and the current loop count value corresponding to the second loop body is updated.

[0073] In operation S205, it is determined whether the current loop counter value has reached the preset number of loops corresponding to the second loop body. If yes, the process ends; otherwise, operation S204 is executed.

[0074] According to an embodiment of the present invention, the instruction control unit extracts and obtains the preset feedback configuration information corresponding to the first loop body and the second loop body, as well as the preset number of loops corresponding to each of the two loop bodies, by running a preset instruction set. At the same time, it configures independent loop counters for the two loop bodies by executing the instructions in the preset instruction set, thereby completing the basic information preparation and hardware initialization before the double loop execution.

[0075] The instruction control unit prioritizes initiating the execution flow of the first loop, progressively advancing the core operations within the loop according to the preset number of iterations. After each complete iteration of the first loop, the current loop counter bound to it is immediately updated. Subsequently, this current loop counter is compared in real-time with the preset number of iterations for the first loop. If the current loop counter has not reached the preset number of iterations, the first loop continues to execute and the corresponding counter is updated. If the current loop counter has reached the preset number of iterations, the execution of the first loop is terminated, and the process seamlessly transitions to the second loop's processing flow.

[0076] The execution flow of the second loop is then initiated, proceeding through the core operations within the loop in rounds according to the preset number of iterations. After each complete iteration of the second loop, the current loop counter bound to the second loop is updated synchronously. Next, this current loop counter is compared in real-time with the preset number of iterations for the second loop. If the current loop counter has not reached the preset number of iterations, the second loop continues to execute and the corresponding counter is updated. If the current loop counter has reached the preset number of iterations, the execution of the second loop terminates, completing the entire double-loop process.

[0077] By acquiring the preset feedback configuration information and preset number of cycles for the two loop bodies, the loop operation is executed sequentially and the current loop count value is updated. It is then determined whether the preset number of cycles has been reached to decide whether to continue execution or enter the next stage. This achieves phased loop control and improves the flexibility and adaptability of the system.

[0078] According to an embodiment of the present invention, the feedback module further includes a communication control unit and a block random access memory; the communication control unit is configured to receive a preset instruction set and multiple different preset feedback configuration information issued by a host computer, and forward them to the instruction control unit; the instruction control unit is further configured to: store the received multiple different preset feedback configuration information into corresponding independent storage areas of the block random access memory; parse the preset instruction set to determine the target configuration identifier, and read the corresponding preset feedback configuration information from the block random access memory according to the target configuration identifier, and provide it to the feedback execution unit.

[0079] The communication control unit can use a dedicated communication controller chip as its core, coupled with signal conditioning circuits, protocol conversion modules, and data buffer units, to construct a high-speed and stable communication link with the host computer. Specifically, it receives preset instruction sets and multiple different preset feedback configuration information from the host computer through a preset communication interface. The interface supports full-duplex communication and uses differential signal transmission to reduce electromagnetic interference and ensure data transmission reliability. The communication control unit forwards the preset instruction sets and preset feedback configuration information to the instruction control unit through an internal high-speed bus. During the forwarding process, an interrupt signal is used to notify the instruction control unit to receive data, and the data is temporarily stored in the buffer unit to avoid data loss due to the instruction control unit being busy.

[0080] Block random access memory (BRAM), as a dedicated storage medium, can adopt a multi-port parallel access architecture to support high-speed read and write operations of the instruction control unit. Internally, it is divided into multiple independent storage areas through hardware logic, each area corresponding to a unique area identifier (such as an address range). The area size can be dynamically configured according to the maximum data volume of preset feedback configuration information.

[0081] After receiving multiple different preset feedback configuration information forwarded by the communication control unit, the instruction control unit first classifies and identifies each configuration information through the storage management module, assigns a unique configuration identifier to each configuration information, and establishes a mapping table between the configuration identifier and the storage area identifier, storing it in its own built-in non-volatile memory.

[0082] Subsequently, the instruction control unit, through the write control interface of the block random access memory (RAM), writes the corresponding preset feedback configuration information into the designated independent storage area of ​​the RAM according to the storage area identifier in the mapping table. During the writing process, the target storage unit is located by the address decoding circuit. After triggering the write enable signal, the configuration information is latched into the storage unit byte by byte or word by word. At the same time, the occupancy status (stored / free) of each storage area is recorded to avoid storage conflicts.

[0083] During the configuration information reading phase, the instruction control unit can parse the received preset instruction set by executing instructions from the preset instruction set. Next, it extracts the opcode, target configuration identifier, and read control parameters from the instruction set. The target configuration identifier corresponds one-to-one with the configuration identifier stored in the block random access memory (RAM). After parsing, the instruction control unit queries the mapping table between configuration identifiers and storage area identifiers through the storage management module to obtain the RAM storage area address (start and end addresses) corresponding to the target configuration identifier. Subsequently, it sends a read request through the RAM read control interface, specifying the target storage area address.

[0084] After responding to the request, the block random access memory continuously reads out the preset feedback configuration information in the corresponding storage area through the data output port. The instruction control unit generates a configuration information ready signal by executing relevant instructions, triggering the feedback execution unit to carry out association mapping processing based on the configuration information.

[0085] The communication control unit receives preset instruction sets and various feedback configuration information from the host computer and forwards them to the instruction control unit. These configuration information are stored in an independent area of ​​the block random access memory. The instruction control unit parses the instruction set to determine the target configuration identifier and reads the corresponding feedback configuration information from the memory for use by the feedback execution unit. This achieves flexible configuration management and efficient information transmission, improving the system's adaptability and operating efficiency.

[0086] Figure 3 A schematic diagram of module interaction of a global feedback control system for qubits according to an embodiment of the present invention is shown.

[0087] like Figure 3 As shown, the host computer 301 establishes a communication connection with the communication control unit 303, and is responsible for sending preset instruction sets, preset feedback configuration information, and other data downwards. The synchronization signal source 302 is connected to the instruction control unit 304, continuously providing a global synchronization clock signal and a synchronization trigger signal. The synchronization trigger signal is used to start the instruction control unit to parse instructions one by one. The communication control unit 303 maintains bidirectional data interaction with the instruction control unit 304, forwarding the content sent by the host computer 301 to the instruction control unit 304 on one hand, and receiving the status information returned by the instruction control unit 304 on the other.

[0088] Meanwhile, both are connected to the feedback execution unit 305. The instruction control unit 304 sends control instructions to the feedback execution unit 305, while the communication control unit 303 is responsible for data transmission between the feedback execution unit 305 and the outside world. Based on the received instructions and configuration information, the feedback execution unit 305 completes the association mapping and other processing work of the quantum bit state information.

[0089] By leveraging a dedicated connection between the host computer and the communication control unit, the stability of command and configuration information transmission is ensured. The integration of a synchronization signal source allows the command control unit to maintain synchronized execution with other units, preventing processing errors caused by timing discrepancies. The division of labor and collaboration among the communication control unit, command control unit, and feedback execution unit clearly defines the functional boundaries of each module, improves the overall efficiency of feedback processing through efficient internal interaction, and also reserves clear interface space for future functional expansion.

[0090] According to an embodiment of the present invention, the feedback module further includes: an identifier register configured to assign a corresponding state identifier bit to each second qubit, wherein the state identifier bit is a first state indicating that the feedback strategy for the corresponding second qubit has been generated, or a second state indicating that the feedback strategy for the corresponding second qubit has not been generated; the feedback execution unit is further configured to: update the state identifier bit of the corresponding second qubit in the identifier register from the second state to the first state in response to the feedback strategy for generating a single second qubit.

[0091] The identifier register utilizes a distributed register group built into the FPGA, relying on a parallel access architecture to ensure the real-time and efficient reading and writing of the status identifier bit, adapting to the high-speed response requirements of qubit feedback control. Internally, the identifier register is organized and divided according to the control and measurement chassis number and the channel number of the second qubit, assigning a unique and independent status identifier bit to each second qubit. This identifier bit is stored using a single-bit binary data format. A preset single binary value represents the second state (indicating that the feedback strategy for the corresponding second qubit has not been generated), while the other opposing binary value represents the first state (indicating that the feedback strategy for the corresponding second qubit has been generated). This single-bit storage format saves register storage space while enabling rapid state rewriting and identification.

[0092] During the initialization phase and before each feedback loop task begins, the flag register, based on the global initialization instruction executed by the instruction control unit, uses its built-in clearing circuit to uniformly set the state flag bits corresponding to all second qubits to the second state. Simultaneously, the flag register incorporates a state latching circuit and access control logic, granting only write access to the feedback execution unit and read-only query access to the instruction control unit. This prevents unauthorized operations from causing state flag bit corruption and ensures data reliability.

[0093] After generating the feedback strategy for a single second qubit, the feedback execution unit triggers the update process of the state flag bit. The entire process relies on synchronous timing logic to achieve precise and efficient state rewriting. Specifically, the corresponding state flag bit is rewritten from the original second state to the first state according to the synchronous timing logic. The entire rewriting operation has no additional delay and is seamlessly connected with the feedback strategy generation process.

[0094] After the update is completed, the relevant information of this update operation (target second qubit identifier, update timestamp, and status before and after the update) can be temporarily stored in the internal operation log cache for subsequent manual query and verification of progress.

[0095] For scenarios where multiple sets of second-qubit feedback strategies are generated in parallel, multiple state flag bits can be rewritten simultaneously. After the entire cycle task is completed, the flag register will be reset to the second state under the trigger of the instruction control unit's reset instruction, preparing for the next round of feedback task.

[0096] By assigning a status flag bit to each second qubit in the flag register within the feedback module, the generation status of the feedback strategy can be tracked in real time. After generating a feedback strategy for a second qubit, the feedback execution unit updates the corresponding status flag bit from "not generated" to "generated," thereby achieving precise monitoring of the feedback strategy generation progress and improving the manageability and reliability of the system.

[0097] Figure 4 A flowchart illustrating the feedback output of a global feedback control system for qubits according to an embodiment of the present invention is shown.

[0098] like Figure 4 As shown, this embodiment includes operations S401 to S404.

[0099] In operation S401, the state flag bits corresponding to each second qubit in the flag register are read, and the total duration of multiple feedback strategies is monitored and generated based on the clock cycle.

[0100] In operation S402, determine whether all multiple status flag bits are in the first state. If yes, then execute operation S404; otherwise, execute operation S403.

[0101] In operation S403, determine whether the total duration has reached the preset duration. If yes, execute operation S404; otherwise, execute operation S401.

[0102] In operation S404, an output instruction is issued to the feedback execution unit so that the feedback execution unit outputs the generated multiple feedback strategies.

[0103] According to an embodiment of the present invention, the instruction control unit establishes a stable connection with the identifier register through a dedicated parallel read interface. Based on the address encoding system preset in the identifier register, it notifies the execution of relevant instructions to read the state identifier bits corresponding to each second qubit in batches. The instruction control unit temporarily stores all read state identifier bit data in a built-in high-speed state buffer. This read operation is not performed once, but is synchronized with the global clock cycle, periodically refreshing the data in the state buffer to ensure timely capture of the generation state changes of the feedback strategy for each second qubit, meeting the real-time requirements of quantum feedback control.

[0104] While reading the status flag, the instruction control unit relies on the clock module and timer counter to monitor the total duration based on the clock cycle. When the feedback task starts, the instruction control unit triggers the timer counter to reset and initialize by executing the instruction set, while locking the system's global clock cycle as the timing reference. The counter increments its count value once every complete clock cycle, and through real-time conversion of "clock cycle × current count value", it continuously updates and generates the cumulative total duration of multiple feedback strategies. The preset duration is pre-loaded into a dedicated duration comparison register as the termination judgment benchmark for total duration monitoring. During the timing process, the duration conversion module and the counter remain synchronized to ensure the accuracy and continuity of the total duration data, while not interfering with the reading operation of the status flag, thus enabling the parallel and coordinated advancement of the two tasks.

[0105] The parallel logic judgment module built into the instruction control unit performs real-time synchronous detection of two trigger conditions, enabling condition determination without waiting for both tasks to complete. First, it iterates through and verifies all state flag data in the state buffer. If all state flags corresponding to the second qubits represent the first state generated by the feedback strategy, the logic judgment module outputs a "state met" trigger signal. Second, the duration comparison module compares the real-time calculated total duration with the preset duration in the duration comparison register. If the current total duration is greater than or equal to the preset duration, regardless of whether all state flags meet the criteria, a "duration met" trigger signal is output. Meeting either condition triggers the subsequent process, eliminating the need for both conditions to be met simultaneously. This ensures the efficiency of the feedback task execution and reduces system lag caused by delays in individual qubit strategy generation.

[0106] Upon receiving any trigger signal, the command control unit immediately stops the timer counter's accumulation and locks the data in the status buffer to prevent subsequent status changes from interfering with the command issuance process. Then, the feedback strategy is transmitted to the distribution channel of the corresponding measurement and control chassis, completing the core data output for this round of feedback.

[0107] By monitoring the status flag bits in the flag register and the total duration of generating feedback strategies, the system can promptly issue output instructions to the feedback execution unit when all feedback strategies are generated or the preset duration is reached, ensuring efficient output of feedback strategies and improving the system's response speed and stability.

[0108] According to an embodiment of the present invention, the feedback execution unit is further configured to: in response to an identifier reset instruction issued by the instruction control unit, reset the state identifier bit corresponding to each second quantum bit in the identifier register from the first state to the second state; wherein the identifier reset instruction is issued by the instruction control unit before each round of execution.

[0109] The reset operation of the identifier register by the instruction control unit is entirely driven by user-written instructions. It is only recommended to perform the reset action before the execution of each feedback loop task. The purpose is to clear the state residue of the previous feedback task and prevent interference with the experimental results of the current round. At the same time, the reset is not triggered immediately after the completion of each loop task, allowing the user sufficient time to query the state. This allows the user to read the state identifier bits of each second quantum bit in the identifier register, verify the completion of the generation of the feedback strategy in this round, and realize the traceability of experimental results and anomaly investigation.

[0110] Triggered by user commands, the instruction control unit, during the initialization phase before each feedback loop task execution, completes preparatory work such as reading preset feedback configuration information, clearing the loop counter, and verifying the readiness status of the feedback execution unit, and immediately generates a flag reset instruction. The instruction control unit issues this flag reset instruction to the flag register through a dedicated high-speed instruction bus. The timing of this instruction issuance follows the user-written instruction logic, which can be flexibly adjusted by the user according to experimental needs, without being limited to a fixed node before the loop.

[0111] After receiving the flag reset instruction from the instruction control unit, the flag register triggers the internal reset preparation signal and immediately locks the external write access permissions of the status flag bits corresponding to all second qubits (only retaining the operation permissions of the reset-specific logic) to prevent interference from write operations of the feedback execution unit during the reset process, ensuring the orderly progress of the reset process. At the same time, it returns an instruction reception confirmation signal to the instruction control unit to inform that the reset process has officially started.

[0112] Subsequently, the identifier register, relying on its built-in global parallel reset logic circuit, achieves batch reset of the state identifier bits corresponding to all second qubits, eliminating the need for addressing and rewriting bit by bit, significantly improving reset efficiency to meet the high-speed advancement requirements of cyclic tasks. This global reset logic circuit is synchronized with the system's global high-precision clock. Upon receiving the reset preparation signal, it triggers a global reset pulse according to a preset timing sequence, uniformly and synchronously rewriting all identifier bits in the register array that are in the first state (representing the generated feedback strategy) to the second state (representing the ungenerated feedback strategy). The rewriting process employs a parallel operation architecture, with all state identifier bits resetting synchronously without any delay, ensuring that before each cycle starts, all second qubit state identifier bits are in a unified initial reference state, providing a clean state foundation for the current feedback experiment and reducing the deviation of residual states from the previous experiment from the current result.

[0113] Once the instruction control unit receives the reset completion confirmation signal from the identifier register, it can confirm that the identifier register has completed the reset of all status identifier bits, satisfying the start conditions for this round of task looping. Subsequently, the subsequent process can proceed in an orderly manner, issuing corresponding control commands to the feedback execution unit to initiate the feedback strategy generation for this round of task looping. This ensures that each round of task looping is based on a clean and consistent identifier register state, guaranteeing the stability and traceability of the feedback control process.

[0114] When the current cycle task ends, the system will not automatically trigger the reset process. The status flag information of each second quantum bit in this cycle will be retained in the flag register. Users can read this status information through the host computer or dedicated query interface to check the completion status of the feedback strategy generation in this cycle, whether there are any quantum bits without generated strategies, etc., to provide data support for experimental analysis. After the user completes the query and writes the reset instruction for the next cycle according to the experimental requirements, the reset process for the next cycle will be started.

[0115] If the flag register fails to reset within the preset time limit, a reset error alarm signal will be sent to the instruction control unit. Upon receiving the alarm, the instruction control unit will pause the start of the current cycle task, record the error information, and report it to the host computer. Simultaneously, a retry mechanism can be triggered to reissue the flag reset command, reducing the impact of the abnormal state on the execution of subsequent feedback tasks. This error information will also be stored for later user query and troubleshooting.

[0116] By receiving an identifier reset instruction from the instruction control unit before each cycle execution, the state identifier bit of each second quantum bit in the identifier register is reset from "generated" to "not generated", preparing for the generation of a new round of feedback strategy, ensuring that the system maintains accurate state tracking throughout the cycle, and enhancing the reliability and continuity of quantum bit feedback control.

[0117] According to an embodiment of the present invention, the feedback module further includes: an information input unit configured to receive and aggregate the state information of multiple first qubits according to the hardware connection order of each readout module; and an information output unit configured to distribute the feedback strategy generated by the association mapping process to the corresponding readout module based on the hardware output order of the control and measurement chassis to which each second qubit belongs.

[0118] The information input unit uses a high-speed interface adapter circuit and a data aggregation control module as its core hardware carrier. Its core function is to accurately match the hardware connection sequence of each readout module to achieve orderly reception and aggregation of status information. At the hardware connection level, the information input unit is equipped with multiple parallel input interfaces. The interface types are strictly matched with the output interfaces of the readout modules. Each interface corresponds to one readout module, and the physical arrangement order of the interfaces corresponds one-to-one with the hardware connection sequence of the readout modules, forming a fixed mapping relationship between interface numbers and readout modules. This mapping relationship is pre-stored in the built-in register of the input unit, providing a basis for sequence recognition.

[0119] During reception, the information input unit monitors the connection and data transmission status of each input interface in real time through the interface status detection circuit, ensuring a stable communication link with all readout modules. When a readout module uploads the status information of the first qubit, the information input unit synchronously receives the data transmitted from each interface according to the pre-stored mapping relationship between the interface number and the readout module. Simultaneously, the timing synchronization module locks the system's global clock to ensure consistent data reception timing across all channels, preventing sequence errors caused by transmission delays.

[0120] For the received multi-channel status information, the information input unit performs batch caching and format normalization through the data aggregation control module. First, each channel of data is temporarily stored in a high-speed cache, and a unique identifier (such as the read module number and interface number) is added to each channel of data according to the receiving order (i.e., the hardware connection order of the read modules). Then, the normalized batch data is converted into a unified data format recognizable by the feedback execution unit and transmitted to the feedback execution unit via the internal high-speed bus, completing the aggregation and delivery of status information.

[0121] The information output unit consists of a distribution control logic module, a multi-output interface array, and a queue buffer unit. Its core objective is to achieve precise, targeted distribution of feedback strategies based on the hardware output order of the control and measurement chassis to which the second qubit belongs. During the distribution preparation phase, the information output unit pre-stores a mapping table between the second qubit identifier and its corresponding control and measurement chassis and readout module. Simultaneously, it defines the hardware output order of each control and measurement chassis (this order is determined by the physical layout of the chassis and the bus addressing order during system deployment, and is pre-configured in the distribution strategy register of the output unit). The feedback strategy generated by the feedback execution unit carries the identifier information of the target second qubit. After receiving these feedback strategies, the information output unit temporarily stores them in the queue buffer unit to avoid congestion caused by concurrent distribution.

[0122] During the distribution process, the distribution control logic module of the information output unit first parses the second qubit identifier in each feedback strategy. It then determines the control and measurement chassis to which the qubit belongs by querying the association mapping table. Based on the pre-stored hardware output order, it sorts the feedback strategies corresponding to different control and measurement chassis, generating a distribution queue arranged according to the hardware output order.

[0123] Subsequently, the distribution control logic module distributes the feedback strategy to the corresponding readout module of the measurement and control chassis according to the queue order through a multi-output interface array. Each output interface corresponds to a readout module of one measurement and control chassis, and the activation order of the interfaces is consistent with the hardware output order of the measurement and control chassis to ensure that the distribution process conforms to the preset hardware sequence requirements. During distribution, the output unit establishes interaction with the readout module through a handshake signal. After the readout module returns a receive-ready signal, the output unit sends the feedback strategy data. After sending, it receives a receive confirmation signal from the readout module to ensure that the strategy data is delivered completely. For scenarios with parallel distribution across multiple measurement and control chassis, the output unit adopts a multi-channel parallel transmission architecture, allocating independent bandwidth resources to different channels. Conflict detection circuitry avoids interface conflicts during concurrent distribution, ensuring the efficiency and orderliness of the distribution process.

[0124] The system integrates the state information of the first quantum bit in the order of hardware connection through the information input unit, and distributes the feedback strategy to the corresponding readout module in the order of hardware output through the information output unit. The feedback module realizes efficient information integration and accurate distribution, enabling the system to have the ability to comprehensively process global information.

[0125] Figure 5 A schematic diagram of the global interaction of a quantum bit global feedback control system according to an embodiment of the present invention is shown.

[0126] like Figure 5As shown, the feedback module integrates a communication control module, an instruction control module, a feedback execution unit, an information input unit containing qubit inputs 1 to p, and an information output unit containing qubit outputs 1 to p. Externally, the module is connected to readout module one, readout module two, readout module three, and readout module m.

[0127] The information input unit interfaces with each readout module, receiving state information from multiple sets of qubits uploaded by all readout modules and converging this information to the feedback execution unit. The communication control module interacts with external devices, forwarding the acquired preset instruction set and preset feedback configuration information to the instruction control module. Based on this information, the instruction control module issues control commands to the feedback execution unit, guiding it to perform association mapping processing on the input state information. After processing, the feedback execution unit transmits the generated feedback strategy to the information output unit, which then distributes it to each readout module accordingly.

[0128] The multi-channel design of the information input unit enables centralized reception of state information from multiple qubits, avoiding the chaos of dispersed transmission. The coordinated operation of command control and feedback execution ensures the controllability and accuracy of the feedback processing. The corresponding distribution mechanism of the information output unit ensures that the feedback strategy can be accurately matched to the target readout module. The overall structure is adaptable to complex scenarios with multiple qubits and multiple readout modules, effectively improving the global coordination efficiency and adaptability of qubit feedback control.

[0129] According to another embodiment of the present invention, assuming that a quantum computing experimental system contains p qubits, the readout modules and control modules corresponding to these qubits are deployed in multiple measurement and control chassis. The feedback module is responsible for acquiring the state information of these p qubits uploaded by all readout modules, and after subsequent processing, distributing the corresponding feedback strategy to the readout modules of each corresponding measurement and control chassis. Finally, the control module in each chassis executes the corresponding feedback action.

[0130] Global feedback control includes two core modes: one-to-one and two-to-one. In the one-to-one global feedback control mode, each qubit implements self-feedback control, that is, it determines whether its corresponding control module should perform a feedback action based on the state information of a single qubit. In the two-to-one global feedback control mode, the feedback strategy of the control module corresponding to a single qubit is determined by comprehensively judging the state information of two qubits.

[0131] For example, when the state information of two specified qubits is 0, the control module of the corresponding qubit does not perform any action; otherwise, the control module outputs an X-gate waveform. When the state information of two specified qubits is 1, the control module of the other corresponding qubit does not perform any action; otherwise, the control module also outputs an X-gate waveform.

[0132] To address the unique characteristics of quantum computing feedback experiments, the data bits used to trigger various functional instructions can be clearly defined, as shown in Table 2.

[0133] Table 2:

[0134]

[0135] As shown in Table 2, data bits 31 to 8 are reserved bits with no specific function assignment. Data bit 7, when set to 1, is used to reset all feedback completion flag registers; when set to 0, no related operation is performed. Data bit 6, when set to 1, is used to directly flush feedback data to the output interface; when set to 0, no corresponding operation occurs. Data bit 5, when set to 1, is used to update the preset feedback configuration information in the feedback execution unit; when set to 0, no related operation occurs. Data bits 4 to 0 are used to identify the unique identifier of the preset feedback configuration information, thereby enabling precise retrieval of different preset feedback configuration information.

[0136] The host computer sends the block random access memory and preset feedback configuration information through the communication control unit. The preset feedback configuration information is stored in the block random access memory built into the FPGA. This block random access memory is pre-divided into several independent storage areas of fixed size, each area specifically storing a set of preset feedback configuration information. The preset feedback configuration information is shown in Table 3.

[0137] Table 3:

[0138]

[0139] As shown in Table 3, the block random access memory stores a series of Reg register data. Each Reg register is 16 bits wide and corresponds to a qubit in the output interface of the feedback module, indicating that the qubit information of the input interface indexed by the Reg value is transmitted to the output interface.

[0140] The upper part of the table is the feedback processing table used by global one-to-one feedback control. For example, if the value in Reg1 corresponding to Qout_1 is 10, it means that the state information (or processed information) input from the 10th interface is passed to the output interface of Qout_1.

[0141] The lower half of the table is the feedback processing table used by the global two-to-one feedback control. For example, if the value of Reg1_1 corresponding to Qout_1 is 10 and the value of Reg1_2 is 11, it means that the feedback command needs to be passed to the output interface of Qout_1 after comprehensively judging the two state information input from the 10th and 11th interfaces.

[0142] The system initiates the operation of the command control unit with an external synchronization trigger signal, thereby ensuring the synchronization of the feedback module with the entire measurement and control system. This ensures that the operation sequence of each link remains consistent and avoids affecting the accuracy of feedback control due to timing deviations. Under the orderly control of the preset instruction set, the system will complete preparatory operations such as resetting the feedback completion flag registers and reading and loading the corresponding preset feedback configuration information in advance, laying the foundation for the subsequent formal feedback process.

[0143] Subsequently, the readout modules of each control unit complete the reading and acquisition of the corresponding qubit state information, and then aggregate all the acquired qubit state information to the feedback module for further processing by the feedback execution unit. The feedback module, based on the pre-loaded preset feedback configuration information, completes the feedback processing and information routing for each qubit. Since the qubit state reading operations of each readout module are not completely synchronized, the completion time of the corresponding qubit feedback operations also varies. Therefore, each qubit or group of qubits is equipped with a dedicated identifier register to indicate in real time whether the corresponding feedback operation has been completed.

[0144] Once the feedback information for all qubits has been processed, the feedback module distributes the feedback strategy to the readout modules of the corresponding measurement and control chassis via the output interface. Then, through dedicated hardware connections within the measurement and control chassis, the feedback strategy is forwarded to the control module within the same chassis, which executes the corresponding feedback operation. If there is a delay in the feedback operation for some qubits, the output feedback information can be forcibly flushed after a preset time using a preset instruction set. This reduces the risk of system crashes due to individual qubits not participating in the feedback operation, ensuring the smooth progress of the feedback process. Subsequently, the system will continue to cycle through and complete a new round of feedback operations under the control of the preset instruction set, supporting the continuous and stable conduct of quantum computing experiments.

[0145] Figure 6 A flowchart of a global feedback control method for qubits according to an embodiment of the present invention is shown.

[0146] like Figure 6 As shown, this embodiment includes operations S610 to S640.

[0147] When operating the S610, the state information of multiple first qubits is acquired by multiple readout modules distributed in different measurement and control chassis, and the state information is sent to the feedback module.

[0148] When operating the S620, the feedback module performs correlation mapping processing on multiple state information based on preset feedback configuration information to generate feedback strategies for the second qubits measured and controlled by each measurement and control chassis, and distributes the generated feedback strategies to the readout modules of the corresponding measurement and control chassis.

[0149] When operating the S630, the received feedback strategy is forwarded to the control module in the same measurement and control chassis through each readout module.

[0150] When operating the S640, each control module generates a corresponding control waveform based on the received feedback strategy and outputs the control waveform to the corresponding second quantum bit.

[0151] According to an embodiment of the present invention, the readout module in each measurement and control box is respectively connected to the target first quantum bit, and the quantum state signal is acquired by the analog-to-digital converter and preprocessed and digitized. Then, the state information of each first quantum bit is synchronously sent to the feedback module through a high-speed communication link.

[0152] After receiving multiple status messages, the feedback module invokes the mapping rules in the preset feedback configuration information to perform association mapping operations on the status messages, generating a feedback strategy adapted to the second qubit in each measurement and control chassis. Then, based on the correspondence between the feedback strategy and the measurement and control chassis, the strategy is accurately pushed to the readout module of the corresponding measurement and control chassis through a targeted distribution mechanism.

[0153] After receiving the feedback strategy, the readout module of each measurement and control chassis forwards the feedback strategy directly to the matching control module in the same measurement and control chassis through the high-speed backplane bus inside the measurement and control chassis, so as to realize the efficient transmission of strategy inside the chassis.

[0154] The control module analyzes the received feedback strategy, extracts waveform parameters and generates corresponding baseband control signals. After digital-to-analog conversion and power amplification, a control waveform that meets the requirements is obtained. Finally, the control waveform is precisely output to the corresponding second quantum bit through a dedicated quantum control channel to complete quantum state control.

[0155] The readout modules distributed in different control and measurement chassis acquire the state information of the first qubit and send it to the feedback module. The feedback module performs correlation mapping processing on these state information based on preset feedback configuration information, generates a feedback strategy for the second qubit, and distributes it to the readout modules in the corresponding control and measurement chassis. The readout modules then forward the feedback strategy to the control module in the same chassis. The control module generates a control waveform and outputs it to the second qubit accordingly. This achieves fully automated control from state monitoring to precise control, improving the efficiency and accuracy of global feedback control of the qubit.

[0156] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0157] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0158] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A global feedback control system for qubits, characterized in that, The system includes: Multiple measurement and control chassis, each of the measurement and control chassis includes a readout module and a control module, wherein the readout module is configured to acquire the state information of a first quantum bit, and the control module is configured to output a control waveform to a second quantum bit to change the state of the second quantum bit; The feedback module is configured to receive the state information of the first quantum bit sent by the readout module of each of the measurement and control boxes, perform association mapping processing on the state information of multiple first quantum bits based on preset feedback configuration information, generate a feedback strategy for the second quantum bit measured and controlled by each of the measurement and control boxes, and distribute each feedback strategy to the readout module of the corresponding measurement and control box. The readout module is further configured to receive the feedback strategy sent by the feedback module and forward the feedback strategy to the corresponding control module in the same measurement and control chassis, so that the control module generates a control waveform that matches the feedback strategy; The feedback module includes: The instruction control unit is configured to parse a preset instruction set and send corresponding control instructions to the feedback execution unit. The feedback execution unit is configured to, in response to the received control command, perform association mapping processing on the state information of multiple first qubits according to the mapping rules in the preset feedback configuration information; The mapping rules include: a one-to-one mapping rule for determining the feedback strategy for a single second qubit based on the state information of a single first qubit; a many-to-one mapping rule for jointly determining the feedback strategy for a single second qubit based on the state information of multiple first qubits; a one-to-many mapping rule for jointly determining the feedback strategy for multiple second qubits based on the state information of a single first qubit; and a many-to-many mapping rule for jointly determining the feedback strategy for multiple second qubits based on the state information of multiple first qubits.

2. The system according to claim 1, characterized in that, When the mapping rule is the many-to-one mapping rule or the many-to-many mapping rule, the feedback execution unit is further configured to: In response to the control command, and based on the preset feedback configuration information, a preset strategy generation algorithm is invoked and executed to perform joint operations on the received state information of multiple first qubits, and a feedback strategy for the second qubit is generated based on the operation results.

3. The system according to claim 1, characterized in that, The instruction control unit is further configured to: Obtain the preset feedback configuration information and preset number of iterations corresponding to the target loop body; The target loop body is executed based on the preset number of loops to control the feedback execution unit to repeatedly execute the following operations, and to update the current loop count value after each execution, until the current loop count value reaches the preset number of loops: Based on the preset feedback configuration information, the state information of the received multiple first qubits is processed by association mapping to generate feedback strategies corresponding to the second qubits measured and controlled by each of the measurement and control boxes, and the generated multiple feedback strategies are output.

4. The system according to any one of claims 1-2, characterized in that, The feedback module also includes a communication control unit and a block-shaped random access memory; The communication control unit is configured to receive the preset instruction set and multiple different preset feedback configuration information issued by the host computer, and forward them to the instruction control unit; The instruction control unit is further configured to: store the received multiple different preset feedback configuration information into corresponding independent storage areas of the block random access memory; parse the preset instruction set to determine the target configuration identifier, and read the corresponding preset feedback configuration information from the block random access memory according to the target configuration identifier, and provide it to the feedback execution unit.

5. The system according to claim 1, characterized in that, The feedback module also includes: The identifier register is configured to assign a corresponding state identifier bit to each of the second qubits, wherein the state identifier bit is a first state indicating that the feedback strategy of the corresponding second qubit has been generated, or a second state indicating that the feedback strategy of the corresponding second qubit has not been generated. The feedback execution unit is further configured to: in response to the feedback strategy for generating a single second qubit, update the state flag bit in the flag register corresponding to the second qubit from the second state to the first state.

6. The system according to claim 5, characterized in that, The instruction control unit is further configured to: Read the state flag bit corresponding to each second quantum bit in the flag register, and generate the total duration of multiple feedback strategies based on clock cycle monitoring; In response to multiple status flag bits being in the first state, or the total duration reaching a preset duration, an output instruction is sent to the feedback execution unit so that the feedback execution unit outputs the generated multiple feedback strategies.

7. The system according to claim 5, characterized in that, The feedback execution unit is further configured to: In response to the identifier reset instruction issued by the instruction control unit, the state identifier bit corresponding to each second quantum bit in the identifier register is reset from the first state to the second state; The identifier reset command is issued by the command control unit before each cycle execution.

8. The system according to claim 1, characterized in that, The feedback module also includes: The information input unit is configured to receive and aggregate the state information of the first qubits according to the hardware connection order of each readout module; The information output unit is configured to distribute the feedback strategy generated by the correlation mapping process to the corresponding readout module based on the hardware output order of the control and measurement chassis to which each second quantum bit belongs.

9. A global feedback control method for qubits, characterized in that, The method includes: The state information of multiple first qubits is obtained by multiple readout modules distributed in different measurement and control chassis, and the state information is sent to the feedback module. The feedback module performs association mapping processing on multiple states based on preset feedback configuration information to generate a feedback strategy for the second quantum bit measured and controlled by each of the measurement and control boxes, and distributes the generated feedback strategies to the readout module of the corresponding measurement and control box. The received feedback strategy is forwarded to the control module in the same measurement and control chassis through each of the readout modules; Each of the aforementioned control modules generates a corresponding control waveform based on the received feedback strategy and outputs the control waveform to the corresponding second quantum bit. The step of performing association mapping processing on multiple states based on preset feedback configuration information includes: parsing a preset instruction set through an instruction control unit and issuing corresponding control instructions to a feedback execution unit; and, in response to the received control instructions, performing association mapping processing on the states of multiple first qubits according to the mapping rules in the preset feedback configuration information through the feedback execution unit. The mapping rules include: a one-to-one mapping rule for determining the feedback strategy for a single second qubit based on the state information of a single first qubit; a many-to-one mapping rule for jointly determining the feedback strategy for a single second qubit based on the state information of multiple first qubits; a one-to-many mapping rule for jointly determining the feedback strategy for multiple second qubits based on the state information of a single first qubit; and a many-to-many mapping rule for jointly determining the feedback strategy for multiple second qubits based on the state information of multiple first qubits.

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