A graphics processor, a task execution method, an electronic device, and a storage medium

Abstract

The application discloses a kind of graphic processor, task execution method, electronic equipment and storage medium, graphic processor at least includes filter calculation unit, execution unit, first data loading unit and second data loading unit;First data loading unit is used to load the execution data of first filter task, and the execution data of first filter task is stored into first buffer;Second data loading unit is used to load the execution data of second filter task, and the execution data of second filter task is stored into second buffer;Execution unit is used to filter calculation unit in first buffer and second buffer, screening target execution data satisfying full load condition, and target execution data is transmitted to filter calculation unit;Filter calculation unit is used to filter calculation to target execution data.The technical scheme of the present application can realize the maximization of filter calculation unit bandwidth utilization, improve the execution efficiency of graphic processor filter task.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a graphics processor, a task execution method, an electronic device, and a storage medium. Background Technology

[0002] In a graphics processing unit (GPU), filtering is a very important computational task, such as bilinear interpolation, trilinear filtering, anisotropic filtering, and matrix dot product in graphics rendering tasks.

[0003] In existing technologies, to maximize the utilization of the filtering computation units within the graphics processing unit (GPU) and hide memory access latency, an architecture is often adopted where multiple front-end data loading units correspond to a smaller number of filtering computation units. For example, two front-end data loading units correspond to one filtering computation unit, thereby masking the idle time of the computation unit caused by memory access latency or other factors, and improving the utilization rate of the filtering computation unit. Assuming the bandwidth of the filtering computation unit is n (n>1), when n execution data are loaded in parallel through the data loading unit, the bandwidth of the filtering computation unit can be maximized.

[0004] However, not all filtering tasks can load execution data in parallel; scenarios involving serial loading of execution data are unavoidable. Taking a multi-layer texture reading task in a graphics processing unit (GPU) as an example, when performing filtering operations on the execution data for this task, the front-end data loading unit can only read data from different texture storage addresses in multiple iterations. Similarly, in cache access conflict scenarios, the front-end data loading unit can only serially and repeatedly read the different data required for each filtering calculation. Consequently, the amount of data processed by the filtering calculation unit in a single calculation process will be reduced, resulting in the computing unit's bandwidth not being fully utilized, leading to a waste of computing resources and time. Summary of the Invention

[0005] This invention provides a graphics processor, a task execution method, an electronic device, and a storage medium, which can maximize the bandwidth utilization of the filtering calculation unit and improve the execution efficiency of the graphics processor's filtering task.

[0006] According to one aspect of the present invention, a graphics processor is provided, the graphics processor including at least a filtering calculation unit, an execution unit, a first data loading unit, and a second data loading unit;

[0007] The first data loading unit is used to load the execution data of the first filtering task and store the execution data of the first filtering task into the first buffer.

[0008] The second data loading unit is used to load the execution data of the second filtering task and store the execution data of the second filtering task into the second buffer.

[0009] The execution unit is used to filter target execution data that meets the full load condition of the filtering calculation unit in the first buffer and the second buffer, and transmit the target execution data to the filtering calculation unit.

[0010] The filtering calculation unit is used to perform filtering calculations on the target execution data.

[0011] According to another aspect of the present invention, a task execution method is provided, applied to a graphics processor, the method comprising:

[0012] During the current clock cycle, load the execution data of the first filtering task and store the execution data of the first filtering task into the first buffer;

[0013] During the current clock cycle, load the execution data of the second filtering task and store the execution data of the second filtering task into the second buffer;

[0014] In the first buffer and the second buffer, target execution data that meets the full load condition of the filtering calculation unit is filtered, and the target execution data is filtered and calculated.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0016] At least one graphics processor; and

[0017] A memory communicatively connected to the at least one processor; wherein,

[0018] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the task execution method described in any embodiment of the present invention.

[0019] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute the task execution method described in any embodiment of the present invention.

[0020] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the task execution method described in any embodiment of the present invention.

[0021] The technical solution provided by this invention, by deploying a filtering calculation unit, an execution unit, a first data loading unit, and a second data loading unit in a graphics processor, wherein the first data loading unit is used to load the execution data of a first filtering task and store the execution data of the first filtering task in a first buffer, and the second data loading unit is used to load the execution data of a second filtering task and store the execution data of the second filtering task in a second buffer; the execution unit is used to filter target execution data that meets the full load condition of the filtering calculation unit in the first buffer and the second buffer, and transmit the target execution data to the filtering calculation unit, and the filtering calculation unit is used to perform filtering calculations on the target execution data, can maximize the bandwidth utilization of the filtering calculation unit and improve the execution efficiency of the graphics processor's filtering tasks.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a graphics processor performing a filtering task in the prior art;

[0025] Figure 2 This is a schematic diagram of the structure of a graphics processor according to Embodiment 1 of the present invention;

[0026] Figure 3 This is a flowchart of a task execution method provided in Embodiment 2 of the present invention;

[0027] Figure 4 This is a flowchart of another task execution method provided in Embodiment 3 of the present invention;

[0028] Figure 5 This is a flowchart of another task execution method provided in Embodiment 4 of the present invention;

[0029] Figure 6 This is a schematic diagram of a graphics processor performing a filtering task according to Embodiment 4 of the present invention;

[0030] Figure 7 This is a schematic diagram of the electronic device structure for implementing the task execution method of Embodiment 5 of the present invention. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] Figure 1 This is a schematic diagram of a graphics processor performing a filtering task in existing technology, such as... Figure 1 As shown, the graphics processor includes a filter unit (FILTER) with a bandwidth of 4, meaning it can perform calculations on four independent data points simultaneously within a single clock cycle. Furthermore, this filter unit can correspond to two data loading units (i.e.,...). Figure 1 The solid rectangle in the image is used to load the execution data for the filtering calculation.

[0034] Within the first clock cycle (CYCLE0), a data loading unit corresponding to the filtering calculation unit can load the execution data corresponding to the filtering task TaskA. If all the execution data corresponding to TaskA needs to be read in multiple loops, then the data loading unit can only load a portion of the execution data corresponding to TaskA within CYCLE0 (i.e., ...). Figure 1 The two solid circles corresponding to CYCLE0 (the dashed circles represent the execution data to be loaded in the next clock cycle) are used to transfer these two loaded execution data to the filtering calculation unit for calculation. Since the filtering calculation unit is occupied by the execution data corresponding to TaskA, the other data loading unit cannot load the execution data of other filtering tasks, thus causing the running thread of the other data loading unit to be blocked. For example, Figure 1As shown, "Task A Loop 0" is the data group in which Task A loads data in a loop within CYCLE0;

[0035] During the second clock cycle (CYCLE1), the remaining two execution data for TaskA are loaded (i.e., Figure 1 The solid circle corresponding to CYCLE1 and the dashed circle representing the execution data loaded in CYCLE0 are shown in the diagram. Simultaneously, the filtering calculation unit outputs the calculation results of the TaskA execution data input from CYCLE0. For example... Figure 1 As shown, "Task A Loop1" is the data group in which Task A loads data in a loop within CYCLE1;

[0036] Within the third clock cycle (CYCLE2), another data loading unit corresponding to the filtering calculation unit can load the execution data corresponding to the filtering task TaskB. If all the execution data corresponding to TaskB can be loaded in parallel, then the data loading unit will be able to load all the execution data corresponding to TaskB within CYCLE2 (i.e., ...). Figure 1 (The solid-line triangle corresponding to CYCLE2 in the middle), and transmits these execution data to the filtering calculation unit. At the same time, the filtering calculation unit outputs the calculation results of the remaining execution data of TaskA input in CYCLE1; where, for example Figure 1 As shown, "Task B Loop 0" is the data group in which Task B loads data in a loop within CYCLE2;

[0037] Within the fourth clock cycle (CYCLE3), a data loading unit corresponding to the filtering calculation unit can load the execution data corresponding to the filtering task TaskC. If all the execution data corresponding to TaskC can be loaded in parallel, then the data loading unit will be able to load all the execution data corresponding to TaskC within CYCLE3 (i.e., ...). Figure 1 (The solid-line diamond corresponding to CYCLE3 in the middle), and transmits these execution data to the filtering calculation unit. At the same time, the filtering calculation unit outputs the calculation results of the TaskB execution data input by CYCLE2. Among them, such as Figure 1 As shown, "Task C Loop 0" is the data group that Task C loads data in a loop within CYCLE3.

[0038] like Figure 1 As shown, the bandwidth of the filtering calculation unit will be 50% idle under CYCLE0 and CYCLE1. Under four clock cycles CYCLE0-CYCLE3, the filtering calculation unit completes two filtering tasks, and the data loading unit loads the execution data of three filtering tasks.

[0039] For filtering tasks performed by graphics processors, the scenario of sequentially loading execution data is unavoidable. Therefore, the amount of data calculated by the filtering calculation unit in a single calculation process will be reduced, resulting in the calculation unit bandwidth not being fully utilized, causing a waste of computing resources and time.

[0040] Therefore, this embodiment provides a graphics processor. Figure 2 This is a schematic diagram of the structure of the graphics processor, as shown below. Figure 2 As shown, the graphics processor includes at least a filtering calculation unit 201, an execution unit 202, a first data loading unit 203, and a second data loading unit 204.

[0041] The first data loading unit 203 is used to load the execution data of the first filtering task and store the execution data of the first filtering task into the first buffer.

[0042] The second data loading unit 204 is used to load the execution data of the second filtering task and store the execution data of the second filtering task into the second buffer.

[0043] Execution unit 202 is used to filter target execution data that meets the full load condition of the filtering calculation unit in the first buffer and the second buffer, and transmit the target execution data to the filtering calculation unit;

[0044] The filtering calculation unit 201 is used to perform filtering calculations on the target execution data.

[0045] In this embodiment, each data loading unit corresponds to a data throttling buffer. Taking two data loading units as an example, the first data loading unit 203 corresponds to the first buffer, and the second data loading unit 204 corresponds to the second buffer. The buffers are used to cache the execution data loaded by the data loading units. Specifically, within the current clock cycle of the graphics processor, the first data loading unit 203 can load the execution data corresponding to the first filtering task (i.e., the data that needs to be filtered) and store the execution data in the first buffer. At the same time, the second data loading unit 204 can load the execution data corresponding to the second filtering task and store the execution data in the second buffer.

[0046] In one embodiment of this invention, the bandwidth of the filtering calculation unit 201 is N, used to calculate N execution data of the same filtering task within a single clock cycle. The number of execution data loaded by the data loading unit (i.e., the first data loading unit 203 or the second data loading unit 204) within a single clock cycle is M, where M and N are positive integers, and N... M. The depth of the buffer (i.e., the first buffer or the second buffer) is L, where L is an integer greater than 1. The buffer is used to store the execution data corresponding to L filtering tasks simultaneously.

[0047] Within the current clock cycle, the execution unit 202 can determine whether the execution data in the first buffer and the second buffer meet the full load condition of the filtering calculation unit 201 based on the bandwidth of the filtering calculation unit 201, and take the execution data that meets the full load condition as the target execution data, and then transmit this target execution data to the filtering calculation unit 201.

[0048] After obtaining the target execution data, the filtering calculation unit 201 can process the target execution data using a preset filtering algorithm. Optionally, the filtering algorithm may include bilinear interpolation, trilinear filtering, anisotropic filtering, matrix dot product, etc., and this embodiment does not limit it.

[0049] In this embodiment, for the scenario of serially loading execution data in the graphics processor filtering task, a corresponding data interception buffer is established for each data loading unit, and only the target execution data that meets the full load condition of the filtering calculation unit is transmitted. For example, if the execution data in the first buffer does not meet the full load condition, but the execution data in the second buffer does meet the full load condition, the execution data in the second buffer will occupy the filtering calculation unit first, which can avoid the filtering calculation unit from being idle, thereby solving the problem of bandwidth waste and low execution efficiency of filtering tasks in the prior art, thus maximizing the bandwidth utilization of the filtering calculation unit. Secondly, in order to improve the execution efficiency of the filtering task, compared with the method of directly expanding the number of filtering calculation units in the prior art, the hardware cost of establishing the data interception buffer in this embodiment is lower, and it is more adaptable to complex data flow access patterns or task scenarios.

[0050] The technical solution provided in this embodiment, by deploying a filtering calculation unit, an execution unit, a first data loading unit, and a second data loading unit in the graphics processor, wherein the first data loading unit is used to load the execution data of the first filtering task and store the execution data of the first filtering task in a first buffer, and the second data loading unit is used to load the execution data of the second filtering task and store the execution data of the second filtering task in a second buffer; the execution unit is used to filter target execution data that meets the full load condition of the filtering calculation unit in the first buffer and the second buffer, and transmit the target execution data to the filtering calculation unit, and the filtering calculation unit is used to perform filtering calculations on the target execution data, can maximize the bandwidth utilization of the filtering calculation unit and improve the execution efficiency of the graphics processor's filtering tasks.

[0051] This second embodiment provides a task execution method. Figure 3 The flowchart illustrates the task execution method. This embodiment is applicable to a graphics processor loading execution data for a filtering task and transmitting the execution data to a filtering calculation unit, enabling the filtering calculation unit to perform calculations on the execution data. This method can be executed by the graphics processor. Figure 3 As shown, the method includes:

[0052] Step 310: During the current clock cycle, load the execution data of the first filtering task and store the execution data of the first filtering task into the first buffer.

[0053] Step 320: During the current clock cycle, load the execution data of the second filtering task and store the execution data of the second filtering task into the second buffer.

[0054] Step 330: In the first buffer and the second buffer, filter the target execution data that meets the full load condition of the filtering calculation unit, and perform filtering calculation on the target execution data.

[0055] The technical solution provided in this embodiment maximizes the bandwidth utilization of the filtering calculation unit and improves the execution efficiency of the graphics processor's filtering tasks by loading the execution data of the first filtering task in the current clock cycle, storing the execution data of the first filtering task in the first buffer, loading the execution data of the second filtering task in the current clock cycle, storing the execution data of the second filtering task in the second buffer, and filtering the target execution data in the first and second buffers to meet the full load conditions of the filtering calculation unit.

[0056] Figure 4 This is a flowchart of another task execution method provided in Embodiment 3 of the present invention. This embodiment is a further refinement of the above embodiments. Figure 4 As shown, the method includes:

[0057] Step 410: During the current clock cycle, load the execution data of the first filtering task and store the execution data of the first filtering task into the first buffer.

[0058] Step 420: During the current clock cycle, load the execution data of the second filtering task and store the execution data of the second filtering task into the second buffer.

[0059] Step 430: Determine whether the number of data to be executed in the first buffer and the number of data to be executed in the second buffer are equal to the maximum number of data processed by the filtering calculation unit in a single clock cycle. If yes, proceed to step 440; otherwise, proceed to step 450.

[0060] Step 440: Obtain the triggering order of the first filtering task and the second filtering task, and filter the target execution data according to the triggering order.

[0061] In this embodiment, specifically, within the current clock cycle, if the number of executed data in the first buffer and the number of executed data in the second buffer are both equal to the maximum number of data, then the triggering order of the first filtering task and the second filtering task is obtained, and the filtering task with the earlier triggering order is taken as the target filtering task, and then the execution data corresponding to the target filtering task is taken as the target execution data to be transmitted.

[0062] Step 450: If the number of execution data in the second buffer is equal to the maximum number of data, and the number of execution data in the first buffer is less than the maximum number of data, then the execution data in the second buffer is used as the target execution data.

[0063] In this embodiment, specifically, if the amount of data to be executed in the first buffer is less than the maximum amount of data that the filtering calculation unit can process in a single clock cycle, that is, if the execution data of the first filtering task needs to be loaded serially in multiple steps, then the remaining execution data of the first filtering task can be loaded in the next clock cycle and stored in the first buffer.

[0064] Accordingly, within the current clock cycle, if the amount of data to be executed in the first buffer is equal to the maximum amount of data, and the amount of data to be executed in the second buffer is less than the maximum amount of data, then the data to be executed in the first buffer is used as the target data to be executed. In the next clock cycle, the remaining data to be executed corresponding to the second filtering task is loaded by the second data loading unit, and then the remaining data to be executed corresponding to the second filtering task is stored in the second buffer.

[0065] Step 460: The target execution data is transmitted to the filtering calculation unit, and the target execution data is processed by the filtering calculation unit.

[0066] The technical solution provided in this embodiment loads the execution data of the first filtering task in the current clock cycle and stores the execution data of the first filtering task in the first buffer. Then, it loads the execution data of the second filtering task in the current clock cycle and stores the execution data of the second filtering task in the second buffer. If the number of execution data in both the first and second buffers is equal to the maximum number of data processed by the filtering calculation unit in a single clock cycle, the target execution data is filtered according to the triggering order of the first and second filtering tasks. If the number of execution data in the second buffer is equal to the maximum number of data, and the number of execution data in the first buffer is less than the maximum number of data, the execution data in the second buffer is used as the target execution data. Finally, the target execution data is transmitted to the filtering calculation unit. By processing the target execution data through the filtering calculation unit, the bandwidth utilization of the filtering calculation unit can be maximized, thereby improving the execution efficiency of the graphics processor's filtering tasks.

[0067] Figure 5 This is a flowchart of a task execution method provided in Embodiment 4 of the present invention. This embodiment is a further refinement of the above embodiments. Figure 5 As shown, the method includes:

[0068] Step 510: Within the current clock cycle, determine whether there is remaining cache capacity in the first buffer according to the preset depth corresponding to the first buffer. If yes, proceed to step 520; otherwise, proceed to step 550.

[0069] The preset depth can be the upper limit of the amount of data that the buffer can hold. Optionally, the remaining buffer capacity can be determined based on the amount of data currently stored in the first buffer and the preset depth.

[0070] In this embodiment, specifically, if the first buffer has remaining cache capacity, then step 520 is performed to load the execution data; if the first buffer does not have remaining cache capacity, that is, when the first buffer has been filled by the execution data loaded by the first data loading unit in the current clock cycle, then step 550 is performed to filter the target execution data.

[0071] Step 520: Load the execution data of the first filtering task and store the execution data of the first filtering task into the first buffer.

[0072] Step 530: Based on the preset depth corresponding to the second buffer, determine whether there is remaining buffer capacity in the second buffer. If yes, proceed to step 540; otherwise, proceed to step 550.

[0073] In this embodiment, specifically, if the second buffer has remaining cache capacity, then step 540 is executed to load the execution data; if the second buffer does not have remaining cache capacity, that is, when the second buffer has been filled by the execution data loaded by the second data loading unit in the current clock cycle, then step 550 is executed to filter the target execution data.

[0074] Step 540: Load the execution data of the second filtering task and store the execution data of the second filtering task into the second buffer.

[0075] Step 550: In the first buffer and the second buffer, filter the target execution data that meets the full load condition of the filtering calculation unit, and transfer the target execution data to the filtering calculation unit.

[0076] In one embodiment of this example, filtering target execution data that meets the full load condition of the filtering calculation unit in the first buffer and the second buffer includes: if there are multiple filtering tasks corresponding to the full load condition of the filtering calculation unit in the first buffer or the second buffer, then the target execution data of the target filtering task is filtered according to the triggering order of the multiple filtering tasks.

[0077] In a specific embodiment, taking the first buffer as an example, if there are multiple filtering tasks corresponding to execution data in the first buffer at the same time, and these execution data all meet the full load condition of the filtering calculation unit, then the triggering order corresponding to the multiple filtering tasks can be obtained, and the filtering task with the earliest triggering order can be taken as the target filtering task.

[0078] Step 560: The target execution data is processed by the filtering calculation unit.

[0079] Based on the above embodiments, Figure 6 This is a schematic diagram of a graphics processor performing a filtering task in this embodiment, as shown below. Figure 6 As shown, the graphics processor includes a filter unit (FILTER) with a bandwidth of 4, meaning it can perform calculations on four independent data points simultaneously within a single clock cycle. Furthermore, this filter unit can correspond to two data loading units (i.e.,...). Figure 6 The solid-line rectangle in the image includes the first data loading unit and the second data loading unit. Each data loading unit corresponds to a data throttling buffer assemble fifo.

[0080] Within the first clock cycle (CYCLE0), the first data loading unit can load the execution data corresponding to the filtering task TaskA. If all the execution data corresponding to TaskA needs to be read in multiple loops, then the first data loading unit can only load a portion of the execution data corresponding to TaskA within CYCLE0 (i.e., ...). Figure 6 The two solid circles corresponding to CYCLE0 and the dashed circles represent the execution data to be loaded in the next clock cycle. These two loaded execution data are stored in the first buffer. Simultaneously, the second data loading unit can load the execution data corresponding to the filtering task TaskB. If all the execution data corresponding to TaskB can be loaded in parallel, then the second data loading unit can load all the execution data corresponding to TaskB within CYCLE0 (i.e., ...). Figure 6 (The solid triangle corresponding to CYCLE0 in the middle), and store these execution data into the second buffer. Since the execution data in the second buffer meets the full load condition of the filtering calculation unit, the execution data in the second buffer can be transferred to the filtering calculation unit, which will then perform calculation processing on the execution data.

[0081] During the second clock cycle (CYCLE1), all execution data corresponding to TaskA is loaded (i.e., Figure 6 The solid circle corresponding to CYCLE1 is stored in the first buffer. Simultaneously, the second data loading unit can load the execution data corresponding to the filtering task TaskC. If all execution data corresponding to TaskC can be loaded in parallel, then the second data loading unit can load all execution data corresponding to TaskC within CYCLE1 (i.e., ...). Figure 6 (The solid diamond corresponding to CYCLE1 in the middle), and store these execution data into the second buffer. At this time, the execution data in the first buffer and the second buffer both meet the full load condition of the filter calculation unit. However, since the triggering order of TaskA is earlier than that of TaskC, the execution data in the first buffer is transferred to the filter calculation unit first, and the filter calculation unit performs calculation processing on the execution data. At the same time, the filter calculation unit outputs the calculation result of the TaskB execution data input by CYCLE0.

[0082] Within the third clock cycle (CYCLE2), the first data loading unit can load the execution data corresponding to the filtering task TaskD. If all the execution data corresponding to TaskD needs to be read in multiple loops, then the first data loading unit can only load a portion of the execution data corresponding to TaskD within CYCLE2 (i.e., ...). Figure 6In the CYCLE2 section, the solid-lined four-pointed star represents the data to be loaded in the next clock cycle, while the dashed-lined four-pointed star represents the execution data to be loaded in the next clock cycle. Since there is spare capacity in the second buffer, the second data loading unit can also load the execution data corresponding to the filtering task TaskE, and load the execution data corresponding to TaskE (i.e.,...) Figure 6 The solid line ⊕ corresponding to CYCLE2 is stored in the second buffer, and the filtering calculation unit outputs the calculation result of the TaskA execution data input from CYCLE1.

[0083] Will Figure 6 and Figure 1 The comparison shows that the task execution method provided in this embodiment can enable the filtering calculation unit to complete the filtering task that the existing scheme executes in four clock cycles in three clock cycles, ensuring that the bandwidth utilization of the filtering calculation unit reaches 100%. By constructing a data throttling buffer corresponding to each data loading unit, the data loading unit can load the execution data to the maximum extent. The execution data of a certain filtering task that has been loaded will not block the execution data of the next task, but will be uniformly cached in a fixed buffer. Compared with the prior art, which loads the execution data of three filtering tasks in four clock cycles, this application can load the execution data of five filtering tasks in three clock cycles, thereby greatly improving the loading efficiency of the filtering task execution data.

[0084] The technical solution provided in this embodiment determines whether there is remaining cache capacity in the first buffer based on the preset depth corresponding to the first buffer. If so, the execution data corresponding to the first filtering task is loaded by the first data loading unit and stored in the first buffer. Based on the preset depth corresponding to the second buffer, it determines whether there is remaining cache capacity in the second buffer. If so, the execution data corresponding to the second filtering task is loaded by the second data loading unit and stored in the second buffer. Target execution data that meets the full load condition of the filtering calculation unit is filtered in the first and second buffers and transmitted to the filtering calculation unit. By processing the target execution data through the filtering calculation unit, the bandwidth utilization of the filtering calculation unit can be maximized, thereby improving the execution efficiency of the graphics processor's filtering task.

[0085] Figure 7A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0086] like Figure 7 As shown, the electronic device 10 includes at least one graphics processor 11 and a memory, such as read-only memory (ROM) or random access memory (RAM), communicatively connected to the at least one graphics processor 11. The memory stores computer programs executable by the at least one graphics processor. The graphics processor 11 can perform various appropriate actions and processes based on the computer program stored in the read-only memory 12 or loaded from the storage unit 18 into the random access memory 13. The random access memory 13 can also store various programs and data required for the operation of the electronic device 10. The graphics processor 11, read-only memory 12, and random access memory 13 are interconnected via a bus 14. Input / output (I / O) interfaces are also connected to the bus 14.

[0087] Multiple components in electronic device 10 are connected to input / output interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of monitors, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks. Graphics processor 11 executes the various methods and processes described above, such as task execution methods.

[0088] In some embodiments, the task execution method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via read-only memory 12 and / or communication unit 19. When the computer program is loaded into random access memory 13 and executed by graphics processor 11, one or more steps of the task execution method described above may be performed. Alternatively, in other embodiments, graphics processor 11 may be configured to execute the task execution method by any other suitable means (e.g., by means of firmware).

[0089] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chips (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0090] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0091] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0092] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0093] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0094] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system. It addresses the shortcomings of traditional physical hosts and Virtual Private Servers (VPS) in terms of management difficulty and weak business scalability.

[0095] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0096] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A graphics processor, characterized in that, The graphics processor includes at least a filtering calculation unit, an execution unit, a first data loading unit, and a second data loading unit; The first data loading unit is used to load the execution data of the first filtering task and store the execution data of the first filtering task into the first buffer. The second data loading unit is used to load the execution data of the second filtering task and store the execution data of the second filtering task into the second buffer. The execution unit is used to filter target execution data that meets the full load condition of the filtering calculation unit in the first buffer and the second buffer, and transmit the target execution data to the filtering calculation unit. The filtering calculation unit is used to perform filtering calculations on the target execution data; The execution unit is further configured to: obtain the triggering order of the first filtering task and the second filtering task if the number of execution data in the first buffer and the number of execution data in the second buffer are both equal to the maximum number of data processed by the filtering calculation unit in a single clock cycle; and filter the target execution data according to the triggering order of the first filtering task and the second filtering task.

2. The graphics processor according to claim 1, characterized in that, The bandwidth of the filtering calculation unit is N, which is used to calculate N execution data of the same filtering task in a single clock cycle; the number of execution data loaded by the data loading unit in a single clock cycle is M. Where M and N are positive integers, and N M.

3. The graphics processor according to claim 1, characterized in that, The depth of the buffer is L; Where L is an integer greater than 1; the buffer is used to store the execution data corresponding to L filtering tasks simultaneously.

4. A task execution method, characterized in that, Applied to the graphics processor of claim 1, the method includes: During the current clock cycle, load the execution data of the first filtering task and store the execution data of the first filtering task into the first buffer; During the current clock cycle, load the execution data of the second filtering task and store the execution data of the second filtering task into the second buffer; In the first buffer and the second buffer, target execution data that meets the full load condition of the filtering calculation unit is filtered, and the target execution data is filtered and calculated. Specifically, in the first buffer and the second buffer, the target execution data that meets the full load condition of the filtering calculation unit is filtered, including: if the number of execution data in the first buffer and the number of execution data in the second buffer are both equal to the maximum number of data processed by the filtering calculation unit in a single clock cycle, then the triggering order of the first filtering task and the second filtering task is obtained; and the target execution data is filtered according to the triggering order of the first filtering task and the second filtering task.

5. The method according to claim 4, characterized in that, In the first buffer and the second buffer, target execution data that meets the full load condition of the filtering calculation unit is filtered, including: Determine whether the number of data to be processed in the first buffer and the number of data to be processed in the second buffer are equal to the maximum number of data processed by the filtering calculation unit in a single clock cycle; If the amount of execution data in the second buffer is equal to the maximum amount of data, and the amount of execution data in the first buffer is less than the maximum amount of data, then the execution data in the second buffer will be used as the target execution data.

6. The method according to claim 5, characterized in that, After using the execution data in the second buffer as the target execution data, the process also includes: In the next clock cycle, the remaining execution data of the first filtering task is loaded and stored in the first buffer.

7. The method according to claim 4, characterized in that, Loading the execution data of the first filtering task and storing the execution data of the first filtering task into the first buffer includes: Based on the preset depth corresponding to the first buffer, determine whether there is remaining cache capacity in the first buffer; If so, load the execution data of the first filtering task and store the execution data of the first filtering task into the first buffer.

8. The method according to claim 4, characterized in that, Load the execution data of the second filtering task and store the execution data of the second filtering task into the second buffer, including: Based on the preset depth corresponding to the second buffer, determine whether there is remaining cache capacity in the second buffer; If so, load the execution data of the second filtering task and store the execution data of the second filtering task into the second buffer.

9. The method according to claim 4, characterized in that, In the first buffer and the second buffer, target execution data that meets the full load condition of the filtering calculation unit is filtered, including: If there are multiple filtering tasks in the first buffer or the second buffer that satisfy the full load condition of the filtering calculation unit, then the target execution data is filtered according to the triggering order of the multiple filtering tasks.

10. An electronic device, characterized in that, The electronic device includes: At least one graphics processor; A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one graphics processor to enable the at least one graphics processor to perform the task execution method according to any one of claims 4-9.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the task execution method according to any one of claims 4-9.

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