Capacitor and method of manufacturing the same, semiconductor structure

Abstract

Embodiments of the present disclosure provide a capacitor and a manufacturing method thereof and a semiconductor structure, to solve how to improve stability and durability of the capacitor. The capacitor comprises: a first electrode layer and a second electrode layer arranged at intervals, a capacitor dielectric layer, and at least one of a first interface layer and a second interface layer, the capacitor dielectric layer being located between the first electrode layer and the second electrode layer; the first interface layer is located between the first electrode layer and the capacitor dielectric layer, and the second interface layer is located between the second electrode layer and the capacitor dielectric layer, wherein the first interface layer and the second interface layer each have a monomolecular layer structure. In this way, the stability and durability of the capacitor are improved.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more particularly to a capacitor, a method for manufacturing the capacitor, and a semiconductor structure. Background Technology

[0002] A capacitor is a passive electronic component used to store electrical charge. It typically consists of a first electrode layer, a second electrode layer, and a dielectric layer located between the first and second electrode layers. Traditionally, the dielectric layer is made of silicon dioxide. Due to its low dielectric constant, the thickness of the dielectric layer needs to be continuously reduced to obtain sufficient capacitance. When the thickness of the dielectric layer decreases to a certain level, the quantum tunneling effect intensifies dramatically, leading to an exponential increase in leakage current, which in turn increases device power consumption and reduces reliability.

[0003] To address this issue, the industry has proposed replacing traditional silicon dioxide with high-dielectric-constant (High-K) materials, hoping to increase the physical thickness of the capacitor dielectric layer while maintaining the same equivalent capacitance, thereby suppressing tunneling leakage, reducing device power consumption, and improving reliability. However, as device dimensions continue to shrink, the thickness of the capacitor dielectric layer is constantly decreasing, weakening the advantages of high-dielectric-constant materials and leading to a decrease in the actual dielectric constant (K value) of the capacitor dielectric layer or an increase in leakage current. Summary of the Invention

[0004] This disclosure provides a capacitor, a method for manufacturing the same, and a semiconductor structure.

[0005] The technical solution of this disclosure embodiment is implemented as follows: On one hand, embodiments of this disclosure provide a capacitor, the capacitor comprising: a first electrode layer and a second electrode layer disposed at intervals; a capacitor dielectric layer located between the first electrode layer and the second electrode layer; at least one of a first interface layer and a second interface layer, wherein the first interface layer is located between the first electrode layer and the capacitor dielectric layer, and the second interface layer is located between the second electrode layer and the capacitor dielectric layer, wherein both the first interface layer and the second interface layer have a monolayer structure.

[0006] In some embodiments, the capacitor further includes at least one of a third interface layer and a fourth interface layer; the third interface layer is located between the first interface layer and the first electrode layer, wherein the density of the third interface layer is greater than the density of the first electrode layer; the fourth interface layer is located between the second interface layer and the second electrode layer, wherein the density of the fourth interface layer is greater than the density of the second electrode layer.

[0007] In some embodiments, the material of the third interface layer comprises a metal nitride; the material of the fourth interface layer comprises a metal nitride.

[0008] In some embodiments, where the capacitor includes the first interface layer, the capacitor further includes a fifth interface layer and a sixth interface layer, wherein the fifth interface layer is located between the first electrode layer and the first interface layer, and the sixth interface layer is located between the first interface layer and the capacitor dielectric layer, wherein the fifth interface layer and the first electrode layer are made of the same material, the sixth interface layer and the capacitor dielectric layer are made of the same material, the fifth interface layer and the first interface layer have the same elements but different materials, and the sixth interface layer and the first interface layer have the same elements but different materials.

[0009] In some embodiments, where the capacitor includes the second interface layer, the capacitor further includes a seventh interface layer and an eighth interface layer, wherein the seventh interface layer is located between the capacitor dielectric layer and the second interface layer, and the eighth interface layer is located between the second interface layer and the second electrode layer, wherein the seventh interface layer and the capacitor dielectric layer are made of the same material, the eighth interface layer and the second electrode layer are made of the same material, the seventh interface layer and the second interface layer have the same elements but different materials, and the eighth interface layer and the second interface layer have the same elements but different materials.

[0010] In some embodiments, the material of the first interface layer includes an organosilane or a polymer; the material of the second interface layer includes the organosilane or the polymer.

[0011] In some embodiments, the polymeric material includes polymethyl methacrylate or a polymer composed of poly(3,4-ethylenedioxythiophene) and polystyrene sulfonate.

[0012] In some embodiments, the thickness of the first interface layer ranges from 0.5 nm to 3 nm; the thickness of the second interface layer ranges from 0.5 nm to 3 nm.

[0013] In some embodiments, the material of the capacitor dielectric layer includes metal oxides or perovskites.

[0014] On the other hand, embodiments of this disclosure also provide a method for manufacturing a capacitor, the method comprising: forming a first electrode layer; sequentially forming a capacitor dielectric layer and a second electrode layer on the surface of the first electrode layer; forming a first interface layer between the first electrode layer and the capacitor dielectric layer and / or forming a second interface layer between the second electrode layer and the capacitor dielectric layer, wherein the first interface layer and the second interface layer both have a monolayer structure.

[0015] In some embodiments, the step of forming the first interface layer includes: depositing a passivation material having a monolayer structure on the surface of the first electrode layer facing the capacitor dielectric layer to form the first interface layer; the step of forming the second interface layer includes: depositing the passivation material having the monolayer structure on the surface of the capacitor dielectric layer facing the second electrode layer to form the second interface layer.

[0016] In some embodiments, the step of forming the first interface layer includes: spin-coating a polymeric material onto the surface of the first electrode layer facing the capacitor dielectric layer to form the first interface layer; the step of forming the second interface layer includes: spin-coating a polymeric material onto the surface of the capacitor dielectric layer facing the second electrode layer to form the second interface layer.

[0017] In some embodiments, the method of manufacturing the capacitor further includes: forming a third interface layer between the first interface layer and the first electrode layer and / or forming a fourth interface layer between the second interface layer and the second electrode layer, wherein the density of the third interface layer is greater than the density of the first electrode layer, and the density of the fourth interface layer is greater than the density of the second electrode layer.

[0018] In some embodiments, the step of forming the third interface layer includes: nitriding the surface of the first electrode layer facing the capacitor dielectric layer to form the third interface layer; the step of forming the fourth interface layer includes: depositing a conductive layer on the surface of the capacitor dielectric layer facing the second electrode layer; and performing the nitriding treatment on the surface of the conductive layer to form the fourth interface layer.

[0019] In some embodiments, when the first interface layer is formed between the first electrode layer and the capacitor dielectric layer, the method of manufacturing the capacitor further includes: forming a fifth interface layer between the first electrode layer and the first interface layer, wherein the fifth interface layer and the first electrode layer are made of the same material, and the fifth interface layer and the first interface layer have the same elements but different materials; and forming a sixth interface layer between the first interface layer and the capacitor dielectric layer, wherein the sixth interface layer and the capacitor dielectric layer are made of the same material, and the sixth interface layer and the first interface layer have the same elements but different materials.

[0020] In some embodiments, when a second interface layer is formed between the second electrode layer and the capacitor dielectric layer, the method of manufacturing the capacitor further includes: forming a seventh interface layer between the capacitor dielectric layer and the second interface layer, wherein the seventh interface layer and the capacitor dielectric layer are made of the same material, and the seventh interface layer and the second interface layer have the same elements but different materials; and forming an eighth interface layer between the second interface layer and the second electrode layer, wherein the eighth interface layer and the second electrode layer are made of the same material, and the eighth interface layer and the second interface layer have the same elements but different materials.

[0021] In another aspect, embodiments of this disclosure also provide a semiconductor structure, the semiconductor structure comprising: a transistor structure; and the capacitor described in any of the above embodiments, wherein the source or drain of the transistor structure is connected to the first electrode layer of the capacitor.

[0022] In this embodiment, by providing a first interface layer with a monolayer structure between the first electrode layer and the dielectric layer of the capacitor, an ultrathin, controllable, and stable first interface layer can be actively constructed between the first electrode layer and the dielectric layer, thereby helping to suppress interfacial reactions between the first electrode layer and the dielectric layer. Similarly, by providing a second interface layer with a monolayer structure between the second electrode layer and the dielectric layer, an ultrathin, controllable, and stable second interface layer can be actively constructed between the second electrode layer and the dielectric layer, thereby helping to suppress interfacial reactions between the second electrode layer and the dielectric layer. This helps to reduce the defect density of the dielectric layer and control the evolution of its microstructure, thereby improving the stability and durability of the capacitor. Attached Figure Description

[0023] Figure 1 A cross-sectional view of a first type of capacitor provided in an embodiment of this disclosure; Figure 2 A cross-sectional view of a second type of capacitor provided in an embodiment of this disclosure; Figure 3 A cross-sectional view of a third type of capacitor provided in an embodiment of this disclosure; Figure 4 A cross-sectional view of a fourth type of capacitor provided in an embodiment of this disclosure; Figure 5 This is a schematic flowchart illustrating a method for manufacturing a capacitor according to an embodiment of the present disclosure. Detailed Implementation

[0024] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0025] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0026] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0028] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0030] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0031] In one example, the process for forming a capacitor includes: preparing a first electrode layer (also known as a lower electrode) on the surface of a substrate; subsequently depositing a high dielectric constant material on the first electrode layer and performing an annealing process to form a capacitor dielectric layer; and finally preparing a second electrode layer (also known as an upper electrode) on the capacitor dielectric layer to form a complete capacitor structure.

[0032] However, during the formation of the capacitor dielectric layer, chemical reactions or interface defects can occur between the first electrode layer and the high dielectric constant material. Specifically, on the one hand, interdiffusion and chemical reactions can occur between the first electrode layer and the high dielectric constant material. For example, the material of the first electrode layer (e.g., titanium nitride (TiN)) can chemically react with a high dielectric constant material (e.g., hafnium dioxide (HfO2)) to form an interface layer (e.g., titanium oxynitride (TiON)) with low K value and high defects, resulting in a decrease in the effective K value of the capacitor dielectric layer and an increase in leakage current. On the other hand, oxygen vacancy accumulation can occur between the first electrode layer and the high dielectric constant material. For example, when a high dielectric constant material (e.g., hafnium dioxide (HfO2), zirconium dioxide (ZrO2), etc.) comes into contact with a material of the first electrode layer (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), due to the difference in their oxidation potentials, oxygen ions diffuse from the region of high chemical potential to the region of low chemical potential. When the first electrode layer has a strong affinity for oxygen, it will "steal" oxygen from the high-dielectric-constant material, leaving a large number of oxygen vacancies at the interface. This leads to severe bias temperature instability and random telegraph noise. Furthermore, when using high-dielectric-constant materials to form the capacitor dielectric layer, these materials are typically deposited in an amorphous state. Therefore, if the nucleation density is insufficient, the annealing temperature is too high, or the film thickness is too thin during subsequent annealing, a few nuclei will preferentially grow, resulting in a coarse and non-uniform microstructure. This creates localized weaknesses and causes the capacitor dielectric layer to break down far below its design life or rated voltage.

[0033] To address at least one of the aforementioned technical problems, in some embodiments, an additional interface barrier layer is provided between the first electrode layer and the capacitor dielectric layer to suppress interfacial reactions between them. For example, an interface barrier layer made of titanium oxide (TiO2) or aluminum oxide (Al2O3) is provided between the first electrode layer and the capacitor dielectric layer. However, while these interface barrier layer materials are effective in conventional schemes using hafnium dioxide (HfO2)-based materials as high-dielectric-constant materials for the capacitor dielectric layer, they exhibit significant drawbacks in schemes using perovskite materials as high-dielectric-constant materials for the capacitor dielectric layer. Specifically, an inherent chemical reaction occurs between the perovskite material and the interface barrier layer material.

[0034] For example, alumina (Al₂O₃), as an amphoteric oxide, reacts with basic strontium oxide (SrO) in perovskite materials such as strontium titanate (SrTiO₃) to form a low-dielectric-constant strontium aluminate (SrAl₂O₄) impurity phase. Titanium oxide (TiO₂), on the other hand, readily undergoes a solid-state reaction with barium oxide (BaO) in perovskite materials such as barium titanate (BaTiO₃) to form non-stoichiometric products and generate oxygen vacancies. Simultaneously, aluminum ions (Al₂O₃) are also generated.3+ ) or titanium ions (Ti 4+ Aluminum oxide (Al₂O₃) can interdiffuse into the perovskite lattice, causing doping defects. Furthermore, the oxidation potential mismatch between Al₂O₃ and perovskite drives oxygen vacancies to accumulate at the interface. Additionally, titanium oxide (TiO₂) is readily reduced to trivalent titanium ions (TiO₂) under high-temperature reducing atmospheres. 3+ This results in electronic defects that increase leakage current, and these reactions together destroy the crystal structure and electrical properties of perovskite.

[0035] In view of at least one of the above-mentioned technical problems, this disclosure provides a capacitor.

[0036] Figure 1 A cross-sectional view of a first type of capacitor provided in an embodiment of this disclosure. The following is in conjunction with... Figure 1 The capacitor provided in the embodiments of this disclosure will be described by way of example.

[0037] Reference Figure 1 As shown, this embodiment of the present disclosure provides a capacitor 100, which includes a first electrode layer 102, a second electrode layer 104, a dielectric layer 106, and a first interface layer 108. The first electrode layer 102 and the second electrode layer 104 are spaced apart, the dielectric layer 106 is located between the first electrode layer 102 and the second electrode layer 104, and the first interface layer 108 is located between the first electrode layer 102 and the dielectric layer 106. The first interface layer 108 has a monolayer structure. Specifically, a monolayer structure refers to an ordered two-dimensional thin film with a thickness of only a single molecule size, formed by closely packed molecules.

[0038] In some embodiments, the materials of the first electrode layer 102 and the second electrode layer 104 both include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polycrystalline silicon, or any combination thereof.

[0039] In some embodiments, the capacitor dielectric layer 106 is made of a high dielectric constant material, such as a metal oxide or perovskite. The metal oxide includes hafnium-based oxide materials, such as hafnium dioxide (HfO2) and hafnium silicate (HfSiO2). x (x is approximately 3.5 to 4.5), hafnium oxynitride (HfON), hafnium zirconium oxide (HfZrO) x(x is approximately 1.8 to 2.2), etc. Perovskite materials are a class of composite oxides with the general formula ABO3 or derived structures, mainly including titanate materials, such as barium titanate (BaTiO3), strontium titanate (SrTiO3), barium strontium titanate (BST), lead titanate (PbTiO3), lead zirconate titanate (PZT), etc. Due to their extremely high intrinsic dielectric constant (reaching hundreds or even thousands), perovskite materials are ideal candidates for next-generation high-density storage and advanced integration. In this embodiment, by setting a first interface layer 108 with a monomolecular structure between the first electrode layer 102 and the capacitor dielectric layer 106, an ultrathin, controllable, and stable interface layer can be actively constructed between the first electrode layer 102 and the capacitor dielectric layer 106, thereby helping to suppress the interface reaction between the first electrode layer 102 and the capacitor dielectric layer 106, reduce the defect density of the capacitor dielectric layer 106, and control the evolution of the microstructure, thereby improving the stability and durability of the capacitor.

[0040] In other embodiments, reference is made to Figure 1 As shown, the capacitor includes a first electrode layer 102, a second electrode layer 104, a capacitor dielectric layer 106, and a second interface layer 110. The first electrode layer 102 and the second electrode layer 104 are spaced apart. The capacitor dielectric layer 106 is located between the first electrode layer 102 and the second electrode layer 104. The second interface layer 110 is located between the second electrode layer 104 and the capacitor dielectric layer 106. The second interface layer 110 has a monolayer structure.

[0041] In this embodiment, by providing a second interface layer 110 with a monomolecular structure between the second electrode layer 104 and the capacitor dielectric layer 106, an ultrathin, controllable, and stable interface layer can be actively constructed between the second electrode layer 104 and the capacitor dielectric layer 106. This helps to suppress the interface reaction between the second electrode layer 104 and the capacitor dielectric layer 106, reduce the defect density of the capacitor dielectric layer 106, and control the evolution of the microstructure, thereby improving the stability and durability of the capacitor.

[0042] In other embodiments, reference is made to Figure 1 As shown, the capacitor includes a first electrode layer 102, a second electrode layer 104, a capacitor dielectric layer 106, a first interface layer 108, and a second interface layer 110. The first electrode layer 102 and the second electrode layer 104 are spaced apart. The capacitor dielectric layer 106 is located between the first electrode layer 102 and the second electrode layer 104. The first interface layer 108 is located between the first electrode layer 102 and the capacitor dielectric layer 106. The second interface layer 110 is located between the second electrode layer 104 and the capacitor dielectric layer 106. Both the first interface layer 108 and the second interface layer 110 have a monolayer structure.

[0043] In this embodiment, by providing a first interface layer 108 with a monomolecular structure between the first electrode layer 102 and the capacitor dielectric layer 106, and a second interface layer 110 with a monomolecular structure between the second electrode layer 104 and the capacitor dielectric layer 106, ultrathin, controllable, and stable interface layers can be actively constructed between the first electrode layer 102 and the capacitor dielectric layer 106, and between the second electrode layer 104 and the capacitor dielectric layer 106. This helps to suppress the interface reaction between the first electrode layer 102 and the capacitor dielectric layer 106, as well as the interface reaction between the second electrode layer 104 and the capacitor dielectric layer 106, thereby reducing the defect density of the capacitor dielectric layer 106 and controlling the evolution of the microstructure, and further improving the stability and durability of the capacitor.

[0044] In some embodiments, the material of the first interface layer 108 includes an organosilane or a polymer; the material of the second interface layer 110 includes an organosilane or a polymer.

[0045] In some embodiments, when the capacitor includes both a first interface layer 108 and a second interface layer 110, the materials of the first interface layer 108 and the second interface layer 110 may be the same. For example, the materials of the first interface layer 108 and the second interface layer 110 may both be organosilanes, or the materials of the first interface layer 108 and the second interface layer 110 may both be polymer materials.

[0046] In other embodiments, when the capacitor includes both a first interface layer 108 and a second interface layer 110, the materials of the first interface layer 108 and the second interface layer 110 may be different. For example, the material of the first interface layer 108 is an organosilane, and the material of the second interface layer 110 is a polymer. Alternatively, the material of the second interface layer 110 is an organosilane, and the material of the first interface layer 108 is a polymer.

[0047] In this embodiment, the first interface layer 108 of the organosilane or polymer material can serve as a passivation layer located between the first electrode layer 102 and the capacitor dielectric layer 106, blocking the interfacial chemical reaction pathway between the first electrode layer 102 and the capacitor dielectric layer 106, thereby effectively mitigating the decrease in the effective K value and the increase in leakage current of the capacitor dielectric layer 106 caused by the interfacial reaction. Similarly, the second interface layer 110 of the organosilane or polymer material can serve as a passivation layer located between the second electrode layer 104 and the capacitor dielectric layer 106, blocking the interfacial chemical reaction pathway between the second electrode layer 104 and the capacitor dielectric layer 106, thereby effectively mitigating the decrease in the effective K value and the increase in leakage current of the capacitor dielectric layer 106 caused by the interfacial reaction.

[0048] In some embodiments, the polymeric material includes polymethyl methacrylate (PMMA) or a polymer composed of poly(3,4-ethylenedioxythiophene) and polystyrene sulfonate. PMMA, commonly known as plexiglass or acrylic, is a thermoplastic polymer with a high light transmittance of up to 92% and is easily precision-processed. The organic polymer composed of poly(3,4-ethylenedioxythiophene) and polystyrene sulfonate (PSS) (i.e., PEDOT:PSS) is currently the most widely used water-soluble conductive polymer composite material. It consists of a core-shell structure formed by the conjugated conductive polymer PEDOT and the polyanionic electrolyte PSS bonded by ionic bonds. PEDOT provides electronic conductivity, while PSS imparts excellent water dispersibility and film-forming properties. PEDOT:PSS exhibits high transparency (visible light transmittance greater than 80%), good thermal stability (decomposition temperature greater than 250°C), excellent mechanical flexibility, and biocompatibility, and can be used to prepare transparent conductive films through spin coating, inkjet printing, and other methods.

[0049] In some embodiments, the thickness of the first interface layer 108 ranges from 0.5 nm to 3 nm, for example, 0.5 nm, 1 nm, 2 nm, or 3 nm. The thickness of the second interface layer 110 ranges from 0.5 nm to 3 nm, for example, 0.5 nm, 1 nm, 2 nm, or 3 nm.

[0050] It should be noted that the lower limit of the thickness of the first interface layer 108 and the second interface layer 110 is set at 0.5 nm based on the requirement of continuous coverage. The monolayer molecular thickness of PEDOT:PSS is approximately 0.3 nm to 0.5 nm, and the monomer unit thickness of PMMA is approximately 0.5 nm. It is understandable that when the thickness of the spin-coated PEDOT:PSS or PMMA is less than its monolayer molecular thickness, it is difficult to form a continuous interface layer (first interface layer 108 or second interface layer 110) without pinholes. Simultaneously, due to the series capacitance effect, the upper limit of the thickness of the first interface layer 108 and the second interface layer 110 should be controlled at 3 nm. For example, when the thickness of the PEDOT:PSS (k value approximately 10) interface layer exceeds 3 nm, the effective k value of the capacitor dielectric layer 106 of the strontium titanate (SrTiO3) material (k value 300) will plummet from 187 to below 75, resulting in a capacitance density loss exceeding 75%. Meanwhile, 3nm is the critical point for maintaining both tunneling conductivity and bulk conductivity. Interface layers (first interface layer 108 or second interface layer 110) exceeding this thickness may themselves become leakage channels. Furthermore, in cylindrical capacitor designs, interface layers larger than 3nm can lead to insufficient top sealing and bottom coverage of high aspect ratio holes. In addition, the mismatch in thermal expansion coefficients at the interface between organic and inorganic materials can also cause significant shear stress and interface delamination risks when the interface layer thickness exceeds 3nm.

[0051] In this embodiment, by setting an ultrathin interface layer with a single-molecule structure between the electrode layer and the capacitor dielectric layer, and setting the thickness of the interface layer to be in the range of 0.5nm to 3nm, the requirement for continuous coverage of the interface layer is met, the effective decrease in the effective k-value and leakage of the capacitor dielectric layer are effectively mitigated, and good bottom coverage can be achieved in the capacitor hole with a high aspect ratio without forming a top seal. At the same time, the risk of shear stress and interface delamination is effectively mitigated, thereby improving the stability and durability of the capacitor.

[0052] Figure 2 A cross-sectional view of a second type of capacitor provided in an embodiment of this disclosure. (See reference...) Figure 2 As shown, in some embodiments, the capacitor 200 includes: a first electrode layer 102, a second electrode layer 104, a capacitor dielectric layer 106, a first interface layer 108, a second interface layer 110, a third interface layer 202, and a fourth interface layer 204. The third interface layer 202 is located between the first interface layer 108 and the first electrode layer 102. The first interface layer 108 is located between the third interface layer 202 and the capacitor dielectric layer 106. The capacitor dielectric layer 106 is located between the first interface layer 108 and the second interface layer 110. The second interface layer 110 is located between the capacitor dielectric layer 106 and the fourth interface layer 204. The fourth interface layer 204 is located between the second interface layer 110 and the second electrode layer 104. The density of the third interface layer 202 is greater than the density of the first electrode layer 102, and the density of the fourth interface layer 204 is greater than the density of the second electrode layer 104.

[0053] In this embodiment, by providing a highly dense third interface layer 202 between the first interface layer 108 and the first electrode layer 102, the diffusion of oxygen ions from the capacitor dielectric layer 106 into the first electrode layer 102 can be effectively suppressed, thereby effectively improving the stability of the capacitor. Similarly, by providing a highly dense fourth interface layer 204 between the second interface layer 110 and the second electrode layer 104, the diffusion of oxygen ions from the capacitor dielectric layer 106 into the second electrode layer 104 can be effectively suppressed, thereby effectively improving the stability of the capacitor.

[0054] In other embodiments, the capacitor includes a first electrode layer 102, a second electrode layer 104, a capacitor dielectric layer 106, a first interface layer 108, a second interface layer 110, and a third interface layer 202. The third interface layer 202 is located between the first electrode layer 102 and the first interface layer 108. The first interface layer 108 is located between the third interface layer 202 and the capacitor dielectric layer 106. The capacitor dielectric layer 106 is located between the first interface layer 108 and the second interface layer 110. The second interface layer 110 is located between the capacitor dielectric layer 106 and the second electrode layer 104. The density of the third interface layer 202 is greater than that of the first electrode layer 102.

[0055] In this embodiment, by providing a third interface layer 202 with high density between the first interface layer 108 and the first electrode layer 102, the diffusion of oxygen ions in the capacitor dielectric layer 106 into the first electrode layer 102 can be effectively suppressed, thereby effectively improving the stability of the capacitor.

[0056] In other embodiments, the capacitor includes a first electrode layer 102, a second electrode layer 104, a capacitor dielectric layer 106, a first interface layer 108, a second interface layer 110, and a fourth interface layer 204. The first interface layer 108 is located between the first electrode layer 102 and the capacitor dielectric layer 106. The capacitor dielectric layer 106 is located between the first interface layer 108 and the second interface layer 110. The second interface layer 110 is located between the capacitor dielectric layer 106 and the fourth interface layer 204. The fourth interface layer 204 is located between the second interface layer 110 and the second electrode layer 104. The density of the fourth interface layer 204 is greater than the density of the second electrode layer 104.

[0057] In this embodiment, by providing a fourth interface layer 204 with high density between the second interface layer 110 and the second electrode layer 104, the diffusion of oxygen ions from the capacitor dielectric layer 106 into the second electrode layer 104 can be effectively suppressed, thereby effectively improving the stability of the capacitor.

[0058] In some embodiments, the material of the third interface layer 202 may be the same as the material of the first electrode layer 102, but their densities differ. The material of the fourth interface layer 204 may be the same as the material of the second electrode layer 104, but their densities differ. For example, the material of the third interface layer 202 includes a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)); the material of the fourth interface layer 204 includes a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)). The microstructure of the material of the third interface layer 202 is more compact than that of the material of the first electrode layer 102, resulting in a higher density of the third interface layer 202 than the first electrode layer 102. Similarly, the microstructure of the material of the fourth interface layer 204 is more compact than that of the material of the second electrode layer 104, resulting in a higher density of the fourth interface layer 204 than the second electrode layer 104.

[0059] Figure 3 A cross-sectional view of a third type of capacitor provided in an embodiment of this disclosure. (See reference...) Figure 3As shown, in some embodiments, when the capacitor includes a first interface layer 108, the capacitor further includes a fifth interface layer 302 and a sixth interface layer 304. The fifth interface layer 302 is located between the first electrode layer 102 and the first interface layer 108, and the sixth interface layer 304 is located between the first interface layer 108 and the capacitor dielectric layer 106. The fifth interface layer 302 and the first electrode layer 102 are made of the same material, the sixth interface layer 304 and the capacitor dielectric layer 106 are made of the same material, the fifth interface layer 302 and the first interface layer 108 have the same elements but different materials, and the sixth interface layer 304 and the first interface layer 108 have the same elements but different materials.

[0060] refer to Figure 3 As shown, capacitor 300 includes a first electrode layer 102, a second electrode layer 104, a capacitor dielectric layer 106, a first interface layer 108, a fifth interface layer 302, and a sixth interface layer 304. The fifth interface layer 302 is located between the first electrode layer 102 and the first interface layer 108, the first interface layer 108 is located between the fifth interface layer 302 and the sixth interface layer 304, the sixth interface layer 304 is located between the first interface layer 108 and the capacitor dielectric layer 106, and the capacitor dielectric layer 106 is located between the sixth interface layer 304 and the second electrode layer 104.

[0061] It should be noted that the fifth interface layer 302 and the first interface layer 108 have the same elements but different materials. Specifically, this means that the base materials of the fifth interface layer 302 and the first interface layer 108 are different, but both base materials contain the same elements. Similarly, the sixth interface layer 304 and the first interface layer 108 have the same elements but different materials. Specifically, this means that the base materials of the sixth interface layer 304 and the first interface layer 108 are different, but both base materials contain the same elements.

[0062] When the capacitor simultaneously includes a first interface layer 108, a fifth interface layer 302, and a sixth interface layer 304, the fifth interface layer 302, the first interface layer 108, and the sixth interface layer 304 can jointly form a composition-gradient layer with a continuous gradient in chemical composition and elemental ratio. For example, when the material of the first electrode layer 102 is titanium nitride (TiN) and the material of the capacitor dielectric layer 106 is hafnium dioxide (HfO2), the materials of the fifth interface layer 302, the first interface layer 108, and the sixth interface layer 304 are, in sequence, titanium nitride (TiN), titanium oxynitride (TiON), and hafnium dioxide (HfO2). It should be noted that the example of the materials of the fifth interface layer 302, the first interface layer 108, and the sixth interface layer 304 being titanium nitride (TiN), titanium oxynitride (TiON), and hafnium dioxide (HfO2) is merely one example. In practical applications, the materials of the fifth interface layer 302, the first interface layer 108, and the sixth interface layer 304 can be reasonably selected based on the materials of the first electrode layer 102 and the capacitor dielectric layer 106.

[0063] In this embodiment of the present disclosure, by providing a fifth interface layer 302, a first interface layer 108, and a sixth interface layer 304 with gradually changing composition between the first electrode layer 102 and the capacitor dielectric layer 106, the lattice mismatch and chemical potential difference between the first electrode layer 102 and the capacitor dielectric layer 106 can be effectively alleviated.

[0064] Figure 4 A cross-sectional view of a fourth type of capacitor provided in an embodiment of this disclosure. (See reference...) Figure 4 As shown, in some embodiments, when the capacitor includes a second interface layer 110, the capacitor further includes a seventh interface layer 402 and an eighth interface layer 404. The seventh interface layer 402 is located between the capacitor dielectric layer 106 and the second interface layer 110, and the eighth interface layer 404 is located between the second interface layer 110 and the second electrode layer 104. The seventh interface layer 402 and the capacitor dielectric layer 106 are made of the same material, the eighth interface layer 404 and the second electrode layer 104 are made of the same material, the seventh interface layer 402 and the second interface layer 110 have the same elements but different materials, and the eighth interface layer 404 and the second interface layer 110 have the same elements but different materials.

[0065] refer to Figure 4As shown, capacitor 400 includes a first electrode layer 102, a second electrode layer 104, a capacitor dielectric layer 106, a second interface layer 110, a seventh interface layer 402, and an eighth interface layer 404. The capacitor dielectric layer 106 is located between the first electrode layer 102 and the seventh interface layer 402; the seventh interface layer 402 is located between the capacitor dielectric layer 106 and the second interface layer 110; the second interface layer 110 is located between the seventh interface layer 402 and the eighth interface layer 404; and the eighth interface layer 404 is located between the second interface layer 110 and the second electrode layer 104.

[0066] It should be noted that the seventh interface layer 402 and the second interface layer 110 having the same elements but different materials specifically means that the matrix materials of the seventh interface layer 402 and the second interface layer 110 are different, but both matrix materials contain the same elements. Similarly, the eighth interface layer 404 and the second interface layer 110 having the same elements but different materials specifically means that the matrix materials of the eighth interface layer 404 and the second interface layer 110 are different, but both matrix materials contain the same elements.

[0067] When the capacitor simultaneously includes a second interface layer 110, a seventh interface layer 402, and an eighth interface layer 404, the seventh interface layer 402, the second interface layer 110, and the eighth interface layer 404 can jointly form a composition-gradient layer with a continuous gradient in chemical composition and elemental ratio. For example, when the material of the second electrode layer 104 is titanium nitride (TiN) and the material of the capacitor dielectric layer 106 is hafnium dioxide (HfO2), the materials of the seventh interface layer 402, the second interface layer 110, and the eighth interface layer 404 are, respectively, hafnium dioxide (HfO2), titanium oxynitride (TiON), and titanium nitride (TiN). It should be noted that the example of the materials of the seventh interface layer 402, the second interface layer 110, and the eighth interface layer 404 being hafnium dioxide (HfO2), titanium oxynitride (TiON), and titanium nitride (TiN) is merely one example. In practical applications, the materials of the seventh interface layer 402, the second interface layer 110 and the eighth interface layer 404 can be reasonably selected based on the materials of the first electrode layer 102 and the capacitor dielectric layer 106.

[0068] In this embodiment of the present disclosure, by providing a seventh interface layer 402, a second interface layer 110, and an eighth interface layer 404 with gradually changing composition between the capacitor dielectric layer 106 and the second electrode layer 104, the lattice mismatch and chemical potential difference between the capacitor dielectric layer 106 and the second electrode layer 104 can be effectively alleviated.

[0069] In some embodiments, the capacitor includes, but is not limited to, a parallel plate capacitor, a cylindrical capacitor, a cup-shaped capacitor, or a cylindrical capacitor.

[0070] As described above, setting an interface layer between the electrode layer and the dielectric layer of a capacitor essentially involves creating a film layer that is chemically, structurally, and electrically compatible with the perovskite dielectric layer 106, achieving thermodynamic equilibrium and kinetic compatibility. Traditional alumina (Al₂O₃) or titanium dioxide (TiO₂), due to their inherent chemical reactivity, often become destroyers rather than protectors of capacitors. This disclosure focuses on "interface engineering" to construct a seamless, defect-controlled interface layer at the atomic scale. This is the only way to unleash the potential of perovskite's ultra-high dielectric constant while simultaneously achieving its stability and durability.

[0071] Based on a concept similar to that of the capacitor described above, this disclosure also provides a method for manufacturing a capacitor. Figure 5 This is a schematic flowchart illustrating a method for manufacturing a capacitor according to an embodiment of this disclosure. It should be noted that... Figure 5 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 5 The steps shown can be rearranged in order according to actual needs. (Refer to...) Figure 5 As shown, the method includes: Step S102: Form the first electrode layer; Step S104: A capacitor dielectric layer and a second electrode layer are sequentially formed on the surface of the first electrode layer; Step S106: A first interface layer is formed between the first electrode layer and the capacitor dielectric layer and / or a second interface layer is formed between the second electrode layer and the capacitor dielectric layer, wherein both the first interface layer and the second interface layer have a monolayer structure.

[0072] In this embodiment, by forming a first interface layer with a monolayer structure between the first electrode layer and the capacitor dielectric layer, interfacial reactions between the first electrode layer and the capacitor dielectric layer can be effectively suppressed. Similarly, by forming a second interface layer with a monolayer structure between the second electrode layer and the capacitor dielectric layer, interfacial reactions between the second electrode layer and the capacitor dielectric layer can be effectively suppressed. This is beneficial for reducing the defect density of the capacitor dielectric layer and controlling the evolution of its microstructure, thereby improving the stability and durability of the capacitor.

[0073] The formation processes of the first electrode layer, the second electrode layer, and the capacitor dielectric layer include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0074] In some embodiments, the step of forming a first interface layer includes: depositing a passivation material having a monolayer structure on the surface of the first electrode layer toward the capacitor dielectric layer to form a first interface layer; the step of forming a second interface layer includes: depositing a passivation material having a monolayer structure on the surface of the capacitor dielectric layer toward the second electrode layer to form a second interface layer.

[0075] Here, the passivation material includes organosilanes. When the material of the first interface layer is a passivation material, the formation process of the first interface layer includes, but is not limited to, ALD (Alternating Layer Deposition). Similarly, when the material of the second interface layer is a passivation material, the formation process of the second interface layer includes, but is not limited to, ALD. The ALD process can achieve precise control at the monolayer level through self-confined surface reactions.

[0076] In some embodiments, the step of forming a first interface layer includes: spin-coating a polymeric material onto the surface of the first electrode layer facing the capacitor dielectric layer to form a first interface layer; the step of forming a second interface layer includes: spin-coating a polymeric material onto the surface of the capacitor dielectric layer facing the second electrode layer to form a second interface layer.

[0077] Here, polymeric materials include PEDOT:PSS or PMMA.

[0078] When the material of the first interface layer is PEDOT:PSS, the process steps for forming the first interface layer are as follows: A commercially available solution (such as Clevios PH1000) is filtered through a PTFE membrane and then dropped onto the surface of the first electrode layer, which has been treated with UV-ozone to increase its hydrophilicity. The solution is then spin-coated at 3000 rpm to 6000 rpm for 30 to 60 seconds, followed by pre-baking at 80°C to 120°C to remove the solvent. In some embodiments, the film-forming properties can be improved by adding dimethyl sulfoxide (DMSO) to the PEDOT:PSS solution, or the thickness of the first interface layer can be precisely controlled using a multilayer spin-coating and cleaning process. Similarly, when the material of the second interface layer is PEDOT:PSS, the second interface layer can also be formed using a similar process described above.

[0079] When the first interface layer is made of PMMA, the process steps for forming the first interface layer are as follows: A 0.2 wt% to 0.5 wt% solution (i.e., PMMA solution) of a low molecular weight polymer (50 kDalton to 950 kDalton) is prepared by dissolving it in an organic solvent (such as anisole or chlorobenzene). This solution is then dropped onto a first electrode layer that has undergone hydrophobication treatment with hexamethyldisilazane (HMDS) or cleaning with acetone, and spin-coated at a higher rotation speed (4000 rpm to 8000 rpm) for 40 to 60 seconds. It is important to note that during the formation of the first interface layer of PMMA, the device coated with the PMMA solution should be allowed to stand at room temperature for 5 to 10 minutes to allow the solvent to evaporate slowly, followed by baking at 80°C to remove any residual solvent. In some embodiments, after the PMMA solution is dried, an oxygen plasma etching process can be used to trim any excessively thick portions of the PMMA material to ensure uniform thickness throughout the final first interface layer. Similarly, when the second interface layer is made of PMMA, the second interface layer can also be formed using a similar process described above.

[0080] The core difference between the two schemes described above, which utilize PEDOT:PSS and PMMA to form the first interface layer, lies in the fact that PEDOT:PSS material is hydrophilic and relies on electrostatic self-assembly, resulting in poor thermal stability and limited 3D coverage. PMMA material, on the other hand, is highly hydrophobic, allowing for precise control of the first interface layer thickness by adjusting the solution concentration. It also exhibits better thermal stability, and the low surface tension of its organic solvent facilitates deep-pore filling. However, complete solvent removal is necessary to avoid contaminating the subsequently formed capacitor dielectric layer.

[0081] In some embodiments, the method of manufacturing a capacitor further includes: forming a third interface layer between a first interface layer and a first electrode layer and / or forming a fourth interface layer between a second interface layer and a second electrode layer, wherein the density of the third interface layer is greater than the density of the first electrode layer, and the density of the fourth interface layer is greater than the density of the second electrode layer.

[0082] Here, the surface of the first electrode layer facing the capacitor dielectric layer can be modified to form a third interface layer with a higher density than the first electrode layer. Similarly, the surface of the second electrode layer facing the capacitor dielectric layer can be modified to form a fourth interface layer with a higher density than the second electrode layer.

[0083] In some embodiments, the step of forming a third interface layer includes: nitriding the surface of the first electrode layer toward the capacitor dielectric layer to form a third interface layer; the step of forming a fourth interface layer includes: depositing a conductive layer on the surface of the capacitor dielectric layer toward the second electrode layer; and nitriding the surface of the conductive layer to form a fourth interface layer.

[0084] The nitriding processes used to form the third and fourth interface layers include, but are not limited to, plasma nitriding. Plasma nitriding of the first electrode layer can increase the microscopic compactness of the material on the surface of the first electrode layer facing the capacitor dielectric layer, thereby forming a third interface layer with a density greater than that of the first electrode layer. Similarly, plasma nitriding of the second electrode layer can increase the microscopic compactness of the material on the surface of the conductive layer, thereby forming a fourth interface layer with a density greater than that of the second electrode layer.

[0085] It is understandable that surface modification treatments include nitriding. Of course, surface modification treatments can also be other processes, such as carburizing.

[0086] The formation process of the conductive layer includes, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0087] In this embodiment of the present disclosure, a dense nitrided layer is formed between the electrode layer and the capacitor dielectric layer by nitriding treatment, thereby effectively suppressing the diffusion of oxygen ions from the capacitor dielectric layer into the electrode layer.

[0088] In some embodiments, when a first interface layer is formed between the first electrode layer and the capacitor dielectric layer, the method of manufacturing the capacitor further includes: forming a fifth interface layer between the first electrode layer and the first interface layer, wherein the fifth interface layer and the first electrode layer are made of the same material, and the fifth interface layer and the first interface layer have the same elements but different materials; and forming a sixth interface layer between the first interface layer and the capacitor dielectric layer, wherein the sixth interface layer and the capacitor dielectric layer are made of the same material, and the sixth interface layer and the first interface layer have the same elements but different materials.

[0089] The formation processes of the fifth and sixth interface layers include, but are not limited to, CVD, PVD, ALD, or any combination thereof.

[0090] Here, the supply rates of the materials for the first interface layer (such as titanium oxynitride (TiON)), the fifth interface layer (such as titanium nitride (TiN)), and the sixth interface layer (hafnium dioxide (HfO2)) can be independently controlled using a deposition process to form a composition-gradient layer with a continuous compositional transition from titanium nitride (TiN) and titanium oxynitride (TiON) to hafnium dioxide (HfO2) on the surface of the first electrode layer. This effectively alleviates the lattice mismatch and chemical potential difference between the capacitor dielectric layer and the first electrode layer.

[0091] In some embodiments, when a second interface layer is formed between the second electrode layer and the capacitor dielectric layer, the method of manufacturing the capacitor further includes: forming a seventh interface layer between the capacitor dielectric layer and the second interface layer, wherein the seventh interface layer and the capacitor dielectric layer are made of the same material, and the seventh interface layer and the second interface layer have the same elements but different materials; and forming an eighth interface layer between the second interface layer and the second electrode layer, wherein the eighth interface layer and the second electrode layer are made of the same material, and the eighth interface layer and the second interface layer have the same elements but different materials.

[0092] The formation processes of the seventh and eighth interface layers include, but are not limited to, CVD, PVD, ALD, or any combination thereof.

[0093] Here, the supply rates of the materials for the second interface layer (such as titanium oxynitride (TiON)), the seventh interface layer (hafnium dioxide (HfO2)), and the eighth interface layer (such as titanium nitride (TiN)) can be independently controlled using a deposition process to form a composition-gradient layer with a continuous compositional transition from hafnium dioxide (HfO2) and titanium oxynitride (TiON) to titanium nitride (TiN) on the surface of the capacitor dielectric layer. This effectively alleviates the lattice mismatch and chemical potential difference between the capacitor dielectric layer and the second electrode layer.

[0094] This disclosure also provides a semiconductor structure, which includes a transistor structure and a capacitor as described in any of the above embodiments, wherein the source or drain of the transistor structure is connected to the first electrode layer of the capacitor.

[0095] Here, the semiconductor structure can be at least a portion of a memory. As examples, the memory can include Dynamic Random Access Memory (DRAM), Dual Data Rate Synchronous Dynamic Random Access Memory (DDR), DDR2, DDR3, DDR4, DDR5, LPDDR, GDDR, Flash Memory, Static Random-Access Memory (SRAM), etc.

[0096] Based on a concept similar to the semiconductor structure described above, this disclosure also provides an electronic device. The electronic device includes a processor and a memory electrically connected to the processor; the memory includes the semiconductor structure described in any of the above embodiments.

[0097] Electronic devices can be terminals or other devices besides terminals. For example, electronic devices can include mobile phones, tablets, laptops, PDAs, in-vehicle electronic devices, mobile internet devices (MIDs), augmented reality (AR) / virtual reality (VR) devices, robots, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), as well as servers, network attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines.

[0098] Processing devices typically control the overall operation of electronic devices. As examples, processing devices may include a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0099] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0100] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A capacitor, characterized in that, include: A first electrode layer and a second electrode layer are spaced apart; A capacitor dielectric layer, wherein the capacitor dielectric layer is located between the first electrode layer and the second electrode layer; The material of the capacitor dielectric layer includes metal oxides or perovskites; At least one of a first interface layer and a second interface layer, wherein the first interface layer is located between the first electrode layer and the capacitor dielectric layer, and the second interface layer is located between the second electrode layer and the capacitor dielectric layer, wherein both the first interface layer and the second interface layer have a monolayer structure; the material of the first interface layer includes an organosilane or a polymer; the material of the second interface layer includes the organosilane or the polymer; the first interface layer is used to suppress interdiffusion interface reactions between the capacitor dielectric layer and the first electrode layer, and the second interface layer is used to suppress interdiffusion interface reactions between the capacitor dielectric layer and the second electrode layer; At least one of a third interface layer and a fourth interface layer, wherein the third interface layer is located between the first interface layer and the first electrode layer, and the fourth interface layer is located between the second interface layer and the second electrode layer, wherein the density of the third interface layer is greater than the density of the first electrode layer, and the density of the fourth interface layer is greater than the density of the second electrode layer.

2. The capacitor according to claim 1, characterized in that, The material of the third interface layer includes metal nitrides; the material of the fourth interface layer includes metal nitrides.

3. The capacitor according to claim 1, characterized in that, The polymeric material includes polymethyl methacrylate or a polymer composed of poly(3,4-ethylenedioxythiophene) and polystyrene sulfonate.

4. The capacitor according to claim 1, characterized in that, The thickness of the first interface layer ranges from 0.5 nm to 3 nm; the thickness of the second interface layer ranges from 0.5 nm to 3 nm.

5. A method for manufacturing a capacitor, characterized in that, include: Form the first electrode layer; A capacitor dielectric layer and a second electrode layer are sequentially formed on the surface of the first electrode layer; The material of the capacitor dielectric layer includes metal oxides or perovskites; A first interface layer is formed between the first electrode layer and the capacitor dielectric layer, and / or a second interface layer is formed between the second electrode layer and the capacitor dielectric layer. Both the first and second interface layers have a monolayer structure. The material of the first interface layer includes an organosilane or a polymer; the material of the second interface layer includes the organosilane or the polymer. The first interface layer is used to suppress interdiffusion interface reactions between the capacitor dielectric layer and the first electrode layer, and the second interface layer is used to suppress interdiffusion interface reactions between the capacitor dielectric layer and the second electrode layer. A third interface layer is formed between the first interface layer and the first electrode layer and / or a fourth interface layer is formed between the second interface layer and the second electrode layer, wherein the density of the third interface layer is greater than the density of the first electrode layer and the density of the fourth interface layer is greater than the density of the second electrode layer.

6. The method for manufacturing a capacitor according to claim 5, characterized in that, The step of forming the first interface layer includes: depositing a passivation material having a monolayer structure on the surface of the first electrode layer facing the capacitor dielectric layer to form the first interface layer; The step of forming the second interface layer includes: depositing the passivation material having the monolayer structure on the surface of the capacitor dielectric layer toward the second electrode layer to form the second interface layer.

7. The method for manufacturing a capacitor according to claim 5, characterized in that, The step of forming the first interface layer includes: spin-coating a polymer material onto the surface of the first electrode layer facing the capacitor dielectric layer to form the first interface layer; The step of forming the second interface layer includes: spin-coating a polymer material onto the surface of the capacitor dielectric layer facing the second electrode layer to form the second interface layer.

8. The method for manufacturing a capacitor according to claim 5, characterized in that, The step of forming the third interface layer includes: nitriding the surface of the first electrode layer facing the capacitor dielectric layer to form the third interface layer; The step of forming the fourth interface layer includes: depositing a conductive layer on the surface of the capacitor dielectric layer facing the second electrode layer; and performing the nitriding treatment on the surface of the conductive layer to form the fourth interface layer.

9. A semiconductor structure, characterized in that, include: Transistor structure; And the capacitor as claimed in any one of claims 1 to 4, wherein the source or drain of the transistor structure is connected to the first electrode layer of the capacitor.

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