Method and apparatus for common-mode voltage elimination and current ripple minimization in a three-level inverter

Abstract

The application discloses a three-level inverter common-mode voltage elimination and current ripple minimization method and device, and aims at the problem of significant increase of phase current total harmonic distortion (THD) in a traditional common-mode voltage elimination method (CMVE). All feasible switch state sequences for realizing the CMVE are discussed, and optimal switch state sequences under various modulation ratios and voltage vector angles are obtained. The concept of harmonic flux error is adopted to quantitatively evaluate the current ripple generated by each sequence in a switching period. The important influence of initial switching instant of the same switch state sequence on the effective value of the harmonic flux error is revealed. According to the optimal switch state sequence and optimal delay time, the final mirror-symmetrical pulse width modulation driving signal sequence is obtained through phase-shifting operation, and the sequence is applied to a double three-phase three-level inverter. The method can eliminate the common-mode voltage, significantly reduce the THD of the phase current and maintain the output performance of the motor.

Description

Technical Field

[0001] This application relates to the field of common-mode voltage elimination technology for dual three-phase permanent magnet synchronous motors, and in particular to a method and apparatus for common-mode voltage elimination and current ripple minimization in a three-level inverter. Background Technology

[0002] With the continuous improvement of wind power generation capacity, multiphase permanent magnet synchronous motors (PMSMs) and neutral-point clamped three-level (NPC-3L) converters have been widely used. However, the switching operation of the converter also generates high-frequency common-mode voltage (CMV), which can produce destructive bearing currents through capacitive coupling. This shaft current causes electrochemical erosion on the bearing surface, leading to abnormal vibration and temperature rise. Therefore, suppressing CMV is crucial to ensuring the reliable operation of wind turbine bearings.

[0003] PWM modulation optimization is a key technique for mitigating common-mode voltage (CMV). For conventional two-level (2L) converters driving three-phase PMSMs, PNH Le and MS Hassan et al. employed carrier inversion or bus clamping strategies between different windings to achieve partial CMV reduction. However, the 2L converter topology contains only eight basic switching vectors, making complete common-mode voltage cancellation (CMVE) impossible. The NPC-3L converter, with its greater number of switching states, makes CMVE possible. Of the 27 basic switching vectors in the NPC-3L topology, seven inherently generate zero CMV, and SK Sahoo et al. utilized only these zero vectors to achieve CMVE. However, due to the inability to use the maximum-length voltage space vector, this strategy is only effective when the modulation index is below 0.866, a limitation faced by other methods.

[0004] As the number of phases in a PMSM increases, the limitations of conventional common-mode voltage suppression methods described above are alleviated. For example, in dual three-phase permanent magnet synchronous motors (DTP-PMSM), Z. Liu et al. utilized its inherent even-phase symmetry to enable two-level converters to achieve common-mode voltage elimination through precise PWM edge synchronization between adjacent phases. This type of PWM phase-shifting technique is also applicable to the NPC-3L converter, and its applicability can be extended to the entire modulation region. However, compared to conventional space vector modulation (SVM), these PWM phase-shifting methods inevitably increase the total harmonic distortion (THD) of the output current. Although recent studies have shown that THD can be slightly improved by refining the selection of switching state sequences, the fundamental contradiction between common-mode voltage elimination and current quality remains unresolved. Currently, no research has clearly identified which switching state sequence achieves optimal output current quality.

[0005] Therefore, how to achieve common-mode voltage elimination without increasing the THD of the output current and maintaining the system performance is a key issue in the field of common-mode voltage suppression research. Summary of the Invention

[0006] In view of this, embodiments of this application provide a method and apparatus for common-mode voltage elimination and current ripple minimization in a three-level inverter. This method introduces the concept of harmonic flux linkage error and quantitatively evaluates the current ripple generated by each switching state sequence within one switching cycle. Analysis shows that the effective value (RMS) of the harmonic flux linkage error depends not only on the selection of the switching state sequence but also on the position of the starting pulse. By analyzing and selecting the optimal switching state sequence under arbitrary modulation and voltage vector angles, common-mode voltage elimination with THD optimization as the goal is achieved. This method achieves complete common-mode voltage elimination under different modulation ratios, and the total harmonic distortion of the phase current does not decrease significantly, maintaining system performance while eliminating common-mode voltage.

[0007] According to a first aspect of the embodiments of this application, a method for common-mode voltage elimination and current ripple minimization in a three-level inverter is provided, comprising: Within one control cycle, the phase current and rotational angular velocity of the dual three-phase permanent magnet synchronous motor are collected; Based on the phase current and rotational angular velocity, the phase current in the fundamental subspace and harmonic subspace is obtained by vector space decoupling transformation, and the phase current in the synchronous rotating coordinate system is further obtained by Park transformation. Based on the phase current in the synchronous rotating coordinate system, closed-loop control is performed according to the given reference value. After passing through the PI regulator, the reference voltage in the synchronous rotating coordinate system is obtained. The reference voltage in the fundamental subspace and harmonic subspace is obtained by inverse Park transform. Based on the reference voltages of the fundamental subspace and harmonic subspace, the reference voltages in the three-phase stationary coordinate system are obtained through vector space decoupling inverse transformation. The desired duty cycle is obtained and a comparison value is generated using an SPWM modulation strategy. Based on the reference voltages of the fundamental subspace, the electrical angle and modulation ratio are calculated. Based on the principles of common-mode voltage elimination and current ripple minimization, an optimal switching state sequence table and an optimal delay table are constructed. The optimal switching state sequence and optimal delay time are obtained by looking up the tables based on the electrical angle and modulation ratio. Based on the optimal switching state sequence, optimal delay time, and comparison value, after PWM sequence phase shifting operation, the final mirror-symmetric pulse width modulation drive signal sequence is generated and applied to the three-level inverter.

[0008] Optionally, based on the principles of common-mode voltage elimination and current ripple minimization, an optimal switching state sequence table and an optimal delay time table are constructed. The optimal switching state sequence and optimal delay time are obtained by looking up the tables based on the electrical angle and modulation ratio, specifically including: Based on the reference voltage in the three-phase stationary coordinate system, the output voltage of each phase winding is subtracted from the reference voltage to obtain the harmonic voltage error containing only high-frequency components. The harmonic flux error is obtained by integrating it over a single switching cycle. The effective value of the harmonic flux error is obtained by summing the squares of the harmonic flux errors of each phase. The switching state sequence between two adjacent switching cycles is simplified for the first time. The simplified switching state sequence is divided into several sequence groups. All switching state sequences in each sequence group are different only in terms of delay time. When the effective value of the harmonic flux error in each sequence group is minimized, a unique switching state sequence is obtained, thus completing the second simplification of the switching state sequence. Based on each combination of electrical angle and modulation ratio, in the simplified switching state sequence, the switching state sequence corresponding to the minimum effective value of harmonic flux linkage error is selected, and the optimal switching state sequence table and its corresponding optimal delay time table are constructed; based on the electrical angle and modulation ratio, the optimal switching state sequence and optimal delay time are obtained by looking up the table.

[0009] Optionally, based on the optimal switching state sequence, optimal delay time, and comparison value, after a PWM sequence phase-shifting operation, a final mirror-symmetric pulse width modulation drive signal sequence is generated and applied to the three-level inverter, including: The rising edge time of the first phase of the target switching state sequence is calculated based on the optimal delay time. Then, the rising and falling edges of adjacent phases are connected end-to-end according to the optimal switching state sequence to obtain the phase-shifted mirror-symmetric pulse width modulation drive signal sequence. Based on the generation method requirements of the mirror symmetric pulse width modulation drive signal sequence, the two comparison values ​​of each phase are updated only at the maximum value of the triangular carrier in the control cycle, so that the equivalent switching cycle is half of the control cycle. The distance between the two comparison values ​​of each phase determines the duty cycle of the generated PWM pulse.

[0010] According to a second aspect of the embodiments of this application, an apparatus for common-mode voltage elimination and current ripple minimization of a three-level inverter is provided, comprising: The sampling module is used to collect the phase current and rotational angular velocity of a dual three-phase permanent magnet synchronous motor within one control cycle; The coordinate transformation module is used to obtain the phase current in the fundamental subspace and harmonic subspace by using vector space decoupling transformation based on the phase current and rotation angular velocity, and further use Park transformation to obtain the phase current in the synchronous rotating coordinate system. The control module is used to perform closed-loop control based on the phase current in the synchronous rotating coordinate system and a given reference value. After passing through a PI regulator, the reference voltage in the synchronous rotating coordinate system is obtained, and the reference voltage in the fundamental subspace and harmonic subspace is obtained by inverse Park transform. The modulation module is used to obtain the reference voltage in the three-phase stationary coordinate system based on the reference voltage in the fundamental subspace and harmonic subspace according to the vector space decoupling inverse transformation, and to obtain the desired duty cycle and generate a comparison value using the SPWM modulation strategy; to calculate the electrical angle and modulation ratio based on the reference voltage in the fundamental subspace; and to construct the optimal switching state sequence table and the optimal delay table according to the principles of common-mode voltage elimination and current ripple minimization, and to obtain the optimal switching state sequence and the optimal delay time by looking up the table based on the electrical angle and modulation ratio. The phase-shifting operation module is used to generate the final mirror-symmetric pulse width modulation drive signal sequence after the optimal switching state sequence, optimal delay time and comparison value are phase-shifted through the PWM sequence, and then apply it to the three-level inverter.

[0011] According to a third aspect of the embodiments of this application, an electronic device is provided, comprising: One or more processors; Memory, used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors perform the method as described in the first aspect.

[0012] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided that stores computer instructions thereon, which, when executed by a processor, implement the steps of the method as described in the first aspect.

[0013] The technical solutions provided by the embodiments of this application may include the following beneficial effects: As can be seen from the above embodiments, the method of the present invention constructs an optimal switching state sequence table and an optimal delay time table under the principles of common-mode voltage elimination and current ripple minimization. While achieving complete elimination of common-mode voltage, it significantly reduces the THD of the motor phase current, effectively maintaining the performance of the motor system and exhibiting excellent common-mode voltage elimination effect. The present invention discovers that the starting position of the switching state sequence has a significant impact on current ripple, analyzes and simplifies the switching state sequence that satisfies CMVE, and generates a mirror-symmetric pulse width modulation drive signal sequence after PWM phase shifting operation based on the selected optimal switching state sequence and optimal time delay, which can achieve global THD optimization of the motor. Compared with the latest CMV elimination method, it can effectively reduce THD across the entire speed range. The present invention can be extended to two-level converters.

[0014] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0016] Figure 1 This is a flowchart illustrating a method for common-mode voltage elimination and current ripple minimization in a three-level inverter, according to one embodiment.

[0017] Figure 2 This is a closed-loop control block diagram of an NPC-3L DTP-PMSM drive system based on a CMVE-PWM strategy, as shown in one embodiment.

[0018] Figure 3 This is a diagram showing a six-phase output voltage modulation waveform and the corresponding duty cycle curve according to an embodiment.

[0019] Figure 4 This is a flowchart illustrating a method for generating a mirror-symmetric PWM by comparing triangular carrier waves, according to one embodiment.

[0020] Figure 5 It is shown according to one embodiment when cmpR i >cmpF i The waveforms of the time carrier and the modulated wave.

[0021] Figure 6 It is shown according to one embodiment when cmpR i ≤ cmpF i The waveforms of the time carrier and the modulated wave.

[0022] Figure 7 This is a comparison of the first winding output voltage waveforms of the ABCXYZ and BCXYZA sequences shown in one embodiment.

[0023] Figure 8 This is a comparison of the harmonic chain waveforms and root mean square values ​​of the ABCXYZ and BCXYZA sequences shown in one embodiment.

[0024] Figure 9 The ABCXYZ sequence shown in one embodiment is in [0, Different delay times within the range RMS value of lower harmonic flux .

[0025] Figure 10 This is a schematic diagram illustrating seven steps for implementing PWM phase-shifting operation according to one embodiment; Figure 11 The schematic diagram of the proposed CMVE-PWM modulation algorithm is shown according to one embodiment; Figure 12 The results show a comparison of the output voltage of four methods at a rated motor speed of 500 rpm, as illustrated in one embodiment.

[0026] Figure 13 The results show a comparison of common-mode voltage at a motor rated speed of 500 rpm using four methods illustrated in one embodiment.

[0027] Figure 14 The results show a comparison of the common-mode voltage micro-waveforms at a motor rated speed of 500 rpm using four methods illustrated in one embodiment.

[0028] Figure 15 The results show the phase current comparison at a rated motor speed of 500 rpm using four methods illustrated in one embodiment.

[0029] Figure 16 The results are a comparison of the phase current FFT at a rated motor speed of 500 rpm using four methods illustrated in one embodiment.

[0030] Figure 17 The results show the THD comparison of four methods at different motor speeds, based on one embodiment.

[0031] Figure 18 This is a block diagram illustrating a common-mode voltage elimination and current ripple minimization device for a three-level inverter according to one embodiment. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0033] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0034] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0035] Figure 1 This is a flowchart illustrating a method for common-mode voltage elimination and current ripple minimization in a three-level inverter, according to one embodiment. Figure 1 As shown, the method may include the following steps: S1: Within one control cycle, collect the phase current and rotational angular velocity of the dual three-phase permanent magnet synchronous motor; Specifically, taking a dual three-phase permanent magnet synchronous motor with a rated speed of 500 rpm as an example, its rated current is 4A, the number of pole pairs is 5, and the stator inductance is... =9.7mH, stator resistance =1.8Ω, oscilloscope sampling frequency set to 500kHz, DC bus voltage =100V, the DSP and FPGA used are TMS320F28335 and EP3C16Q240C8N respectively, and the switching frequency is set to =10kHz, dead time is 2μs; Figure 2 The diagram shows the closed-loop control of the NPC-3L DTP-PMSM drive system based on the CMVE-PWM strategy, and the phase currents of the two sets of motor windings are collected at the current moment. , , , and rotational angular velocity This provides basic information for the control of dual three-phase permanent magnet synchronous motors.

[0036] S2: Based on the phase current and rotational angular velocity, the phase current in the fundamental subspace and harmonic subspace is obtained by vector space decoupling transformation, and the phase current in the synchronous rotating coordinate system is further obtained by Park transformation. Specifically, the motor phase current collected at the current moment , , , Through VSD transformation, it is converted into phase current in the fundamental subspace. , Phase current in harmonic subspace , VSD static transformation matrix as follows: (1) Phase current in stationary coordinate system , , , Converted to phase current in a rotating coordinate system using the Park transformation. , , , This provides the necessary information for the dual closed-loop control of the DTP-PMSM, and the Parker transform matrix. as follows: (2) S3: Based on the phase current in the synchronous rotating coordinate system, closed-loop control is performed according to the given reference value. After passing through the PI regulator, the reference voltage in the synchronous rotating coordinate system is obtained. The reference voltage in the fundamental subspace and harmonic subspace is obtained by inverse Park transform. Specifically, the phase current in the rotating coordinate system , , , They are respectively used as reference currents in the fundamental subspace. , Reference current in harmonic subspace , The negative feedback is used for closed-loop control, and after passing through the proportional-integral regulator in the current loop, the reference voltage in the rotating coordinate system is obtained. , , , The reference voltage in the stationary coordinate system is obtained by inverse Park transformation. , , , This provides the necessary information for the CMVE-PWM algorithm, namely the matrix of the inverse Parker transform. as follows: (3) S4: Based on the reference voltages in the fundamental and harmonic subspaces, the reference voltages in the three-phase stationary coordinate system are obtained using the vector space decoupling inverse transformation. The desired duty cycle is obtained using an SPWM modulation strategy, and a comparison value is generated. Based on the reference voltages in the fundamental subspace, the electrical angle and modulation ratio are calculated. Based on the principles of common-mode voltage elimination and current ripple minimization, an optimal switching state sequence table and an optimal delay time table are constructed. The optimal switching state sequence and optimal delay time are obtained by looking up the tables based on the electrical angle and modulation ratio. This step includes the following sub-steps: S41: Based on the reference voltages in the fundamental subspace and harmonic subspace, the reference voltages in the three-phase stationary coordinate system are obtained by inverse vector space decoupling transformation, and the desired duty cycle is obtained by using the SPWM modulation strategy and a comparison value is generated; based on the reference voltages in the fundamental subspace, the electrical angle and modulation ratio are calculated. Specifically, based on the reference voltage in the fundamental subspace , Reference voltage in harmonic subspace , VSD inverse transformation is used Obtain the reference voltage in the three-phase stationary coordinate system and The duty cycle of the six-phase expectation is obtained through normalization. and Six-phase output voltage modulation wave and the corresponding duty cycle , like Figure 3 As shown; using as Figures 4-6 The mirror-symmetric switching state sequence generation method shown generates the initial six-phase 12 comparison values ​​(cmpR). i and cmpF i and the initial switching state sequence; based on the reference voltage in the fundamental subspace. and Calculate its electrical angle and modulation ratio.

[0037] S42: Based on the reference voltage in the three-phase stationary coordinate system, the output voltage of each phase winding is subtracted from the reference voltage to obtain the harmonic voltage error containing only high-frequency components. The harmonic flux error is obtained by integrating it in a single switching cycle. The effective value of the harmonic flux error is obtained by summing the squares of the harmonic flux errors of each phase. Specifically, a Fast Fourier Transform (FFT) is performed on the acquired phase current, and the THD value is calculated based on the current harmonic spectrum distribution. THD is used to quantify the ratio of all harmonic energies to the fundamental frequency energy, and it is defined as follows: (4) in, Fundamental wave energy, , , …, This represents the energy of each of the remaining harmonics. According to equation (4), the calculation of THD requires at least one complete fundamental period. ~ Numerical analysis requires first implementing a PWM modulation strategy to generate current for at least one fundamental cycle before its harmonic spectrum can be evaluated. Therefore, the research focuses on a single switching cycle.T s Based on the micro harmonic flux linkage error of a purely inductive load The effective value is proportional to THD, and adopts To evaluate the current ripple over a switching cycle; assuming that in each switching cycle... Within this range, the reference output voltage of each phase winding remains constant. Subtracting the reference voltage from the instantaneous output voltage yields the harmonic voltage error, which contains only high-frequency components: (5) in, This represents the instantaneous output voltage of each phase. This represents the reference output voltage for each phase. The harmonic voltage error of each phase can be represented by equation (5), which can eliminate the non-integer fundamental period components, thereby achieving the effect of harmonic voltage error for each phase. Analysis of the high-frequency harmonic characteristics generated by different switching state sequences within the system; Integrating both sides of equation (5) yields the harmonic flux linkage error. ,Right now: (6) According to equation (6), It is a modulation ratio m and voltage vector electric angle Related variables; based on a switching cycle The internal phases produced They are not the same, therefore the combined effect of all phases needs to be considered. The root mean square value of the harmonic flux linkage error is defined as the root mean square value of the sum of the squares of the harmonic flux linkage errors of each phase, that is: (7) Based on the inductive reactance of the motor windings under normal operating conditions Much greater than resistance Therefore, the motor system can be approximated as a purely inductive load, and the root mean square value of the harmonic flux can be obtained. It is proportional to the root mean square value of the harmonic current, so the harmonic flux linkage is selected. To evaluate the current ripple magnitude within a switching cycle; S43: The switching state sequence between two adjacent switching cycles is simplified for the first time. The simplified switching state sequence is divided into several sequence groups. All switching state sequences in each sequence group are different only in terms of delay time. When the effective value of the harmonic flux error in each sequence group is minimized, the corresponding unique switching state sequence is obtained, thus completing the second simplification of the switching state sequence. Specifically, based on the alignment sequence of CMVE, there are a total of 6! = 720 feasible switching state sequences that satisfy the conditions, all of which can produce the same equivalent fundamental output voltage, but they differ in their THD of the current; based on each switching state sequence in a single The THD value within the period is used as an evaluation index, and redundant sequences are simplified to construct a method for evaluating arbitrary voltage vector electrical angles. and modulation ratio m A PWM modulation strategy for achieving optimal THD under certain conditions (CMVE-PWM); Since the symmetry of the switch state sequence is lost after a shift operation, to avoid the flux accumulation effect, adjacent switching cycles are... The sequence of switch states is reversed, for example, in a... If the sequence ABCXYZ is used, then in two adjacent... The internal sequence should be adjusted to ABCXYZ–ZYXCBA. Due to symmetry, the original 720 sequences can be reduced to 360. For simplicity, the second one will be omitted in the following text. The sequence of switch states within; Based on the fact that certain sequences only have cyclic permutation relationships (e.g., ABCXYZ, BCXYZA, CXYZAB, XYZABC, YZABCX, ZABCXY), it can be known that they exist within one period. The end-to-end PWM waveforms formed within the sequence are identical, differing only in their initial positions. These sequences are defined as a cyclic sequence group, expressed as: (8) in, Indicates the CSG number, j Indicates the circular shift index. P For cyclic permutation operators, Indicates the first k The basic switching state sequence of a CSG; Figure 7 A comparison of the ABCXYZ sequence and the BCXYZA sequence on the output voltage waveform of the first group of three-phase windings shows that a time delay is introduced into the ABCXYZ sequence. Subsequently, its waveform was completely identical to the BCXYZA sequence, indicating that in the same... The six sequences in the group are all obtained by transforming the same basic switch state sequence through different time delays, corresponding to six different delay times, and the delay time is determined by the duty cycle of each phase; Figure 8These are the harmonic flux linkage trajectories of two sequences, ABCXYZ and BCXYZA. The gray curve represents the sum of squares of the harmonic flux linkages for each phase, and the gray area represents each switching state sequence in one... T s Root mean square value of harmonic flux generated internally It can be seen that the switch state sequence is generated It is related to the initial position of the sequence; in other words, the delay time. It will have an impact The calculation results can be obtained for each There must exist an optimal delay time. ∈[0, ], making To obtain the minimum value, that is, within the same... All six sequences within the group can achieve the same optimal solution.

[0038] Figure 9 It is the ABCXYZ sequence at different delay times ∈[0, The corresponding [below] The numerical changes show that when = At that time, the ABCXYZ sequence can obtain the minimum harmonic flux linkage, thus generating the minimum current ripple. Therefore, by sequentially calculating each group... Optimal delay time The original 360 switch state sequences (i.e. 60 CSGs) can be further simplified to 60 sequences; S43: Based on each combination of electrical angle and modulation ratio, select the switching state sequence corresponding to the minimum effective value of harmonic flux linkage error from the simplified switching state sequence, and construct the optimal switching state sequence table and its corresponding optimal delay time table; based on the electrical angle and modulation ratio, look up the table to obtain the optimal switching state sequence and the optimal delay time.

[0039] Specifically, based on the simplified sequence of 60 switch states, ∈[0°, 60°] and m ∈[0, 1] is divided into 20 equal intervals. For each ( , m ) Combined operating conditions, calculate the minimum value corresponding to each switching state sequence. The optimal switch state sequence corresponding to each data point is obtained as shown in Table I, where 1-60 represent the simplified 60 switch state sequence numbers. The correspondence between the code number and the specific switch state sequence is shown in Table II. Table I is different and m The optimal switching state sequence is as follows: Table II: Correspondence between code numbers and specific switch state sequences: As shown in Table I, the distribution of the switch state sequences obtained through numerical optimization is relatively discrete, which is difficult to implement in actual engineering. Therefore, it is necessary to further simplify these isolated data points. Considering that some operating points may have multiple switch state sequences that simultaneously achieve the optimal result, these sequences can be equivalently substituted. In addition, considering the unavoidable errors in the numerical calculation process, isolated data points can be replaced by approximations within an acceptable error range (set to ≤5% in this invention). After the above processing, the simplified results are shown in Table III. It should be emphasized that Table III only provides one possible simplification scheme. Its degree of simplification is limited by the capacity of the actual lookup table (LUT) and the computational burden. The degree of simplification in practical applications depends on the specific application requirements, such as the processor's computing power and storage resources. Table III shows different simplified results. and m The optimal switching state sequence is as follows: After simplifying Table III and adding sector numbers, we can obtain the optimal switch state sequence selection table as shown in Table IV. The switch state sequence configuration of sectors IV-VI is exactly the same as that of sectors I-III, so it is not given again in the table. Table IV shows the optimal switching state sequence selection and sector division for the proposed CMVE-PWM modulation strategy: According to each of the tables in Table IV ( , m The optimal switching state sequence is selected by combination, and the optimal delay time corresponding to each switching state sequence is shown in Table V. ), This represents the time interval between the rising edge of the first phase PWM and the maximum value of the triangular carrier wave, with its value relative to the switching period. The values ​​are represented in per-unit form; since the optimal delay times of sectors III and V are the same as those of sector I, and the optimal delay times of sectors IV and VI are the same as those of sector II, they are not listed in the table for simplicity. Reference voltage obtained from S3 and Information can be used to calculate the voltage vector electrical angle. and modulation ratio m ,according to( , m By looking up tables IV and V, the optimal switch state sequence Seq( , m and optimal delay time ( , m ); The optimal delay time of the CMVE-PWM modulation strategy proposed in Table V is as follows: S5: Based on the optimal switching state sequence, optimal delay time, and comparison value, after a phase-shifting operation of the switching state sequence, the final mirror-symmetric pulse width modulation drive signal sequence is generated and applied to the three-level inverter. This step includes the following sub-steps: S51: Calculate the rising edge time of the first phase of the target switching state sequence based on the optimal delay time, and then connect the rising and falling edges of adjacent phases end-to-end according to the optimal switching state sequence to obtain the phase-shifted mirror symmetric pulse width modulation drive signal sequence. Specifically, the seven steps of the phase-shifting operation of the proposed CMVE-PWM method are as follows: Figure 10 As shown, ①: According to ( , m ) Select the optimal switch state sequence Seq( from table IV) , m ), ②: According to ( , m Look up table V to select the optimal delay time. ( , m ), ③-⑦: According to ( , m Determine the position of the first rising edge of the PWM according to Seq( , m The rising and falling edges of adjacent PWM phases are connected end to end to obtain the final mirror-symmetric pulse width modulation drive signal sequence. S52: According to the generation method requirements of the mirror symmetric pulse width modulation drive signal sequence, the two comparison values ​​of each phase are updated only at the maximum value of the triangular carrier in the control cycle, so that the equivalent switching cycle is half of the control cycle. The distance between the two comparison values ​​of each phase determines the duty cycle of the generated PWM pulse. Specifically, based on the phase-shifted switching state sequence, the following is adopted: Figures 4-6 The PWM generation method shown uses two comparison values ​​to update the two comparison values ​​cmpR / F of each phase at the maximum value of the triangular carrier wave. i This generates the final switching state sequence for each control cycle and applies it to the dual three-phase three-level inverter.

[0040] Based on the example described, the schematic diagram of the proposed CMVE-PWM modulation method is as follows: Figure 11 As shown, to verify the effectiveness of the proposed CMVE-PWM method, a comparative experimental study was conducted with the traditional SPWM method, the common-mode voltage suppression (CMVR) method using reverse carriers in two sets of windings, and the recently proposed common-mode voltage elimination method (DPSPWM).

[0041] Figure 12 This is a comparison of the output voltage results of four methods at the motor's rated speed of 500 rpm. Figure 13 The results show the common-mode voltage comparison of the four methods at a rated motor speed of 500 rpm. The results indicate that SPWM generates the largest CMV amplitude, while the CMVR method using reverse carrier can achieve a certain degree of CMV attenuation. Both DPSPWM and the proposed CMVE-PWM methods show further CMV suppression effects.

[0042] Figure 14 This is a comparison of the common-mode voltage microwaveforms of four methods at a motor rated speed of 500 rpm. The results show that SPWM has the best performance in both windings ( and The common-mode voltage rises or falls almost simultaneously in the CMVR, resulting in the maximum total common-mode voltage. CMVR can only achieve this at... and The two modes achieve partial cancellation, while DPSPWM and CMVE-PWM can maintain near-complete cancellation, which further verifies the superior performance of DPSPWM and CMVE-PWM in common-mode voltage elimination.

[0043] Figure 15 These are the results of a comparison of phase current using four methods at a motor's rated speed of 500 rpm. Figure 16 The results show a comparison of the phase current FFT of four methods at a motor rated speed of 500 rpm. The results indicate that the total harmonic distortion (THD) of the phase current of SPWM and CMVR are 2.19% and 2.12%, respectively, and their performance is almost the same. Although DPSPWM can achieve common-mode voltage cancellation (CMVE), its phase current THD increases significantly to 3.85%. In contrast, the CMVE-PWM proposed in this invention reduces the THD to 2.98%, indicating that this method can effectively improve THD performance while maintaining common-mode voltage cancellation (CMVE).

[0044] Figure 17The results show the THD comparison of the four methods at different motor speeds. The results indicate that under different speed conditions, the THD performance of SPWM and CMVR is basically similar, while the proposed CMVE-PWM has a lower THD than DPSPWM throughout the entire speed range. This further verifies the good adaptability of the algorithm under different operating conditions.

[0045] In summary, this invention proposes a method for common-mode voltage elimination and current ripple minimization in dual three-phase three-level inverters. The innovation of this method lies in revealing, under CMVE constraints, the significant impact of the starting position of the switching state sequence on current ripple; analyzing and simplifying all switching state sequences satisfying the CMVE condition; quantitatively evaluating the current ripple generated by each sequence within one switching cycle using the concept of harmonic flux linkage error; and proposing a switching state sequence selection method to achieve global THD optimization. Based on the optimal switching state sequence and optimal delay time, the final PWM is obtained using a dual-comparison PWM generation method after phase shifting. Based on this method, it is possible to significantly reduce the THD of the phase current while eliminating common-mode voltage and maintaining the motor's output performance. Compared with the latest common-mode voltage elimination methods, this method can effectively reduce THD across the entire speed range. This invention can be extended to two-level converters.

[0046] Corresponding to the aforementioned embodiment of common-mode voltage elimination and current ripple minimization for a three-level inverter, this application also provides an embodiment of a common-mode voltage elimination and current ripple minimization device for a three-level inverter.

[0047] Figure 18 This is a block diagram illustrating a common-mode voltage cancellation and current ripple minimization device for a three-level inverter according to an exemplary embodiment. (Refer to...) Figure 18 The device includes: Sampling module 1 is used to collect the phase current and rotational angular velocity of a dual three-phase permanent magnet synchronous motor within one control cycle; The coordinate transformation module 2 is used to obtain the phase current in the fundamental subspace and harmonic subspace by using vector space decoupling transformation based on the phase current and rotational angular velocity, and further use Park transformation to obtain the phase current in the synchronous rotating coordinate system. Control module 3 is used to perform closed-loop control based on the phase current in the synchronous rotating coordinate system and a given reference value. After passing through a PI regulator, the reference voltage in the synchronous rotating coordinate system is obtained, and the reference voltage in the fundamental subspace and harmonic subspace is obtained by inverse Park transform. Modulation module 4 is used to obtain the reference voltage in the three-phase stationary coordinate system based on the reference voltage in the fundamental subspace and harmonic subspace according to the vector space decoupling inverse transformation, and to obtain the desired duty cycle and generate a comparison value using the SPWM modulation strategy; to calculate the electrical angle and modulation ratio based on the reference voltage in the fundamental subspace; and to construct the optimal switching state sequence table and the optimal delay table according to the principles of common-mode voltage elimination and current ripple minimization, and to obtain the optimal switching state sequence and the optimal delay time by looking up the table based on the electrical angle and modulation ratio. Phase-shifting operation module 5 is used to generate the final mirror-symmetric pulse width modulation drive signal sequence after PWM sequence phase-shifting operation based on the optimal switching state sequence, optimal delay time and comparison value, and apply it to the three-level inverter.

[0048] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0049] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0050] Accordingly, this application also provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; and when the one or more programs are executed by the one or more processors, causing the one or more processors to implement the method and apparatus described above for common-mode voltage elimination and current ripple minimization of a dual three-phase three-level inverter.

[0051] Accordingly, this application also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the method described above for common-mode voltage elimination and current ripple minimization in a dual three-phase three-level inverter.

[0052] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0053] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for eliminating common-mode voltage and minimizing current ripple in a three-level inverter, characterized in that, include: Within one control cycle, the phase current and rotational angular velocity of the dual three-phase permanent magnet synchronous motor are collected; Based on the phase current and rotational angular velocity, the phase current in the fundamental subspace and harmonic subspace is obtained by vector space decoupling transformation, and the phase current in the synchronous rotating coordinate system is further obtained by Park transformation. Based on the phase current in the synchronous rotating coordinate system, closed-loop control is performed according to the given reference value. After passing through the PI regulator, the reference voltage in the synchronous rotating coordinate system is obtained. The reference voltage in the fundamental subspace and harmonic subspace is obtained by inverse Park transform. Based on the reference voltages of the fundamental subspace and harmonic subspace, the reference voltages in the three-phase stationary coordinate system are obtained through vector space decoupling inverse transformation. The desired duty cycle is obtained and a comparison value is generated using an SPWM modulation strategy. Based on the reference voltages of the fundamental subspace, the electrical angle and modulation ratio are calculated. Based on the principles of common-mode voltage elimination and current ripple minimization, an optimal switching state sequence table and an optimal delay table are constructed. The optimal switching state sequence and optimal delay time are obtained by looking up the tables based on the electrical angle and modulation ratio. Based on the optimal switching state sequence, optimal delay time, and comparison values, after a PWM sequence phase-shifting operation, a final mirror-symmetric pulse width modulation drive signal sequence is generated and applied to the three-level inverter. Specifically, this includes: calculating the rising edge time of the first phase of the target switching state sequence based on the optimal delay time; then connecting the rising and falling edges of adjacent phases end-to-end according to the optimal switching state sequence to obtain the phase-shifted switching state sequence; and, according to the generation method requirements of the mirror-symmetric pulse width modulation drive signal sequence, updating the two comparison values ​​of each phase only at the maximum value of the triangular carrier wave in the control cycle, so that the equivalent switching cycle is half of the control cycle, and the distance between the two comparison values ​​of each phase determines the duty cycle of the generated PWM pulse.

2. The method for common-mode voltage elimination and current ripple minimization of a three-level inverter according to claim 1, characterized in that, Based on the principles of common-mode voltage elimination and current ripple minimization, an optimal switching state sequence table and an optimal delay time table are constructed. The optimal switching state sequence and optimal delay time are obtained by looking up the tables based on the electrical angle and modulation ratio, including: Based on the reference voltage in the three-phase stationary coordinate system, the output voltage of each phase winding is subtracted from the reference voltage to obtain the harmonic voltage error containing only high-frequency components. The harmonic flux error is obtained by integrating it over a single switching cycle. The effective value of the harmonic flux error is obtained by summing the squares of the harmonic flux errors of each phase. The switching state sequence between two adjacent switching cycles is simplified for the first time. The simplified switching state sequence is divided into several sequence groups. All switching state sequences in each sequence group are different only in terms of delay time. When the effective value of the harmonic flux error in each sequence group is minimized, a unique switching state sequence is obtained, thus completing the second simplification of the switching state sequence. Based on each combination of electrical angle and modulation ratio, in the simplified switching state sequence, the switching state sequence corresponding to the minimum effective value of harmonic flux linkage error is selected, and the optimal switching state sequence table and its corresponding optimal delay time table are constructed; based on the electrical angle and modulation ratio, the optimal switching state sequence and optimal delay time are obtained by looking up the table.

3. A device for common-mode voltage elimination and current ripple minimization in a three-level inverter, characterized in that, include: The sampling module is used to collect the phase current and rotational angular velocity of a dual three-phase permanent magnet synchronous motor within one control cycle; The coordinate transformation module is used to obtain the phase current in the fundamental subspace and harmonic subspace by using vector space decoupling transformation based on the phase current and rotation angular velocity, and further use Park transformation to obtain the phase current in the synchronous rotating coordinate system. The control module is used to perform closed-loop control based on the phase current in the synchronous rotating coordinate system and a given reference value. After passing through a PI regulator, the reference voltage in the synchronous rotating coordinate system is obtained, and the reference voltage in the fundamental subspace and harmonic subspace is obtained by inverse Park transform. The modulation module is used to obtain the reference voltage in the three-phase stationary coordinate system based on the reference voltage in the fundamental subspace and harmonic subspace according to the vector space decoupling inverse transformation, and to obtain the desired duty cycle and generate a comparison value using the SPWM modulation strategy; to calculate the electrical angle and modulation ratio based on the reference voltage in the fundamental subspace; and to construct the optimal switching state sequence table and the optimal delay table according to the principles of common-mode voltage elimination and current ripple minimization, and to obtain the optimal switching state sequence and the optimal delay time by looking up the table based on the electrical angle and modulation ratio. The phase-shifting operation module is used to generate a final mirror-symmetric pulse width modulation drive signal sequence after phase-shifting the PWM sequence based on the optimal switching state sequence, optimal delay time, and comparison value, and then apply it to the three-level inverter. Specifically, it includes: calculating the rising edge time of the first phase of the target switching state sequence based on the optimal delay time; then connecting the rising and falling edges of adjacent phases end-to-end according to the optimal switching state sequence to obtain the phase-shifted switching state sequence; according to the generation method requirements of the mirror-symmetric pulse width modulation drive signal sequence, updating the two comparison values ​​of each phase only at the maximum value of the triangular carrier wave in the control cycle, so that the equivalent switching cycle is half of the control cycle, and the distance between the two comparison values ​​of each phase determines the duty cycle of the generated PWM pulse.

4. The common-mode voltage elimination and current ripple minimization device for a three-level inverter according to claim 3, characterized in that, Based on the principles of common-mode voltage elimination and current ripple minimization, an optimal switching state sequence table and an optimal delay time table are constructed. The optimal switching state sequence and optimal delay time are obtained by looking up the tables based on the electrical angle and modulation ratio, including: Based on the reference voltage in the three-phase stationary coordinate system, the output voltage of each phase winding is subtracted from the reference voltage to obtain the harmonic voltage error containing only high-frequency components. The harmonic flux error is obtained by integrating it over a single switching cycle. The effective value of the harmonic flux error is obtained by summing the squares of the harmonic flux errors of each phase. The switching state sequence between two adjacent switching cycles is simplified for the first time. The simplified switching state sequence is divided into several sequence groups. All switching state sequences in each sequence group are different only in terms of delay time. When the effective value of the harmonic flux error in each sequence group is minimized, a unique switching state sequence is obtained, thus completing the second simplification of the switching state sequence. Based on each combination of electrical angle and modulation ratio, in the simplified switching state sequence, the switching state sequence corresponding to the minimum effective value of harmonic flux linkage error is selected, and the optimal switching state sequence table and its corresponding optimal delay time table are constructed; based on the electrical angle and modulation ratio, the optimal switching state sequence and optimal delay time are obtained by looking up the table.

5. An electronic device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1-2.

6. A computer-readable storage medium storing computer instructions thereon, characterized in that, When executed by the processor, this instruction implements the steps of the method as described in any one of claims 1-2.

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