A unified vector timing construction method for ripple optimization of multi-parallel converters

Abstract

This invention discloses a unified vector timing construction method for ripple optimization of multi-parallel converters. This method constructs a near-three-voltage vector set based on a reference voltage and generates a basic vector sequence library by progressively varying the total number of conducting switching devices in parallel branches, forming a unified modulation framework applicable to any number of parallel converters. Based on the basic vector sequence library, a symmetrical vector timing unit is constructed, and by repeatedly expanding this basic unit, a complete vector timing sequence applicable to any number of parallel converters is formed. Furthermore, the switching timing sequence of each parallel branch is determined based on the complete vector timing sequence. Two types of triangular carrier initial angle configuration schemes and two complementary modulation waves and their corresponding operating modes are proposed to generate the switching timing sequence of each parallel branch. This method optimizes output current ripple while providing modulation degrees of freedom for optimizing other performance indicators.

Description

Technical Field

[0001] This invention relates to multi-parallel converters, and more specifically to a vector timing unified construction method for ripple optimization of multi-parallel converters. Background Technology

[0002] With the continuous growth in demand for high-power power supply in the industrial sector, multi-parallel converters have been widely used in various high-power application scenarios such as high-power motor drives, grid-connected wind power generation, and uninterruptible power supplies. Multi-parallel power converters employ a topology of multiple two-level converters directly connected in parallel, effectively reducing system size and hardware costs while doubling system capacity, making it the preferred current expansion topology solution for high-power applications.

[0003] However, during the operation of multi-parallel converters, output current ripple remains a key bottleneck restricting system performance improvement. Output current ripple not only reduces power conversion efficiency but also severely affects the operating accuracy and lifespan of load equipment. Especially in scenarios with high power quality requirements, such as precision motor drives and new energy grid connection, excessive current ripple can directly lead to the system's inability to operate normally and stably.

[0004] Currently, the most widely used technology for ripple suppression in multi-parallel converters is carrier phase-shift modulation. This method achieves ripple cancellation by adjusting the carrier phase of each parallel branch. However, this method cannot control timing and has significant limitations: it is only applicable to parallel scenarios with a specific number of converters. When the number of parallel converters is adjusted, the carrier phase configuration scheme needs to be redesigned, resulting in poor versatility and limited ripple suppression effect. Furthermore, existing technologies generally lack a unified modulation scheme applicable to any number of parallel converters. Most modulation methods are designed for parallel systems with a fixed number of converters. Once the number of parallel converters changes, the vector timing and switching control strategy need to be redesigned, leading to poor system scalability, high debugging costs, and difficulty in meeting the practical needs of flexible power level expansion in engineering applications. In addition, existing vector timing construction methods often focus only on the single objective of ripple suppression, without providing redundant timing options. This fails to provide modulation space for improving other key performance indicators such as switching loss optimization and circulating current suppression, making it difficult to adapt to the multi-objective optimization requirements under complex operating conditions.

[0005] Therefore, there is an urgent need for a vector timing construction method that can adapt to any number of parallel converters, effectively optimize output current ripple, and has high versatility while taking into account the coordinated optimization of multiple performance indicators. Summary of the Invention

[0006] The purpose of this invention is to provide a unified method for constructing vector timing for output current ripple optimization, in order to solve the technical problems existing in the prior art, such as poor universality, limited ripple suppression effect, and poor scalability. While optimizing output current ripple, it provides modulation degrees of freedom for optimizing other performance indicators, thereby promoting the further improvement of the overall performance of multi-parallel converter systems.

[0007] The technical solution to achieve the purpose of this invention is as follows:

[0008] A unified vector timing construction method for ripple optimization of multiple parallel converters includes:

[0009] Step 1: Based on the reference voltage and the number of parallel units, determine a starting voltage vector using a preset judgment rule. The starting voltage vector belongs to the set of the top three voltage vectors. Based on the starting voltage vector, generate a voltage vector sequence by progressively changing the number of conducting devices in each phase. All voltage vectors in the voltage vector sequence belong to the set of the top three voltage vectors. The top three voltage vectors refer to the set of the top three voltage vectors in the vector plane after sorting them from smallest to largest according to the voltage vector differential magnitude between them and the reference voltage.

[0010] Step 2: From the voltage vector sequence described in Step 1, select four consecutive voltage vectors according to the arrangement order of the voltage vector sequence to form an asymmetric vector timing basic unit; with the fourth voltage vector in the asymmetric vector timing basic unit as the center of symmetry, mirror the four consecutive voltage vectors in the opposite order to form a symmetric vector timing basic unit containing seven voltage vectors; wherein, by changing the starting position of the four consecutive voltage vectors, multiple vector timing basic units can be formed;

[0011] Step 3: Based on the four voltage vectors contained in the vector timing basic unit, establish a corresponding set of equations according to the volt-second balance principle, set constraints in the set of equations, and solve for the duty cycle of the four voltage vectors; then, based on the four voltage vectors, determine the duty cycle of each phase online through a preset judgment rule.

[0012] Step 4: Repeat the arrangement of the symmetric vector timing basic unit N times according to the number of parallel units N to construct a complete vector timing suitable for the number of parallel units N;

[0013] Step 5: Based on the complete vector timing sequence, determine the total number of conducting devices in all parallel branches of each phase at each time, and allocate the number of conducting devices among the parallel branches to generate the switching timing sequence corresponding to each parallel branch. The same vector timing sequence can form multiple redundant switching timing sequences.

[0014] Step 6: Based on the switching timing of each parallel branch generated in Step 5, determine the carrier configuration of each parallel branch to realize the switching timing; wherein, the carrier configuration includes four different triangular carrier initial angle sequences, and the parity of the sum of the number of conducting devices in all parallel branches of each phase is used to determine the two types of triangular carrier configurations adopted by each phase parallel branch.

[0015] Step 7: Based on the carrier configuration obtained in Step 6 and the phase duty cycles obtained in Step 3, set two types of complementary modulation waves and two corresponding complementary operation modes. In different operation modes, the comparison relationship between the modulation wave and the carrier is reversed.

[0016] Step 8: Sort the three-phase reference voltages according to their magnitudes, determine each phase as the maximum, intermediate or minimum value, and allocate the corresponding modulation wave and carrier configuration accordingly to generate the corresponding vector timing sequence, thereby realizing a unified implementation scheme for the entire sector.

[0017] Furthermore, step 1 specifically includes:

[0018] Define three variables p, q, and r, respectively, satisfying:

[0019]

[0020] in, , and These represent the maximum, median, and minimum values ​​determined after sorting based on the magnitude relationships of the three-phase voltages:

[0021]

[0022] Let p s q s and r s The floor values ​​of p, q, and r are respectively:

[0023]

[0024] In the formula p s q s and r s Let S be a natural number. max S mid and S min Let be the total number of switching devices connected to the positive terminal of the DC bus in each parallel branch belonging to the maximum, intermediate, and minimum value phases, respectively. Each voltage vector in the vector plane can be uniquely represented as... For example, if at a certain moment the maximum value of the three-phase reference voltage is phase A, the intermediate value is phase B, and the minimum value is phase C, then S max =S a Smid =S b S min =S c S a ,S b and S c These represent the total number of switching devices connected to the positive terminal of the DC bus in each of the N parallel branches belonging to phases A, B, and C, respectively.

[0025] make Determine the starting vector of the voltage vector sequence. The initial voltage vector belongs to the set of the three nearest voltage vectors of the reference voltage, and at the same time, let Determine the termination vector of the voltage vector sequence. ;

[0026] When p s With q s +r s When both are odd or both are even, use Starting with the vector, the total number of conducting phases is incremented by 1 in the order of maximum value phase, intermediate value phase, and minimum value phase, and this incrementing process is repeated until the termination vector is reached. The sequence that forms the vector time series contains A vector; the progressive process is as follows:

[0027]

[0028] When p s With q s +r s The parity of the two numbers differs; that is, when one is odd and the other is even, the parity is determined by... Starting with the vector, the total number of conducting phases is incremented by 1 in the order of intermediate phase, maximum phase, and minimum phase, and this incrementing process is repeated until the termination vector is reached. The sequence that forms the vector time series contains A vector; the progressive process is as follows:

[0029]

[0030] All voltage vectors in the two voltage vector sequences belong to the set of the three nearest voltage vectors of the reference voltage; the three nearest voltage vectors refer to the set of the top three voltage vectors in the vector plane after sorting them from smallest to largest according to the voltage vector differential magnitude between them and the reference voltage.

[0031] Furthermore, the construction process of the asymmetric vector timing basic unit and the symmetric vector timing basic unit in step 2 is as follows:

[0032] Four consecutive voltage vectors are selected according to the arrangement order of the voltage vector sequence described in step 1 to form an asymmetric vector timing basic unit; for the voltage vector sequence containing M voltage vectors, four consecutive voltage vectors are selected sequentially by means of a sliding window to form (M-3) asymmetric vector timing basic units; with the fourth voltage vector in the asymmetric vector sequence as the center of symmetry, the first three voltage vectors are mirrored in the opposite order to form a symmetric vector timing basic unit containing seven voltage vectors;

[0033] based on A vector can generate An asymmetric vector timing basic unit, the specific production process is as follows:

[0034] choose The first to fourth vectors in the sequence generate the first set of asymmetric sequences:

[0035]

[0036] choose The second to fifth vectors in the sequence generate the second set of asymmetric sequences:

[0037]

[0038] And so on, select the first To the The nth vector is generated. A set of asymmetric sequences.

[0039] Then, the basic temporal unit for generating the first set of symmetric vectors for the first set of asymmetric sequences is:

[0040] .

[0041] Furthermore, the specific steps in step 3 to obtain the duty cycle of the four voltage vectors include:

[0042] For the four voltage vectors contained in the asymmetric vector timing basic unit determined in step 2, the four voltage vectors are decomposed into components in a three-phase non-orthogonal stationary coordinate system. At any given moment, only two phase axes of the three phase axes are selected as the decomposition basis axes. The two decomposition basis axes are not fixed in advance, but are determined in real time according to the magnitude relationship of the instantaneous values ​​of the three-phase voltages: the instantaneous values ​​of the three-phase reference voltages are compared to determine the phase with the largest reference voltage value and the phase with the middle voltage value, and the two corresponding phase axes are selected as the two basis axes of the voltage vector decomposition at the current moment. At the same time, a corresponding set of equations is established according to the volt-second balance principle, and constraints are set in the set of equations to solve for the duty cycle of the four voltage vectors.

[0043] Further, in step 3, the duty cycle of each phase is determined online through a preset judgment rule. Specifically, based on the four voltage vectors contained in the asymmetric vector timing basic unit, the number of switching devices connected to the DC positive terminal in the parallel branches corresponding to the maximum value phase, intermediate value phase, and minimum value phase during the action of each voltage vector is determined, and an expression for the number of conduction devices in each phase is established. According to the duty cycle of each voltage vector, the number of conduction devices corresponding to each voltage vector is multiplied by its duty cycle and summed. The result is divided by the total number of parallel branches N to obtain the duty cycle of the maximum value phase, intermediate value phase, and minimum value phase.

[0044] Further, step 4 repeats the symmetrical vector timing basic unit determined in step 3 N times to construct a complete vector timing sequence suitable for the number of parallel units N. Since the head vector and tail vector in the symmetrical vector timing basic unit are the same vector, the complete vector timing sequence contains (6N+1) voltage vectors, where N is the number of parallel units. For example, repeating the symmetrical vector timing basic unit N times results in:

[0045] .

[0046] Further, in step 5, based on the complete vector timing sequence, the total number of switching devices connected to the DC positive terminal in each parallel branch corresponding to each phase in the timing sequence is determined. Under the premise of satisfying the constraint of the total number of switching devices, the number of switching devices is allocated among each parallel branch to generate the switching timing sequence corresponding to each parallel branch. Among them, the same vector timing sequence corresponds to multiple redundant switching timing sequences that satisfy the constraint of the number of switching devices. These redundant switching timing sequences can all be used for ripple optimization.

[0047] Furthermore, step 6 determines the carrier configuration of each parallel branch, specifically including:

[0048] In the first type of carrier configuration, the initial phase angle of each triangular carrier used by each parallel branch is:

[0049] ,

[0050] Where k is a natural number and takes a value between 0 and N-1, then the first type of carrier configuration has N equivalent initial phase angles, and N is the number of parallel stations;

[0051] In the second type of carrier configuration, the initial phase angle of each triangular carrier used by each parallel branch is:

[0052] ,

[0053] Where k is a natural number and takes a value between 0 and N-1, then the second type of carrier configuration has N equivalent initial phase angles, and N is the number of parallel stations;

[0054] In the third type of carrier configuration, the initial phase angle of each triangular carrier used by each parallel branch is:

[0055] ,

[0056] Where k is a natural number and takes a value between 0 and N-1, then there are N equivalent initial phase angles for the third type of carrier configuration, and N is the number of parallel stations;

[0057] In the fourth type of carrier configuration, the initial phase angle of each triangular carrier used in each parallel branch is:

[0058] ,

[0059] Where k is a natural number and takes a value between 0 and N-1, then the fourth type of carrier configuration has N equivalent initial phase angles, and N is the number of parallel stations;

[0060] Based on the parity of the sum of the number of switching devices connected to the positive terminal of the DC bus in each parallel branch, one of the fourth type of carrier configurations is selected: when the sum of the number of switching devices is even, the first type of carrier configuration or the second type of carrier configuration is selected; when the sum of the number of switching devices is odd, the third type of carrier configuration or the fourth type of carrier configuration is selected. After selecting the carrier configuration type, according to the switching timing of each parallel branch, N equivalent initial phase angles of the selected carrier configuration are allocated to the corresponding parallel branches to determine the initial angle of the triangular carrier of each parallel branch.

[0061] Furthermore, step 7 identifies two types of complementary modulation waves and their corresponding two complementary operating modes, specifically including:

[0062] Based on the duty cycle of each phase determined in step 3, and in conjunction with the time distribution pattern of the three-phase switching sequence, determine the modulation wave type used by the parallel branch to which each phase belongs;

[0063] The first and third types of modulation waves are modulation waves that are proportional to the duty cycle of the corresponding phase. The second and fourth types of modulation waves are modulation waves that are complementary to the first and third types of modulation waves, respectively. That is, the first type of modulation wave and the second type of modulation wave in the same phase, and the third type of modulation wave and the fourth type of modulation wave satisfy the following: the sum of the two is equal to a preset proportional coefficient; wherein, the preset proportional coefficient is determined by the carrier amplitude or the modulator range.

[0064] Simultaneously, the operating mode is determined based on the modulation wave type. The operating modes include a first operating mode and a second operating mode, which are logically opposite to each other. The first operating mode is as follows: when the triangular carrier wave is less than the modulation wave, a high-level signal is output to turn on the corresponding switching device; when the triangular carrier wave is greater than or equal to the modulation wave, a low-level signal is output to turn off the corresponding switching device. The second operating mode is as follows: when the triangular carrier wave is greater than or equal to the modulation wave, a high-level signal is output to turn on the corresponding switching device; when the triangular carrier wave is less than the modulation wave, a low-level signal is output to turn off the corresponding switching device.

[0065] Type I and Type III modulated waves use the first operating mode; Type II and Type IV modulated waves use the second operating mode.

[0066] A vector timing unified construction device for ripple optimization of multiple parallel converters, comprising:

[0067] The voltage vector sequence generation unit determines a starting voltage vector based on the reference voltage and the number of parallel units using a preset judgment rule. Based on the starting voltage vector, a voltage vector sequence is generated by progressively changing the number of conducting switches in each phase. The starting voltage vector and all voltage vectors in the voltage vector sequence belong to the set of the top three voltage vectors. The set of the top three voltage vectors refers to the set of the top three voltage vectors in the vector plane after sorting them from smallest to largest according to the voltage vector differential magnitude between them and the reference voltage.

[0068] The timing basic unit construction unit selects four consecutive voltage vectors based on the voltage vector sequence to form an asymmetric vector timing basic unit; taking the fourth voltage vector in the asymmetric vector timing basic unit as the center of symmetry, the four consecutive voltage vectors are mirrored in reverse order to form a symmetric vector timing basic unit containing seven voltage vectors; wherein, by changing the starting position of the four consecutive voltage vectors, multiple asymmetric vector timing basic units are formed.

[0069] The duty cycle calculation unit, based on the four voltage vectors contained in the asymmetric vector timing basic unit, establishes a corresponding set of equations according to the volt-second balance principle, sets constraints in the set of equations, solves the duty cycle of the four voltage vectors, and then determines the duty cycle of each phase online through preset judgment rules.

[0070] A complete vector timing construction unit is formed by repeatedly arranging the symmetrical vector timing basic unit N times according to the number of parallel units N, thereby constructing a complete vector timing suitable for the number of parallel units N;

[0071] The switching timing generation unit determines the total number of conducting devices in all parallel branches of each phase at each time according to the complete vector timing, and allocates the number of conducting devices among the parallel branches to generate the switching timing corresponding to each parallel branch.

[0072] The carrier configuration determination unit determines the carrier configuration of each parallel branch according to the switching timing corresponding to each parallel branch;

[0073] The modulation wave and operation mode determination unit determines two types of complementary modulation waves and two corresponding complementary operation modes based on the obtained carrier configuration and the obtained phase duty cycles. Under different operation modes, the comparison relationship between the modulation wave and the carrier is reversed.

[0074] The vector timing generation unit sorts the three-phase reference voltages according to their magnitudes, determines each phase as its maximum, intermediate, or minimum value, and allocates the corresponding modulation wave and carrier configuration accordingly to generate the corresponding vector timing, thereby achieving vector timing uniformity across the entire sector.

[0075] Compared with existing technologies, the beneficial effects of this invention are as follows: This invention constructs a near-three voltage vector set based on a reference voltage, and generates a vector sequence base library by progressively changing the total number of conducting switching devices in parallel branches, forming a unified modulation framework applicable to any number of parallel converters; based on the vector sequence base library, a symmetrical vector timing basic unit is constructed, and a complete vector timing sequence applicable to any number of parallel converters is formed by repeatedly expanding this timing basic unit; further, the switching timing sequence of each parallel branch is determined based on the complete vector timing sequence, and two types of triangular carrier initial angle configuration schemes and two complementary modulation waves and their corresponding operating modes are proposed to generate the switching timing sequence of each parallel branch, realizing unified modulation of any number of parallel converters, with strong versatility and good scalability; this invention significantly optimizes the output current ripple and improves power quality; the modulation framework of this invention is simple and reliable, and has low engineering implementation difficulty. Attached Figure Description

[0076] Figure 1 This is a diagram showing the parallel structure of a multi-parallel converter bridge.

[0077] Figure 2This is a diagram of the grid-side structure of multiple parallel converters.

[0078] Figure 3 This is a diagram showing the sector division of the 0~60° vector plane for three parallel units.

[0079] Figure 4 This is a diagram showing the sector division of the 0~60° vector plane for four parallel units.

[0080] Figure 5 This is a diagram showing the sector division of the 0~60° vector plane for five parallel units.

[0081] Figure 6 This diagram illustrates two types of modulation waves and operating modes for multiple parallel converters.

[0082] Figure 7 The diagrams show the three-phase current waveform, single-phase circulating current waveform, and zero-sequence circulating current waveform under a modulation scheme of 0.3 using the present application and a conventional modulation strategy.

[0083] Figure 8 The diagrams show the three-phase current waveforms, single-phase circulating current waveforms, and zero-sequence circulating current waveforms under a modulation scheme of 0.6 using the present application and a conventional modulation strategy.

[0084] Figure 9 The diagrams show the three-phase current waveforms, single-phase circulating current waveforms, and zero-sequence circulating current waveforms under a modulation scheme of 0.9 using the present application and a conventional modulation strategy. Detailed Implementation

[0085] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0086] This embodiment provides a unified vector timing construction method for ripple optimization of multi-parallel converters. This method constructs a near-three-voltage vector set based on a reference voltage and generates a basic vector sequence library by progressively varying the total number of conducting switching devices in parallel branches, forming a unified modulation framework applicable to any number of parallel converters. Based on the basic vector sequence library, a symmetrical vector timing unit is constructed, and by repeatedly expanding this basic timing unit, a complete vector timing sequence applicable to any number of parallel converters is formed. Furthermore, the switching timing sequence of each parallel branch is determined based on the complete vector timing sequence. A triangular carrier initial angle configuration scheme and two complementary modulation waves and their corresponding operating modes are proposed to generate the switching timing sequence of each parallel branch. Specific embodiments of this method include:

[0087] Multi-parallel converter topology diagram as follows Figure 1 and Figure 2 . Among them, the DC-side bridge arms are directly connected in parallel as Figure 1 , and the AC-side is connected in parallel through a filter inductor as Figure 2 . Among them, i a1 , i b1 and i c1 represent the three-phase currents of the first converter; i ak , i bk and i<( ck represent the three-phase currents of the k-th converter; i aN , i bN and i cN represent the three-phase currents of the N-th converter; V DC represents the DC bus voltage, 1 < k < N, and N is the total number of converters. e<( a , e b and e c represent the AC-side power supply (a resistive load can be used in the inverter mode); L1 and L respectively represent the bridge arm inductor and the grid-connected filter inductor.

[0088] According to Figure 1 and Figure 2 , establish the KVL equation and obtain:

[0089] (1)

[0090] In the formula, u a1o , u b1o and u c1o represent the three-phase output voltages of the first converter; u ako , u bko and u cko represent the three-phase output voltages of the k-th converter; u aNo , u bNo and u cNo represent the three-phase output voltages of the N-th converter. Taking the k-th converter as an example, the three-phase output voltages satisfy:

[0091] (2)

[0092] According to formula (1) and formula (2), it is obtained that the output voltage of the converter satisfies:

[0093] (3)

[0094] Since the three-phase voltages and currents are symmetrical, e a +e b +e c = 0, i a +i b +i c = 0. According to formula (3), the common-mode voltage expression is obtained:

[0095] (4)

[0096] Substituting equation (4) into equation (3), we obtain the expression for the converter output voltage:

[0097] (5)

[0098] The equivalent output voltage expression of the converter satisfies:

[0099] (6)

[0100] For N parallel converters, there are 8 N There are 3×N switch state combinations, corresponding to 3×N 2 +3 × N + 1 basic vectors. Definition Let N represent the total number of switching devices connected to the positive terminal of the DC bus in the three-phase parallel branches, with values ​​ranging from 0 to N. This leads to the mathematical model in the three-phase stationary coordinate system:

[0101] (7)

[0102] Further simplification yields the vector plane expression in a two-phase stationary coordinate system:

[0103] (8)

[0104] Taking 3 to 5 units in parallel as an example, we get Figures 3-5 For N parallel converters, each voltage vector in the voltage vector plane can be uniquely represented as: , with V 210 For example, 2 represents S a =2, 1 indicates S b =1, 0 indicates S c =0. According to Figures 3-5 It can be seen that as the number of parallel units increases, the vector plane subdivision becomes more refined, the target vector synthesis error through the near three-vector method becomes smaller, and the output current quality becomes higher.

[0105] Based on the reference voltage and the number of parallel units, a starting voltage vector is determined using a preset judgment rule. This starting voltage vector belongs to the set of the three nearest voltage vectors of the reference voltage. (U is used to...) a u b and u c This represents the reference voltages for phases A, B, and C, expressed in terms of the DC bus voltage V. DC The three-phase reference voltage is normalized to obtain the normalized three-phase voltage:

[0106]

[0107] The three-phase per-unit voltages are sorted according to their magnitudes, and the maximum values ​​are determined accordingly. median and minimum value ,in:

[0108]

[0109] Define three variables p, q, and r, respectively, satisfying:

[0110] (9)

[0111] Let p s q s and r s Let p, q, and r be the floor values ​​of p, q, and r, respectively, where p s q s and r s If is a natural number, then:

[0112] (10)

[0113] Define S max S mid and S min Let be the total number of switching devices connected to the positive terminal of the DC bus in each parallel branch belonging to the maximum, intermediate, and minimum value phases, respectively. Each voltage vector in the vector plane can be uniquely represented as... For example, if at a certain moment the maximum value of the three-phase reference voltage is phase A, the intermediate value is phase B, and the minimum value is phase C, then S max =S a S mid =S b S min =S c S a ,S b and S c These represent the total number of switching devices connected to the positive terminal of the DC bus in each of the N parallel branches belonging to phases A, B, and C.

[0114] make Determine the starting vector of the vector sequence. The initial voltage vector belongs to the set of the three nearest voltage vectors of the reference voltage, and at the same time, let Determine the termination vector of the vector sequence. .

[0115] When p s With q s +r sWhen both are odd or both are even, use Starting with the vector, the total number of conducting phases is incremented by 1 in the order of maximum value phase, intermediate value phase, and minimum value phase, and this incrementing process is repeated until the termination vector is reached. The sequence that forms the vector time series contains A vector. The incrementing process is as follows:

[0116]

[0117] When p s With q s +r s The parity of the two numbers differs; that is, when one is odd and the other is even, the parity is determined by... Starting with the vector, the total number of conducting phases is incremented by 1 in the order of intermediate phase, maximum phase, and minimum phase, and this incrementing process is repeated until the termination vector is reached. The sequence that forms the vector time series contains A vector. The progressive process is as follows:

[0118]

[0119] Furthermore, the duty cycle expressions of each basic vector are solved by selecting the basic vector and volt-second balance.

[0120] For including The voltage vector sequence of a voltage vector can be formed by sequentially selecting four consecutive voltage vectors using a sliding window method. Asymmetric vector timing basic unit, wherein the asymmetric vector timing basic unit is:

[0121]

[0122] Then its corresponding symmetric vector time-series basic unit is:

[0123]

[0124] The above units are repeated N times to construct a complete vector timing sequence suitable for the number of parallel units N. Here, V1 and V4 are redundant vectors sharing the same vertex vector. On the vector plane, the four vectors are projected onto the axes containing the maximum and median values, using... , , and Represents the projected components on the axis containing the maximum phase; using , , and This represents the projected component on the axis containing the intermediate phase. Based on the volt-second balance principle, a corresponding system of equations is established, and constraints are set within this system. Solving for these equations yields the duty cycles d1, d2, d3, and d4 of the four voltage vectors.

[0125] (11)

[0126] Among them, u max and u mid These represent the projections of the reference vector onto the maximum phase axis and the intermediate phase axis, respectively; k represents the allocation coefficients of V1 and V4. T F For the coefficient matrix, when the rank is 4, the duty cycle expression has a unique solution:

[0127] (12)

[0128] For the four non-clamped fundamental vectors V1, V2, V3, and V4, S xmax S xmid and S xmin V x The sum of the number of switching devices connected to the positive terminal of the DC bus in each parallel branch belonging to the maximum, intermediate, and minimum phases of the vector; the sequence of the sum of the number of switching devices corresponding to the asymmetric vector timing basic unit composed of the four basic vectors; and the sequence of the sum of the number of switching devices corresponding to the asymmetric vector timing basic unit composed of the four basic vectors. The corresponding duration of action is Solve for the three-phase action time to satisfy: .

[0129] When a non-clamping modulation strategy is used, the expression differs depending on the four basic vectors selected. This is based on the three-phase reference voltage u. a u b and u c Given the magnitude of u, calculate the duty cycle of the corresponding phase. a >u b >u c , then d a =d max d b =d mid d c =d min And so on for other sectors.

[0130] There are four types of carriers. In the first type of carrier configuration, the initial phase angle of each triangular carrier used by each parallel branch is: In this case, k is a natural number and its value is between 0 and N-1. Then, the first type of carrier configuration has N equivalent initial phase angles, and N is the number of parallel stations.

[0131] In the second type of carrier configuration, the initial phase angle of each triangular carrier used by each parallel branch is: In this case, k is a natural number and its value is between 0 and N-1. Then, the second type of carrier configuration has N equivalent initial phase angles, where N is the number of parallel stations.

[0132] In the third type of carrier configuration, the initial phase angle of each triangular carrier used by each parallel branch is: ,

[0133] Where k is a natural number and takes a value between 0 and N-1, then the third type of carrier configuration has N equivalent initial phase angles, and N is the number of parallel stations.

[0134] In the fourth type of carrier configuration, the initial phase angle of each triangular carrier used in each parallel branch is: In this case, k is a natural number and its value is between 0 and N-1. Therefore, there are N equivalent initial phase angles for the fourth type of carrier configuration, where N is the number of parallel stations.

[0135] Based on the parity of the sum of the number of switching devices connected to the positive terminal of the DC bus in the parallel branch to which each phase belongs, one of the fourth type of carrier configurations is selected: when the sum of the number of switching devices is even, the first type of carrier configuration or the second type of carrier configuration is selected; when the sum of the number of switching devices is odd, the third type of carrier configuration or the fourth type of carrier configuration is selected.

[0136] For multi-parallel converters, there are two types of modulation waves and operating modes, such as Figure 6 As shown:

[0137] When selecting a Type I or Type III carrier, the modulation wave expression is u. mx =d x When using ×PRD, the operating mode is defined as follows: when the carrier wave is less than the modulated wave, the output is high; when the carrier wave is greater than the modulated wave, the output is low.

[0138] When selecting a Type II or Type IV carrier, the modulation wave expression is u. mx =(1-d x When using )×PRD, the operating mode is defined as follows: when the carrier wave is less than the modulated wave, the output is low; when the carrier wave is greater than the modulated wave, the output is high.

[0139] Based on the above carrier configuration and operating mode, as well as the duration of the three-phase duty cycle, the switching signals of all converters are obtained; at the same time, arbitrarily swapping the in-phase carriers of the i-th converter and the j-th converter will not affect the output current ripple performance of the converter.

[0140] Taking three units connected in parallel as an example, with a modulation index of 0.3 and an angle of 10°, the three-phase reference voltages satisfy the following:

[0141] (13)

[0142] The three-phase reference voltage satisfies u a >u b >u c Substituting into equation (13), we get:

[0143] (14)

[0144] p in equation (14) s q s and r s Natural numbers not greater than p, q, and r, respectively. s q s and r s Taking all zeros, we get:

[0145] (15)

[0146] make Determine the starting vector of the vector sequence. For three units in parallel, the termination vector ,at this time , .by The triangle containing the reference vector is labeled (0,0,0), as follows: Figure 3 Initial vector and termination vector correspond A set of basic vectors forms a candidate vector library for the smallest triangle containing the reference vector. Where p s q s and r s If all values ​​are 0 and all are even, then all vectors in the triangle are incremented by 1 in the order of maximum value phase, intermediate value phase, and minimum value phase, to form the basic vector unit group of the smallest triangle:

[0147] (16)

[0148] The selected non-clamped sequence exists Various combinations, corresponding Seed sequence:

[0149] (1) Four basic vectors V 1M V 2M V 3M and V 4M For V 000 V 100 V 110 and V 111The smallest unit of the seven-segment structure is

[0150] (17)

[0151] (18)

[0152] (2) Four basic vectors V 1M V 2M V 3M and V 4M For V 100 V 110 V 111 and V 211 The smallest unit of the seven-segment structure is

[0153] (19)

[0154] (20)

[0155] (3) Four basic vectors V 1M V 2M V 3M and V 4M For V 110 V 111 V 211 and V 221 The smallest unit of the seven-segment structure is

[0156] (twenty one)

[0157] (twenty two)

[0158] (4) Four basic vectors V 1M V 2M V 3M and V 4M For V 111 V 211 V 221 and V 222 The smallest unit of the seven-segment structure is

[0159] (twenty three)

[0160] (twenty four)

[0161] (5) Four basic vectors V 1M V 2M V 3M and V 4M For V 211 V 221 V 222 and V322 The smallest unit of the seven-segment structure is

[0162] (25)

[0163] (26)

[0164] (6) Four basic vectors V 1M V 2M V 3M and V 4M For V 221 V 222 V 322 and V 332 The smallest unit of the seven-segment structure is

[0165] (27)

[0166] (28)

[0167] (7) Four basic vectors V 1M V 2M V 3M and V 4M For V 222 V 322 V 332 and V 333 The smallest unit of the seven-segment structure is

[0168] (29)

[0169] (30)

[0170] Taking three units in parallel as an example, the modulation index is selected as 0.3, the angle is 10°, and the four basic vectors V1, V2, V3 and V4 of the non-clamped sequence are selected as V 000 V 100 V 110 and V 111 At the same time, substituting into equation (12), we get

[0171] (31)

[0172] Among them, V 000a V 100a V 110a and V 111a These represent the vectors V corresponding to the clamping sequence. 000 V 100 V 110 and V 111 The projection of V onto the phase axis of phase a 000b V100b V 110b and V 111b These represent the vectors V corresponding to the clamping sequence. 000 V 100 V 110 and V 111 The projection onto the phase axis of phase b satisfies:

[0173] (32)

[0174] For the four non-clamped fundamental vectors V 000 V 100 V 110 and V 111 The corresponding level is The corresponding duration of action is Solve for the three-phase action time to satisfy: .

[0175] When the total number of conducting phases is even, the first type of carrier configuration is selected: the initial angle of the first three-phase converter is... The initial angle of the second three-phase converter is The initial angle of the third three-phase converter is At the same time, the expression for the first type of modulation wave is chosen as u. mx =d x When using ×PRD, the operating mode is defined as follows: when the carrier wave is less than the modulating wave, the output is high; when the carrier wave is greater than the modulating wave, the output is low. Based on the above carrier configuration and operating mode, as well as the duration of the three-phase duty cycle, the switching signals of all converters are obtained.

[0176] The following are the experimental results of a specific case. In this embodiment, the number of units connected in parallel is 3, the DC side voltage is 400V, and the AC side is a purely resistive load with a resistance of 10Ω; the bridge-side output inductance is 5mH, and the parasitic resistance is negligible; the switching frequency is 10kHz; and the fundamental frequency is 50Hz.

[0177] The simulation mainly demonstrates the optimal ripple performance of this scheme within different modulation ranges. Figure 7 The three-phase current waveform, single-phase circulating current waveform, and zero-sequence circulating current waveform are shown under a modulation intensity of 0.3 using the present invention and a conventional modulation strategy. Figure 8 The diagram illustrates the three-phase current waveform, single-phase circulating current waveform, and zero-sequence circulating current waveform under a modulation scheme of 0.6 using both the present invention and a conventional modulation strategy. Figure 9 The three-phase current waveform, single-phase circulating current waveform, and zero-sequence circulating current waveform are shown under a modulation scheme of 0.9 using the present invention and a conventional modulation strategy. Figures 7 to 9 This demonstrates that the present invention improves the output current quality without sacrificing single-phase circulating current and zero-sequence circulating current.

[0178] This embodiment also provides a vector timing unified construction device for ripple optimization of multiple parallel converters, including:

[0179] The voltage vector sequence generation unit determines a starting voltage vector based on the reference voltage and the number of parallel units using a preset judgment rule. Based on the starting voltage vector, a voltage vector sequence is generated by progressively changing the number of conducting switches in each phase. The starting voltage vector and all voltage vectors in the voltage vector sequence belong to the set of the top three voltage vectors. The set of the top three voltage vectors refers to the set of the top three voltage vectors in the vector plane after sorting them from smallest to largest according to the voltage vector differential magnitude between them and the reference voltage.

[0180] The timing basic unit construction unit selects four consecutive voltage vectors based on the voltage vector sequence to form an asymmetric vector timing basic unit; taking the fourth voltage vector in the asymmetric vector timing basic unit as the center of symmetry, the four consecutive voltage vectors are mirrored in reverse order to form a symmetric vector timing basic unit containing seven voltage vectors; by changing the starting position of the four consecutive voltage vectors, multiple asymmetric vector timing basic units are formed.

[0181] The duty cycle calculation unit, based on the four voltage vectors contained in the asymmetric vector timing basic unit, establishes a corresponding set of equations according to the volt-second balance principle, sets constraints in the set of equations, solves the duty cycle of the four voltage vectors, and then determines the duty cycle of each phase online through preset judgment rules.

[0182] A complete vector timing construction unit is formed by repeatedly arranging the symmetrical vector timing basic unit N times according to the number of parallel units N, thereby constructing a complete vector timing suitable for the number of parallel units N;

[0183] The switching timing generation unit determines the total number of conducting devices in all parallel branches of each phase at each time according to the complete vector timing, and allocates the number of conducting devices among the parallel branches to generate the switching timing corresponding to each parallel branch.

[0184] The carrier configuration determination unit determines the carrier configuration of each parallel branch according to the switching timing corresponding to each parallel branch;

[0185] The modulation wave and operation mode determination unit determines two types of complementary modulation waves and two corresponding complementary operation modes based on the obtained carrier configuration and the obtained phase duty cycles. Under different operation modes, the comparison relationship between the modulation wave and the carrier is reversed.

[0186] The vector timing generation unit sorts the three-phase reference voltages according to their magnitudes, determines each phase as its maximum, intermediate, or minimum value, and allocates the corresponding modulation wave and carrier configuration accordingly to generate the corresponding vector timing, thereby achieving vector timing uniformity across the entire sector.

[0187] This invention innovatively proposes a unified vector timing construction method for ripple optimization in multi-parallel converters. The designed method can effectively suppress current ripple. The timing set includes various redundant vector timings and switching timings, which, while optimizing output current ripple, provide modulation degrees of freedom for optimizing other performance indicators.

[0188] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and incorporate common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A unified vector timing construction method for ripple optimization of multi-parallel converters, characterized in that, include: Step 1: Based on the reference voltage and the number of parallel units, determine a starting voltage vector using a preset judgment rule. Based on the starting voltage vector, generate a voltage vector sequence by progressively changing the number of conducting devices in each phase. The starting voltage vector and all voltage vectors in the voltage vector sequence belong to the set of the top three voltage vectors. The set of the top three voltage vectors refers to the set of the top three voltage vectors in the vector plane after sorting them from smallest to largest according to the voltage vector differential magnitude between them and the reference voltage. Step 2: Select four consecutive voltage vectors based on the voltage vector sequence to form an asymmetric vector timing basic unit; with the fourth voltage vector in the asymmetric vector timing basic unit as the center of symmetry, mirror the four consecutive voltage vectors in reverse order to form a symmetric vector timing basic unit containing seven voltage vectors; wherein, by changing the starting position of the four consecutive voltage vectors, multiple asymmetric vector timing basic units are formed. Step 3: Based on the four voltage vectors contained in the asymmetric vector timing basic unit, establish the corresponding set of equations according to the volt-second balance principle, set the constraint conditions in the set of equations, solve for the duty cycle of the four voltage vectors, and then determine the duty cycle of each phase online through the preset judgment rules. Step 4: Repeat the arrangement of the symmetric vector timing basic unit N times according to the number of parallel units N to construct a complete vector timing suitable for the number of parallel units N; Step 5: Based on the complete vector timing sequence, determine the total number of conducting devices in all parallel branches of each phase at each time, and allocate the number of conducting devices among the parallel branches to generate the switching timing sequence corresponding to each parallel branch; Step 6: Determine the carrier configuration of each parallel branch according to the switching timing corresponding to each parallel branch; Step 7: Based on the carrier configuration obtained in Step 6 and the phase duty cycles obtained in Step 3, determine the two types of complementary modulation waves and the corresponding two complementary operation modes. In different operation modes, the comparison relationship between the modulation wave and the carrier is reversed. Step 8: Sort the three-phase reference voltages according to their magnitudes, determine each phase as the maximum, intermediate or minimum value, and allocate the corresponding modulation wave and carrier configuration accordingly to generate the corresponding vector timing sequence, thereby achieving vector timing unification across the entire sector.

2. The vector timing unified construction method for ripple optimization of multi-parallel converters according to claim 1, characterized in that, Step 1 specifically includes: Define three variables p, q, and r, respectively, satisfying: in, , and These represent the maximum, median, and minimum values ​​determined after sorting according to the magnitude relationship of the three-phase standard voltages, respectively. N is the total number of parallel converters, and V... DC This is the DC bus voltage; Let p s q s and r s The floor values ​​of p, q, and r are respectively: In the formula p s q s and r s It is a natural number; Define S max S mid and S min These represent the total number of conducting switching devices connected to the positive terminal of the DC bus in each parallel branch belonging to the maximum, intermediate, and minimum value phases, respectively. Each voltage vector on the vector plane is uniquely represented as... ;make Determine the starting vector of the voltage vector sequence. At the same time, let Determine the termination vector of the voltage vector sequence. ; When p s With q s +r s When both are odd or both are even, take the... Starting with the vector, the total number of conducting phases is incremented by 1 in the order of maximum value phase, intermediate value phase, and minimum value phase, and this incrementing process is repeated until the termination vector is reached. Generate a voltage vector sequence, which contains One vector; When p s With q s +r s When the parity is different, with Starting with the vector, the total number of conducting phases is incremented by 1 in the order of intermediate phase, maximum phase, and minimum phase, and this incrementing process is repeated until the termination vector is reached. Generate a voltage vector sequence, which contains A vector.

3. The vector timing unified construction method for ripple optimization of multi-parallel converters according to claim 1, characterized in that, For a voltage vector sequence containing M voltage vectors, four consecutive voltage vectors are selected sequentially using a sliding window method to form M-3 asymmetric vector timing basic units.

4. The vector timing unified construction method for ripple optimization of multi-parallel converters according to claim 1, characterized in that, Step 3, in order to obtain the duty cycle of the four voltage vectors, specifically includes: for the four voltage vectors contained in the asymmetric vector timing basic unit, in the three-phase non-orthogonal stationary coordinate system, at any given moment, only two of the three phase axes are selected as the decomposition basis axes to decompose the four voltage vectors. At the same time, a corresponding set of equations is established based on the volt-second balance principle, and constraints are set in the set of equations to obtain the duty cycle of the four voltage vectors.

5. The vector timing unified construction method for ripple optimization of multi-parallel converters according to claim 4, characterized in that, The decomposition basis axes are determined in real time based on the magnitude relationship of the instantaneous values ​​of the three-phase voltages. Specifically, the instantaneous values ​​of the three-phase reference voltages are compared to determine the phase with the largest reference voltage value and the phase with the middle voltage value. The corresponding phase axes are then selected as the two basis axes for the voltage vector decomposition at the current moment.

6. The vector timing unified construction method for ripple optimization of multi-parallel converters according to claim 4, characterized in that, In step 3, the duty cycle of each phase is determined online using preset judgment rules, specifically as follows: Based on the four voltage vectors contained in the asymmetric vector timing basic unit, during the period of action of each voltage vector, the number of switching devices connected to the DC positive terminal in the parallel branches corresponding to the maximum value phase, intermediate value phase, and minimum value phase are determined respectively, and an expression for the number of conduction devices in each phase is established; according to the duty cycle of each voltage vector, the number of conduction devices corresponding to each voltage vector is multiplied by its duty cycle and summed, and the summation result is divided by the total number of parallel branches N to obtain the duty cycle of the maximum value phase, intermediate value phase, and minimum value phase.

7. The vector timing unified construction method for ripple optimization of multi-parallel converters according to claim 1, characterized in that, When repeating the arrangement in step 4, the first and last voltage vectors of adjacent repeating units are the same, and the complete vector timing sequence contains 6N+1 voltage vectors.

8. The vector timing unified construction method for ripple optimization of multi-parallel converters according to claim 1, characterized in that, The carrier configuration described in step 6 includes four different triangular carrier initial angle sequences, determined based on the parity of the sum of the number of conducting devices in all parallel branches of each phase: when the sum of the number of conducting devices is even, the first or second type of carrier configuration is selected; when the sum of the number of conducting devices is odd, the third or fourth type of carrier configuration is selected. After selecting the carrier configuration type, according to the switching timing of each parallel branch, N equivalent initial phase angles from the selected carrier configuration are allocated to the corresponding parallel branches to determine the initial angle of the triangular carrier for each parallel branch; wherein, the initial angles of the four types of carrier configurations are: In the first type of carrier configuration, the initial phase angle of each triangular carrier used by each parallel branch is: Where k is a natural number and takes a value between 0 and N-1, the first type of carrier configuration has N equivalent initial phase angles; In the second type of carrier configuration, the initial phase angle of each triangular carrier used by each parallel branch is: Where k is a natural number and takes a value between 0 and N-1, the second type of carrier configuration has N equivalent initial phase angles; In the third type of carrier configuration, the initial phase angle of each triangular carrier used by each parallel branch is: Where k is a natural number and takes a value between 0 and N-1, the third type of carrier configuration has N equivalent initial phase angles; In the fourth type of carrier configuration, the initial phase angle of each triangular carrier used in each parallel branch is: Where k is a natural number and takes a value between 0 and N-1, the fourth type of carrier configuration has N equivalent initial phase angles, and N is the number of parallel stations.

9. The vector timing unified construction method for ripple optimization of multi-parallel converters according to claim 1, characterized in that, Step 7 identifies two types of complementary modulation waves and their corresponding two complementary action modes, specifically including: Based on the duty cycle of each phase and the time distribution pattern of the three-phase switching timing, the modulation wave type used by the parallel branch to which each phase belongs is determined: the first and third types of modulation waves are modulation waves proportional to the duty cycle of the corresponding phase, and the second and fourth types of modulation waves are modulation waves complementary to the first and third types of modulation waves, respectively. That is, the first and second types of modulation waves of the same phase, and the third and fourth types of modulation waves satisfy the following: their sum is equal to a preset proportional coefficient; wherein, the preset proportional coefficient is determined by the carrier amplitude or the modulator range. The operating mode is determined based on the modulation wave type: the operating mode includes a first operating mode and a second operating mode, which are logically opposite to each other; the first operating mode is: when the triangular carrier wave is less than the modulation wave, a high-level signal is output to turn on the corresponding switching device; when the triangular carrier wave is greater than or equal to the modulation wave, a low-level signal is output to turn off the corresponding switching device; the second operating mode is: when the triangular carrier wave is greater than or equal to the modulation wave, a high-level signal is output to turn on the corresponding switching device; when the triangular carrier wave is less than the modulation wave, a low-level signal is output to turn off the corresponding switching device. Type I and Type III modulated waves use the first operating mode; Type II and Type IV modulated waves use the second operating mode.

10. A vector timing unified construction device for ripple optimization of multiple parallel converters, characterized in that, include: The voltage vector sequence generation unit determines a starting voltage vector based on the reference voltage and the number of parallel units using a preset judgment rule. Based on the starting voltage vector, a voltage vector sequence is generated by progressively changing the number of conducting switches in each phase. The starting voltage vector and all voltage vectors in the voltage vector sequence belong to the set of the top three voltage vectors. The set of the top three voltage vectors refers to the set of the top three voltage vectors in the vector plane after sorting them from smallest to largest according to the voltage vector differential magnitude between them and the reference voltage. The timing basic unit construction unit selects four consecutive voltage vectors based on the voltage vector sequence to form an asymmetric vector timing basic unit; taking the fourth voltage vector in the asymmetric vector timing basic unit as the center of symmetry, the four consecutive voltage vectors are mirrored in reverse order to form a symmetric vector timing basic unit containing seven voltage vectors; wherein, by changing the starting position of the four consecutive voltage vectors, multiple asymmetric vector timing basic units are formed. The duty cycle calculation unit, based on the four voltage vectors contained in the asymmetric vector timing basic unit, establishes a corresponding set of equations according to the volt-second balance principle, sets constraints in the set of equations, solves for the duty cycle of the four voltage vectors, and then determines the duty cycle of each phase online through preset judgment rules. A complete vector timing construction unit is formed by repeatedly arranging the symmetrical vector timing basic unit N times according to the number of parallel units N, thereby constructing a complete vector timing suitable for the number of parallel units N; The switching timing generation unit determines the total number of conducting devices in all parallel branches of each phase at each time according to the complete vector timing, and allocates the number of conducting devices among the parallel branches to generate the switching timing corresponding to each parallel branch. The carrier configuration determination unit determines the carrier configuration of each parallel branch according to the switching timing corresponding to each parallel branch; The modulation wave and operation mode determination unit determines two types of complementary modulation waves and two corresponding complementary operation modes based on the obtained carrier configuration and the obtained phase duty cycles. Under different operation modes, the comparison relationship between the modulation wave and the carrier is reversed. The vector timing generation unit sorts the three-phase reference voltages according to their magnitudes, determines each phase as its maximum, intermediate, or minimum value, and allocates the corresponding modulation wave and carrier configuration accordingly to generate the corresponding vector timing, thereby achieving vector timing uniformity across the entire sector.

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