A motor load adaptive adjustment method based on analog circuit

Abstract

The application provides a motor load adaptive adjustment method based on an analog circuit, and relates to the technical field of motor control, and comprises the following steps: converting a load current in a motor loop into a first voltage signal, and generating a mode selection signal based on the amplitude of the signal and its change rate; wherein when the amplitude of the first voltage signal exceeds a first threshold value and its change rate exceeds a second threshold value, the mode selection signal indicates a dynamic response mode; otherwise, the mode selection signal indicates a steady state adjustment mode; when indicating the steady state adjustment mode, the first voltage signal is introduced into a first path, and the path comprises a first error amplifier with a first proportional coefficient; when indicating the dynamic response mode, the first voltage signal is introduced into a second path, and the path comprises a second error amplifier with a second proportional coefficient greater than the first proportional coefficient; and a motor driving signal is generated and output according to an adjustment signal output by the selected path.

Description

Technical Field

[0001] This application relates to the field of motor control technology, specifically to a motor load adaptive adjustment method based on analog circuits. Background Technology

[0002] In the field of motor control, especially in motor load adaptive regulation systems based on analog circuits, overload protection or constant current control is commonly achieved by detecting the motor current and comparing it with a preset threshold. Traditional methods typically rely solely on whether the current amplitude exceeds a fixed threshold as the judgment criterion. This single criterion has inherent defects: if the threshold is set too high, the system will respond slowly to sudden load increases (such as stalled rotor), which may cause damage to the motor or drive circuit before the protection action is taken; if the threshold is set too low, the system is susceptible to malfunctions due to transient interference or the impact of normal starting current, leading to frequent and unnecessary adjustments, which seriously affects the smoothness and continuity of motor operation.

[0003] To address the response speed issue, some solutions incorporate current change rate detection, but this is typically used as an independent protection channel, connected in parallel with amplitude protection logic. While this approach can respond more quickly to rapid current increases, it cannot distinguish between normal acceleration processes and actual faults: the current change rate is also large during normal motor startup, easily leading to false protection; while during actual overload, if the change rate is not high (such as slow loading to overcurrent), protection may not be triggered.

[0004] Furthermore, in the regulation stage, traditional analog circuits often use error amplifiers with fixed parameters. Fixed-gain designs struggle to balance steady-state accuracy and dynamic response speed: high gain is beneficial for quickly suppressing overcurrent but easily induces steady-state oscillations; low gain ensures smooth operation but results in sluggish dynamic response. Although some solutions attempt to address different operating conditions by switching the gain, their switching logic is often based solely on current amplitude exceeding the threshold, making them susceptible to interference and leading to frequent mode switching, which in turn introduces instability.

[0005] Therefore, there is a lack of an adjustment method in the existing technology that can achieve a balance between steady-state accuracy and dynamic response speed. Summary of the Invention

[0006] In view of the above-mentioned defects or deficiencies in the prior art, this application aims to provide a motor load adaptive adjustment method based on analog circuits to achieve a balance between steady-state accuracy and dynamic response speed of motor control; including the following steps: Convert the load current in the motor circuit into a first voltage signal; The system receives the first voltage signal and generates a mode selection signal based on the amplitude and rate of change of the signal; wherein, when the amplitude of the first voltage signal exceeds a first threshold and its rate of change exceeds a second threshold, the mode selection signal indicates a dynamic response mode; otherwise, the mode selection signal indicates a steady-state regulation mode. According to the mode selection signal, the first voltage signal is introduced into different analog processing paths; wherein, when the indication is steady-state adjustment mode, the first voltage signal is introduced into the first path, which includes a first error amplifier with a first proportional coefficient; when the indication is dynamic response mode, the first voltage signal is introduced into the second path, which includes a second error amplifier with a second proportional coefficient, the second proportional coefficient being greater than the first proportional coefficient. Based on the adjustment signal output from the selected path, generate and output the motor drive signal.

[0007] According to the technical solution provided in this application, receiving the first voltage signal and generating a mode selection signal based on the amplitude and rate of change of the signal includes the following steps: The first voltage signal is compared with a reference voltage corresponding to the first threshold by a first voltage comparator, and a first logic signal is output. The first voltage signal is differentiated by a differentiating circuit to obtain a differential voltage signal corresponding to the rate of change. The differential voltage signal is then compared with a reference voltage corresponding to the second threshold by a second voltage comparator to output a second logic signal. The mode selection signal is generated by performing a logical AND operation on the first logic signal and the second logic signal using an AND gate circuit.

[0008] According to the technical solution provided in this application, the step of guiding the first voltage signal into different analog processing paths according to the mode selection signal includes the following steps: Determine whether a preset hold time has elapsed since the most recent mode selection signal indicated dynamic response mode; If so, the first voltage signal is directed to different analog processing paths according to the mode selection signal. The determination of whether a preset hold time has elapsed since the most recent mode selection signal indicated dynamic response mode is implemented by an analog monostable multivibrator circuit; the analog monostable multivibrator is triggered by the rising edge of the mode selection signal and outputs a high-level or low-level signal with a duration equal to the preset hold time.

[0009] According to the technical solution provided in this application, after determining whether a preset holding time has elapsed since the most recent mode selection signal indicated dynamic response mode, the method further includes the following steps: If not, the signal is received from the first voltage signal and then directly imported into the second path.

[0010] According to the technical solution provided in this application, at the moment when the mode selection signal switches from indicating dynamic response mode back to indicating steady-state adjustment mode, and the preset hold time has elapsed, the following step is further included: Before switching the input path of the first voltage signal from the second path to the first path, a bias voltage is applied to the input terminal of the first error amplifier so that the output voltage of the first error amplifier at the moment of switching matches the level of the adjustment signal output by the second error amplifier at the moment before switching.

[0011] According to the technical solution provided in this application, after converting the load current in the motor circuit into a first voltage signal, the method further includes the following steps: The first voltage signal is subjected to low-pass filtering to extract the slowly varying component that reflects the long-term trend of load change. Based on the slowly varying component, the reference input voltage of the first error amplifier is dynamically generated so that the target adjustment point in the steady-state adjustment mode can be automatically adjusted to follow the long-term variation trend of the load.

[0012] According to the technical solution provided in this application, the step of dynamically generating the reference input voltage of the first error amplifier based on the slowly varying component includes the following steps: The gradually changing component is subjected to amplitude limiting processing so that its voltage value is limited between a preset lower limit voltage and an upper limit voltage to obtain the amplitude-limited gradually changing component; the lower limit voltage corresponds to the minimum reference when the motor is running under no-load, and the upper limit voltage corresponds to the maximum safety reference when the motor is under rated load. The limiting gradually varying component is weighted and summed with the fixed base reference voltage to generate the reference input voltage, wherein the weighting coefficient of the limiting gradually varying component is less than 1.

[0013] According to the technical solution provided in this application, the first threshold and the second threshold are dynamically adjusted based on the real-time voltage of the motor drive power supply; the dynamic adjustment is configured such that both the first threshold and the second threshold are negatively correlated with the real-time voltage.

[0014] According to the technical solution provided in this application, after comparing the differential voltage signal with a reference voltage corresponding to the second threshold through a second voltage comparator and outputting a second logic signal, the method further includes the following steps: The second logic signal is input into an analog integrator circuit, which integrates the voltage of the second logic signal when it is high. The output voltage of the analog integrator circuit is compared with a reference voltage corresponding to a preset integration threshold by a third voltage comparator. When the output voltage of the analog integrator circuit reaches the preset integration threshold, the third voltage comparator outputs a valid confirmation signal to one input of the AND gate circuit. The AND gate circuit generates a mode selection signal indicating the dynamic response mode only when it simultaneously receives a valid first logic signal and a valid acknowledgment signal.

[0015] According to the technical solution provided in this application, the following steps are also included: Acquire and record transient waveform data of the first voltage signal during the dynamic response mode; The transient waveform data is matched with multiple preset load disturbance feature patterns to identify the current load disturbance type; the preset load disturbance feature patterns include pulse disturbance, ramp disturbance, and periodic oscillation disturbance. Based on the current load disturbance type, adjust the proportional gain of the second error amplifier and / or adjust the compensation network parameters of the dynamic response control loop in the second path to achieve optimal dynamic adjustment characteristics that match the current load disturbance type.

[0016] Compared with the prior art, the beneficial effects of this application are as follows: I. Accurate identification and intelligent response to load status: By simultaneously monitoring the amplitude and rate of change of the load current, and only determining the dynamic response mode that requires emergency handling when both exceed the corresponding thresholds, it effectively distinguishes between real dangerous load changes (such as stall) and transient disturbances or normal transient processes, greatly reducing the probability of misjudgment and improving system reliability.

[0017] Second, it fundamentally solves the contradiction between steady-state accuracy and dynamic response speed: by setting up dual adjustment paths with different proportional coefficients (low gain in steady-state path and high gain in dynamic path) and intelligently switching according to the mode selection result, the system can maintain high accuracy and low jitter during stable operation, and can quickly switch to high gain mode to strongly suppress inrush current during sudden overload, thus achieving the optimal balance between stability and dynamic performance.

[0018] Third, it improves the overall adaptability and robustness of the system: This method is implemented using analog circuits, retaining the advantages of analog systems such as high real-time performance and strong anti-interference capability. The dual-criteria decision-making mechanism enhances the adaptability to complex load conditions and electrical noise, ensuring stable and reliable operation of the system under various conditions.

[0019] IV. Simple structure, low cost, and easy implementation: Based on conventional analog circuit modules (sampling, differentiation, comparator, error amplifier, etc.), it does not require digital processors or complex algorithms, which reduces costs and development difficulty, and facilitates its application in cost-sensitive or environmentally demanding motor drive products. Attached Figure Description

[0020] Figure 1 A flowchart illustrating the steps of the motor load adaptive adjustment method based on analog circuits provided in this application; Figure 2 A schematic diagram of the structure of the analog circuit control system provided in this application.

[0021] The text labels in the image represent: 1. Current sampling module; 2. Pattern recognition module; 3. First error amplifier; 4. Second error amplifier; 5. Motor; 6. Drive output module. Detailed Implementation

[0022] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0023] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0024] Example 1 As mentioned in the background section, to address the problems in the prior art, this application proposes a motor load adaptive adjustment method based on analog circuits to achieve a balance between steady-state accuracy and dynamic response speed in motor control; such as Figure 1 As shown, it includes the following steps: S1. Convert the load current in the motor circuit into a first voltage signal; S2. Receive the first voltage signal and generate a mode selection signal based on the amplitude and rate of change of the signal; wherein, when the amplitude of the first voltage signal exceeds a first threshold and its rate of change exceeds a second threshold, the mode selection signal indicates a dynamic response mode; otherwise, the mode selection signal indicates a steady-state adjustment mode. S3. According to the mode selection signal, the first voltage signal is introduced into different analog processing paths; wherein, when the indication is steady-state adjustment mode, the first voltage signal is introduced into the first path, which includes a first error amplifier 3 with a first proportional coefficient; when the indication is dynamic response mode, the first voltage signal is introduced into the second path, which includes a second error amplifier 4 with a second proportional coefficient, the second proportional coefficient being greater than the first proportional coefficient. S4. Generate and output motor drive signals based on the adjustment signals output by the selected path.

[0025] Specifically, this method uses a method such as Figure 2 The analog circuit control system shown includes a current sampling module 1, a pattern recognition module 2, a dual-path adjustment module, and a drive output module 6. Current sampling module 1 converts the load current in the motor circuit into a first voltage signal; The pattern recognition module 2 receives the first voltage signal and generates a pattern selection signal based on the amplitude and rate of change of the signal. The dual-path adjustment module selects the mode and directs the first voltage signal to different analog processing paths. The drive output module 6 generates a motor drive signal based on the adjustment signal output from the selected path, so as to adaptively adjust the motor load.

[0026] Specifically, the load current in the motor circuit is converted into a first voltage signal. This is achieved by connecting a precision sampling resistor (e.g., 5 milliohms) in series in the motor drive circuit. When the load current flows through this resistor, a weak voltage drop signal is generated according to Ohm's law (U=IR). This signal is then fed into an instrumentation amplifier circuit (or differential amplifier circuit) composed of a precision operational amplifier. This amplifier circuit has a high common-mode rejection ratio and adjustable gain (e.g., 50 times), amplifying the weak current signal and converting it into a first voltage signal suitable for subsequent circuit processing (e.g., 0-5V range, corresponding to 0-100A current). This signal is the basis for all subsequent judgments and controls.

[0027] The process involves receiving a first voltage signal and generating a mode selection signal based on its amplitude and rate of change. This requires two parallel monitoring steps: monitoring the absolute level (amplitude) of the signal and monitoring the rate of change (rate of change). Specifically, a voltage comparator compares the first voltage signal with a preset first threshold voltage (e.g., 3V, corresponding to a 60A current). Simultaneously, a differentiating circuit composed of capacitors and resistors performs real-time differentiation on the first voltage signal to obtain a differential voltage signal reflecting the rate of current change. This differential signal is then compared with a preset second threshold voltage (e.g., corresponding to a current change rate > 50A / second) by another voltage comparator. Finally, an analog-to-digital logic circuit (e.g., an AND gate chip) generates a high-level mode selection signal only when both comparator outputs are logic high (indicating simultaneous amplitude and rate of change exceeding limits), indicating that the system should enter dynamic response mode; otherwise, the signal is low, indicating steady-state regulation mode. This dual-condition criterion effectively distinguishes between real, dangerous load surges and ordinary disturbances or normal transient processes.

[0028] Based on the mode selection signal, the first voltage signal is fed into different analog processing paths. Specifically, this is implemented by constructing two parallel analog signal conditioning and amplification channels. The inputs of these two channels are selected by an analog switch (such as a CMOS analog switch chip) controlled by the mode selection signal. When the switch is switched to the first path, the signal enters the first error amplifier 3. This amplifier is typically composed of an operational amplifier, and its feedback resistor network is configured with a low closed-loop gain (i.e., the first proportional gain, for example, Kp1=5), giving it mild regulation characteristics, suitable for fine, overshoot-free regulation in steady state. When the switch is switched to the second path, the signal enters the second error amplifier 4. The feedback network of this amplifier is configured with a significantly higher closed-loop gain (i.e., the second proportional gain, for example, Kp2=50), giving it strong regulation capabilities, enabling a fast and large-amplitude response to error signals.

[0029] Based on the adjustment signal output from the selected path, a motor drive signal is generated and output. Specifically, the output voltage of the selected error amplifier is used as the adjustment signal and sent to the subsequent motor drive power stage. This power stage can be a linear power amplifier circuit that directly amplifies the adjustment signal to drive motor 1; more commonly, the adjustment signal is sent to a voltage-controlled oscillator or PWM modulator to generate a PWM wave with a corresponding duty cycle, which is then used to drive motor 1 through a power MOSFET bridge, thereby achieving continuous and smooth adjustment of the voltage or current of motor 1.

[0030] Technical Principles and Effects: The technical principle lies in simulating a rudimentary intelligent reflex arc: by jointly judging two parameters (amplitude and rate of change), it identifies the nature of the load state (whether it is a steady change or a critical sudden change), and selects the most suitable control strategy (low-gain fine control or high-gain strong suppression) accordingly. The technical effect it achieves is to resolve the inherent contradictions of traditional single-parameter or fixed-gain analog controllers: while ensuring smooth and accurate steady-state operation, it can achieve rapid and powerful intervention in sudden overloads or stalls at the millisecond level, thereby significantly improving the overall dynamic performance, reliability, and adaptability of the motor drive system, all achieved through low-cost, fast-responding pure analog circuitry.

[0031] In a preferred embodiment, receiving the first voltage signal and generating a mode selection signal based on the amplitude and rate of change of the signal includes the following steps: The first voltage signal is compared with a reference voltage corresponding to the first threshold by a first voltage comparator, and a first logic signal is output. Specifically, the first voltage comparator can be a general-purpose voltage comparator chip such as the LM393. Its non-inverting input is connected to the aforementioned first voltage signal, and its inverting input is connected to a stable and adjustable first threshold reference voltage (e.g., 3.0V) generated by a precision voltage regulator (e.g., TL431) and a resistor divider network. When the current of motor 1 increases, causing the first voltage signal to exceed 3.0V, the comparator output flips from a low level (e.g., 0V) to a high level (e.g., 5V), which is the first logic signal (a high level indicates that the amplitude exceeds the limit).

[0032] The first voltage signal is differentiated by a differentiating circuit to obtain a differential voltage signal corresponding to the rate of change. The differential voltage signal is then compared with a reference voltage corresponding to the second threshold by a second voltage comparator to output a second logic signal. Specifically, the differentiating circuit is a typical first-order RC high-pass filter circuit. Its time constant (τ=R×C) needs to be reasonably selected according to the electrical time constant of the motor system to ensure that the output differential voltage signal can truly reflect the rate of change of current, while not excessively amplifying high-frequency noise. For example, choosing R=10kΩ and C=100nF yields τ=1ms. This circuit amplifies the changing component in the first voltage signal and outputs a voltage signal proportional to the rate of change of current. The output signal of the differentiating circuit is sent to a second voltage comparator (such as another channel of the LM393). The inverting input of the comparator is connected to another second threshold reference voltage set by a voltage divider network, which corresponds to the maximum allowable safe rate of change of current. When the differential voltage exceeds this threshold, the comparator outputs a high-level second logic signal (indicating that the rate of change exceeds the limit).

[0033] The mode selection signal is generated by performing a logical AND operation on the first logic signal and the second logic signal using an AND gate circuit.

[0034] Specifically, the mode selection signal is generated by performing a logical AND operation on the first and second logic signals using an AND gate circuit. This AND gate circuit can be a two-input AND gate from a 74 series digital logic chip (such as the 74HC08). The logic signals output from the two comparators are connected to the two inputs of the AND gate. According to the logic rules of the AND gate, the output is high only when both inputs are simultaneously high. Therefore, the mode selection signal output by the AND gate is high only when both the first logic signal (amplitude exceeding the limit) and the second logic signal (rate of change exceeding the limit) are valid, indicating the dynamic response mode.

[0035] Specifically, the pattern recognition module 2 includes an amplitude comparison submodule and a differential comparison submodule connected in parallel. The amplitude comparison submodule compares a first voltage signal with a reference voltage corresponding to a first threshold through a first voltage comparator and outputs a first logic signal. The differential comparison submodule performs differential processing on the first voltage signal through a differential circuit to obtain a differential voltage signal corresponding to the rate of change, and compares the differential voltage signal with a reference voltage corresponding to a second threshold through a second voltage comparator and outputs a second logic signal.

[0036] In a preferred embodiment, the step of guiding the first voltage signal into different analog processing paths according to the mode selection signal includes the following steps: Determine whether a preset hold time has elapsed since the most recent mode selection signal indicated dynamic response mode; If so, the first voltage signal is directed to different analog processing paths according to the mode selection signal. The determination of whether a preset hold time has elapsed since the most recent mode selection signal indicated dynamic response mode is implemented by an analog monostable multivibrator circuit; the analog monostable multivibrator is triggered by the rising edge of the mode selection signal and outputs a high-level or low-level signal with a duration equal to the preset hold time.

[0037] Specifically, the system determines whether a preset hold time has elapsed since the most recent mode selection signal indicated dynamic response mode. This determination is implemented by an analog monostable multivibrator circuit. A monostable multivibrator is an analog or digital logic circuit with transient characteristics, characterized by outputting a fixed-width pulse each time it is triggered. In this implementation, a dedicated monostable multivibrator chip (such as 74HC123) can be used, or it can be built using a general-purpose operational amplifier, comparator, and RC timing components.

[0038] To determine whether a preset hold time has elapsed since the most recent mode selection signal indicated dynamic response mode, an analog monostable multivibrator circuit is used. Specifically, the mode selection signal output from the AND gate is used as the trigger input for the monostable multivibrator. It is specifically limited to triggering on the rising edge of this signal; that is, the monostable multivibrator is triggered only at the instant the mode transitions from steady state to dynamic (the signal's low-to-high edge).

[0039] The analog monostable multivibrator is triggered by the rising edge of the mode selection signal and outputs a high-level or low-level signal with a duration equal to the preset hold time. After being triggered, the output (assuming the Q terminal) immediately transitions to an active state (e.g., high level) and begins a timing process. The length of the timing (i.e., the preset hold time) is determined by the values ​​of the externally connected resistors and capacitors, following the formula T≈kRC (where k is a chip constant). For example, by selecting R=1MΩ and C=10μF, a hold time of approximately 10 seconds can be achieved. During this preset time, regardless of changes in the trigger input signal, the output of the monostable multivibrator will be forced to remain in the active state (high level). Only when the hold time ends will the output return to the inactive state (low level). This output signal serves as the hold state flag for path switching.

[0040] If so, the first voltage signal is directed to different analog processing paths according to the mode selection signal. The logic of this step is that when the output of the monostable multivibrator is in an invalid state (low level, indicating that the hold time has expired), the control of path switching is returned to the real-time mode selection signal. At this time, the system resumes normal judgment and, depending on whether it is a steady-state or dynamic mode, directs the signal to the corresponding first or second path.

[0041] The technical principle of this implementation is the introduction of a time inertia or delayed release mechanism. Its core idea is that once the system enters dynamic response mode due to a real danger, it must be forced to maintain this state for a sufficiently long time to ensure that the impact is fully suppressed, the system state stabilizes, and it avoids exiting the strong protection mode due to a slight signal drop before the fault is completely eliminated. The achieved technical effect is the complete elimination of the repeated mode switching phenomenon caused by small signal fluctuations at load threshold boundaries. This one-touch locking and delayed release logic greatly enhances the robustness and reliability of the system when facing complex and fluctuating loads, making the adaptive adjustment process more decisive and effective.

[0042] In a preferred embodiment, after determining whether a preset hold time has elapsed since the most recent mode selection signal indicated dynamic response mode, the method further includes the following steps: If not, the signal is received from the first voltage signal and then directly imported into the second path.

[0043] Specifically, a path selection priority logic is constructed, dominated by the output signal of a monostable multivibrator (MSF). In the actual circuit, this can be implemented using analog switches (such as the CD4066) or a combination of logic gates and analog switches. The control logic is designed as follows: the output signal of the MSF (hold status flag) has the highest priority. When it is active (high level, indicating the hold time is complete), regardless of the current state of the real-time mode selection signal, the analog switch is forced to connect the first voltage signal to the second path (i.e., the second error amplifier 4 in the dynamic response path). Only when the MSF output is inactive (low level, indicating the hold time has expired) is the path selection control delegated to the real-time mode selection signal, and normal path switching is performed.

[0044] The technical principle of this implementation is to establish an emergency priority principle. It clearly layers the entire control logic: the first priority is the mandatory protection period (hold-off time), during which the primary goal is to suppress the fault as quickly as possible, and a high-gain dynamic response strategy is enforced. The second priority is the normal intelligent judgment period (after the hold-off time), during which the optimal adjustment strategy is selected based on the real-time characteristics of the current load. The technical effect achieved is to ensure the consistency and thoroughness of the control strategy. It ensures that after each identified severe load change event, the system receives a complete, undisturbed, and powerful handling period, thereby preventing protection actions from being interrupted or weakened, ensuring that each adaptive adjustment is completed successfully, fundamentally improving the effectiveness of protection and the overall security of the system.

[0045] In a preferred embodiment, at the moment when the mode selection signal switches from indicating dynamic response mode back to indicating steady-state adjustment mode, and the preset hold time has elapsed, the following step is further included: Before switching the input path of the first voltage signal from the second path to the first path, a bias voltage is applied to the input terminal of the first error amplifier 3 so that the output voltage of the first error amplifier 3 at the moment of switching matches the level of the adjustment signal output by the second error amplifier 4 at the moment before switching.

[0046] First, it's necessary to define the triggering condition: the moment when the mode selection signal switches from indicating dynamic response mode back to indicating steady-state adjustment mode, and the preset hold time has elapsed. This indicates that the hold time of the monostable multivibrator has ended (the output becomes invalid), and simultaneously, the real-time mode selection signal generated by the AND gate also jumps from high (dynamic mode) back to low (steady-state mode). This moment is the critical point at which the path needs to switch back from the second path to the first path.

[0047] The specific implementation of applying a bias voltage to the input of the first error amplifier 3 requires a precise bias injection circuit. The core of this circuit is a sample-and-hold module and a voltage injection path controlled by an analog switch. Sampling Phase: At the last moment before the system is in dynamic response mode (i.e., before the switching occurs), a voltage follower consisting of a high-input-impedance operational amplifier samples the regulation signal output from the second error amplifier 4 in real time. This signal represents the control amount required to suppress overload under the current load conditions. The sampled voltage value is stored on a high-quality, low-leakage capacitor (e.g., a polypropylene film capacitor). Switching and Injection Phase: When the mode selection signal is detected to switch from indicating dynamic response mode back to indicating steady-state regulation mode (a narrow pulse can be generated by a simple RC differentiator circuit or an edge detector), this pulse controls an analog switch to close briefly. At the instant of closure, the voltage on the storage capacitor (i.e., the output voltage of the second error amplifier 4 just before the switching) is injected into the summing node (typically the inverting input) of the first error amplifier 3 through a buffer amplifier and a precision resistor network. The injected current will generate a corresponding voltage at the output of the first error amplifier 3. Bias voltage matching: By designing the gain of the injection path (i.e., the ratio of the injection resistor to the feedback resistor of the first error amplifier 3), the voltage generated at the output of the first error amplifier 3 is exactly equal to the previously sampled and held voltage value, assuming the input signal of the first error amplifier 3 (which has now switched to the first voltage signal) is zero. Thus, at the instant the switching occurs, although control is transferred from the second amplifier to the first amplifier, the final adjustment signal received by the drive output module 6 is continuous in level without any abrupt changes.

[0048] The goal of this entire process is to match the output voltage of the first error amplifier 3 at the instant of switching with the level of the adjustment signal output by the second error amplifier 4 at the moment before switching. By pre-applying the aforementioned bias voltage, the output of the first error amplifier 3 is preset to the same level as the system control quantity at the initial moment of operation.

[0049] The technical principle of this implementation is state initialization or pre-synchronization. It recognizes that two independent analog amplifier circuits, even with the same input signal, may have different outputs due to factors such as internal offset voltage and subtle differences in the feedback network. Direct switching would cause a jump in control input, resulting in torque disturbance in motor 1. This solution achieves seamless handover of control by actively calibrating the output of the taking-over amplifier (first error amplifier 3) to the state of the predecessor (second error amplifier 4) at the moment of switching. The resulting technical effect is extremely significant: it completely eliminates any secondary voltage or current jumps that may occur during mode switching, making the speed or torque changes of motor 1 extremely smooth. This not only improves the operational quality of high-end applications (such as precision servos and medical equipment) but also reduces the impact of switching stress on power devices and mechanical transmission components, improving the lifespan and reliability of the entire system. This is a model of integrating high-reliability system design concepts into analog circuit control.

[0050] In a preferred embodiment, after converting the load current in the motor circuit into a first voltage signal, the method further includes the following step: The first voltage signal is subjected to low-pass filtering to extract the slowly varying component that reflects the long-term trend of load change. Specifically, low-pass filtering is implemented using a passive or active low-pass filter with an extremely low cutoff frequency. The time constant of this filter (typically in the range of seconds to tens of seconds) must be much larger than the normal fluctuation period of the motor load, but smaller than the duration of a fundamental change in load conditions. For example, for the clamping motor of an injection molding machine, one working cycle might be 10 seconds; therefore, the filter time constant could be set to 20-30 seconds to smooth out fluctuations within a single cycle and extract the load variation trend during the production of different products. A simple RC filter circuit can be used, followed by a voltage follower for buffering; for higher precision requirements, multi-stage filtering or an operational amplifier-based active low-pass filter can be used.

[0051] The slowly varying component is the voltage signal output from the aforementioned low-pass filter. It filters out all high-frequency noise, transient interference, and rapid load fluctuations in the first voltage signal, retaining only its slowly drifting DC and extremely low-frequency components. This signal essentially reflects the trend of the average load level or load base value borne by motor 1 over a relatively long period (several minutes or longer).

[0052] Based on the slowly varying component, the reference input voltage of the first error amplifier 3 is dynamically generated so that the target adjustment point in the steady-state adjustment mode can be automatically adjusted to follow the long-term change trend of the load.

[0053] Specifically, the implementation of dynamically generating the reference input voltage of the first error amplifier 3 based on the slowly varying component requires a dynamic reference generation circuit. The first error amplifier 3 is typically configured to compare a first voltage signal (representing the actual current) with its reference input voltage (representing the target current). Traditionally, this reference voltage is fixed. In this scheme, the fixed reference is replaced with a variable reference modulated by the slowly varying component. In specific circuit implementation, the slowly varying component signal can be passed through an adder circuit composed of operational amplifiers. The other input of the adder is connected to the original fixed reference voltage. The output of the adder, i.e., the weighted sum of the two, is provided to the first error amplifier 3 as the new dynamic reference input voltage. Thus, the target point for steady-state adjustment is no longer fixed, but will appropriately rise as the load's long-term trend increases and appropriately fall as the trend decreases. The purpose of this step is to enable the target adjustment point in the steady-state adjustment mode to automatically adjust in accordance with the long-term trend of load changes. For example, as the amount of goods on the conveyor belt gradually increases, the gradual component will rise slowly, and the dynamic reference will also rise accordingly. The system will actively increase the target value of the steady-state operating current of motor 1 to drive the increased load more easily and avoid being pushed to the overcurrent edge before responding passively.

[0054] The technical principle of this implementation is feedforward target optimization or load tracking. It breaks away from the traditional feedback system paradigm of passive adjustment based solely on current errors. By introducing a signal reflecting historical load trends, it proactively and gradually corrects the adjustment target. The resulting technical effects are multifaceted: First, it optimizes energy efficiency, enabling the operating point of motor 1 to adaptively match load demands, avoiding over-driving under light loads or insufficient reserve under heavy loads. Second, it improves system comfort; because the target point is adjusted gradually, the system does not need frequent large-scale adjustments to cope with slowly changing loads, resulting in smoother and quieter operation. Finally, it provides insights for preventative maintenance; a continuously abnormally increasing gradually varying component can serve as an early warning indicator of equipment wear or failure. This endows a simple analog control system with preliminary intelligence similar to an advanced energy management system.

[0055] In a preferred embodiment, dynamically generating the reference input voltage of the first error amplifier 3 based on the slowly varying component includes the following steps: The gradually changing component is subjected to amplitude limiting processing so that its voltage value is limited between a preset lower limit voltage and an upper limit voltage to obtain the amplitude-limited gradually changing component; the lower limit voltage corresponds to the minimum reference when the motor 1 is running under no-load, and the upper limit voltage corresponds to the maximum safety reference when the motor 1 is under rated load. The limiting gradually varying component is weighted and summed with the fixed base reference voltage to generate the reference input voltage, wherein the weighting coefficient of the limiting gradually varying component is less than 1.

[0056] Specifically, the implementation of limiting the gradually changing component requires a voltage clamping circuit. This can be achieved in several ways: the most direct is to use a pair of back-to-back Zener diodes, connected respectively between the gradually changing component signal line and the positive and negative power supplies (or reference ground). When the signal voltage exceeds the breakdown voltage of the Zener diodes, it is clamped. A more precise solution is to use a precision limiting circuit composed of operational amplifiers or a window comparator combined with analog switches. The core is to set an upper and lower limit voltage for the gradually changing component that must not be exceeded. The lower limit voltage usually corresponds to the voltage converted by the minimum current required for motor 1 to run under no-load conditions; this is the theoretical lower limit for the system to operate stably. The upper limit voltage corresponds to the voltage converted by the rated load or maximum safe continuous current of motor 1; this is the safe upper limit of the equipment design. Any gradually changing component value exceeding this range due to abnormal filtering circuitry or extreme interference will be forcibly pulled back within the boundaries, thus obtaining a safe limited gradually changing component.

[0057] Specifically, the key to the weighted summation of the limited, gradually varying component and the fixed base reference voltage lies in the design of the weighted summation circuit. This is typically accomplished by an adder (either an inverting or non-inverting adder) composed of an operational amplifier. The adder has two input channels: one for the limited, gradually varying component and the other for the fixed base reference voltage. The weighting coefficient is determined by selecting the ratio of the input resistance to the feedback resistance of the two input channels. The weighting coefficient for the limited, gradually varying component is less than 1, meaning that the input resistance to the limited, gradually varying component must be greater than the input resistance to the fixed base reference voltage, or attenuated by an additional voltage divider network before being fed into the adder. For example, the gain of the fixed reference channel is set to 0.7, and the gain of the gradually varying component channel is set to 0.3. In this way, the fixed reference dominates (70%) in the final reference input voltage, while the influence of the gradually varying component is moderate (30%). This design ensures the overall stability of the reference voltage and prevents it from being excessively affected by fluctuations in the gradually varying component. The output of the aforementioned adder circuit is the generated reference input voltage. It is a composite reference signal that includes both a stable base value and a certain proportion of load trend information that has been safety-limited.

[0058] The technical principle of this implementation is gentle adaptation under safety constraints. Through amplitude limiting, it adds an insurmountable physical safety boundary to the open adaptive concept, an essential consideration in engineering practice, preventing the adaptive logic from leading the system into a dangerous area due to unforeseen events (such as sensor failure). By weighted summation and ensuring the trend component weight is less than 1, it cleverly balances adaptability and stability. Excessive trend weight may cause the system baseline to oscillate excessively with load fluctuations, even triggering positive feedback oscillations; while appropriate weights allow the system to gently track load trends while maintaining a strong anchorage around a fixed baseline, avoiding baseline drift and loss of control. The achieved technical effect is to endow the system with self-optimization capabilities during long-term operation, while absolutely guaranteeing its behavioral safety boundary under any abnormal conditions, making this advanced function reliably applicable to industrial fields with stringent reliability requirements.

[0059] In a preferred embodiment, the first threshold and the second threshold are dynamically adjusted based on the real-time voltage of the motor drive power supply; the dynamic adjustment is configured such that both the first threshold and the second threshold are negatively correlated with the real-time voltage.

[0060] Specifically, power supply voltage monitoring involves connecting the positive terminal (Vbus) of the motor drive power supply directly to ground via a high-resistance resistor divider network. The voltage division ratio is carefully calculated so that, within the normal operating range of the power supply voltage (e.g., 12V to 48V), the voltage at the midpoint of the divider network (i.e., the monitoring point) is at a level easily handled by subsequent circuitry (e.g., below 3.3V). This monitoring point voltage is a linearly scaled-down signal of the real-time voltage. A voltage follower buffers this signal to prevent subsequent circuitry from overloading it.

[0061] Dynamic Threshold Generation: The configuration is dynamically adjusted so that both the first and second thresholds are negatively correlated with the real-time voltage. This requires implementing an inverting or attenuating function in the circuit. A typical circuit for achieving negative correlation is an inverting proportional amplifier constructed using operational amplifiers. The buffered monitoring point voltage is fed into the input of the inverting amplifier. By setting the ratio of the amplifier's feedback resistor to its input resistor (i.e., the gain, set to a negative value, such as -0.2), its output voltage will be inversely proportional to the input voltage. This output voltage can then serve as the dynamic first threshold. When the power supply voltage increases, this threshold voltage decreases; when the power supply voltage decreases, this threshold voltage increases. Another way to achieve negative correlation is to use in-phase attenuation combined with reference subtraction. First, the monitoring point voltage is attenuated by less than 1 in-phase (e.g., gain +0.5), and then this attenuated voltage is subtracted from a fixed, high-precision reference voltage. The output of the subtractor also meets the requirement of being negatively correlated with the power supply voltage. For the second threshold (rate of change threshold), the exact same circuit structure can be used to generate another voltage negatively correlated with the power supply voltage, and its proportional coefficient can be independently set according to different requirements for sensitivity to the rate of change of current. In the step of receiving the first voltage signal and generating a mode selection signal based on the amplitude and rate of change of the signal, the thresholds for comparing the amplitude and the rate of change are dynamic thresholds output by the first threshold generation circuit and the second threshold generation circuit at the current moment, respectively. This means that in the comparator circuit described above, the pin that was originally connected to a fixed reference voltage should now be connected to the real-time changing voltage output by the aforementioned dynamic threshold generation circuit. The first voltage comparator and the second voltage comparator will use these two dynamic thresholds as comparison references, respectively.

[0062] In a preferred embodiment, after comparing the differential voltage signal with a reference voltage corresponding to the second threshold using a second voltage comparator and outputting a second logic signal, the method further includes the following steps: The second logic signal is input into an analog integrator circuit, which integrates the voltage of the second logic signal when it is high. The output voltage of the analog integrator circuit is compared with a reference voltage corresponding to a preset integration threshold by a third voltage comparator. When the output voltage of the analog integrator circuit reaches the preset integration threshold, the third voltage comparator outputs a valid confirmation signal to one input of the AND gate circuit. The AND gate circuit generates a mode selection signal indicating the dynamic response mode only when it simultaneously receives a valid first logic signal and a valid acknowledgment signal.

[0063] Specifically, the second logic signal is input into an analog integrator circuit, which is implemented as a basic integrator circuit composed of an operational amplifier. The core of this circuit is a capacitor C_int located in the operational amplifier feedback loop, and an input resistor R_int connected between the inverting input and the second logic signal source. When the second logic signal output by the second comparator is high (e.g., 5V), this high voltage charges C_int with a constant current through R_int. The output voltage of the integrator (measured from the op-amp output) will decrease linearly with time (for an inverting integrator) or increase linearly (for a non-inverting integrator configuration). The slope of the output voltage change is inversely proportional to the product of R_int and C_int (i.e., the integration time constant τ_int). For example, setting R_int = 100kΩ and C_int = 1μF, then τ_int = 0.1 seconds, meaning that for every 0.1 seconds of continuous high-level input, the integrator output will change by a fixed voltage amplitude. The function of this integrator circuit is to convert the duration of the second logic signal being high into a continuously accumulating voltage value.

[0064] The second step involves comparing the output voltage of the analog integrator circuit with a reference voltage corresponding to a preset integration threshold using a third voltage comparator. This requires a new comparator circuit. The integrator's output voltage is connected to one input of the third voltage comparator (such as another LM393), while the other input of the comparator is connected to a preset integration threshold reference voltage V_th_int. This threshold voltage V_th_int determines the required duration of the second logic signal high level to trigger an acknowledgment. For example, if V_th_int is set to require a continuous high-level integration of 5 milliseconds, then a transient high-level pulse with a duration of less than 5 milliseconds will not be able to bring the integrated voltage to the threshold.

[0065] In the third step, when the output voltage of the analog integrator circuit reaches the preset integration threshold, the third voltage comparator outputs a valid confirmation signal, defining the logic for generating the confirmation signal. Once the integration voltage reaches or exceeds V_th_int, the output state of the third comparator flips, generating a valid confirmation signal (e.g., changing from low to high). Simultaneously, a reset mechanism must be designed: when the second logic signal goes low, an analog switch or transistor controlled by this signal needs to quickly release the charge across the integration capacitor C_int (short-circuit discharge), resetting the integrator output voltage to zero, preparing for the next judgment.

[0066] The fourth step is to integrate it into the original logic: A secondary AND gate is added to the complete logic chain that generates the mode selection signal. The two inputs of this secondary AND gate receive the first logic signal from the first voltage comparator and the valid acknowledgment signal from the third voltage comparator, respectively. The secondary AND gate outputs a high-level final mode selection signal, indicating that the system enters dynamic response mode, only when both the first logic signal and the valid acknowledgment signal are simultaneously high. Therefore, the final condition for the system to enter dynamic response mode is precisely defined as: the current amplitude exceeds the limit (first logic signal is high), and the state of exceeding the current rate of change is confirmed to have sufficient persistence and energy accumulation (valid acknowledgment signal is high).

[0067] In a preferred embodiment, the following steps are also included: Acquire and record transient waveform data of the first voltage signal during the dynamic response mode; The transient waveform data is matched with multiple preset load disturbance feature patterns to identify the current load disturbance type; the preset load disturbance feature patterns include pulse disturbance, ramp disturbance, and periodic oscillation disturbance. Based on the current load disturbance type, adjust the proportional coefficient of the second error amplifier 4 and / or adjust the compensation network parameters of the dynamic response control loop in the second path to achieve optimal dynamic adjustment characteristics that match the current load disturbance type.

[0068] Specifically, the first step is to acquire and record the transient waveform data of the first voltage signal during the dynamic response mode. This requires an analog waveform feature extraction circuit. Since it is a purely analog system, it cannot perform digital storage and complex calculations. Therefore, the recording here does not refer to digital recording, but rather to the real-time extraction and temporary storage of several physical quantities that reflect the key characteristics of the waveform within hundreds of milliseconds of the disturbance occurring. This can be achieved through a set of parallel analog processing channels with different dynamic characteristics: Peak detection channel: A peak hold circuit consisting of a high-speed operational amplifier, diodes and holding capacitors is used to capture and hold the maximum value of the first voltage signal (representing current) during dynamic mode in real time.

[0069] Rise time detection channel: Using a differentiating circuit combined with threshold comparison, it detects the time required for the current to rise from the initial value to the peak value (or a certain proportion).

[0070] Energy / Area Detection Channel: An integrator integrates the current signal (i.e., the difference between the first voltage signal and the steady-state reference) that exceeds the steady-state threshold during dynamic mode, and its output voltage value is proportional to the area or energy of the disturbance pulse.

[0071] Oscillation detection channel: A bandpass filter with its center frequency set near the possible resonant frequency of the motor system is used in conjunction with an envelope detector circuit to detect whether there are continuous oscillation components of a specific frequency during the response process.

[0072] The second step involves matching the characteristics of the transient waveform data with multiple preset load disturbance characteristic patterns. The key to this is an analog feature matching and decision circuit. This circuit sends the output voltage of each of the aforementioned characteristic channels to multiple voltage window comparators. Each window comparator has a preset voltage range corresponding to a characteristic threshold value for a typical disturbance pattern.

[0073] Pulse-type disturbance: characterized by a very high peak value, extremely short rise time, moderate energy area, and no significant oscillation. The corresponding window comparator settings are: high peak value, short rise time, moderate integral voltage, and low oscillation envelope voltage.

[0074] Ramp-type disturbance: characterized by medium peak value, long rise time, large energy area, and no oscillation. Corresponding characteristics: medium peak value, long rise time, high integral voltage, and low oscillating envelope voltage.

[0075] Periodic oscillations: Characterized by potentially low peak values, but significant oscillation envelope voltage and sustained energy. Corresponding: Oscillation envelope voltage exceeds a high threshold.

[0076] When the output logic combination of a certain set of window comparators matches a preset mode, it is determined to be the current load disturbance type.

[0077] The third step involves adjusting the proportional gain of the second error amplifier 4 and / or adjusting the compensation network parameters of the dynamic response control loop in the second path, based on the current load disturbance type. This requires a parameter-reconfigurable analog controller. The proportional gain of the second error amplifier 4 can be achieved by switching different resistors in its feedback resistor network, for example, by using a multiplexer analog switch to select different feedback resistors. The compensation network parameters of the dynamic response control loop (typically an RC network connected in series in the amplifier feedback loop to adjust phase and gain frequency characteristics) can also be changed by switching different resistors or capacitors using an analog switch.

[0078] For pulse-type disturbances: the system requires the fastest possible suppression. In this case, the proportional gain of the second error amplifier 4 can be adjusted to the maximum (by selecting the smallest feedback resistor), and the compensation network may be switched to maximize the loop bandwidth and achieve the fastest initial response speed.

[0079] For ramp-type disturbances: the load increases slowly but continuously, requiring strong steady-state suppression but not necessarily extremely fast initial velocity. In this case, a high proportional gain can be maintained, but the compensation network can be adjusted to provide stronger integral action, eliminate steady-state error, and prevent the current from being continuously pushed up.

[0080] For periodic oscillations: This indicates that the system may have been excited into resonance. The primary task at this point is to suppress the oscillations. This might involve appropriately reducing the proportional gain to decrease overshoot, or specifically switching to a compensation network that includes specific notch filtering frequencies or phase lead compensation to disrupt the oscillation conditions and allow the system to stabilize quickly.

[0081] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are only preferred embodiments of this application. It should be noted that due to the limitations of written expression, while there are objectively infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the inventive concept and technical solution to other situations without modification, should all be considered within the scope of protection of this application.

Claims

1. A method for adaptive adjustment of motor load based on analog circuits, characterized in that, Includes the following steps: Convert the load current in the motor circuit into a first voltage signal; The system receives the first voltage signal and generates a mode selection signal based on the amplitude and rate of change of the signal; wherein, when the amplitude of the first voltage signal exceeds a first threshold and its rate of change exceeds a second threshold, the mode selection signal indicates a dynamic response mode; otherwise, the mode selection signal indicates a steady-state regulation mode. According to the mode selection signal, the first voltage signal is introduced into different analog processing paths; wherein, when the indication is steady-state adjustment mode, the first voltage signal is introduced into the first path, which includes a first error amplifier (3) with a first proportional coefficient; when the indication is dynamic response mode, the first voltage signal is introduced into the second path, which includes a second error amplifier (4) with a second proportional coefficient, the second proportional coefficient being greater than the first proportional coefficient; Based on the adjustment signal output from the selected path, generate and output the motor drive signal; During the dynamic response mode, the method further includes the following steps: The transient waveform characteristics of the first voltage signal are extracted through parallel analog processing channels; the analog processing channels include: The peak detection channel, consisting of a high-speed operational amplifier, diodes, and a holding capacitor, forms a peak hold circuit used to capture the maximum value of the first voltage signal during dynamic mode; The rise time detection channel, consisting of a differentiating circuit and a threshold comparison circuit, is used to detect the time required for the current to rise from its initial value to its peak value. The energy detection channel integrates the current signal that exceeds the steady-state threshold during dynamic mode using an integrator. The oscillation detection channel consists of a bandpass filter with a center frequency set near the resonant frequency of the motor system and an envelope detection circuit. The transient waveform characteristics are fed into multiple voltage window comparators for analog feature matching to identify the current load disturbance type. The current load disturbance type is one of pulse disturbance, ramp disturbance, and periodic oscillation disturbance. Pulse disturbance corresponds to high peak value, short rise time, medium integral voltage, and low oscillation envelope voltage; ramp disturbance corresponds to medium peak value, long rise time, high integral voltage, and low oscillation envelope voltage; periodic oscillation disturbance corresponds to oscillation envelope voltage exceeding a high threshold. Based on the current load disturbance type, adjust the scaling factor of the second error amplifier (4) and / or adjust the compensation network parameters of the dynamic response control loop in the second path.

2. The motor load adaptive adjustment method based on analog circuits according to claim 1, characterized in that: The step of receiving the first voltage signal and generating a mode selection signal based on the amplitude and rate of change of the signal includes the following steps: The first voltage signal is compared with a reference voltage corresponding to the first threshold by a first voltage comparator, and a first logic signal is output. The first voltage signal is differentiated by a differentiating circuit to obtain a differential voltage signal corresponding to the rate of change. The differential voltage signal is then compared with a reference voltage corresponding to the second threshold by a second voltage comparator to output a second logic signal. The mode selection signal is generated by performing a logical AND operation on the first logic signal and the second logic signal using an AND gate circuit.

3. The motor load adaptive adjustment method based on analog circuits according to claim 1, characterized in that: The step of selecting the first voltage signal according to the mode selection signal and guiding it into different analog processing paths includes the following steps: Determine whether a preset hold time has elapsed since the most recent mode selection signal indicated dynamic response mode; If so, the first voltage signal is directed to different analog processing paths according to the mode selection signal. The determination of whether a preset hold time has elapsed since the most recent mode selection signal indicated dynamic response mode is implemented by an analog monostable multivibrator circuit; the analog monostable multivibrator is triggered by the rising edge of the mode selection signal and outputs a high-level or low-level signal with a duration equal to the preset hold time.

4. The motor load adaptive adjustment method based on analog circuits according to claim 3, characterized in that: After determining whether a preset hold time has elapsed since the most recent mode selection signal indicated dynamic response mode, the method further includes the following steps: If not, the signal is received from the first voltage signal and then directly imported into the second path.

5. The motor load adaptive adjustment method based on analog circuits according to claim 3, characterized in that: At the moment when the mode selection signal switches from indicating dynamic response mode back to indicating steady-state adjustment mode, and the preset hold time has elapsed, the following steps are further included: Before switching the input path of the first voltage signal from the second path to the first path, a bias voltage is applied to the input terminal of the first error amplifier (3) so that the output voltage of the first error amplifier (3) at the moment of switching matches the level of the adjustment signal output by the second error amplifier (4) a moment before switching.

6. The motor load adaptive adjustment method based on analog circuits according to claim 1, characterized in that: After converting the load current in the motor circuit into a first voltage signal, the following steps are also included: The first voltage signal is subjected to low-pass filtering to extract the slowly varying component that reflects the long-term trend of load change. Based on the slowly varying component, the reference input voltage of the first error amplifier (3) is dynamically generated so that the target adjustment point in the steady-state adjustment mode can be automatically adjusted to follow the long-term change trend of the load.

7. The motor load adaptive adjustment method based on analog circuits according to claim 6, characterized in that: The process of dynamically generating the reference input voltage of the first error amplifier (3) based on the slowly varying component includes the following steps: The gradually changing component is subjected to amplitude limiting processing so that its voltage value is limited between a preset lower limit voltage and an upper limit voltage to obtain the amplitude-limited gradually changing component; the lower limit voltage corresponds to the minimum reference when the motor is running under no-load, and the upper limit voltage corresponds to the maximum safety reference when the motor is under rated load. The limiting gradually varying component is weighted and summed with the fixed base reference voltage to generate the reference input voltage, wherein the weighting coefficient of the limiting gradually varying component is less than 1.

8. The motor load adaptive adjustment method based on analog circuits according to claim 1, characterized in that: The first threshold and the second threshold are dynamically adjusted based on the real-time voltage of the motor drive power supply; the dynamic adjustment is configured such that both the first threshold and the second threshold are negatively correlated with the real-time voltage.

9. The motor load adaptive adjustment method based on analog circuits according to claim 2, characterized in that: After comparing the differential voltage signal with a reference voltage corresponding to the second threshold using a second voltage comparator and outputting a second logic signal, the method further includes the following steps: The second logic signal is input into an analog integrator circuit, which integrates the voltage of the second logic signal when it is high. The output voltage of the analog integrator circuit is compared with a reference voltage corresponding to a preset integration threshold by a third voltage comparator. When the output voltage of the analog integrator circuit reaches the preset integration threshold, the third voltage comparator outputs a valid confirmation signal to one input of the AND gate circuit. The AND gate circuit generates a mode selection signal indicating the dynamic response mode only when it simultaneously receives a valid first logic signal and a valid acknowledgment signal.

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