A method and system for N-state M-dimensional progressive ordering encoding based on dual-constraint mapping

Abstract

This invention discloses an N-state M-dimensional progressive ordinal encoding method and system based on dual-constraint mapping, belonging to the field of high-performance computing and high-dimensional information processing. The method outputs a fixed-length steady-state core encoding through six mapping loops: state, dual constraints, progressive reduction, ordinal construction, array evolution, and dimensional convergence. The dual-constraint mapping supports two-point determination of the ordinal direction through state space closure and phase consistency constraints (including a special case of rotational calibration markers). The system includes corresponding functional modules, supports in-memory computing mode switching under N and M configurations, and achieves zero-redundancy error correction using the logical self-consistency of dual-constraint mapping. This invention specifically achieves holographic bidirectional mapping for protein structure prediction and sequence reverse design through left-right rotational hedging evolution. This invention solves the defects of computation-memory separation and large error correction overhead, significantly improving computational adaptability and making it suitable for multi-dimensional data scenarios such as AI decision-making and biomolecular simulation.

Description

Technical Field

[0001] This invention belongs to the fields of high-performance computing, data encoding and high-dimensional information processing technology. Specifically, it relates to an N-state M-dimensional progressive ordinal encoding method and system based on dual-constraint mapping, and further relates to degenerate encoding based on ordinal calculation and self-consistency verification and correction of communication / transmission payload. Background Technology

[0002] In high-dimensional data processing scenarios, separating the encoding and computation processes introduces additional conversion overhead; using a single quantization method for different data distributions reduces representation efficiency; furthermore, the lack of constraints on state cardinality and ordinal hierarchy configuration increases implementation complexity. To improve feasibility and scalability, a structured representation that can be directly used for array operations during the encoding phase is needed, maintaining the closure of the state set and the consistency of the ordinal mapping through constraint mapping. Simultaneously, state flips or readout perturbations may occur during storage / transmission / array operations. Traditional error correction techniques typically rely on additional parity bits or redundant encoding, increasing bandwidth and storage burden; therefore, a correction mechanism compatible with mapping closure is required. Furthermore, to adapt to communication and transmission, a payload organization method that uses both the state space and ordinal addresses as encoded words and can perform decomposition and correction is needed.

[0003] In existing technologies, the conversion overhead caused by the separation of encoding and computation reduces the efficiency of high-dimensional data processing. A single quantization method is difficult to adapt to data with different distributions and is prone to redundancy in state representation. Traditional error correction techniques rely on additional check bits, which increases storage bandwidth and transmission burden, making them difficult to adapt to narrow bandwidth and low-overhead application scenarios. At the same time, the determination of the order position usually relies on three or more points of positioning, which has high operational complexity and lacks a simplified implementation path under specific conditions. In addition, if the rotation characteristic does not form a closed loop with the double constraint mapping and order position calculation, it is difficult to play a role in the selection of correction path. The above defects together make existing technologies insufficient in terms of feasibility, adaptability and efficiency, and difficult to meet the needs of high-performance computing, communication transmission, machine learning and industrial control scenarios. Purpose of the invention

[0004] This invention aims to address the problems in existing technologies, such as the conversion overhead caused by the separation of encoding and computation, the representation redundancy caused by using a single quantization method for different data distributions, the storage / bandwidth burden caused by the reliance on additional parity bits in traditional error correction techniques, and the high operational complexity caused by the reliance on three or more points for determining the order position. It provides a technical solution with a closed loop of "double-constraint mapping—progressive reduction mapping—order position construction mapping—array evolution mapping—dimensional convergence mapping," used to output a steady-state core code with a preset bit width. This achieves a closed-loop process of encoding—computation—correction—adaptation—control, improving feasibility, adaptability, and efficiency while reducing implementation overhead. Furthermore, it provides a redundancy correction mechanism based on the self-consistency of double-constraint mapping, enabling error detection and correction without relying on additional parity bits. It also provides an implementation method that uses state-space coded words or preset bit-width degenerate codes as communication / transmission payloads and can perform verification and correction. Rotation control correction is an optional implementation special case used to optimize the correction path selection and two-point orientation when carrying rotation calibration markers, without changing the core concept of this invention. Terminology Definitions and Symbol Explanations

[0005] The basic state set is a set of discrete state symbols, which must contain at least the binary state {0,1}; it can also be a multi-state or extended state set.

[0006] State space closure constraint mapping: a constraint mapping used to limit the mapping result to members of a preset state set; if the mapping result exceeds the preset state set, the closure of the mapping result can be ensured by rolling back to the previous valid state, truncating invalid symbols, remapping to the nearest neighbor state in the set, or setting it to the preset default state (the above methods are all equivalent implementation methods).

[0007] Sequence Consistency Constraint Mapping: This is used to ensure a consistent sequence mapping relationship between hierarchical sequence addresses and state symbols. The consistent sequence mapping relationship can be achieved through a preset sequence mapping table, hierarchical sequence address monotonicity rules, or symbol-address correspondence table. The specific implementation method is not unique.

[0008] Aperiodic scaling factor: preferably an irrational number (e.g., the golden ratio Φ≈0.618034, √2≈1.414213, etc.), whose discrete approximation can be obtained by fraction p / q (p and q are positive integers) or rounding operation k=round(S·α) (S is a preset scaling factor, α is the aperiodic scaling factor), and the specific value does not constitute a limitation of the present invention.

[0009] Hierarchical bit address: An address vector or encoded bit string used to locate the hierarchical position of a composite state in an M-dimensional bit space.

[0010] Sequence Scale Bit Group: A set of identifier bits (including event flag bits) used to characterize hierarchical sequence address and array operation events.

[0011] Steady-state core encoding: a pre-defined bit-width encoded bit string output by the dimension convergence mapping.

[0012] Preset bit width: The fixed output bit width configured by the control module can be dynamically set according to the application scenario or the statistical characteristics of the input data. The specific bit width value does not constitute a limitation of the present invention.

[0013] Constraint deviation identifier Δ: The deviation value or deviation vector output by the self-consistency check mapping.

[0014] State-space coded word: A coded structure consisting of a state symbol sequence S and its hierarchical address A, represented as W=(S,A).

[0015] Degenerate code: A pre-defined bit-width encoded bit string output by performing a bit reduction mapping on a state-space codeword.

[0016] Rotation calibration identifier: A calibration identifier generated by rotation control correction and associated with the candidate state sequence, used to provide discrimination information on sequence direction, correction path or reduction priority.

[0017] Ordered position pairs: When two position points carry a rotational calibration mark, the two points form an ordered pair (point 1 → point 2), which enables the two points to determine the positional direction; when they do not carry a rotational calibration mark, the two points only form an undirected pair, and the positional direction is determined by the orientation metric mapping of at least three points.

[0018] Objective function: A weighted function consisting of driving components, coupling components, constraint components, and span components. The weighting coefficients can be configured by the control module according to the actual application scenario. The specific weight allocation does not constitute a limitation of the present invention.

[0019] Chiral hedging: In this invention, it refers to using the alternation or combination of the first rotation opcode and the second rotation opcode to make the phase deviation of the candidate path cancel each other out or enhance each other, thereby quickly determining the corrected path or target path that satisfies the double constraint mapping without the need for a complete traversal; the chiral hedging is an optional implementation of rotation control correction.

[0020] Reverse mapping / path inversion: refers to the process of inverting the original state sequence or initial parameters based on the steady-state core encoding or target sequence state and utilizing the logical invertibility of double-constraint mapping. Key operation definition (mapping chain exposed)

[0021] Input: Data D, state cardinality N, ordinal level M, reduction level L Output: Steady-state core encoding C 1) B = f_map(D) / / State mapping 2) B' = f_dual(B) / / Closure constraint mapping + ordinal consistency constraint mapping 3) S = f_reduce(B', L) / / Progressive reduction mapping 4) A = f_rank(S, M) / / Ordinal construction mapping (hierarchical ordinal address / scale bit) 5) E = f_array(S, A, N) / / Array evolution mapping (event flags / scale bit groups) 6) C = f_collapse(A, E) / / Dimensional convergence mapping (Boolean reduction / lookup table reduction) Redundancy correction (self-consistency check mapping, correction mapping and rotation special case)

[0022] (1) Self-consistency verification mapping: Perform self-consistency verification mapping f_check on the candidate state sequence obtained by steady-state core encoding or its reverse mapping to generate constraint deviation identifier Δ; Δ includes at least closure deviation and sequence deviation. Threshold conditions are configured by the control module, for example, triggered by Δ≥1 or triggered by deviation type.

[0023] (2) Correction mapping: When the triggering condition is met, the correction mapping f_correct is executed to output the correction result that satisfies the closure constraint mapping and the order consistency constraint mapping. The correction mapping can be a combination of dual flip, neighborhood substitution or iterative reduction, and does not introduce additional check bits.

[0024] (3) Rotation control correction (optional special case): In an optional embodiment, two complementary opcodes, a first rotation opcode and a second rotation opcode, are predefined, corresponding to two opposite state migration directions. A rotation sequence combination is generated based on the duality attribute or Δ of the input data, and the rotation sequence combination is mapped to a correction path; the rotation sequence combination simultaneously generates a rotation calibration identifier. When a rotation calibration identifier is carried between two ordinal points, the two points form an ordered ordinal pair, thus allowing the ordinal direction to be determined by the two points; when no rotation calibration identifier is carried, the ordinal direction is determined by the orientation metric mapping of at least three ordinal points. Order geometric calculation and relation field mapping

[0025] (1) Geometric relationship: The hierarchical address is represented as an integer vector (a1, a2, ..., a...). M ), calculate the Euclidean distance d between two ordinal address vectors a and b. e Or Manhattan distance d m The distance calculation results are then mapped to similarity determination results or used as input for array operation selection mapping.

[0026] (2) Relationship field construction: In the default embodiment, at least three ordinal points or data points are selected to determine the orientation metric mapping; the orientation metric mapping generates a quantitative description of the internal hierarchical relationship field, including driving components, coupling components, constraint components, and span components. In the embodiment with rotation calibration identifier, at least two ordinal points are selected to form an ordered ordinal pair, and the ordinal direction is determined based on the ordered ordinal pair to generate the orientation metric mapping.

[0027] (3) Disturbance-Response Mapping, Path Inversion, and Parameter Generation: The external input change is mapped to a disturbance vector, and the disturbance vector is mapped to a set of candidate ordinal paths and an ordinal response sequence based on the relation field; given the target ordinal state or the target steady-state core encoding, the path inversion mapping is performed to output the target path; the target path is mapped to an atomic state unit operation sequence or a set of control parameters, so that it minimizes the disturbance metric and maximizes the objective function (a weighted function composed of four types of components) under the condition of satisfying the constraint components. The above mapping supports forward design mapping or reverse inversion mapping. Degenerate recoding (K→N)

[0028] In the process of mapping K initial logic states or their combinations to the basic state flow, degeneracy mapping can be performed: perform binary complementary dual reduction on the initial logic states to generate core logic frames; then calculate the degeneracy remainder of the core logic frames (e.g., bitwise XOR and modulo N), and map the degeneracy remainder to the basic state values ​​through a mapping table or lookup table logic, thereby obtaining the basic state flow consistent with the N states. Data simplification based on ordinal calculation and communication / transmission payload

[0029] (1) State space code word construction: Map the input data to a state symbol sequence S and calculate its hierarchical address A; construct the code word W=(S,A).

[0030] (2) Sequence reduction mapping output degenerate code: Perform sequence reduction mapping g_reduce(W) on the encoded word W to output a preset bit-width degenerate code G; the g_reduce can be implemented by a Boolean reduction function, a lookup table reduction function or a segmented reduction function.

[0031] (3) Load verification and correction: The receiver performs self-consistency verification mapping on the load W or G to obtain Δ, and performs correction mapping when the trigger condition is met, and outputs the corrected W^ or G^; In an optional embodiment, the acceptable load set is defined by the closed constraint mapping and the sequence consistency constraint mapping, and the loads that deviate from the set are corrected by the nearest neighbor mapping or the preset substitution mapping; The transmitter can perform perturbation mapping on the discrete approximate parameters of the non-periodic scaling factor to generate different sequence calibration identifiers, so that the loads present parameterized differences. Executable pseudocode example (fully disclosed)

[0032] # Example: Self-consistency check mapping and spin control correction (illustrated logic) Function f_check(S_star,closed_set, rank_rule): Δ = 0 For each element s in S_star: If s does not belong to closed_set: Δ = Δ + 1 If rank_rule is monotonic: For i from 1 to len(S_star)-1: If S_star[i] < S_star[i-1]: Δ = Δ + 1 Return Δ Function f_spin_correct(S_star, Δ, opL, opR): #opL / opR: Two complementary opcodes (spin special case) If Δ is not triggered: Return S_star Generate spin sequence combo = select_combo(Δ) # Lookup table / threshold mapping executes opcode opL / opR on the candidate positions of S_star according to the combo mapping Output S_hat and spin_tag (spin calibration flag) Return (S_hat, spin_tag) Additional Example (Two-Point Orientation Special Case)

[0033] In an optional embodiment, sequence points P1 and P2 are selected. If the spin_tag of the correction mapping output is bound to (P1, P2), then (P1, P2) constitutes an ordered sequence pair P1→P2, and the sequence direction is determined accordingly for generating the orientation metric mapping and correction path direction selection. If the spin_tag is not bound, then at least three sequence points are used to determine the orientation metric mapping. Attached Figure Description

[0034] Figure 1 : Schematic diagram of the method mapping chain (S1–S6); Figure 2 System module structure diagram; Figure 3 : Schematic diagram of sequence calibration identifier generation; Figure 4 : Schematic diagram of mode switching and bypass isolation; Figure 5 : Schematic diagram of redundancy correction mapping chain; Figure 6 : Schematic diagram of state-space coded words and communication / transmission payload; Figure 7 : Rotation calibration mark and schematic diagram of two-point orientation special case.

[0035] Example: Machine Learning Application (Ordinal Path Selection and Parameter Update Mapping) In an embodiment of a machine learning application, the input data is a set of feature vectors or a sample sequence. The system constructs an updatable logical topology based on the quantitative description of the relationship field and the output result of the perturbation-response mapping; maps the gradient of the driving component to the rank path selection weight, and performs an associated link identification mapping and a rank path reduction mapping on the set of candidate rank paths of the sample; and uses the constraint deviation identifier Δ output by the self-consistency verification mapping as an internal constraint signal to drive the parameter update mapping of the atomic state unit operation sequence or the set of control parameters, so as to output a classification identifier, a retrieval identifier, a clustering label, or a decision recommendation identifier under the constraint of a preset evaluation function.

[0036] Embodiment supplement: Numerical embodiment and quantization rules (for sufficient disclosure) Supplementary embodiment: Realization of fast decision mapping based on chiral hedging (special case of helix direction) This embodiment illustrates how the system completes the output of decision identifiers without performing hierarchical addressing traversal in high-performance inference or fast decision scenarios. This embodiment is a special implementation manner of the helix direction and does not limit the protection scope of the present invention. 1) Construction of logical spin states (helix direction operation sequence)

[0037] Map the set of decision variables to be processed into a basic state flow, and the control module calls the first helix direction operation code and the second helix direction operation code to generate a combination of helix direction operation sequences; in the M-dimensional rank space, pre-generate dual path descriptions for the set of candidate rank paths (for example, map different deviation types to different helix direction combinations according to the look-up table rule) as candidate inputs for subsequent correction mapping and path selection mapping. 2) Cross-level consistency discrimination of resonant remainders

[0038] In one embodiment, a discrete approximation parameter of an aperiodic scaling factor is introduced to generate a rank calibration identifier; when the rank calibration identifier corresponding to the input data satisfies the consistency condition with the set of allowed paths determined by the quantitative description of the relationship field, the system determines that the candidate path satisfies the rank consistency constraint mapping, and accordingly selects the only acceptable path or the nearest neighbor acceptable path in the helix direction dual path. The consistency condition can be realized by remainder consistency, calibration identifier equality, or satisfaction of a preset threshold distance discrimination. 3) Path reduction output under dimension convergence mapping

[0039] When the constraint deviation identifier Δ obtained by performing the self-consistency verification mapping satisfies the stop condition (for example, Δ = 0 or Δ < T), the system performs a rank dimension reduction mapping on the rank calibration bit group corresponding to the selected path, outputs a steady-state core code with a preset bit width, and maps the steady-state core code to a decision identifier or a control identifier; wherein, the reduction mapping can adopt one or a combination of exclusive OR reduction, majority vote reduction, or look-up table reduction. 4) Path generation overhead suppression under bypass configuration (optional)

[0040] In one optional implementation, the control module sets some sequence address generation units to a bypass state based on the statistical characteristics of the input data or the objective function constraints, so that the output of the dual constraint mapping module or the progressive reduction module is directly input into the N-state array and / or the dimension convergence module, thereby reducing the overhead of the sequence address generation link; thus, in applications that require rapid output of decision identifiers, such as autonomous driving obstacle avoidance and financial risk hedging, processing latency is reduced and response consistency is improved. Example A: Basic Encoding Process (N=2, M=3, Text Data)

[0041] Input: 1000 Chinese characters; convert the Chinese characters to Unicode and form a bit string to obtain a 16000-bit 0 / 1 basic state stream.

[0042] Dual-constraint mapping: Perform closed-loop constraint mapping and ordinal consistency constraint mapping; in an optional embodiment, a discrete approximation of an aperiodic scaling factor Φ≈0.618034 is used to participate in the generation of ordinal calibration identifiers.

[0043] Progressive reduction mapping: 1000 16-bit core frames are obtained by hierarchical reduction.

[0044] Sequence mapping: Construct a three-dimensional sequence space and generate hierarchical sequence addresses.

[0045] Dimensional convergence mapping: The reduction yields a 1-bit core code × 1000, with an overall compression ratio of approximately 16:1; the core code bit width is a preset bit width, which can be configured by control parameters. Example B: Redundancy Correction Triggering and Correction Process (Δ Calculation and Correction Mapping)

[0046] Input: coded payload containing bit-flipping perturbations; reverse mapping yields candidate sequence S*.

[0047] Self-consistency check: Closure deviation Δ c Counting for out-of-bounds symbols; sequence deviation Δ r For the count of violations of the order consistency rule.

[0048] Triggering condition: Let trigger = α·Δ c + β·Δ r ≥ T; where α∈[0.6,0.8], β∈[0.2,0.4], and T∈[1.0,2.0] are the configuration parameters of the control module.

[0049] Correction mapping: After triggering, perform one or a combination of dual flip mapping, neighborhood replacement mapping, or iterative reduction mapping; recalculate Δ′ after correction, and output the correction sequence or the updated core code when Δ′ meets the stop condition (e.g., Δ′ = 0 or Δ′ < T). Example C: Communication payload transmission (send - channel - receive)

[0050] Transmitter: Construct the state space codeword W=(S,A), and it can be further reduced to obtain a preset bit-width degenerate code G (e.g., 256 bits).

[0051] Channel: Simulate a transmission perturbation with a bit flip error rate of 10 -4 of.

[0052] Receiver: Perform a self-consistency check mapping on the received payload to obtain Δ; when Δ meets the trigger condition, perform the correction mapping and output the corrected W^ or G^.

[0053] Statistical example: In 1000 transmission experiments, the correction success rate can reach over 99% (specifically depending on the threshold T, the mapping table, and the correction strategy). Optional implementation example of the rotation direction operation code (for supporting rotation direction special cases)

[0054] Define the first rotation direction operation code opL and the second rotation direction operation code opR as two types of complementary operation codes; in an optional embodiment, they can be identified by 2 bits: opL = 01, opR = 10; corresponding to two opposite migration directions of the atomic state unit.

[0055] Rotation direction sequence generation: Select a combination sequence according to the interval of Δ, for example, select opL when Δ ∈ [1,2], select opR when Δ ∈ [3,4], and select the alternating combination opL - opR when Δ ≥ 5.

[0056] Two-point orientation correction: When the sequence point pair (P1,P2) is bound with a rotation direction calibration identifier, it forms an ordered sequence point pair P1→P2, and at this time, the sequence position direction can be determined by two points; when not bound with a rotation direction calibration identifier, at least three points are still used to determine the orientation metric mapping. Example formula for relationship field quantization (for supporting drive / coupling / constraint / span components)

[0057] In an optional embodiment, the coupling component can be quantified as follows: coupling(i,j) = similarity(S_i,S_j) × exp(-λ·distance(A_i,A_j)) similarity(S_i,S_j): Similarity of state sequences (e.g., cosine similarity); distance(A_i,A_j): The distance between hierarchical bit addresses (e.g., Manhattan distance); λ is the attenuation coefficient, preferably 0.1~1.0. Example of the correspondence between channel disturbance types and correction mapping strategies Supplementary Example D: Bidirectional Protein Design and Sequence Evolution Based on Chiral Hedging

[0058] This embodiment illustrates how, under the special case of optional chiral (left / right) opcodes, the system utilizes the offsetting combination of the first and second chiral opcodes to achieve closed-loop processing of protein structure prediction (from sequence to form) and reverse sequence design (from form to sequence). The "chiral offsetting" in this invention refers to using alternating combinations of the first and second chiral opcodes to create a calibration effect where candidate sequence paths mutually cancel or enhance each other, thereby quickly determining acceptable paths without performing a full traversal.

[0059] 1. Forward structure mapping (structure prediction) Input encoding: Obtain an amino acid sequence to be predicted, map it to a set of basic states according to step S1 of claim 1, and in an optional embodiment, unify the multi-symbol alphabet into a basic state flow consistent with the N-state set through degenerate recoding as described in claim 6.

[0060] Spin evolution: The control module is activated, and the first spin direction opcode (left spin) is called in the N-state array to drive the atomic state units to perform state transformation along the first state migration direction to generate candidate sequence paths oriented towards structural conformation; the candidate paths can be filtered by the driving and constraint components of the relation field described in claim 5.

[0061] Phase offset consistency calibration and convergence: The system simultaneously introduces a second rotation opcode (right-handed) feedback path related to environmental constraints to perform rotation phase offset consistency calibration on candidate ordinal paths; when the rotation phase offset consistency calibration reduces the deviation of the ordinal consistency constraint mapping and satisfies the self-consistency verification condition, the dimensional convergence mapping outputs a steady-state core code with a preset bit width as the structural fingerprint code of the protein's steady-state conformation.

[0062] 2. Inverse sequence inversion (sequence design) Target anchoring: Pre-define the target space geometric topological features (e.g., the set of geometric constraints of receptor binding sites) and convert them into target ordinal calibration sets or target steady-state core codes in M-dimensional ordinal space.

[0063] Path inversion: According to the path inversion mapping described in claim 5, under the constraint of the relation field, the candidate sequence path set is deduced from the target sequence state, and the candidate amino acid state sequence set is derived from the candidate path.

[0064] Hedging identification and output: In the N-state amino acid primitive array, the self-consistency verification mapping described in claim 3 is performed on the candidate amino acid state sequence to obtain the constraint deviation identifier Δ; when Δ meets the preset trigger condition and converges to zero (or below the threshold) after correction mapping, the corresponding amino acid coding sequence is output as the reverse design result.

[0065] 3. Chiral calibration and accuracy control (two-point orientation special case) In the bidirectional evolution process, in one optional embodiment, the system records a spin-tag and binds it to two key ordinal points to form an ordered ordinal pair; at this point, the ordinal direction can be determined by the two points (see [link to documentation]). Figure 7 The two-point orientation special case shown is used to generate an orientation metric map and reduce the computational cost of orientation determination.

[0066] When a single-point mutation or local disturbance in the input sequence causes a shift in the structural fingerprint encoding, the system outputs a constraint deviation identifier Δ through sequence consistency constraint mapping and self-consistency verification mapping, and triggers a correction mapping based on Δ to quickly update the structural fingerprint encoding, thereby achieving rapid reconstruction and correction of the structural prediction results.

[0067] Application scenario expansion (exemplary, not constituting a limitation on the implementation method) Bioinformatics encoding: For example, N=4 maps DNA bases, and M is used to characterize fragment hierarchy; single-symbol bias is identified and feature indexes are generated by correcting the mapping.

[0068] Classical simulation aid for quantum circuits: using discrete sampled states as N states and M to represent circuit levels; outputting core codes through reduction mapping for retrieval and verification.

[0069] Lightweight edge inference and uplink transmission: Output the core encoded sequence as the uplink payload in M=0 or low M configuration to reduce bandwidth usage.

[0070] Lightweight Blockchain Node Verification: Using the self-consistency verification mapping output Δ of the payload as a fast consistency criterion, lightweight verification is achieved.

[0071] Industrial control state machine: N corresponds to the number of discrete states of the equipment, and M corresponds to the control logic level; abnormal states are corrected or replaced in real time through correction mapping.

Claims

1. A method for encoding N-state M-dimensional progressive order positions based on dual-constraint mapping, characterized in that, include: S1 State Mapping: Acquire input data and map the input data to a set of basic states according to a preset state duality rule; The preset state duality rule is either a binary complementary duality rule or a multivariate duality rule, specifically determined by the type of the basic state set. For example, a binary complementary duality rule considers 00 and 11, and 01 and 10 as complementary pairs; a multivariate duality rule groups multi-valued symbols according to a preset complementary relationship. The basic state set contains at least binary state representations, and the mapping adopts uniform or non-uniform transformation based on the distribution characteristics of the input data. The uniform transformation is an equiprobability mapping, and the non-uniform transformation is an adaptive mapping based on the information entropy of the input data. S2 Dual-Constraint Mapping: A dual-constraint mapping process is performed on the basic state set. This process includes at least: state-space closure constraint mapping and sequence consistency constraint mapping. The state-space closure constraint mapping limits the mapping result to members of a preset state set, while the sequence consistency constraint mapping ensures a consistent sequence mapping relationship between sequence addresses and state symbols at different levels. In an optional embodiment, a discrete approximation of an aperiodic scaling factor is introduced to generate a sequence calibration identifier for the basic state set. This identifier is used in the sequence consistency constraint mapping. The generation rule for the sequence calibration identifier is r_i = (x_i·k) mod q, where x_i is a discrete sequence element in the basic state set, k is a discrete approximation of the aperiodic scaling factor, and k = round(S·α), where S is a preset scaling factor, α is the aperiodic scaling factor, and q is a preset modulus. This generation rule is illustrative and does not constitute a limitation of the invention. A preset modulus correlation exists between k and q, ensuring that the sequence calibration identifier r_i... The value range of matches the physical representation range of the N-state set, and the association relationship is configured by the control module and does not constitute a limitation of the present invention; S3 Progressive Reduction Mapping: Performs hierarchical nested reduction mapping on the basic state flow after double constraint mapping to generate a composite state sequence, and each level of reduction mapping retains at least the feature representation of the previous level; S4 Sequence Mapping: The composite state sequence is mapped to hierarchical sequence addresses in an M-dimensional sequence space to construct a multi-level nested sequence structure; where N is used to characterize the size of the discrete state set that the atomic state unit can stably maintain, and M is used to characterize the number of levels of the sequence address. N and M are technically non-interchangeable. S5 Array Evolution Mapping: In an N-state array composed of multiple atomic state units, at least one of the following operations is performed on the corresponding atomic state unit according to the hierarchical sequence address: read, write, flip, compare, or multi-value state switching, and the operation is mapped to a sequence scaling bit group or an event flag bit group. S6 Dimensional Convergence Mapping: Perform dimensional reduction mapping on the ordinal scaling bit group or event flag bit group to output a steady-state core code with a preset bit width; wherein the preset bit width is configured by the control module according to the statistical characteristics of the input data or actual application requirements, and the specific bit width value does not constitute a limitation of the present invention; the dimensional reduction mapping is implemented using state collapse guided by dimensional consistency constraint mapping so that the output code represents the evolution convergence result guided by the constrained field; the dimensional reduction mapping is implemented based on a preset Boolean reduction function or a lookup table reduction function, wherein the Boolean reduction function includes one or more combinations of XOR reduction, AND / OR reduction, and majority voting reduction; Where N≥2, M≥0; when M=0, the method enters the pure N-dimensional processing mode; when M>0, the method enters the N-state M-dimensional collaborative processing mode.

2. A dual-constraint mapping-based N-state M-dimensional progressive order encoding and processing system, used to execute the method described in claim 1, or independently implement N-state M-dimensional data processing, characterized in that, include: The state input module is used to acquire input data and perform state mapping to output a basic set of states; The dual-constraint mapping module is used to perform state space closure constraint mapping and order consistency constraint mapping on the basic state set, and in an optional embodiment, it generates order calibration identifiers based on discrete approximations of non-periodic scaling factors. The progressive reduction module is used to perform hierarchical nested reduction mapping on the basic state flow after double constraint mapping to generate a composite state sequence. The M-dimensional sequence progression module is used to map a composite state sequence into a hierarchical sequence address in an M-dimensional sequence space and output the sequence index group. An N-state array, comprising multiple atomic state units and readout circuits, write circuits, and comparison circuits coupled to the atomic state units, is used to enable the physical state machine to perform at least one of the following operations on the atomic state units based on the hierarchical bit address: cross-dimensional readout, write, atomic-level flip, comparison, or multi-value state switching, and to perform energy self-consistency determination to output an event flag bit group. The dimension convergence module is used to perform ordinal dimension reduction mapping on the ordinal scaling bit group or event flag bit group to output a steady-state core code with a preset bit width. The control module is used to configure N and M and to switch modes; when M is configured as 0, the control module bypasses the sequence address generation path of the M-dimensional sequence progression module, so that the output of the dual constraint mapping module or the progression reduction module is directly input into the N-state array and / or the dimension convergence module to enter the pure N-dimensional processing mode.

3. The method according to claim 1, characterized in that, It also includes a redundancy correction step: performing a self-consistency verification mapping on the candidate state sequence obtained by the steady-state core code of the preset bit width or its reverse mapping, to generate a constraint deviation identifier Δ based on the state space closure constraint mapping and the order consistency constraint mapping; wherein Δ includes at least the closure deviation (the number of symbols in the candidate state sequence that do not belong to the preset state set) and the order deviation (the number of times the candidate state sequence violates the order consistency constraint mapping), and the calculation rule of Δ is configured by the control module; when Δ satisfies the preset triggering condition configured by the control parameters, a correction mapping is executed to output a corrected state sequence or an updated steady-state core code that satisfies the dual constraint mapping; wherein the correction mapping includes one or more combinations of dual flip mapping, neighborhood replacement mapping or iterative reduction mapping, and the redundancy correction does not depend on additional check bits; the correction mapping supports the logical self-consistency balance between forward error correction mapping and reverse parameter restoration mapping, that is, the process of determining the correction path is equivalent to the reverse topological inversion of the target state; wherein the correction mapping also includes rotation control correction (optional special case): pre-defining two types of complementary atomic state unit opcodes, namely the first rotation opcode and the second rotation opcode, wherein the first A first rotation opcode and a second rotation opcode are used to drive atomic state units to perform state transformations along two preset opposite state transition directions. The first rotation opcode and the second rotation opcode can be implemented through a 2-bit identifier or a preset operation table, and their specific encoding form does not constitute a limitation of the present invention. Based on the duality attribute of the input data or the constraint deviation identifier Δ, a rotation sequence combination composed of the first rotation opcode and the second rotation opcode is generated through lookup table mapping or threshold mapping, and the rotation sequence combination is mapped as a correction path for the candidate state sequence to offset or enhance the deviation corresponding to the order consistency constraint mapping. Furthermore, the rotation sequence combination is recorded as an order calibration identifier or implicit calibration feature, participates in the reduction priority selection in the dimensional convergence mapping, and is used as part of the calibration constraint to determine the unique correction solution during reverse mapping. When the rotation calibration identifier is carried between two order points of the candidate state sequence, the two order points constitute an ordered order pair, thereby allowing the order direction to be determined by two points for the direction selection of the correction path. When the rotation calibration identifier is not carried, the determination of the order direction adopts the orientation metric mapping of at least three order points.

4. The system according to claim 2, characterized in that, It also includes a redundancy correction module, which includes a self-consistency verification unit and a correction mapping unit; wherein the self-consistency verification unit is used to output a constraint deviation identifier Δ, and the correction mapping unit is used to output a corrected state sequence or an updated steady-state core code when Δ meets a preset trigger condition, and the threshold of the preset trigger condition is configured by the control module.

5. The method according to claim 1, characterized in that, It also includes a sequence geometry calculation step: representing the hierarchical sequence address as an integer vector (a1, a2, ..., aM) or its derived vector, and performing similarity determination or selection mapping based on the geometric relationship between the vectors; the geometric relationship includes one or more of Euclidean distance de=√(∑i=1..M(ai-bi)²), Manhattan distance dm=∑i=1..M|ai-bi|, or geodesic approximate distance; the similarity determination result is used for sequence path filtering, feature comparison, or cluster analysis, and the selection mapping is used to determine the optimal sequence migration path; and, a mapping function h(·) is defined from the steady-state core encoding or sequence calibration bit group of a preset bit width to the feature comparison result, such that without generating the full set... Under the condition of restoring the data, the comparison identifier, retrieval identifier, or clustering label is output based on h(·); This also includes relation field construction and path mapping: at least three ordinal points or data points are selected in the M-dimensional ordinal space, and an orientation metric mapping is determined based on the at least three ordinal points or data points, and a quantitative description of the internal hierarchical relation field is generated from the orientation metric mapping; the quantitative description includes at least four types of metric components: driving components (used to characterize the driving strength of ordinal migration), coupling components (used to characterize the association weight between ordinal points), constraint components (used to characterize the constraint strength of feasible ordinal migration), and span components (used to characterize ordinal distance or hierarchical span); in an optional embodiment, based on the first rotation opcode and The chiral spin combination formed by the second spin direction opcode performs interference cancellation or phase standing wave determination on the phase collision consistency of the relation field to output an asymmetric feature extraction identifier. In the embodiment carrying the spin direction calibration identifier, at least two sequence points are selected to form an ordered sequence pair, and the sequence direction is determined based on the ordered sequence pair to generate the orientation metric mapping. Furthermore, it also includes perturbation-response mapping and path inversion: receiving external input changes and mapping them as perturbation vectors, mapping the perturbation vectors to an internal candidate sequence path set and corresponding sequence response sequences based on the relation field; given a target sequence state or target steady-state core encoding, performing path inversion mapping on the candidate sequence path set to output... The system outputs a target path that satisfies the constraint components; and further includes an intervention parameter generation mapping: mapping the target path to an executable sequence of atomic state unit operations or a set of control parameters, such that the set of control parameters minimizes the perturbation metric and maximizes the objective function while satisfying the constraint components; wherein the perturbation metric is the magnitude of the perturbation vector or the normalized perturbation value, and the objective function is a weighted function composed of driving components, coupling components, constraint components, and span components; the intervention parameter generation mapping supports forward design mapping or inverse inversion mapping; wherein, in a machine learning application embodiment, an updatable logical topology is constructed based on the quantitative description of the relation field and the output of the perturbation-response mapping;By mapping the gradient of the driving component to ordinal path selection weights, association link identification mapping and ordinal path reduction mapping are performed on the ordinal path set of massive input data; and, using the constraint deviation identifier Δ output by the self-consistency verification mapping and correction mapping described in claims 3 and 4 as an internal constraint signal, the parameter update mapping of the atomic state unit operation sequence is driven to output classification identifier, retrieval identifier, clustering label or decision suggestion identifier under the constraints of a preset objective function; in an optional bioinformatics application embodiment, the amino acid sequence is mapped to the basic state flow, the hedging evolution of the first and second rotation opcodes is used to simulate peptide chain spatial folding, and dimensional convergence mapping is performed at the phase hedging consistency resonance point to achieve rapid prediction of protein three-dimensional structure and reverse sequence design.

6. The method according to claim 1, characterized in that, It also includes a degenerate re-encoding step: performing degenerate mapping on K initial logic states or their combinations through dual rules to obtain a basic state flow consistent with the N-state set; wherein the degenerate mapping includes performing binary complementary dual reduction on the initial logic states to generate a fixed-length core logic frame, and mapping the degenerate remainder of the core logic frame to the basic state value; the degenerate remainder is the result of the bitwise XOR sum of the core logic frame modulo N, wherein the bitwise XOR sum is the result of the XOR operation of all bits in the core logic frame, and the modulo operation is used to ensure that the value range of the degenerate remainder matches the size of the N-state set, and the mapping relationship between the remainder and the basic state value is determined by a mapping table or lookup table logic.

7. The system according to claim 2, characterized in that, The control module is used to perform dynamic dimension configuration: without changing the atomic state unit circuit configuration of the N-state array, the number of levels of the sequence address generation logic and the reduction logic is adjusted; the adjustment includes one or more combinations of enabling / disabling some level sequence address generation units, reusing the mapping table, or updating the reduction function parameters; and the control module configures N and M according to the statistical feature mapping results of the input data; for example, when the information entropy of the input data is high and the symbol distribution dispersion is large, a larger N and M can be configured to improve representation efficiency; for example, when the information entropy of the input data is low and the symbol distribution is concentrated, a smaller N and M can be configured to reduce implementation overhead; the statistical features include one or more of information entropy, symbol distribution dispersion, sequence difference statistics, or symbol transition matrix, and the configuration is achieved through table lookup, threshold mapping, or register writing.

8. A communication or transmission method, characterized in that, include: At the transmitting end, a state space codeword or a preset bit-width degenerate code is generated based on the method described in claim 1 or 6, and the state space codeword or the preset bit-width degenerate code is used as the transmission payload; wherein the state space codeword and the preset bit-width degenerate code both satisfy the requirements of state space closure constraint mapping and sequence consistency constraint mapping to ensure the validity of the payload; at the receiving end, a self-consistency verification mapping is performed on the transmission payload to generate a constraint deviation identifier Δ, and a correction mapping is performed when Δ satisfies a preset trigger condition to obtain a corrected payload; wherein the correction mapping includes one or more combinations of dual flip mapping, neighborhood substitution mapping, or iterative reduction mapping; in an optional embodiment, the transmitting end performs a perturbation mapping on the discrete approximate parameters of the aperiodic scaling factor to generate different sequence calibration identifiers, thereby causing parameterized differences in the hierarchical sequence address or degenerate code of the payload.

9. The communication or transmission method according to claim 8, characterized in that, The state space codeword consists of a state symbol sequence S and its hierarchical ordinal address A, represented as W=(S,A); the preset bit-width degenerate code is obtained by performing ordinal reduction mapping on W, and the ordinal reduction mapping defines an acceptable load set based at least on the state space closure constraint mapping and the ordinal consistency constraint mapping, and maps loads that do not belong to the acceptable set to the nearest neighbor load or preset alternative load that satisfies the dual constraint mapping; The nearest neighbor load is the acceptable load with the smallest sequence distance from the deviating load, wherein the sequence distance is one or more of Euclidean distance or Manhattan distance; the preset alternative load is a standard load pre-configured by the control module, and the specific selection method is determined by the correction mapping strategy.

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