Chip control method and chip

Abstract

The application provides a chip control method and a chip, and relates to the technical field of chip communication. The method comprises the following steps: receiving flow control information, wherein the flow control information comprises remote flow control information, the remote flow control information is from a second chip located in a different computing card from the first chip; analyzing the flow control information to obtain a flow limiting address and a back pressure rule; and selectively performing back pressure control on a data transmission request of a data carrying engine and other data transmission requests for the second chip according to the flow limiting address, the back pressure rule and a back pressure switch identifier of the data carrying engine of the first chip.

Description

Technical Field

[0001] This application relates to the field of chip communication technology, and more specifically, to a chip control method and a chip. Background Technology

[0002] In multi-chip interconnected communication architectures, a single chip often needs to establish connections with multiple neighboring chips to enable bidirectional exchange of instructions and data. During actual transmission, if the data rate output by the transmitting chip consistently exceeds the processing capacity of the receiving chip, data backlog will occur at the receiving end, leading to communication congestion. To maintain system stability and transmission reliability, appropriate flow control strategies must be introduced to dynamically adjust the transmission rhythm, thereby matching the actual processing capacity of the receiving end.

[0003] However, when the data sender performs flow control, it often focuses on write requests from its own device to other devices (such as write requests via PCIe), while ignoring data congestion that may be caused by its own data transfer engine, such as the high-performance direct memory access (HDMA) engine. Allowing HDMA to continue writing data to other devices may still lead to data overflow. Summary of the Invention

[0004] The purpose of this application is to address the shortcomings of the prior art by providing a chip control method and chip for backpressure control of data requests from a data transfer engine.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a chip control method applied to a first chip, the method comprising: Receive flow control information, the flow control information including remote flow control information, the remote flow control information coming from a second chip located on a different computing card than the first chip; Parse the flow control information to obtain the rate-limiting address and backpressure rules; Based on the current limiting address, the backpressure rule, and the backpressure switch identifier of the data transfer engine of the first chip, backpressure control is selectively applied to the data transfer requests of the data transfer engine and other data transfer requests to the second chip.

[0006] Optionally, the step of selectively performing backpressure control on data transmission requests from the data transmission engine and other data transmission requests to the second chip based on the current limiting address, the backpressure rule, and the backpressure switch identifier of the data transmission engine of the first chip includes: If the reverse pressure switch is identified as the first identifier, reverse pressure control is applied to the data transmission request sent from the first chip to the second chip according to the current limiting address and the reverse pressure rule; If the reverse pressure switch is identified as the second identifier, reverse pressure control is performed on the data transmission request sent from the first chip to the second chip and the data transmission request of the data transport engine according to the current limiting address and the reverse pressure rule.

[0007] Optionally, the selective backpressure control of data transfer requests from the data transfer engine and other data transfer requests to the second chip includes: If the rate-limiting address is a remote address, the data transmission request of the data transfer engine continues to be transmitted; if the rate-limiting address is a near-end address, the data transmission request of the data transfer engine is subject to backpressure control.

[0008] Optionally, the backpressure control of data transmission requests to the data transport engine includes: Backpressure control is applied to the read data requests sent by the data transfer engine to the storage unit in the first chip and the write data requests sent to the second chip.

[0009] Optionally, the first chip includes a data transfer channel for a data transfer engine sharing an AXI port, a data access channel for accessing local storage units, and a forwarding channel for forwarding access requests. The method further includes: The read requests of the data transport channel are suppressed, and the read requests of the data access channel and the forwarding channel are controlled to continue to be transmitted.

[0010] Optionally, the method further includes: Based on the cache queue state of the first chip, second flow control information is selectively generated, and the second flow control information includes at least: the first congestion level corresponding to the cache queue state; The second flow control information is sent to at least one third chip that communicates with the first chip, so that the at least one third chip performs flow control on data transmission requests sent to the first chip according to the first congestion level.

[0011] Optionally, the step of selectively generating second flow control information based on the cache queue state of the first chip includes: Based on the used capacity of the cache queue of the first chip and the first capacity change trend, the second flow control information is generated. The second flow control information includes the first congestion level and the first capacity change trend.

[0012] Optionally, the cache queue includes a first cache queue and a second cache queue, wherein the first cache queue has a faster read speed than the second cache queue, and the method further includes: Once the used capacity of the first cache queue exceeds a preset capacity threshold, the message sent to the first chip will be cached in the second cache queue.

[0013] Optionally, the method further includes: Process the messages in the first cache queue; When the first cache queue is empty and the second cache queue is not empty, the messages in the second cache queue are written into the first cache queue for processing in sequence; When the number of messages in the second cache queue is less than the preset number of messages, if a new message is received, the new message is determined to be stored in the first cache queue or the second cache queue based on the remaining number of requests and the remaining capacity in the first cache queue.

[0014] Secondly, embodiments of this application also provide a chip, the chip including a flow control module, the flow control module being used to perform the chip control method as described in any of the first aspects.

[0015] The beneficial effects of this application are: The chip control method and chip provided in this application, when receiving remote flow control information sent by a remote chip, can selectively perform back pressure control on the data transmission request of the target data sender from multiple data senders, including the data transfer engine, according to the back pressure switch identifier of the data transfer engine, which can effectively reduce data overflow of the remote chip. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic flowchart illustrating a chip control method provided in an embodiment of this application; Figure 2 An architectural diagram of a first chip provided in an embodiment of this application; Figure 3 A schematic flowchart illustrating a chip control method provided in another embodiment of this application; Figure 4 A schematic block diagram of a flow control information sending unit provided in an embodiment of this application; Figure 5 A system architecture diagram provided for another embodiment of this application; Figure 6 A schematic flowchart illustrating a chip control method provided in another embodiment of this application; Figure 7 This is an architecture diagram of a computing system provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] Furthermore, the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0022] Figure 1 This is a schematic flowchart of a chip control method provided in an embodiment of this application, as shown below. Figure 1 As shown, the method may include: S101. Receive flow control information, including remote flow control information, which comes from a second chip located on a different computing card than the first chip.

[0023] In this embodiment, the first chip and the second chip are located on different computing cards. The first chip can send messages or requests to the second chip through a data transmission channel. The second chip caches the messages or requests sent by the first chip and processes the cached messages or requests one by one.

[0024] Due to limited cache capacity, if the first chip sends messages or requests too quickly, or if the second chip has low processing power, messages or requests will accumulate in the cache, causing congestion or overflow.

[0025] To avoid this situation, the second chip monitors the used capacity of the cache. When the used capacity reaches a preset threshold, the second chip determines that messages or requests are piling up, generates flow control information, and sends it to the first chip. Since the first and second chips are located on different computing cards, the flow control information is remote flow control message (RFCMsg).

[0026] In some embodiments, a flow control information receiving unit is provided in the first chip, and a flow control information sending unit is provided in the second chip. The flow control information sending unit is used to monitor the used capacity of the cache and generate remote flow control information to send to the flow control information receiving unit of the first chip.

[0027] S102. Parse the flow control information to obtain the rate-limiting address and backpressure rules.

[0028] In this embodiment, the flow control information receiving unit of the first chip parses the flow control information and determines the flow limiting address and backpressure rule carried in the flow control information. The flow limiting address can be the address of the data transmission channel between the first chip and the second chip, or it can be the destination memory address in the second chip used to process the message or request sent by the first chip.

[0029] The backpressure rule is used to indicate the backpressure duration or backpressure period of the first chip for messages or requests sent to the second chip.

[0030] In some embodiments, the flow control information includes the congestion level of the second chip. The flow control information receiving unit of the first chip determines the backpressure rule based on the congestion level. The backpressure rule includes the backpressure cycle proportion, which is the number of cycles in which the message to be sent to the destination is blocked within a preset number X flow control cycles. The higher the congestion level, the greater the backpressure cycle proportion.

[0031] For example, if X is 20 cycles and the backpressure cycle ratio is 5, then when the first chip sends messages to the third chip, it can be controlled to stop sending for 5 cycles within every 20 cycles, and send normally for the remaining 15 cycles. This will gradually reduce the receiving pressure on the third chip. By reducing the receiving pressure on the third chip and continuing message processing, congestion can be alleviated. The backpressure cycle ratio can be completed continuously within a fixed number of cycles or intermittently.

[0032] Furthermore, the flow control information includes the congestion level and capacity change trend of the second chip. The flow control information receiving unit of the first chip determines the proportion of backpressure cycles based on the congestion level and capacity change trend. Under the same congestion level, the proportion of backpressure cycles with an upward capacity change trend is greater than the proportion of backpressure cycles with a downward capacity change trend.

[0033] S103. Based on the current limiting address, back pressure rules, and the back pressure switch identifier of the data transfer engine of the first chip, selectively perform back pressure control on the data transfer request of the data transfer engine and other data transfer requests for the second chip.

[0034] In this embodiment, since there may be multiple data senders in the first chip, such as a general-purpose graphics processing unit (GPGPU) and a data transfer engine, both of which can send messages or requests to the second chip as data senders, when the first chip receives the flow control information sent by the second chip, it cannot distinguish whether the congestion of the second chip is caused by the message or request sent by the data transfer engine or by the message or request sent by other data senders (such as GPGPU). Therefore, a back pressure switch identifier for the data transfer engine is provided.

[0035] The back pressure switch flag for the data transfer engine can be configured via software, indicating whether back pressure control is required for data transfer requests from the data transfer engine.

[0036] Upon receiving the flow control information, the target data sender requiring flow control is determined from the data transfer engine and other data senders based on the back pressure switch identifier of the data transfer engine. According to the back pressure rules, the data transmission request sent by the target data sender to the second chip is subjected to back pressure control.

[0037] In some embodiments, the reverse pressure switch identifier can be determined based on whether the DMA controller in the first chip has sent a data transfer instruction to the data transfer engine. If the DMA controller sends a data transfer instruction to the data transfer engine, instructing the data transfer engine to transfer data between the first chip and the second chip, the reverse pressure switch identifier can be an on identifier. If the DMA controller does not send a data transfer instruction to the data transfer engine, the reverse pressure switch identifier can be a off identifier.

[0038] The chip control method provided in the above embodiments, when receiving remote flow control information sent by a remote chip, selectively performs back pressure control on the data transmission request of the target data sender from multiple data senders, including the data transfer engine, according to the back pressure switch identifier of the data transfer engine, which can effectively reduce data overflow of the remote chip.

[0039] In one possible implementation, the process of S103, which selectively performs backpressure control on data transmission requests from the data transmission engine and other data transmission requests to the second chip based on the current-limiting address, backpressure rules, and the backpressure switch identifier of the data transmission engine of the first chip, may include: If the reverse pressure switch is identified as the first identifier, reverse pressure control is applied to the data transmission request sent from the first chip to the second chip according to the current limiting address and reverse pressure rules; if the reverse pressure switch is identified as the second identifier, reverse pressure control is applied to the data transmission request sent from the first chip to the second chip and the data transmission request of the data transfer engine according to the current limiting address and reverse pressure rules.

[0040] In this embodiment, the reverse pressure switch identifier is used to indicate whether reverse pressure control is required for data transmission requests sent by the data transfer engine to the first chip. If the reverse pressure switch identifier is the first identifier, it indicates that reverse pressure control is required for all data transmission requests sent from the first chip, including the data transfer engine, to the second chip. If the reverse pressure switch identifier is the second identifier, it indicates that reverse pressure control is required not only for all data transmission requests sent from the first chip, including the data transfer engine, to the second chip, but also for data transmission requests of the data transfer engine within the first chip.

[0041] In some embodiments, the reverse voltage switch identifier of the first chip can be configured according to the connection method or communication method between the first chip and the second chip.

[0042] If the first chip communicates with the second chip through a relay chip, the reverse voltage switch identifier can be set as the first identifier; if the first chip and the second chip communicate directly, the reverse voltage switch identifier can be set as the second identifier.

[0043] For example, an enble bit of 0 indicates the first identifier, and an enble bit of 1 indicates the second identifier.

[0044] It should be noted that the data transmission process of other data senders only involves sending data transmission requests to the second chip, while the data transmission process of the data transfer engine involves retrieving data from the first chip and then sending data to the second chip. Backpressure control of the data transmission requests of the data transfer engine can include both the process of retrieving data from the first chip and sending data to the second chip. For example, read requests from the data transfer engine can be controlled regardless of the specific address. Based on the data transfer engine's near-end read-to-far-end characteristic, this avoids the data transfer engine writing data to the remote chip, alleviating congestion on the remote chip. Because the data transfer engine moves data from SrcAdd to DstAdd, and DstAdd is internal to the data engine and not easily observable from the outside, suppressing all Src requests is more efficient from an implementation perspective.

[0045] The chip control method provided in the above embodiments determines the target data sender from the data transfer engine and other data senders based on the reverse pressure switch identifier, and performs reverse pressure control on the data transmission request of the target data sender so that the reverse pressure on the data transmission request matches the data transmission state indicated by the reverse pressure switch identifier, which can effectively prevent data overflow from occurring on the remote chip.

[0046] In one possible implementation, the process of selectively applying backpressure control to data transfer requests from the data transfer engine and other data transfer requests to the second chip in step S103 may include: If the rate-limiting address is a remote address, the data transmission request of the data transfer engine will continue to be transmitted; if the rate-limiting address is a near-end address, the data transmission request of the data transfer engine will be subject to backpressure control.

[0047] In this embodiment, the system typically includes at least a first chip, a second chip, and a third chip. The first chip and the second chip are located on different computing cards but are directly connected. The third chip is connected to the second chip and needs to communicate with the first chip through the second chip. The third chip can be located on the same computing card as the second chip or on different computing cards; this embodiment does not impose any restrictions on this. The second chip serves as a near-end chip of the first chip, and the third chip serves as a far-end chip of the first chip.

[0048] The remote flow control information sent by the second chip to the first chip can be flow control information generated by the second chip itself due to congestion, or it can be flow control information forwarded from the third chip. Since both the first and second chips may send messages or requests to the third chip, when congestion occurs, the third chip sends flow control information to the second chip, which then forwards the flow control information to the first chip.

[0049] During the data transfer process, whether the data is sent to the second chip or the third chip, the data transfer engine can only transfer the data from the first chip to the second chip. If the data needs to be sent to the third chip, the second chip needs to transfer it again.

[0050] When the first chip receives the flow control information, it determines whether the flow-limiting address in the flow control is a near-end address or a far-end address, i.e., the address of the second chip or the third chip. If the flow-limiting address is a near-end address, i.e. the address of the second chip, it is determined that the congestion occurs within the second chip. Then, it applies backpressure control to the data transmission requests of the data transfer engine, reducing or stopping the data transfer engine from sending messages or requests to the second chip.

[0051] If the rate-limiting address is a remote address, i.e., the address of the third chip, and it is determined that the congestion occurs within the third chip and not within the second chip, then there is no need to perform backpressure control on the data transmission requests of the data transfer engine separately. The data transfer engine will normally send messages or requests to the second chip, and the second chip will perform backpressure control according to the regular flow control rules when forwarding them to the third chip. In this way, when the congestion situation of the third chip is relieved, the second chip can quickly forward messages or requests to the third chip.

[0052] For example, the fourth chip and the first chip are located on the same computing card and are connected to the second chip through the first chip. The first chip and the second chip are chips that connect the two computing cards. When the second chip sends remote flow control information to the first chip, the first chip, as the first chip on the local computing card to receive the remote flow control information, can perform separate backpressure control on read requests of its own data transport engine according to the backpressure switch flag being enabled, and perform backpressure control on write requests from other request initiators (such as GPGPU) of its own chip according to the rate-limited address / rate-limited channel. The backpressure control rules for both can be backpressure for Y cycles within X cycles. After receiving the remote flow control information transmitted locally by the first chip, the fourth chip performs backpressure control on messages within the remote rate-limited address according to the remote flow control rules, but does not perform separate backpressure control on read requests of its own data transport engine. The flow control of the fourth chip's data transport engine can be completed by the first chip's flow control of its own chip and the forwarded write requests.

[0053] The chip control method provided in the above embodiments determines whether to apply backpressure control to the data transmission request of the data transfer engine based on whether the current limiting address is a near-end address or a far-end address. This can prevent data overflow from other chips and enable the data transmission request to be sent quickly during congestion recovery, thereby improving transmission efficiency.

[0054] In one possible implementation, the process of backpressure control of data transfer requests from the data transport engine in step S103 above may include: Backpressure control is applied to read data requests sent by the data transfer engine to the storage unit in the first chip and write data requests sent to the second chip.

[0055] In this embodiment, as Figure 1 As shown, during the data transfer process, the data transfer engine often needs to read data from the storage unit of the first chip and then write the read data to the second chip. If only the write data request sent to the second chip is subject to backpressure control during the data transfer engine's data transfer request backpressure control, it may cause the data read by the data transfer engine from the storage unit to become congested in the data transfer engine. Therefore, backpressure control can be applied to both the read data request from the storage unit and the write data request sent to the second chip.

[0056] The chip control method provided in the above embodiments applies back pressure to both read and write data requests from the data transfer engine, thus avoiding data congestion caused by ignoring local reads from the data transfer engine.

[0057] In one possible implementation, the first chip includes a data transfer channel for a data transfer engine sharing an AXI port, a data access channel for accessing local storage units, and a forwarding channel for forwarding access requests. The method may further include: Read requests from the backpressure data transport channel continue to transmit, while read requests from the control data access channel and forwarding channel continue to transmit.

[0058] In this embodiment, Figure 2 An architectural diagram of a first chip provided in an embodiment of this application is shown below. Figure 2As shown, the first chip may include at least one PCIe system, a storage unit, and an on-chip network. The data transfer engine is integrated within the PCIe system. The PCIe system also has virtual channels VC0 and VC1. Virtual channel VC0 is a data access channel, and virtual channel VC1 is a forwarding channel. Data read / write requests from external devices to the storage unit of the first chip are sent to the storage unit through virtual channel VC0. Data read / write requests to storage units other than the first chip are transmitted through virtual channel VC1. Data read / write requests from the data transfer engine and external devices to the storage unit are sent to the storage unit through the same AXI interface of the PCIe system.

[0059] When performing backpressure control on data transfer requests from the data transfer engine, backpressure control is only applied to the data transfer channel used to transmit data transfer requests. Based on the backpressure switch flag, backpressure control is applied to read requests from the data transfer channel within the read request, while read requests from external devices accessing storage units via data access channel VC0 and read requests sent via forwarding channel VC1 are maintained. This reduces the impact on data transmission from non-congested parties.

[0060] The chip control method provided in the above embodiments reverses the read requests of the data transport channel and controls the read requests of the data access channel and forwarding channel to continue to transmit, thereby achieving precise reverse pressure for different types of requests on the same AXI interface.

[0061] In one possible implementation, Figure 3 A schematic flowchart of a chip control method provided in another embodiment of this application is shown below. Figure 3 As shown, the method may further include: S201. Based on the cache queue status of the first chip, selectively generate second flow control information. The second flow control information includes at least the first congestion level corresponding to the cache queue status.

[0062] A flow control information sending unit is set on the first chip. The flow control information sending unit is used to execute steps S201-S202. Figure 4 This is a schematic block diagram of a flow control information sending unit provided in an embodiment of this application, as shown below. Figure 4 As shown, the flow control information sending unit may include: a first buffer queue 11, a capacity monitoring unit 12, and a flow control information generation unit 13. The capacity monitoring unit 12 is communicatively connected to the first buffer queue 11, and the flow control information generation unit 13 is communicatively connected to the capacity monitoring unit 12. Alternatively, a flow control information sending unit can be set on the first chip, or it can be set on each interconnect channel of the first chip.

[0063] In this embodiment, a first cache queue 11 is provided in the first chip. The first cache queue 11 is used to cache all messages sent to the first chip. The messages sent to the first chip can be requests or data. Requests can be read requests or write requests. The messages sent to the first chip are first cached in the first cache queue 11 so that the processing unit in the first chip can cache the messages in the first cache queue 11 one by one.

[0064] The capacity monitoring unit 12 monitors the status of the cache queue in the first cache queue 11 of the first chip. The first cache queue 11 has multiple preset capacity thresholds, each corresponding to a different congestion level. A smaller capacity threshold corresponds to a lower congestion level, and a larger capacity threshold corresponds to a higher congestion level. The unit monitors the used capacity of the first cache queue 11 in real-time or periodically, compares the used capacity of the first cache queue 11 with the multiple capacity thresholds, determines the capacity threshold corresponding to the used capacity of the first cache queue 11, and obtains the first congestion level.

[0065] The flow control information generation unit 13 receives the capacity threshold corresponding to the used capacity / the target area corresponding to the used capacity from the capacity monitoring unit 12. If the cache queue status indicates that the first cache queue 11 has not experienced message congestion, the first chip will not generate the second flow control information. If the cache queue status indicates that the first cache queue 11 has experienced message congestion, the first congestion level corresponding to the target area is determined, and the second flow control information is generated based on the congested interconnect channel (such as a PCIe channel) or the target address range of the congested party and the first congestion level.

[0066] In some embodiments, the first buffer queue 11 is a high-speed buffer, typically a fast first-in-first-out (FIFO) storage unit. The used capacity of the first buffer queue 11 is an indicator of whether the downstream processing capability matches the upstream transmission rate. When the used capacity is almost full, it means that the downstream processing rate is difficult to meet the upstream transmission rate. When the used capacity is small, it means that the downstream processing rate can meet the upstream transmission rate. The system efficiency is highest when the two are matched.

[0067] Furthermore, the first buffer queue 11 can be divided into multiple regions. The capacity monitoring unit 12 is pre-configured with multiple regions and multiple congestion levels. The capacity monitoring unit 12 monitors the target region corresponding to the used capacity of the first buffer queue 11. When a region change event is detected, flow control information is generated.

[0068] Furthermore, the second flow control information may also include: the channel identifier of the interconnect channel where the congested buffer queue in the first chip is located, or the target address range where the first chip is congested. The channel identifier / target address range is used to instruct the second chip to perform backpressure control on messages sent to the interconnect channel / target address range.

[0069] S202. Send second flow control information to a plurality of third chips that can communicate with the first chip, so that each third chip performs flow control on the messages sent to the first chip according to the first congestion level.

[0070] In this embodiment, in order to avoid data overflow in the first cache queue 11 of the first chip, when message congestion occurs in the first cache queue 11 of the first chip, the flow control information generation unit 13 needs to notify all third chips that can communicate with the first chip to perform flow control.

[0071] Specifically, multiple third chips that can communicate with the first chip are identified. These multiple third chips that can communicate with the first chip include: chips that are directly connected to the first chip on the same computing card; chips that are directly connected to the first chip on different computing cards; and chips that are located on different computing cards but can achieve cross-card communication through a relay chip.

[0072] For example, Figure 5 A system architecture diagram provided for another embodiment of this application, such as Figure 5 As shown, chips 1, 2, and 3 can be mounted on the same computing card and communicate with each other. Chips 4 and 5 can also be mounted on the same computing card and communicate with each other. Chips 1 and 4 communicate directly, while chip 5 communicates with chip 1 across cards via chip 4. The first chip can be chip 1, and the third chip can be any one of chips 2, 3, 4, and 5.

[0073] If the third chip is located on the same computing card as the first chip, the flow control information generation unit 13 directly sends the second flow control information as a local flow control message (FCMsg) to the third chip. If the third chip is located on a different computing card than the first chip, the flow control information generation unit 13 generates remote flow control information based on the second flow control information and sends the remote flow control information to the third chip.

[0074] For the third chip that receives the second flow control information, it determines the first congestion level by parsing the second flow control information, and determines the flow control duration or backpressure cycle proportion based on the first congestion level. Based on the flow control duration or backpressure cycle proportion, it performs flow control on the messages sent to the first chip, that is, it stops sending messages to the first chip within the flow control duration, or stops sending messages to the first chip within the corresponding backpressure cycle proportion within the preset data transmission cycle X.

[0075] In some embodiments, the chips are interconnected via PCIe, and a flow control information transmitting unit and / or a flow control information receiving unit can be provided on the first chip. Alternatively, a flow control information transmitting unit and / or a flow control information receiving unit can be provided on each interconnect channel of the first chip.

[0076] For example, a PCIe channel of the first chip, such as PCIe0, is connected to a PCIe channel of the third chip, such as PCIe1. The flow control information sending unit of the PCIe0 of the first chip generates second flow control information and sends the second flow control information to the flow control information sending unit of the PCIe1 of the third chip. The flow control information sending unit of the PCIe1 of the third chip can broadcast the second flow control information to all flow control information receiving units in the third chip.

[0077] Reference Figure 5The connection architecture shown has a corresponding interconnect channel on each chip, such as PCIech (not shown). The PCIech can be used for cross-card connection expansion. Each interconnect channel number corresponds to the chip it belongs to. There is also a noc (not shown) which can be used for interconnection of chips within the card. For example, chip 2 generates local flow control information due to congestion and sends it to chips 1 and 3. The local flow control information includes information type (local), interconnection channel number (corresponding to the fourth chip), congestion level, and forwarding card limit information (2, used to limit the number of forwarding cards; forwarding is allowed when the number is greater than or equal to 1). The corresponding chip that needs flow control can be obtained through the interconnection channel number. Chip 3 can determine the message to be sent by chip 2 that requires flow control based on the interconnection channel number. After receiving the local flow control information, chip 1 performs flow control on the message sent to chip 2 based on the local flow control information. On the other hand, when forwarding is enabled, forwarding generates first remote flow control information. The first remote flow control information includes card number (first computing card), flow-limiting address range (stored in the forwarding content register, the equivalent address range of chip 2 accessed from the perspective of the second computing card), forwarding card limit information (2-1=1, used to limit the number of forwarding cards; forwarding is allowed when the number is greater than or equal to 1), information type (remote), interconnection channel number (which changes and corresponds to chip 1), and congestion level. Congestion level (unchanged); After receiving the first remote flow control information, chip 4 generates and broadcasts the second remote flow control information to chip 5 within the second computing card. The second remote flow control information includes the card number (unchanged, first computing card), the rate-limiting address range (unchanged, the equivalent address range for accessing chip 2 from the perspective of the second computing card), the forwarding card limit information (1, used to limit the number of forwarding cards; forwarding is allowed when the number is greater than or equal to 1), the information type (remote), the interconnection channel number (changed, corresponding to chip 4), and the congestion level (unchanged); If chip 5 is connected to a third computing card, it generates the third remote flow control information based on the second remote flow control information and sends it to the third computing card. The third remote flow control information includes the card number (changed, second computing card), the rate-limiting address range (changed, the equivalent address range for chip 4 from the perspective of the third computing card), the forwarding card limit information (1-1=0, used to limit the number of forwarding cards; cross-card forwarding is not allowed), the information type (remote), the interconnection channel number (changed, corresponding to chip 5), and the congestion level (unchanged). For example, the chip number can also be used directly instead of the interconnection channel number.

[0078] When performing flow control, local flow control can directly determine the chip corresponding to the flow control of the flow limiting channel based on local flow control information; remote flow control can perform flow control on messages within a specific equivalent address range based on the interconnection channel number and equivalent address range of the remote flow control information, thereby achieving fine-grained flow control and flexible adaptation to the interconnection architecture.

[0079] The flow control method provided in the above embodiments generates second flow control information based on the cache queue state of the first chip, and sends the second flow control information to multiple third chips that can communicate with the first chip. This ensures that multiple third chips can perform backpressure control on messages to be sent in advance, reducing the occurrence of data overflow in the first chip. Based on the cache queue state, a first congestion level is determined to generate flow control information that matches the cache queue state, thereby enabling fine-grained flow control of messages sent to the first chip by multiple third chips.

[0080] In one possible implementation, the process of selectively generating second flow control information based on the cache queue state of the first chip in step S201 may include: Based on the used capacity of the cache queue of the first chip and the first capacity change trend, second flow control information is generated. The second flow control information includes: the first congestion level and the first capacity change trend.

[0081] In this embodiment, in addition to monitoring the used capacity of the first cache queue 11, the capacity monitoring unit 22 can also monitor the first capacity change trend of the first cache queue 11. Specifically, the first capacity change trend can be determined by judging the used capacity of two adjacent monitoring times, or it can be determined by the level before and after the congestion level change. For example, if the level before the change is 5 and the level after the change is 4, then the first capacity change trend is decreasing.

[0082] The flow control information generation unit 13 generates second flow control information based on the target address range of the congested interconnection channel or the congested party, the first congestion level, and the first capacity change trend.

[0083] After receiving the second flow control information, multiple third chips determine the flow control duration or backpressure cycle based on the first congestion level and the first capacity change trend. Based on the flow control duration or backpressure cycle, they perform flow control on the messages sent to the first chip, that is, they stop sending messages to the first chip within the flow control duration, or stop sending messages to the first chip for the corresponding number of backpressure cycles within the preset data transmission cycle.

[0084] The chip control method provided in the above embodiments generates second flow control information based on the first congestion level and the first capacity change trend of the buffer queue. This allows multiple third chips to determine the backpressure period according to the congestion level and capacity change trend. This enables the messages sent to the first chip to be matched not only with the congestion level of the first chip's buffer queue but also with the capacity change trend of the first chip's buffer queue, achieving fine-grained flow control. On the one hand, this reduces the occurrence of data overflow in the first chip, and on the other hand, it ensures that the message sending rate of the third chip matches the message processing rate of the first chip, thereby improving message transmission efficiency.

[0085] In one possible implementation, the cache queue includes a first cache queue and a second cache queue, wherein the first cache queue is read faster than the second cache queue. The method may also include: Once the used capacity of the first cache queue exceeds a preset capacity threshold, the message sent to the first chip will be cached in the second cache queue.

[0086] In this embodiment, as Figure 4 As shown, when the used capacity of the first cache queue 11 reaches the maximum capacity limit, the rewrite function of the second cache queue 14 is triggered to cache the subsequently received messages into the second cache queue 14.

[0087] The second buffer queue 14 is typically a slow FIFO. Since this embodiment performs hierarchical backpressure control based on the used capacity of the first buffer queue 11, and the maximum backpressure control strategy is full-cycle flow control, the first buffer queue 11 will not experience the extreme situation of reaching the maximum capacity limit under normal circumstances. However, considering the latency and abnormal situations during message transmission, the second buffer queue 14 is set up. Therefore, the number of messages that the second buffer queue 14 needs to cache is limited, and the second buffer queue 14 can adopt a capacity in the MB range.

[0088] For example, random access memory (RAM) can be used as the first cache unit, and dynamic random access memory (DRAM) can be used as the second cache queue.

[0089] The chip control method provided in the above embodiments can provide backup space for latency and abnormal situations during message transmission by setting two buffer queues, thus preventing extreme situations from occurring.

[0090] In one possible implementation, Figure 6 A schematic flowchart of a chip control method provided in another embodiment of this application is shown below. Figure 6 As shown, the method may further include: S301. Process the messages in the first buffer queue.

[0091] S302. When the first cache queue is empty and the second cache queue is not empty, the messages in the second cache queue are written into the first cache queue for processing in sequence.

[0092] S303. When the number of messages in the second cache queue is less than the preset number of messages, if a new message is received, the new message is stored in the first cache queue or the second cache queue based on the remaining number of requests and the remaining capacity in the first cache queue.

[0093] In this embodiment, during the downstream data processing unit's message processing, messages are sequentially read from the first cache queue 11 in the order of message writing using a first-in-first-out method and decapsulated into AXI transactions before being sent to the downstream data processing unit.

[0094] When the first cache queue 11 changes from its maximum capacity limit state to having some free space, if there are messages in the second cache queue 14, the messages can be read from the second cache queue 14 and placed at the tail of the first cache queue 11. When reading messages from the second cache queue 14, the amount of messages to be read is determined based on the free space in the first cache queue 11. Greedy reading should be avoided to prevent overflow; in this case, the reading priority is higher than that of normal memory access tasks.

[0095] When there is space in the first cache queue 11, data from the second cache queue 14 is written to the tail of the queue first. This avoids the possibility of incorrectly sending flow control information that reduces backpressure control when the available capacity of the first cache queue 11 changes but messages still exist in the second cache queue 14, thus preventing congestion from recurring. In other words, when the second cache queue 14 still has messages, new flow control information is prohibited from being sent to adjust backpressure control, maintaining full-cycle flow control. When the read requests sent from the first cache queue 11 to the second cache queue 14 can completely clear the messages in the second cache queue 14, new flow control information can be sent based on the state of the first cache queue 11.

[0096] If a new message is received at this time, the message can be written to the tail of the second buffer queue 14.

[0097] When the messages in the second cache queue 14 are cleared, or when the number of reads sent from the first cache queue 11 to the second cache queue 14 is greater than or equal to the number of remaining messages in the second cache queue 14, if a new message is received at this time, and if the capacity of the new message plus the remaining space of the first cache queue 11 equals the capacity of the first cache queue 11, it means that the new message will fill the first cache queue 11, then the new message is written to the second cache queue 14; if the capacity of the new message plus the remaining space of the first cache queue 11 is less than the capacity of the first cache queue 11, it means that the new message will not fill the first cache queue 11, then the new message is written to the first cache queue 11 to avoid data overflow and loss.

[0098] The chip control method provided in the above embodiments prioritizes writing data from the second cache queue to the tail of the queue when there is space in the first cache queue. This avoids the erroneous transmission of flow control information that reduces backpressure control when there are still messages in the second cache queue due to changes in the available capacity of the first cache queue, thus preventing congestion from recurring. Based on the remaining number of requests and the remaining capacity in the first cache queue, it determines whether to store new messages in the first or second cache queue to avoid data overflow and loss.

[0099] Based on the chip control method provided in the above embodiments, this application also provides a chip, which includes a flow control module, the flow control module including as follows: Figure 4 The flow control information sending unit and flow control information receiving unit shown are used to execute the chip control method provided in the above embodiments.

[0100] In this embodiment, the chip can be a main computing chip or a slave expansion I / O chip, and each chip can be equipped with a flow control module. The slave expansion I / O chip can be interconnected with the main computing chip via an interconnect channel with high bandwidth, and has multiple storage units to expand the bandwidth and storage capacity of the entire chip system formed with the main computing chip; the main computing chip is equipped with multiple computing cores for parallel data processing.

[0101] The interconnect channels between the main computing chip and the slave expansion I / O chip can be divided into Master ports and Slave ports according to the master-slave relationship. When the main computing chip or the slave expansion I / O chip acts as the initiator, if it is performing a write operation on its own internal storage unit, no backpressure is required. However, if it is performing a write operation on an interconnected device (such as other GP / GPU chips, CPUs, etc.), the interconnected device can perform backpressure when congestion occurs. Therefore, a flow control information receiving unit can be set up on the Master port of the interconnect interface for flow control; when performing read operations on internal storage units or external devices through the Master port, flow control information receiving unit is used for flow control.

[0102] When the interconnect interface of the main computing chip or the expansion I / O chip is used as a slave port, the interconnect device performs write operations through the slave port. The slave port is connected to a flow control information sending unit and a buffer unit. The buffer unit is used to cache data Date and request req. External devices perform read operations through the slave port and cache request req through the buffer unit. The flow control information sending unit monitors the used capacity of the buffer unit and is used to generate flow control messages.

[0103] The chip provided in the above embodiments, when receiving remote flow control information sent by a remote chip, selectively performs back pressure control on the data transmission request of the target data sender from multiple data senders, including the data transfer engine, according to the back pressure switch identifier of the data transfer engine, which can effectively prevent data overflow from occurring on the remote chip.

[0104] In one possible implementation, this application embodiment also provides a computing card, which may include multiple chips, and the multiple chips perform inter-chip backpressure control through a flow control module.

[0105] Specifically, the multiple chips include a main computing chip and at least one slave expansion I / O chip. The interconnection channel between the main computing chip and the slave expansion I / O chip communicates through a control network-on-chip (CNoC). If the first chip and the second chip are located on the same computing card, the flow control information sending unit of the first chip sends the first flow control information to the flow control information receiving unit of the second chip through the CNoC. That is, it performs hardware broadcasting instead of software broadcasting, thereby reducing the latency problem in transmitting the first flow control information.

[0106] If the first chip and the second chip are slave expansion I / O chips located in different computing cards, the first chip and the second chip are connected through a dedicated physical link to realize the communication connection between the two computing cards. The flow control information sending unit of the first chip sends the first flow control information to the flow control information sending unit of the second chip through the dedicated physical link. After receiving the first flow control information, the flow control information sending unit of the second chip broadcasts the first flow control information to the flow control information receiving units of each chip in the same computing card through CNoC.

[0107] During data transmission between the main computing chip and the slave expansion I / O chip, if data congestion occurs due to slow processing speed of the data receiver or excessively fast data transmission by the data sender, the flow control information sending unit of the flow control module of the data receiver generates local flow control information and broadcasts it to the flow control information receiving units of the flow control modules of all chips located on the same computing card. The flow control information receiving units of the flow control modules of all chips then apply back pressure to the data sent to the data receiver through their respective data sending ports to prevent the data congestion situation of the data receiver from worsening.

[0108] For example, the main computing chip sends data to the interconnect channel of the slave expansion I / O chip. The flow control information sending unit of the congested interconnect channel generates local flow control information based on the cache used capacity and sends it to the interconnect channel of the main computing chip and other slave expansion I / O chips. The flow control information receiving units of the interconnect channel of the main computing chip and other slave expansion I / O chips backpressure the data sent to the congested interconnect channel by their respective data sending ports.

[0109] The computing card provided in the above embodiments ensures, through the flow control module set on each chip, that all chips communicating with the target chip with slow message processing speed can perform backpressure control on the message to be sent in advance, thereby reducing the occurrence of data overflow in the target chip with slow message processing speed.

[0110] In one possible implementation, the computing system may include multiple computing cards, each located on the same PCB board, or the computing cards may be located on multiple PCB boards.

[0111] In this embodiment, multiple computing cards located on the same PCB board or different PCB boards can communicate with each other through a dedicated physical link between the expansion I / O chips on the computing cards.

[0112] In some embodiments, computing card A and computing card B are located on the same PCB board. Computing card B writes data to interconnect channel 1 of card A via interconnect channel 0. The flow control information sending unit of the Slave port of interconnect channel 1 of card A generates local flow control information and broadcasts it to various flow control information receiving units within card A. Interconnect channel 0 of card A and interconnect channel 0 of card B are connected via a dedicated physical link. The flow control information receiving unit of interconnect channel 0 of card A notifies the flow control information sending unit of interconnect channel 0 of card A to generate remote flow control information based on the local flow control information and forward the remote flow control information to the flow control information sending unit of interconnect channel 0 of card B. The flow control information sending unit of interconnect channel 0 of card B broadcasts the remote flow control information to various flow control information receiving units within card B. The flow control information sending unit of the chip connecting cards A and B also sends the remote flow control information to the flow control information receiving unit of its own chip for flow control of the chip's data transfer engine.

[0113] In other embodiments, Figure 7 An architecture diagram of a computing system provided in one embodiment of this application, such as... Figure 7As shown, computing cards A and B are located on the same PCB board, while card C is located on another PCB board. Card C is directly connected to card B. Card C reads and writes data to card A via card B. When card A experiences congestion, it generates local flow control information. The flow control information receiving unit of the chip in card A, which is connected to card B, notifies the flow control information sending unit of the chip in card A to forward remote flow control information to card B. After receiving the remote flow control information, card B performs internal backpressure and forwards the remote flow control information to card C. After receiving the remote flow control information, card C performs backpressure control on the messages sent from card C to card A.

[0114] In some embodiments, a host and at least one Peripheral Component Interconnect Express (PCIe) slot are provided on the server motherboard. Each PCIe slot can be used to connect a printed circuit board (PCB). Each PCB has at least one computing card, and each computing card can have one or more computing chips. In some embodiments, each computing card has a master computing chip and at least one slave expansion I / O chip. The first chip can be either the master computing chip or the slave expansion I / O chip, and they can be packaged together or separately. The master computing chip can include a GPGPU, a Direct Memory Access (DMA) controller, and on-chip memory, etc. Each slave expansion I / O chip can provide at least one interconnect channel (such as a PCIe channel). The master computing chip can interact with the slave expansion I / O chips through the interconnect channels, and can also interact with other master computing chips, CPUs, network cards, and other devices through the interconnect channels.

[0115] The computing system provided in the above embodiments ensures that all chips communicating with target chips with slow message processing speeds can perform backpressure control on the messages to be sent in advance through the flow control module set on each computing card chip, thereby reducing the occurrence of data overflow in target chips with slow message processing speeds.

[0116] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip control method, characterized in that, Applied to a first chip, the method includes: Receive flow control information, the flow control information including remote flow control information, the remote flow control information coming from a second chip located on a different computing card than the first chip; Parse the flow control information to obtain the rate-limiting address and backpressure rules; Based on the current limiting address, the backpressure rule, and the backpressure switch identifier of the data transfer engine of the first chip, backpressure control is selectively applied to the data transfer requests of the data transfer engine and other data transfer requests to the second chip. The step of selectively applying backpressure control to data transmission requests from the data transmission engine and other data transmission requests to the second chip, based on the current-limiting address, the backpressure rules, and the backpressure switch identifier of the data transmission engine of the first chip, includes: If the reverse pressure switch is identified as the first identifier, reverse pressure control is applied to the data transmission request sent from the first chip to the second chip according to the current limiting address and the reverse pressure rule; If the reverse pressure switch is identified as the second identifier, reverse pressure control is performed on the data transmission request sent from the first chip to the second chip and the data transmission request of the data transport engine according to the current limiting address and the reverse pressure rule.

2. The method as described in claim 1, characterized in that, The selective backpressure control of data transmission requests from the data transport engine and other data transmission requests to the second chip includes: If the rate-limiting address is a remote address, the data transmission request of the data transfer engine continues to be transmitted; if the rate-limiting address is a near-end address, the data transmission request of the data transfer engine is subject to backpressure control.

3. The method as described in claim 1, characterized in that, The backpressure control of data transmission requests from the data transport engine includes: Backpressure control is applied to the read data requests sent by the data transfer engine to the storage unit in the first chip and the write data requests sent to the second chip.

4. The method as described in claim 1, characterized in that, The first chip includes a data transfer channel for a data transfer engine sharing an AXI port, a data access channel for accessing local storage units, and a forwarding channel for forwarding access requests. The method further includes: The read requests of the data transport channel are suppressed, and the read requests of the data access channel and the forwarding channel are controlled to continue to be transmitted.

5. The method as described in claim 1, characterized in that, The method further includes: Based on the cache queue state of the first chip, second flow control information is selectively generated, and the second flow control information includes at least: the first congestion level corresponding to the cache queue state; The second flow control information is sent to at least one third chip that communicates with the first chip, so that the at least one third chip performs flow control on data transmission requests sent to the first chip according to the first congestion level.

6. The method as described in claim 5, characterized in that, The step of selectively generating second flow control information based on the cache queue state of the first chip includes: Based on the used capacity of the cache queue of the first chip and the first capacity change trend, the second flow control information is generated. The second flow control information includes the first congestion level and the first capacity change trend.

7. The method as described in claim 5, characterized in that, The cache queue includes a first cache queue and a second cache queue, wherein the first cache queue has a faster read speed than the second cache queue, and the method further includes: Once the used capacity of the first cache queue exceeds a preset capacity threshold, the message sent to the first chip will be cached in the second cache queue.

8. The method as described in claim 7, characterized in that, The method further includes: Process the messages in the first cache queue; When the first cache queue is empty and the second cache queue is not empty, the messages in the second cache queue are written into the first cache queue for processing in sequence; When the number of messages in the second cache queue is less than the preset number of messages, if a new message is received, the new message is determined to be stored in the first cache queue or the second cache queue based on the remaining number of requests and the remaining capacity in the first cache queue.

9. A chip, characterized in that, The chip includes a flow control module, which is used to perform the chip control method as described in any one of claims 1-8.

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