Failure sharing method and system for network equipment

Abstract

The invention relates to the technical field of network communication, and provides a failure sharing method and system for network equipment, and the method comprises the steps: distributing a VLAN label set for each port through employing an orthogonal multi-dimensional mapping algorithm based on the number of ports of each output group, constructing a global orthogonal mapping relation, and generating a static forwarding rule of a switching chip according to the global orthogonal mapping relation; the high-level processing chip carries out Hash calculation on the flow and prints a corresponding VLAN label, and the exchange chip carries out identification and copy forwarding according to a static forwarding rule; and when the port fails, the VLAN label set associated with the port is only forbidden at the advanced processing chip side, and the rule of the exchange chip is kept unchanged, so that the fast switching of the flow and the load balancing are realized. According to the method and the device, the problems of high switching delay and inconsistent hash of double chips in a traditional scheme are solved, and the service continuity of the convergence and shunting equipment in a failure scene is remarkably improved.

Description

Technical Field

[0001] This application relates to the field of network communication technology, specifically to a failure sharing method and system for network devices. Background Technology

[0002] Current network traffic splitter devices struggle to simultaneously achieve low switching latency (less time spent adjusting the output group results in less packet loss), accurate data traffic output (the same session request, i.e., source and destination IP addresses being identical, must be output to the same port), and load-balanced output (data traffic should be distributed as evenly as possible across output ports within the output group) during the replication and forwarding process between output groups. This is because most network traffic splitter devices use advanced processing chips for traffic parsing and switching chips for copying and forwarding the processed data traffic, maximizing the utilization of the advanced processing chip's bandwidth. However, this introduces a problem: during traffic replication and forwarding, the switching chip needs to cooperate with the advanced processing chip. This raises the question of whether the two chip hash algorithms (which extract packet features and calculate a hash value using a symmetric mathematical algorithm to determine which output port to use, not discussed further) can be kept consistent. Furthermore, how can the latency of failure sharing be guaranteed when configuring both the advanced processing chip and the switching chip? Therefore, based on the above two issues, the traditional solutions for copying output behavior across multiple output groups in current network splitters generally fall into the following categories: First, the advanced processing chip outputs a copy of the traffic, which is then copied and hashed by the switching chip. The switching chip switches the port states within the output group to ensure latency sharing during failures. However, since the hash calculation for non-copying outputs is handled by the advanced processing chip, while the forwarding for copied outputs is handled by the switching chip, inconsistencies in the hash calculation algorithm can arise, making it impossible to guarantee the accuracy of data traffic output. Furthermore, in orthogonal chassis card-type devices, this solution can lead to exceptionally complex business rules on the switching chip side due to cross-board output scenarios, even presenting situations where certain business scenarios are difficult to resolve. Second, the advanced processing chip outputs a copy of the traffic, calculates a hash value, and assigns a specific tag. The switching chip then identifies this specific tag and performs copying and forwarding. The number of tags is obtained by calculating the least common multiple of the number of ports in different copying output groups. Each tag is bound to a specific port in a different copying output group. When the switching chip identifies this tag, it copies the output to the port bound to that tag, and each bound port copies the same traffic output. When the port status in the replicated output group changes, the least common multiple needs to be recalculated, and the switching chip and advanced processing chip configurations need to be reissued to complete the failover function. This solution can guarantee same source and destination and load balancing, but it cannot guarantee low latency requirements. The time from issuing the switching chip configuration to its effect is very high, even reaching the second level when there are many rules. This is absolutely unacceptable for existing network service systems such as backbone networks and core networks. Summary of the Invention

[0003] To help solve the above-mentioned technical problems, this application provides a method and system for network device failure sharing.

[0004] Firstly, this application provides a method for failure sharing in network devices, employing the following technical solution: A failure sharing method for network devices is applied to an aggregation and distribution device including an advanced processing chip and a switching chip. The aggregation and distribution device is configured with at least two output groups, each output group including at least one output port. The method includes: S1: Based on the number of ports in each output group, an orthogonal multidimensional mapping algorithm is used to assign a set of packet labels to each port in each output group. Each packet label is uniquely mapped to a port in each output group, forming a set of global orthogonal mapping relationships. Based on the global orthogonal mapping relationships, static forwarding rules are generated and sent down to the switching chip. These rules instruct the switching chip to copy and forward traffic carrying packet labels to the set of ports mapped by the label in all output groups. S2: The advanced processing chip processes the input traffic and calculates the hash value. Based on the hash result, the corresponding packet label is marked on the traffic. The switching chip identifies and copies the tagged traffic according to the static forwarding rules. S3: When any output port fails, on the advanced processing chip side, the set of packet labels associated with the failed port in the global orthogonal mapping relationship is removed, and the static forwarding rules of the switching chip remain unchanged, so that subsequent input traffic is only mapped to the remaining packet labels, and the switching chip copies and forwards them to the normal ports of each output group based on the static forwarding rules.

[0005] S1 includes: The orthogonal multidimensional mapping algorithm specifically includes: The aggregation and splitting device has a total of n output groups, and the number of ports in the m-th output group is N. m , The total number T of required message tags is calculated as follows: Assign an n-dimensional coordinate (x1, x2, ..., xn) to each message tag. n ), where the m-th dimension coordinate x m The value range is from 1 to N. m , which represents the port number mapped to the m-th output group of the message label; Based on the preset starting number V0 and the n-dimensional coordinates, a unique message tag number is calculated using a mapping formula: Among them, W m Let be the weight of the m-th dimension, and The weight W of the rightmost dimension n =1.

[0006] S1 includes: Each output group G m Each port x m The number of allocated message tags S(G) m ,x m )for: That is, the product of the number of ports in all output groups except the output group to which the port belongs.

[0007] In step S3, the specific steps of removing the set of message tags associated with the failed port from the global orthogonal mapping relationship include: The failed port is determined to be in its output group G. f Port number x in f All coordinates satisfying the f-th dimension x f =x fThe message tags are removed such that in each of the remaining normal ports, an equal number of message tags originally mapped to the failed port are removed from the message tag set associated with that port. Specifically, this equal number means that for any output group G other than the output group to which the failed port belongs... y The number of packet tags removed from each normal port within the group is the total number of packet tags removed divided by the number of normal ports in the output group. .

[0008] The orthogonal multidimensional mapping algorithm is adaptable to any number of n output groups and any number of N ports within each output group. m And the combination of ports located in arbitrary physical slots, the n-dimensional coordinates (x1, x2, ..., x... n The physical meaning of ) is: a message tag corresponds to an n-tuple consisting of one port in each output group, and the n-tuple is used to define a replication forwarding path in the switching chip.

[0009] In S2, after the set of message tags associated with the failed port is removed, the remaining valid message tags are evenly distributed among all normal ports in each output group.

[0010] Also includes S4: When the failed port is detected to have recovered, the previously removed set of message tags associated with the recovered port is re-enabled on the advanced processing chip side. The advanced processing chip restores the re-enabled message tags for traffic allocation.

[0011] The ports in the output group are distributed in different physical slots, forming a cross-slot output group. In S2, the step of labeling traffic with corresponding message tags according to the hash result specifically includes: ensuring that session traffic with the same source IP address and destination IP address is labeled with the same message tag.

[0012] During the operation of the aggregation and distribution device, including in S3 and S4, the configuration content of the static forwarding rule in the switching chip remains unchanged. The configuration content includes at least the entries of the static forwarding rule and their corresponding forwarding actions.

[0013] Secondly, this application provides a network device failure sharing system, which adopts the following technical solution: A network device failure sharing system includes at least a network aggregation and distribution device, wherein the network aggregation and distribution device includes: an input interface, an advanced processing chip, a switching chip, and at least two output groups; The input interface is used to receive network traffic and send it to the advanced processing chip through the switching chip; The advanced processing chip, connected to the switching chip, is used to perform: The traffic from the switching chip is processed and subjected to deep packet analysis; Perform the tagging operations in S1 and S2 of the network device failure sharing method as described in any one of the first aspects, and all operations on the advanced processing chip side in S3; The switching chip is connected to the advanced processing chip and each of the output groups respectively, and is used for: Receive and store static forwarding rules issued by the application software. The application software generates static forwarding rules based on the user's configuration and sends them to the switching chip through software logic. Perform the identification and copy forwarding operations performed by the switching chip in S2 as described in the first aspect; Each of the output groups includes at least one output port for outputting traffic copied and forwarded by the switching chip; The advanced processing chip is one of the following: FPGA chip, network processor NP chip, DPDK-based smart network card chip, or multi-core CPU.

[0014] In summary, this application addresses the core pain points of traditional dual-chip collaborative hashing solutions, such as inconsistent hashing and high handover latency. It utilizes an advanced processing chip for traffic analysis and processing, calculating hash values ​​to ensure accurate output of data packets with the same source and destination. A switching chip assists in the processing and copying of the traffic, identifying traffic with specific tags for forwarding. Tag allocation is based on a multidimensional orthogonal mapping algorithm, with the advanced processing chip leading the entire process of packet tag allocation (typically VLAN or MPLS, primarily used for high-speed forwarding in Layer 2 / 3 networks to quickly match packet tags and directly forward them to the corresponding output port, reducing packet parsing and improving forwarding efficiency. In this paper, tags are mainly referred to as VLAN tags, hereinafter the same). This completely eliminates the need for configuration intervention from the switching chip in the failure-sharing process, solving the traffic output accuracy problem at its root and significantly reducing handover latency.

[0015] This application follows an algorithm design logic. First, the total number of VLAN tags is determined by multiplying the number of ports in each output group, ensuring a balanced distribution of VLAN tags across ports in the initial state. Then, each VLAN tag is bound to a unique (i,j,k) coordinate using N-dimensional (this application uses three dimensions as an example; the specific number of dimensions depends on the number of output groups) coordinate encoding, constructing an orthogonal mapping relationship between VLAN tags and individual ports in each output group. That is, one VLAN tag corresponds to only one port in each output group. Based on the weighted calculation rules of the product of the number of ports in all dimensions, the advanced processing chip converts the coordinates into unique VLAN tag numbers using a preset mapping formula, completing the precise binding of traffic and VLAN tags. At this point, the switching chip only needs to perform fixed forwarding based on the VLAN tags, without participating in hash calculations or complex rule processing. This mechanism avoids traffic deviations caused by inconsistent hashes between two chips, naturally satisfying the "same source, same destination" requirement.

[0016] When a port fails, thanks to the algorithm-based fixed orthogonal mapping relationship and numbering rules between VLAN tags and ports, only the VLAN tag set corresponding to the failed port needs to be adjusted on the advanced processing chip side to smoothly migrate it to a normal port in the same output group. No configuration changes to the switching chip are required throughout the process. The migration only requires updating the VLAN tag-port binding table inside the advanced processing chip, eliminating the need to recalculate tags or issue numerous rules, significantly reducing handover latency. Simultaneously, the algorithm ensures that the remaining VLAN tags remain evenly distributed across all output groups after migration, and that the VLAN tag number corresponding to the same session remains unchanged, balancing service continuity, traffic accuracy, and VLAN tag resource utilization, comprehensively addressing the pain points of traditional solutions. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall structure of this application in the context of telecommunications value-added services. Figure 2 A diagram illustrating traffic replication and forwarding after the mapping relationship for this application is generated; Figure 3 A diagram illustrating traffic replication and forwarding after the trigger failure of this application is shared; Figure 4 A flowchart is provided for the orthogonal multidimensional mapping algorithm of this application. Detailed Implementation

[0018] The present application will be further described below with reference to the accompanying drawings. The principles of the present application are very clear to those skilled in the art. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

[0019] The network device failure sharing method described in this application is led by an advanced processing chip, with the switching chip assisting in performing fixed forwarding. Specifically, it may include the following steps: S1: First, based on the number of ports in each output group, an orthogonal multidimensional mapping algorithm (described in detail below) is used to calculate and assign a set of packet tags (VLAN tags can be used in this embodiment) to each port in each output group. This algorithm ensures that each VLAN tag is uniquely mapped to a port in each output group, forming a set of global orthogonal mapping relationships. Subsequently, based on this mapping relationship, static forwarding rules are generated and sent to the switching chip. The rules explicitly instruct the switching chip that when traffic carrying a specific VLAN tag is detected, it should be copied and forwarded to the set of ports mapped to that tag in all output groups.

[0020] S2: During the service operation phase, the advanced processing chip performs deep packet inspection on the input traffic, calculates hash values, and tags each piece of traffic with the corresponding VLAN tag based on the hash result to ensure consistency between the tags of traffic within the same session. The tagged traffic is then sent to the switching chip. The switching chip, based on the issued static forwarding rules, identifies the VLAN tags in the traffic, performs a copy-forward operation, and replicates the traffic to multiple output ports specified by the rules.

[0021] S3: When any output port failure is detected, adjustments are made only on the advanced processing chip side. Specifically, all VLAN tags associated with the failed port in the global orthogonal mapping are marked as removed. During this process, the static forwarding rules of the switching chip remain unchanged. The advanced processing chip then stops assigning the removed VLAN tags to traffic. Therefore, subsequent traffic is guided only by the remaining valid VLAN tags and continues to be copied and forwarded to all normal ports through the unchanged static forwarding rules in the switching chip, thereby achieving rapid traffic switching and failure sharing. It should also be noted that the sequence numbers "S1" to "S4" in this application are only for referring to the steps and should not be construed as a restriction on the order of the steps.

[0022] Specifically, in this application's technical solution, an advanced processing chip parses and processes the raw input traffic, calculates a hash value for the processed output traffic, and simultaneously tags it with a specific message tag value. A switching chip then identifies the tags in the processed traffic and performs replication and forwarding. The number of tags is obtained by calculating the Cartesian product of the number of ports in different replication output groups. An orthogonal multidimensional mapping allocation algorithm ensures that each port in each output group occupies an even number of tags. When a port fails, the tags bound to that port are temporarily removed. Simultaneously, these temporarily removed tags allow other ports to remove the same number of tags, ensuring that the traffic after failure sharing is also output in a load-balanced manner. The table below shows a service configuration example; each output group contains cross-slot output ports, and the number of output ports in each output group is different.

[0023]

[0024] Based on the service configuration in Table 1, this application requires 2*3*4=24 VLAN tags. Assuming the VLAN tag values ​​are 2001-2024, the mapping relationship between VLAN tags and ports is allocated using the orthogonal multidimensional mapping algorithm as shown in Table 2 below:

[0025] When the state of port 1 of slot 1 in output group 1 is invalid, the mapping relationship is adjusted as follows:

[0026] When output group G f port x in f In case of failure, the failure handling mechanism is as follows: On the advanced processing chip side, determine the coordinates x of the failed port. f Then, for all coordinates satisfying the condition that the f-th dimension is equal to x... f The VLAN tag is marked as removed. That is, for group G, which is invalid. f In any other output group besides the one to which the failed port belongs, an equal number of tags originally mapped to the failed port will be removed from the VLAN tag set associated with each normal port within that group. y The number of packet tags removed from each normal port within the group is [number missing]. This ensures the uniformity of the impact.

[0027] After the above removal operation is completed, the remaining valid VLAN tags remain evenly distributed across all normal ports in each output group, thus ensuring load balancing of traffic output. Throughout the process, the advanced processing chip tags traffic based on the hash result, ensuring that session traffic with the same source IP and destination IP address is always tagged with the same VLAN tag. Even in the event of a port failure switchover, traffic within the same session is still guided by the same batch of valid VLAN tags, ensuring same source and destination. Furthermore, when users configure replication and forwarding behavior, the software generates static forwarding rules in the switching chip based on the configuration. The configuration content of the static forwarding rules in the switching chip, including entries and forwarding actions, remains unchanged throughout the entire device operation, including S3 failure switchover and S4 port recovery. All adjustments occur only in the tag allocation logic of the advanced processing chip to achieve ultra-low latency switching.

[0028] In an optional embodiment, the process is reversible when the failed port is detected to have recovered. On the advanced processing chip side, the previously removed set of VLAN tags associated with that port is re-enabled. The advanced processing chip resumes assigning these tags to traffic, and the system automatically returns to its initial load balancing state.

[0029] Specifically, as can be seen from the above, when a port in one output group fails, the set of VLAN tags temporarily removed is evenly eliminated for ports in other output groups. For example, each port in output group 2 temporarily removes 4 VLAN tags, and each port in output group 3 temporarily removes 3 VLAN tags. After this temporary removal, each replicated output group fully occupies 12 VLAN tag values ​​from 2013 to 2024, meaning each replicated output group can output a complete set of traffic, meeting the replication requirements of this application. Meanwhile, the 12 VLAN tag values ​​occupied by ports in each replication output group are also proportionally allocated. Each port in output group 2 occupies 4 VLAN tags, and each port in output group 3 occupies 3 VLAN tags. This means that a complete set of traffic in this output group can be evenly distributed across all ports in the output group, avoiding hash imbalance. Furthermore, since the switch only replicates VLAN-tagged traffic (e.g., a flow with VLAN tag = 2013 is replicated to port 2 in slot 2, port 3 in slot 1, and port 6 in slot 1, and so on), and the switching chip only performs replication without hashing, the hash calculation is handled by the advanced processing chip. Therefore, it also ensures that traffic originates from the same source and is destined for the same destination. A traffic forwarding diagram is shown below. Figure 2 As shown.

[0030] according to Figure 2 As shown by the middle arrow, traffic with VLAN tag = 2001 is copied and output to port 1, port 3, and port 6 of slot 1; traffic with VLAN tag = 2020 is copied and output to port 2, port 2, port 4, and port 9 of slot 2. Traffic with other VLAN tags follows the same logic. As can be seen from the diagram, the switching chip does not require complex deep packet analysis logic; it only needs to match the VLAN tags assigned by the advanced processing chip to complete high-speed copying and forwarding. Furthermore, these rules are fully deployed during the initial configuration phase. When ports fail later, the software automatically adjusts the configuration without needing to redeploy the rules; it only needs to adjust the tag values ​​assigned by the advanced processing chip. The advanced processing chip no longer marks the tag values ​​mapped to failed ports, so the switching chip is unaware of this and only needs to forward according to the established matching rules. When port 1 of slot 1 fails, the following... Figure 3 The corresponding VLAN tag = 2001 will not cause traffic to be copied and forwarded. Figure 3 As shown by the dashed line.

[0031] If, based on this, slot 1 port 3 in output group 2 also becomes invalid, the mapping relationship is adjusted as follows:

[0032] It can be seen that when two ports fail, the set of VLAN tags temporarily removed is still uniformly eliminated for other output group ports. For example, each port in output group 1 removes 4 VLAN tags, and each port in output group 3 removes 1 VLAN tag. After this temporary removal, each replication output group fully occupies 8 VLAN tag values ​​from 2017 to 2024. At the same time, the ports in each replication output group also occupy 8 VLAN tag values ​​proportionally. Each port in output group 1 occupies 8 VLAN tags, each port in output group 2 occupies 4 VLAN tags, and each port in output group 3 occupies 2 VLAN tags. This means that a complete set of traffic in this output group can be evenly distributed across each port in the output group without hash imbalance. In addition, since the switch is only responsible for replicating and outputting traffic with VLAN tags, for example, a flow with VLAN tag = 2017 is replicated to port 2 in slot 2, port 4 in slot 2, and port 6 in slot 1 for output, and so on, the switching chip only performs replication and does not perform hash output. The hash calculation is completed by the advanced processing chip, so it can also ensure that the traffic is output from the same source and destination.

[0033] When the state of port 1 in slot 1 of output group 1 switches normally, the mapping relationship is adjusted as follows:

[0034] This application refers to this tag allocation algorithm as the multidimensional orthogonal mapping algorithm. This algorithm can adapt to any number of output groups, any number of ports within the output group, and any combination of ports in slots. At the same time, it ensures the balance of remaining VLAN tags when a port fails and saves VLAN tag resources to the greatest extent. Figure 4 A flowchart is provided for the orthogonal multidimensional mapping algorithm of this application. The algorithm design principle is as follows: 1. Calculate the required number of VLAN tags. Total VLAN tag count: is the product of the number of ports in each output group (ensuring that each port is initially allocated an equal number of VLAN tags).

[0035] The total number T of required VLAN tags is calculated as follows: Assign an n-dimensional coordinate (x1, x2, ..., xn) to each VLAN tag. n ), where the m-th dimension coordinate x m The value range is from 1 to N. m, which represents the port number mapped to the m-th output group by the VLAN tag.

[0036] In the example above, n=3, N1=2, N2=3, and N3=4.

[0037] The total number of VLAN tags is T = 2 * 3 * 4 = 24, and the VLAN tag value range is 2001-2024.

[0038] 2. Calculate the weight values ​​for each dimension. The weight W for the m-th dimension. m =The product of the number of output group ports to the right of this dimension (the weight of the rightmost dimension is fixed at 1 to ensure a unique mapping between the coordinates and the VLAN tag number): .

[0039] When m = n (the rightmost dimension), W n =1 (no right-hand dimension, product is 1).

[0040] In the example above, n=3, N1=2, N2=3, and N3=4.

[0041] W1=N2*N3=3*4=12, W2=N3=4, W3=1.

[0042] 3. Mapping formula between coordinates and tags. The unique VLAN tag number is calculated using n-dimensional coordinates, logically as "starting number + sum of offsets in each dimension": .

[0043] In the example above, n=3 and V0=2001.

[0044] Coordinates (1,1,1): V=2001+(1-1)*12+(1-1)*4+(1-1)*1=2001.

[0045] The coordinates (1,1,1) represent the coordinate mapping formed by the first port of the first output group, the first port of the second output group, and the first port of the third output group.

[0046] Coordinates (2,3,4): V=2001+(2-1)*12+(3-1)*4+(4-1)*1=2024.

[0047] The coordinates (2,3,4) represent the coordinate mapping formed by the second port of the first output group, the third port of the second output group, and the fourth port of the third output group.

[0048] 4. Formula for the size of the port VLAN tag set.

[0049] Output group G mMiddle Port X m Number of VLAN tags = divided by G m The product of the number of ports in all external output groups (initial allocation balanced): .

[0050] In the example above, n=3, N1=2, N2=3, and N3=4.

[0051] S(G1, x1) = N2 * N3 = 3 * 4 = 12, (12 VLAN tags are assigned to each port of output group 1). S(G2, x2) = N1 * N2 = 2 * 4 = 8, (Each port in output group 2 is assigned 8 VLAN tags). S(G3, x3) = N1 * N2 = 2 * 3 = 6, (6 VLAN tags are assigned to each port of output group 3).

[0052] After the VLAN tags are assigned using the multidimensional orthogonal mapping algorithm, the coordinate mapping tables generated in the above example are shown in Tables 6 and 7 below:

[0053]

[0054] After allocation by the orthogonal multidimensional mapping allocation algorithm, once a port status changes and triggers a service failure sharing scenario, it is not necessary to issue the switching chip configuration. Only the output VLAN table entry of the advanced processing chip needs to be reconfigured to complete the failure sharing function.

[0055] This application also proposes a network device failure sharing system, which includes at least a network aggregation and distribution device, the network aggregation and distribution device including: an input interface, an advanced processing chip, a switching chip, and at least two output groups; The input interface is used to receive network traffic and send it to the advanced processing chip through the switching chip; The advanced processing chip, connected to the switching chip, is used to perform: The traffic from the switching chip is processed and subjected to deep packet analysis; Perform the tagging operations in S1 and S2 of the above-mentioned network device failure sharing method, as well as all operations on the advanced processing chip side in S3. The switching chip is connected to the advanced processing chip and each of the output groups respectively, and is used for: Receive and store static forwarding rules issued by the application software. The application software generates static forwarding rules based on the user's configuration and sends them to the switching chip through software logic. Perform the identification and copy forwarding operations performed by the switching chip in S2 above; Each of the output groups includes at least one output port for outputting traffic copied and forwarded by the switching chip; The advanced processing chip is one of the following: FPGA chip, network processor NP chip, DPDK-based smart network card chip, or multi-core CPU.

[0056] In summary, combining Figure 1 In telecommunications value-added service scenarios, aggregation and distribution equipment (used for communication services, its function is to aggregate large amounts of network data to one port, and then distribute the required data to different output ports according to message characteristics such as destination address or protocol type. It is the core hub of the network visualization and monitoring system and is widely used in network operation and maintenance, security monitoring, compliance auditing and business analysis scenarios) is usually composed of switching chips (which complete the reception, forwarding, filtering and management of network data packets at high speed and low latency) and advanced processing chips (usually programmable, supporting customized complex business scenarios and deep message parsing). The advanced chips include FPGA (Field Programmable Gate Array) chips, NP (Network Processing) chips, smart network card chips based on the DPDK (Data Plane Development Kit) platform, or multi-core high-performance CPUs with general architecture. In the following content of this article, FPGA chips will be used to refer to advanced processing chips, and related technical characteristics and application solutions will be based on this setting. After the chip finishes processing the data traffic, it will generally forward the data traffic to the output port (usually an Ethernet optical port, which supports optical module access. Different devices can complete high-speed transmission of data traffic across devices after connecting through optical modules). Since the output ports of splitter devices are typically optical modules connected to backend devices, hardware issues such as optical module or backend device failures can arise. If the ports in the splitter's output group are not adjusted, significant packet loss will occur. To address this, a failover function has emerged. The failover function of a splitter automatically distributes traffic to other working ports in the output group if a port fails, preventing prolonged and excessive packet loss due to the failed port. Therefore, selecting a failover algorithm with low switching latency (lower latency means less packet loss due to the failed port) is crucial. The failover method and system based on splitter devices designed in this application effectively solve the aforementioned problems.

[0057] To further illustrate the inventiveness of this application, the following is stated: Compared to existing technologies, this application constructs the correspondence between VLAN tags and output ports through an orthogonal multidimensional mapping algorithm. When distributing service configurations, the mapping rules are assigned to the switching chip in one go. Subsequently, when failure sharing is triggered, the switching chip configuration does not need to be adjusted; only the configuration of the advanced chip needs to be adjusted to achieve the switching purpose. This significantly reduces the latency caused by configuration switching. Generally, reconfiguring the output table entries of the advanced processing chip in a traffic splitter typically takes about 1.5ms. Therefore, the theoretical average latency of failure sharing in this solution is no higher than 1.5ms.

[0058]

[0059] Traditional least common multiple (LCM) schemes require reallocating the number of rules on the switching chip each time a failover occurs. This means the time consumed increases with the number of rules. Taking a domestically produced 8180 switching chip as an example, theoretical latency calculations for the scenario in the table above show that approximately 12 rules need to be redistributed each failover, resulting in a total latency of approximately 12 * 2 = 24 ms for the switching chip. Advanced processing chips only need to refresh the output table entries once, taking approximately 1.5 ms. The total latency is approximately 24 + 1.5 = 25.5 ms.

[0060] When this solution performs a switching operation, it does not require reallocating the number of rules for the switching chip; it only needs to refresh the output entries of the advanced processing chip, meaning the total latency is approximately 1.5ms.

[0061]

[0062] After actual development and application, the test data of this solution basically matches the theoretical latency and is more than 50% less than the latency required by China Mobile's communication standards. Compared with traditional solutions, the latency is significantly reduced, which can cope with scenarios such as backbone networks that are very sensitive to latency and packet loss.

[0063] Additionally, for any difficult-to-understand terms used in this article, please refer to: China Mobile aggregation and distribution equipment technical specifications; YD / T 4142-2022 Test Methods for Network Aggregation and Distribution Equipment.

[0064] The technical scope of this application is not limited to the contents of the above specification. Those skilled in the art can make various modifications and variations to the above embodiments without departing from the technical concept of this application, and all such modifications and variations should fall within the scope of this application.

Claims

1. A failure sharing method for network devices, applied to a convergence and splitting device including an advanced processing chip and a switching chip, the convergence and splitting device being configured with at least two output groups, each output group including at least one output port, characterized in that, The method includes: S1: Based on the number of ports in each output group, an orthogonal multidimensional mapping algorithm is used to assign a set of packet labels to each port in each output group. Each packet label is uniquely mapped to a port in each output group, forming a set of global orthogonal mapping relationships. Based on the global orthogonal mapping relationships, static forwarding rules are generated and sent down to the switching chip. These rules instruct the switching chip to copy and forward traffic carrying packet labels to the set of ports mapped by the label in all output groups. S2: The advanced processing chip processes the input traffic and calculates the hash value. Based on the hash result, the corresponding packet label is marked on the traffic. The switching chip identifies and copies the tagged traffic according to the static forwarding rules. S3: When any output port fails, on the advanced processing chip side, the set of packet labels associated with the failed port in the global orthogonal mapping relationship is removed. The static forwarding rules of the switching chip remain unchanged, so that subsequent input traffic is only mapped to the remaining packet labels, and the switching chip copies and forwards them to the normal ports of each output group based on the static forwarding rules.

2. The method according to claim 1, characterized in that, S1 includes: The orthogonal multidimensional mapping algorithm specifically includes: The aggregation and splitting device has a total of n output groups, and the number of ports in the m-th output group is N. m , The total number T of required message tags is calculated as follows: Assign an n-dimensional coordinate (x1, x2, ..., xn) to each message tag. n ), where the m-th dimension coordinate x m The value range is from 1 to N. m , which represents the port number mapped to the m-th output group of the message label; Based on the preset starting number V0 and the n-dimensional coordinates, a unique message tag number is calculated using a mapping formula: Among them, W m Let be the weight of the m-th dimension, and The weight W of the rightmost dimension n =1.

3. The method according to claim 2, characterized in that, S1 includes: Each output group G m Each port x m The number of allocated message tags S(G) m ,x m )for: That is, the product of the number of ports in all output groups except the output group to which the port belongs.

4. The method according to claim 2, characterized in that, In step S3, the specific steps of removing the set of message tags associated with the failed port from the global orthogonal mapping relationship include: The failed port is determined to be in its output group G. f Port number x in f All coordinates satisfying the f-th dimension x f =x f The message tags are removed such that in each of the remaining normal ports, an equal number of message tags originally mapped to the failed port are removed from the message tag set associated with that port. Specifically, this equal number means that for any output group G other than the output group to which the failed port belongs... y The number of packet tags removed from each normal port within the group is the total number of packet tags removed divided by the number of normal ports in the output group. .

5. The method according to claim 2, characterized in that, The orthogonal multidimensional mapping algorithm is adaptable to any number of n output groups and any number of N ports within each output group. m And the combination of ports located in arbitrary physical slots, the n-dimensional coordinates (x1, x2, ..., x... n The physical meaning of ) is: a message tag corresponds to an n-tuple consisting of one port in each output group, and the n-tuple is used to define a replication forwarding path in the switching chip.

6. The method according to claim 4, characterized in that, In S2, after the set of message tags associated with the failed port is removed, the remaining valid message tags are evenly distributed among all normal ports in each output group.

7. The method according to claim 4, characterized in that, Also includes S4: When the failed port is detected to have recovered, the previously removed set of message tags associated with the recovered port is re-enabled on the advanced processing chip side. The advanced processing chip restores the re-enabled message tags for traffic allocation.

8. The method according to claim 1, characterized in that, The ports in the output group are distributed in different physical slots, forming a cross-slot output group. In S2, the step of labeling traffic with corresponding message tags according to the hash result specifically includes: ensuring that session traffic with the same source IP address and destination IP address is labeled with the same message tag.

9. The method according to claim 1, characterized in that, During the operation of the aggregation and distribution device, including in S3 and S4, the configuration content of the static forwarding rule in the switching chip remains unchanged. The configuration content includes at least the entries of the static forwarding rule and their corresponding forwarding actions.

10. A network device failure sharing system, comprising at least a network aggregation and distribution device, characterized in that, Network aggregation and distribution equipment includes: input interfaces, advanced processing chips, switching chips, and at least two output groups; The input interface is used to receive network traffic and send it to the advanced processing chip through the switching chip; The advanced processing chip, connected to the switching chip, is used to perform: The traffic from the switching chip is processed and subjected to deep packet analysis; Perform the tagging operations in S1 and S2 of the network device failure sharing method as described in any one of claims 1 to 9, and all operations on the advanced processing chip side in S3; The switching chip is connected to the advanced processing chip and each of the output groups respectively, and is used for: Receive and store static forwarding rules issued by the application software. The application software generates static forwarding rules based on the user's configuration and sends them to the switching chip through software logic. Perform the identification and copy forwarding operation performed by the switching chip in S2 as described in claim 1; Each of the output groups includes at least one output port for outputting traffic copied and forwarded by the switching chip; The advanced processing chip is one of the following: FPGA chip, network processor NP chip, DPDK-based smart network card chip, or multi-core CPU.

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