LED driver circuit and LED driver device
By introducing a pulse signal generation circuit and a reset circuit into the LED driver circuit, the rising edges of the PWM dimming signal and the clock signal are synchronized, thus solving the LED flickering problem caused by the randomness of the PWM dimming signal and achieving stable adjustment of LED brightness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LEN TECH LTD
- Filing Date
- 2026-04-21
- Publication Date
- 2026-07-17
AI Technical Summary
In DC-to-DC constant current LED driver circuits, the random flickering phenomenon caused by the independence of the PWM dimming signal and the clock signal is difficult to avoid effectively.
By introducing a pulse signal generation circuit and a reset circuit into the LED driver circuit, the rising edge of the PWM dimming signal is detected to generate a trigger signal, and the clock signal generation circuit is reset, so that the rising edge of the clock signal is synchronized with the rising edge of the PWM dimming signal, thus avoiding the influence of randomness.
This effectively avoids LED flickering and ensures the stability and consistency of LED brightness adjustment.
Smart Images
Figure CN122093978B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of LED driving technology, and in particular to an LED driving circuit and an LED driving device. Background Technology
[0002] In DC-DC constant current LED driver circuits, pulse width modulation (PWM) dimming signals are typically used to dim the LEDs. The brightness of the LED is adjusted by turning the current flowing through it on and off.
[0003] To prevent electromagnetic interference (EMI), fixed-frequency DC-DC converters are typically used in LED driver circuits. A clock signal is generated by a circuit that outputs a clock signal at a fixed frequency to control the operation of the DC-DC converter. When the user dims the LED, a corresponding dimming PWM signal is generated.
[0004] The dimming PWM signal and the clock signal are two independent signals, and the occurrence time of the dimming PWM signal is random. When the duty cycle of the dimming PWM signal is small, or when high-frequency dimming operations are performed, the randomness of the dimming PWM signal can cause the LED to flicker noticeably. Summary of the Invention
[0005] The purpose of this invention is at least to provide an LED driving circuit and an LED driving device that can effectively avoid the influence of the randomness of PWM dimming signals.
[0006] In a first aspect, the present invention provides an LED driving circuit, comprising: a pulse signal generating circuit, a reset circuit, and a clock signal generating circuit, wherein: the pulse signal generating circuit is coupled to the reset circuit, its input terminal receives a PWM dimming signal, and in response to the rising edge of the PWM dimming signal, generates a trigger signal and outputs it to the reset circuit; the reset circuit is coupled to the clock signal generating circuit of the LED driving circuit, and in response to receiving the trigger signal, outputs a reset signal to the clock signal generating circuit; the clock signal generating circuit, in response to receiving the reset signal, resets the output clock signal, and the first rising edge of the reset clock signal is synchronized with the rising edge of the PWM dimming signal.
[0007] When the rising edge of the PWM dimming signal is detected, the pulse signal generation circuit generates a trigger signal and outputs it to the reset circuit. The reset circuit receives the trigger signal, generates a reset signal, and outputs it to the clock signal generation circuit. The clock signal generation circuit resets the output clock signal, ensuring that the first rising edge of the reset clock signal is synchronized with the rising edge of the PWM dimming signal. This achieves synchronization between the rising edge of the PWM dimming signal and the rising edge of the clock signal generated by the clock signal generation circuit, avoiding the influence of randomness.
[0008] Optionally, the clock signal generation circuit includes: a current source, a capacitor, a first switching unit, a comparator, a delay circuit, and an RS flip-flop, wherein: the first terminal of the current source receives a power supply voltage, and the second terminal of the current source is coupled to the positive input terminal of the comparator, the first terminal of the first switching unit, and the first terminal of the capacitor; the inverting input terminal of the comparator receives a reference voltage, and the output terminal of the comparator is coupled to the S terminal of the RS flip-flop; the Q terminal of the RS flip-flop is coupled to the input terminal of the delay circuit, and the S terminal of the RS flip-flop is coupled to the output terminal of the delay circuit; the control terminal of the first switching unit is coupled to the Q terminal of the RS flip-flop, and the second terminal of the first switching unit is grounded; the second terminal of the capacitor is grounded.
[0009] Optionally, the first switching unit includes a first NMOS transistor; the drain of the first NMOS transistor is coupled to the second terminal of the current source, the gate of the first NMOS transistor is coupled to the Q terminal of the RS flip-flop, and the source of the first NMOS transistor is grounded.
[0010] Optionally, the reset circuit includes a second switching unit; the control terminal of the second switching unit is coupled to the output terminal of the pulse signal generating circuit, the first terminal of the second switching unit is coupled to the second terminal of the current source, and the second terminal of the second switching unit is grounded.
[0011] Optionally, the second switching unit includes a second NMOS transistor; the drain of the second NMOS transistor is coupled to the second terminal of the current source, the gate of the second NMOS transistor is coupled to the output terminal of the pulse signal generation circuit, and the source of the second NMOS transistor is grounded.
[0012] Optionally, the LED driving circuit further includes: an OR gate circuit, whose first input terminal is coupled to the output terminal of the pulse signal generating circuit, whose second input terminal is coupled to the output terminal of the clock signal generating circuit, and whose output terminal outputs a reset clock signal.
[0013] Secondly, the present invention provides an LED driving device, including a DC-DC converter and an LED driving circuit as described above, wherein the input terminal of the DC-DC converter is coupled to the output terminal of the LED driving circuit. Attached Figure Description
[0014] Figure 1 This is a waveform diagram of an existing LED driver circuit; Figure 2 This is a schematic diagram of the structure of an LED driving circuit according to an embodiment of the present invention; Figure 3 This is a waveform diagram of an LED driving circuit according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a pulse signal generation circuit in an embodiment of the present invention; Figure 5 This is a schematic diagram of another pulse signal generation circuit in an embodiment of the present invention. Detailed Implementation
[0015] In practical applications, since the PWM dimming signal is generated based on the user's input dimming operation, its occurrence time is random. When using a fixed-frequency DC-DC converter, a fixed-frequency clock signal generation circuit outputs a fixed-frequency clock signal to control the converter's operating state. Therefore, the time difference between the rising edge of the PWM dimming signal and the rising edge of the clock signal is also random.
[0016] Reference Figure 1 A waveform diagram of an existing LED driver circuit is given. For example... Figure 1 As shown, there is a time difference Tdelay between the rising edge of the PWM dimming signal and the rising edge of the clock signal, and the time difference Tdelay is random. The number of pulses output by the gate signal of the power transistor in the DC-DC converter is also random, which in turn causes the current of the LED to also be random, resulting in obvious flickering of the LED.
[0017] In this embodiment of the invention, when the rising edge of the PWM dimming signal is detected, the pulse signal generation circuit generates a trigger signal and outputs it to the reset circuit. The reset circuit receives the trigger signal, generates a reset signal, and outputs it to the clock signal generation circuit. The clock signal generation circuit resets the output clock signal, ensuring that the first rising edge of the reset clock signal is synchronized with the rising edge of the PWM dimming signal. This achieves synchronization between the rising edge of the PWM dimming signal and the rising edge of the clock signal generated by the clock signal generation circuit, avoiding the influence of randomness and effectively preventing LED flickering caused by randomness.
[0018] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0019] This invention provides an LED driving circuit, referring to... Figure 2 .
[0020] In this embodiment of the invention, the LED driving circuit includes: a pulse signal generating circuit 10, a reset circuit 20, and a clock signal generating circuit 30.
[0021] In a specific implementation, the pulse signal generation circuit 10 can be electrically connected to the reset circuit 20. The input terminal of the pulse signal generation circuit 10 can receive a PWM dimming signal, and the output terminal of the pulse signal generation circuit 10 is coupled to the reset circuit 20. When the pulse signal generation circuit 10 detects the rising edge of the PWM dimming signal, it can generate a trigger signal and output it to the reset circuit 20.
[0022] The reset circuit 20 can also be electrically connected to the clock signal generation circuit 30. When the reset circuit 20 receives a trigger signal, it can output a reset signal to the clock signal generation circuit 30.
[0023] After receiving the reset signal, the clock signal generation circuit 30 resets the output clock signal. The first rising edge of the reset clock signal is synchronized with the rising edge of the PWM dimming signal.
[0024] As can be seen, when the rising edge of the PWM dimming signal is received, the clock signal output by the clock signal generation circuit 30 is reset, so that the first rising edge of the reset clock signal is synchronized with the rising edge of the PWM dimming signal. This achieves synchronization between the rising edge of the PWM dimming signal and the rising edge of the clock signal generated by the clock signal generation circuit 30, avoiding the influence of randomness.
[0025] In practice, the aforementioned PWM dimming signal can be generated when a user performs a dimming operation. Upon detecting a dimming operation by the user, a corresponding PWM dimming signal is generated.
[0026] Specifically, when there is a need for dimming, users can perform dimming operations by rotating the dimming knob, selecting the brightness value, etc.
[0027] In specific implementation, the specific circuit structure of the clock signal generation circuit 30 described above can adopt the clock signal generation circuit 30 described in the prior art.
[0028] In some embodiments, the clock signal generation circuit 30 may include: a current source I, a capacitor C, a first switching unit, a comparator COMP, a delay circuit, and an RS flip-flop, wherein: The first terminal of current source I is input to the power supply voltage VDD, and the second terminal of current source I is coupled to the first terminal of capacitor C, the first terminal of the first switching unit, and the positive input terminal of comparator COMP.
[0029] The inverting input of comparator COMP can accept a reference voltage VREF, and its output is coupled to the source (S) terminal of an RS flip-flop. Comparator COMP compares the input voltage at its non-inverting input with the input voltage at its inverting input and outputs the comparison result to the source (S) terminal of the RS flip-flop.
[0030] The Q terminal of the RS flip-flop is coupled to the input terminal of the delay circuit, and the S terminal of the RS flip-flop is coupled to the output terminal of the delay circuit.
[0031] The control terminal of the first switching unit is coupled to the Q terminal of the RS flip-flop, and the second terminal of the first switching unit is grounded. The second terminal of capacitor C is also grounded.
[0032] In a specific implementation, the first switching unit mentioned above can be a first NMOS transistor MN1; the drain of the first NMOS transistor MN1 is coupled to the second terminal of the current source I, the gate of the first NMOS transistor MN1 is coupled to the Q terminal of the RS flip-flop, and the source of the first NMOS transistor MN1 is grounded.
[0033] In a specific implementation, the reset circuit 20 may include a second switching unit. The control terminal of the second switching unit may be coupled to the output terminal of the pulse signal generating circuit 10, the first terminal of the second switching unit is coupled to the second terminal of the current source I, and the second terminal of the second switching unit is grounded.
[0034] In some embodiments, the second switching unit may include a second NMOS transistor MN2. Specifically, the drain of the second NMOS transistor MN2 is coupled to the second terminal of the current source I, the gate of the second NMOS transistor MN2 is coupled to the output terminal of the pulse signal generation circuit 10, and the source of the second NMOS transistor MN2 is grounded.
[0035] When the pulse signal generation circuit 10 outputs a high-level trigger signal, the second NMOS transistor MN2 is turned on, thereby resetting the clock signal generation circuit 30.
[0036] In a specific implementation, the LED driver circuit may also include an OR gate circuit. The first input terminal of the OR gate circuit is coupled to the output terminal of the pulse signal generation circuit 10, the second input terminal of the OR gate circuit is coupled to the output terminal of the clock signal generation circuit 30, and the output terminal of the OR gate circuit outputs the reset clock signal CLK.
[0037] By setting an OR gate, even if the clock signal output by the clock signal generation circuit 30 happens to be at a high level, it will not affect the level of the reset clock signal CLK.
[0038] Reference Figure 3 The present invention provides a waveform diagram of an LED driving circuit according to an embodiment of the present invention.
[0039] like Figure 3 As shown, at the rising edge of the PWM dimming signal, since the clock signal generation circuit 30 is reset, the rising edge of the clock signal generated after the reset is synchronized with the rising edge of the PWM dimming signal. The rising edge of the PWM dimming signal and the rising edge of the clock signal can be regarded as having no time difference. The number of pulses output by the gate signal of the power transistor in the DC-DC converter is fixed, so the flickering phenomenon of the LED can be effectively avoided.
[0040] Reference Figure 4 A schematic diagram of a pulse signal generation circuit according to an embodiment of the present invention is provided.
[0041] like Figure 4 As shown, the pulse signal generation circuit may include: a first resistor R1, an inverter I1, an AND gate circuit I2, and a capacitor C2, wherein: The first terminal of the first resistor R1 is input to the PWM dimming signal and is coupled to the first input terminal of the AND gate I2; the second terminal of the first resistor R1 is coupled to the first terminal of the capacitor C2 and the input terminal of the inverter I1. The second terminal of capacitor C2 is grounded; the output terminal of inverter I1 is coupled to the second input terminal of AND gate I2; the output terminal of AND gate I2 outputs a trigger signal.
[0042] Reference Figure 5 The present invention provides a schematic diagram of another pulse signal generation circuit in an embodiment of the present invention.
[0043] like Figure 5 As shown, the pulse signal generation circuit may include: a second resistor R2, an inverter I3, an inverter I4, an inverter I5, a capacitor C3, and a NOR gate I6, wherein: The first terminal of the second resistor R2 is input to the PWM dimming signal and is coupled to the input terminal of the inverter I3; the second terminal of the second resistor R2 is coupled to the first terminal of the capacitor C3 and the input terminal of the inverter I4.
[0044] The second terminal of capacitor C3 is grounded. The output of inverter I3 is coupled to the first input of NOR gate I6, the output of inverter I4 is coupled to the input of inverter I5, and the output of inverter I5 is coupled to the second input of NOR gate I6. The output of NOR gate I6 outputs a trigger signal.
[0045] It is understandable that the above Figure 4 and Figure 5 Only two different pulse signal generation circuits are provided. In practical applications, the circuit structure of the pulse signal generation circuit is not limited to those described above. Figure 4 and Figure 5 The circuit structure provided herein. Any circuit that can output a trigger signal upon receiving a PWM dimming signal can be used as the pulse signal generation circuit described in this invention.
[0046] This invention also provides an LED driving device, including a DC-DC converter and the LED driving circuit provided in any of the above embodiments. Specifically, the input terminal of the DC-DC converter is coupled to the output terminal of the LED driving circuit.
[0047] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. An LED driving circuit, characterized in that, include: The circuit includes a pulse signal generation circuit, a reset circuit, a clock signal generation circuit, and an OR gate circuit, among which: The pulse signal generating circuit is coupled to the reset circuit. Its input terminal receives a PWM dimming signal, and in response to the rising edge of the PWM dimming signal, it generates a trigger signal and outputs it to the reset circuit. The reset circuit is coupled to the clock signal generation circuit of the LED driver circuit, and outputs a reset signal to the clock signal generation circuit in response to receiving the trigger signal. The reset circuit includes a second switching unit, the control terminal of the second switching unit is coupled to the output terminal of the pulse signal generation circuit, the first terminal of the second switching unit is coupled to the second terminal of the current source in the clock signal generation circuit, and the second terminal of the second switching unit is grounded. The control terminal of the second switching unit is turned on after receiving the reset signal. The clock signal generation circuit, in response to receiving the reset signal, resets the output clock signal, and the first rising edge of the reset clock signal is synchronized with the rising edge of the PWM dimming signal. The OR gate circuit has its first input terminal coupled to the output terminal of the pulse signal generation circuit, its second input terminal coupled to the output terminal of the clock signal generation circuit, and its output terminal outputting the reset clock signal.
2. The LED driving circuit as described in claim 1, characterized in that, The clock signal generation circuit includes: a current source, a capacitor, a first switching unit, a comparator, a delay circuit, and an RS flip-flop, wherein: The first terminal of the current source is input to the power supply voltage, and the second terminal of the current source is coupled to the positive input terminal of the comparator, the first terminal of the first switching unit, and the first terminal of the capacitor. The inverting input terminal of the comparator receives a reference voltage, and the output terminal of the comparator is coupled to the S terminal of the RS flip-flop. The Q terminal of the RS flip-flop is coupled to the input terminal of the delay circuit, and the R terminal of the RS flip-flop is coupled to the output terminal of the delay circuit. The control terminal of the first switching unit is coupled to the Q terminal of the RS flip-flop, and the second terminal of the first switching unit is grounded. The second terminal of the capacitor is grounded.
3. The LED driving circuit as described in claim 2, characterized in that, The first switching unit includes a first NMOS transistor; the drain of the first NMOS transistor is coupled to the second terminal of the current source, the gate of the first NMOS transistor is coupled to the Q terminal of the RS flip-flop, and the source of the first NMOS transistor is grounded.
4. The LED driving circuit as described in claim 1, characterized in that, The second switching unit includes a second NMOS transistor; the drain of the second NMOS transistor is coupled to the second terminal of the current source, the gate of the second NMOS transistor is coupled to the output terminal of the pulse signal generation circuit, and the source of the second NMOS transistor is grounded.
5. An LED driver device, characterized in that, It includes a DC-DC converter and an LED driving circuit as described in any one of claims 1 to 4, wherein the input terminal of the DC-DC converter is coupled to the output terminal of the LED driving circuit.