A method of fabricating a silicon carbide power device having a self-aligned region

Abstract

This invention relates to a method for fabricating a silicon carbide power device with a self-aligned region. The steps are as follows: a patterned first mask is fabricated on a drift layer to form a first operating port; ion implantation is performed from the first operating port to form a channel of the second conductivity type; then, a first spacer, a second spacer, and a third spacer are sequentially set to form a P-well, a lightly doped source region, and a heavily doped source region of the second conductivity type; the heavily doped source region is etched and ion implanted to form a plug region of the second conductivity type; and ion implantation is performed on the drift layer without a mask to fabricate a lightly doped JFET region of the first conductivity type. This method solves the technical problem in traditional vertical power MOSFET / IGBT devices where the formation of p-wells, p-channels, n-sources, and deep p-plug regions relies on continuous mask / window formation, which requires multiple photolithography masking steps and introduces accumulated alignment errors.

Description

Technical Field

[0001] This invention relates to the field of silicon carbide power device fabrication technology, and in particular to a method for fabricating a silicon carbide power device with a self-aligned region. Background Technology

[0002] In vertical power MOSFET / IGBT devices, conventional techniques for forming p-wells, p-channels, n-sources, and deep p-plug regions rely on successive mask / window formation, which requires multiple mask and photolithography steps, thus introducing accumulated alignment errors.

[0003] Early fabrication methods for vertical MOSFETs and IGBTs, such as US4914047, focused on improving accuracy and reducing process complexity during doped layer formation. This patent introduced a self-aligned process that uses a polysilicon gate mask to form the p-base and N+ source regions without relying on multiple photolithography alignments. Eliminating separate resist masks minimizes positional deviations between the gate and source, improving device uniformity and reducing manufacturing costs. This innovation addresses the challenge of mask misalignment in conventional processes while ensuring an effective short circuit between the source and base regions of vertical devices such as IGBTs and power MOSFETs. Subsequent research highlighted wide-bandgap semiconductors such as SiC, which exhibit superior breakdown strength, thermal conductivity, and carrier mobility compared to silicon. However, the low diffusion coefficient of dopants in SiC makes conventional diffusion-based processes impractical. To address this issue, US20040211980A1 proposed a self-aligned multi-injection process for forming source, buried, and well regions in SiC layers. This method employs sequential etching of a single mask layer to create multiple injection windows in a controlled sequence. This self-aligned SiC process represents a significant step towards scalable and reliable fabrication of high-voltage SiC MOSFETs and IGBTs, overcoming the inherent limitations of dopant diffusion in SiC.

[0004] EP3384522B1 (ABB Schweiz AG, 2019) discloses a semiconductor device and method that further optimizes the electrical characteristics of SiC-based power transistors. This patent introduces a deep, heavily doped P-type plug region extending at least as deep as the well layer. This plug region improves the ohmic contact between the source and well, while reducing the electric field peak in the critical gate oxide region, thereby mitigating parasitic transistor and thyristor effects and minimizing short-channel effects. The method employs a self-aligned mask to form the channel, well, and plug region with high precision. EP4439632A1 describes a method for fabricating a semiconductor device by forming recesses in a semiconductor body through wet chemical etching. This method does not describe how self-alignment between different layers is achieved; the well region and source / emitter region are arranged in different orders so that electrons flow vertically towards the drain contact.

[0005] Therefore, in order to address the above problems, the present invention urgently needs to provide a method for fabricating silicon carbide power devices with self-aligned regions. Summary of the Invention

[0006] The purpose of this invention is to provide a method for fabricating silicon carbide power devices with self-aligned regions. By proposing a silicon carbide power device with self-aligned regions, this invention addresses the technical problem in existing vertical power MOSFET / IGBT devices where the traditional techniques for forming p-wells, p-channels, n-sources, and deep p-plug regions rely on continuous mask / window formation, which requires multiple photolithography masking steps and introduces accumulated alignment errors.

[0007] The present invention provides a method for fabricating a silicon carbide power device with a self-aligned region, comprising the following steps: A drift layer of the first conductivity type layer is prepared on the upper surface of the substrate; A first mask is formed on the upper surface of the drift layer, the first mask is patterned, and a first operation port connected to the drift layer is formed after photolithography. Ion implantation is performed from the first operation port to form a channel of the second conductivity type on the drift layer. A first spacer is provided inside the first mask, and a second operating port communicating with the channel is provided between two adjacent first spacers. Ion implantation is performed on the channel through the second operating port to form a P-well of the second conductivity type. The depth of the P-well is greater than or equal to the depth of the channel. Low-doped ions are implanted into the P-well from the second operating port to form a self-aligned lightly doped source region of the first conductivity type. The depth of the lightly doped source region is less than the depth of the channel and the P-well. A second spacer is provided inside the first spacer, and a third operating port connected to the lightly doped source region is provided between two adjacent second spacers. Highly doped ions are implanted into the lightly doped source region from the third operating port to form a heavily doped source region of the first conductivity type. The depth of the heavily doped source region is greater than the depth of the lightly doped source region and less than the depth of the channel. A third spacer is provided inside the second spacer, and a fourth operating port is provided between two adjacent third spacers. The heavily doped source region is etched through the fourth operating port. After etching, ion implantation is performed to form a plug region of the second conductivity type, thereby obtaining a silicon carbide power device with a self-aligned region. The depth of the plug region of the second conductivity type is greater than or less than the depth of the P well, and the doping concentration of the plug region of the second conductivity type is higher than the doping concentration of the P well. The insertion area is strip-shaped or rectangular in the third dimension; Ion implantation is performed on the drift layer without a mask to prepare a lightly doped JFET region of the first conductivity type. The width of the first spacer is 1-800 nm; the width of the second spacer is 1-200 nm; and the width of the third spacer is 1-1000 nm.

[0008] Preferably, the doping concentration of the lightly doped source region is higher than that of the drift layer; the doping concentration of the heavily doped source region is higher than that of the lightly doped source region. The specific preparation process of the first spacer is as follows: A thin film is deposited at the first operating port of the first mask; Dry etching is performed on the thin film to form a first spacer on the inner side of the first mask. A second operating port is provided between two adjacent first spacers. One side of the first spacer is in close contact with the corresponding inner side of the first mask. The specific preparation process of the second spacer is as follows: A thin film is deposited at the second operating port; Dry etching is performed on the thin film to form a second spacer inside the first spacer. A third operating port is provided between two adjacent second spacers. One side of the second spacer is in close contact with the inner side of the corresponding first spacer. The specific preparation process of the third spacer is as follows: A thin film is deposited at the third operating port; Dry etching is performed on the thin film to form a third spacer inside the second spacer. A fourth operating port is provided between two adjacent third spacers. One side of the third spacer is in close contact with the inner side of the corresponding second spacer.

[0009] Preferably, the widths of the first spacer, the second spacer, and the third spacer are equal.

[0010] The present invention also provides a method for fabricating a silicon carbide power device with a self-aligned region, comprising the following steps: A drift layer of the first conductivity type layer is prepared on the upper surface of the substrate; A first mask is prepared on the upper surface of the drift layer, the first mask is patterned, and a first operation port communicating with the drift layer is formed after photolithography. Ion implantation is performed from the first operation port into the drift layer to form a channel of the second conductivity type. A first spacer is provided inside the first mask, and a second operating port communicating with the channel is provided between two adjacent first spacers. Ion implantation is performed on the channel through the second operating port to form a P-well of the second conductivity type. The depth of the P-well is greater than or equal to the depth of the channel. A second mask is fabricated above the P-well. An operating gap is provided between the two sides of the second mask and the corresponding first spacer. Ions are implanted into the P-well through the operating gap to form a lightly doped source region of the first conductivity type. The depth of the lightly doped source region is less than the depth of the P-well. A second spacer is disposed inside the first spacer. A third operating port communicating with the lightly doped source region is provided between the second spacer and the adjacent second mask. Highly doped ions are implanted into the lightly doped source region from the third operating port to form a heavily doped source region of the first conductivity type. The depth of the heavily doped source region is greater than that of the lightly doped source region and less than that of the channel of the second conductivity type. A third spacer is covered above the heavily doped source region, the second mask is removed, etching is performed at the location where the second mask was removed, and after etching, ion implantation is performed to form a plug region of the second conductivity type, thereby obtaining a silicon carbide power device with a self-aligned region. The depth of the plug region of the second conductivity type is greater than or less than the depth of the P-well, and the doping concentration of the plug region of the second conductivity type is greater than the doping concentration of the P-well. The insertion area is strip-shaped or rectangular in the third dimension; The width of the first spacer is 1-800 nm; the width of the second spacer is 1-200 nm; and the width of the third spacer is 1-1000 nm.

[0011] Preferably, the doping concentration of the lightly doped source region is higher than that of the drift layer; The doping concentration in the heavily doped source region is higher than that in the lightly doped source region; The specific preparation process of the first spacer is as follows: A thin film is deposited at the first operating port of the first mask; Dry etching is performed on the thin film to form a first spacer on the inner side of the first mask. A second operating port is provided between two adjacent first spacers. One side of the first spacer is in close contact with the corresponding inner side of the first mask. The specific preparation process of the second spacer is as follows: A thin film is deposited at a second operating port between adjacent first spacers and second masks; Dry etching is performed on the thin film to form a second spacer inside the first spacer. A third operating port is provided between the second spacer and the second mask. The specific preparation process of the third spacer is as follows: A thin film is deposited at the third operating port to form a third spacer.

[0012] The present invention also provides a method for fabricating a silicon carbide power device with a self-aligned region, comprising the following fabrication steps: A drift layer of the first conductivity type layer is prepared on the upper surface of the substrate; A first mask is prepared on the upper surface of the drift layer, the first mask is patterned, and a first operation port communicating with the drift layer is formed after photolithography. Ion implantation is performed at the first operation port to form a channel of the second conductivity type on the drift layer. A first spacer is provided inside the first mask, and a second operating port is provided on two adjacent first spacers that communicate with the channel. The first mask is removed, and ion implantation is performed on the substrate at the position of the second operating port and the original first mask to form a lightly doped source region of the first conductivity type. The depth of the lightly doped source region is less than the depth of the channel. The first mask is covered again at the original first mask position, and ions are implanted into the lightly doped source region from the second operation port to form a P-well of the second conductivity type. The depth of the P-well is greater than the depth of the channel. A second spacer is disposed inside the first spacer, and a third operating port communicating with the P-well is formed between two adjacent second spacers. Highly doped ions are implanted into the lightly doped source region from the third operating port to form a heavily doped source region of the first conductivity type. The depth of the heavily doped source region is greater than the depth of the lightly doped source region and less than the depth of the P-well and the channel. A third spacer is disposed inside the second spacer, and a fourth operating port connected to the heavily doped source region is formed between two adjacent third spacers. The heavily doped source region is etched through the fourth operating port. After etching, ion implantation is performed to form a plug region of the second conductivity type, thereby obtaining a silicon carbide power device with a self-aligned region. The depth of the plug region of the second conductivity type is greater than or less than the depth of the P-well, and the doping concentration of the plug region of the second conductivity type is greater than the doping concentration of the P-well. The insertion area is strip-shaped or rectangular in the third dimension; The width of the first spacer is 1-800 nm; the width of the second spacer is 1-200 nm; and the width of the third spacer is 1-1000 nm.

[0013] Preferably, the doping concentration of the lightly doped source region is higher than that of the drift layer; The doping concentration in the heavily doped source region is higher than that in the lightly doped source region; The specific preparation process of the first spacer is as follows: A thin film is deposited at the first operating port of the first mask; Dry etching is performed on the thin film to form a first spacer on the inner side of the first mask. The first spacer is in close contact with the inner side of the first mask, and a second operating port is provided between two adjacent first spacers. The specific preparation process of the second spacer is as follows: A thin film is deposited at the second operating port between two adjacent first spacers; The thin film is dry etched to form a second spacer inside the first spacer, and a third operating port is provided between two adjacent second spacers; The specific preparation process of the third spacer is as follows: A thin film is deposited at the third operating port between the second spacers; Dry etching is performed on the thin film to form a third spacer inside the second spacer, and a fourth operating port is provided between two adjacent third spacers.

[0014] Preferably, the widths of the first spacer, the second spacer, and the third spacer are equal.

[0015] The present invention also provides a method for fabricating a silicon carbide power device with a self-aligned region, comprising the following steps: A drift layer of the first conductivity type layer is prepared on the upper surface of the substrate; A first mask is prepared on the upper surface of the drift layer, the first mask is patterned, and a first operation port communicating with the drift layer is formed after photolithography. The drift layer is etched from the first operation port to form a V-shaped or U-shaped groove, and ion implantation is performed to form a second type of conductive channel on the drift layer. A first spacer is prepared inside the first mask. The first spacer is located on the sidewall of the groove. A second operating window is formed between two adjacent first spacers. Ions are implanted into the drift layer from the second operating port to form a P-well of the second conductivity type. The depth of the P-well is greater than or equal to the depth of the channel. Ions are implanted into a P-well of the second conductivity type from the second operating port to form a lightly doped source region of the first conductivity type. The depth of the lightly doped source region is less than the depth of the P-well. A second spacer is prepared inside the first spacer, and a third operating port is formed between two adjacent second spacers. High doping is implanted into the lightly doped source region from the third operating port to form a heavily doped source region of the first conductivity type. The depth of the heavily doped source region is greater than the depth of the lightly doped source region and less than the depth of the P-well and the channel. A third spacer is prepared inside the second spacer, and a fourth operating port is provided between two adjacent third spacers. The heavily doped source region is etched through the fourth operating port. After etching, ion implantation is performed to form a plug region of the second conductivity type, thereby obtaining a silicon carbide power device with a self-aligned region. The depth of the plug region of the second conductivity type is greater than or less than the depth of the P-well, and the doping concentration of the plug region of the second conductivity type is greater than the doping concentration of the P-well. The insertion area is strip-shaped or rectangular in the third dimension; The width of the first spacer is 1-800 nm; the width of the second spacer is 1-200 nm; and the width of the third spacer is 1-1000 nm.

[0016] Preferably, the doping concentration of the lightly doped source region is higher than that of the drift layer; The doping concentration in the heavily doped source region is higher than that in the lightly doped source region; The specific preparation process of the first spacer is as follows: A thin film is deposited at the first operating port of the first mask; Dry etching is performed on the thin film to form a first spacer on the inner side of the first mask. A second operating port is provided between two adjacent first spacers. One side of the first spacer is in close contact with the corresponding inner side of the first mask. The specific preparation process of the second spacer is as follows: A thin film is deposited at the second operating port; Dry etching is performed on the thin film to form a second spacer inside the first spacer. A third operating port is provided between two adjacent second spacers. One side of the second spacer is in close contact with the inner side of the corresponding first spacer. The specific preparation process of the third spacer is as follows: A thin film is deposited at the third operating port; Dry etching is performed on the thin film to form a third spacer inside the second spacer. A fourth operating port is provided between two adjacent third spacers. One side of the third spacer is in close contact with the inner side of the corresponding second spacer.

[0017] By adopting the above technical solution, the present invention has the following beneficial effects: 1. The method for fabricating silicon carbide power devices with self-aligned regions provided by the present invention designs a first spacer, a second spacer, and a third spacer. When the first spacer is set, a self-aligned structure is formed, providing a window for P-well formation. When the second spacer is set, a self-aligned structure is formed, providing a window for lightly doped source regions. When the third spacer is set, a self-aligned structure is formed, providing a window for forming plug regions of a second conductivity type. The lateral dimensions can be precisely set. The lightly doped source regions are used to better define the channel of the second conductivity type and avoid scattering from the heavily doped source regions. The heavily doped source regions are used for ohmic contacts.

[0018] 2. The silicon carbide power device fabrication method with self-aligned region provided by the present invention uses only one mask, and then uses a first spacer, a second spacer and a third spacer to achieve staged implantation, thereby achieving precise control of size, reducing mask misalignment caused by repeated photolithography masking steps, reducing errors, reducing costs, and enabling precise control of the channel and doped region.

[0019] 3. The method for fabricating silicon carbide power devices with self-aligned regions provided by the present invention can form plug regions of a second conductivity type that are self-aligned with the source / well, and can reduce high field peaks in the gate oxide. Attached Figure Description

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a step diagram (I) of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 1. Figure 2 This is a step diagram (II) of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 1. Figure 3 This is a step diagram (III) of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 1. Figure 4 This is a step diagram (IV) of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 1. Figure 5 This is a schematic diagram (cross-sectional view) of the silicon carbide power device structure with a self-aligned region as described in Example 1. Figure 6 This is a schematic diagram (top view) of the silicon carbide power device structure with a self-aligned region as described in Example 1. Figure 7 This is a step diagram (I) of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 2. Figure 8 This is a step diagram (II) of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 2. Figure 9 This is a step diagram (III) of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 2. Figure 10This is a step diagram (IV) of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 2. Figure 11 This is a schematic diagram (top view) of the silicon carbide power device structure with a self-aligned region as described in Example 2. Figure 12 This is a step diagram (I) of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 3. Figure 13 This is a step diagram (II) of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 3. Figure 14 This is a step diagram (III) of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 3. Figure 15 This is a step diagram of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 4; Figure 16 This is a step diagram of the method for fabricating a silicon carbide power device with a self-aligned region as described in Example 4.

[0022] Explanation of reference numerals in the attached figures: 101. Drift layer; 2. First mask; 4. First spacer; 5. Channel; 6. P-well; 7. Second spacer; 8. Lightly doped source region; 9. Heavily doped source region; 10. Third spacer; 11. Plug region; 12. Second mask; 13. Low-doped JFET region. Detailed Implementation

[0023] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] Those skilled in the art should understand that the following specific embodiments or implementation methods are a series of optimized configurations listed to further explain the specific content of the invention. These configuration methods can be combined or used in conjunction with each other, unless the invention explicitly states that some or a specific embodiment or implementation method cannot be associated with or used in conjunction with other embodiments or implementation methods. Furthermore, the following specific embodiments or implementation methods are merely optimized configurations and are not intended to limit the scope of protection of the invention.

[0026] The present invention will be further explained below with reference to specific embodiments.

[0027] Example 1 like Figures 1 to 6 As shown in the figure, this embodiment provides a method for fabricating a silicon carbide power device with a self-aligned region, which includes the following steps: 101) A drift layer 101 of the first conductivity type layer is prepared on the upper surface of the substrate; the substrate is omitted in the figure. 102) A first mask is prepared on the upper end face of the drift layer 101. After the first mask 2 is formed, the first mask 2 is patterned and photolithographically processed to form a first operation port connected to the drift layer 101. Ion implantation is performed from the first operation port to form a second conductivity type channel 5 on the drift layer 101. 103) A first spacer 4 is provided inside the first mask 2, and a second operating port communicating with the channel 5 is provided between two adjacent first spacers 4. Ion implantation is performed on the channel 5 through the second operating port to form a P-well 6 of the second conductivity type. The depth of the P-well 6 is ≥ the depth of the channel 5. 104) Low-doped ions are implanted into P-well 6 from the second operating port to form a self-aligned lightly doped source region 8 of the first conductivity type. The depth of the lightly doped source region 8 is less than the depth of the channel 5 and P-well 6. 105) A second spacer 7 is provided inside the first spacer 4. A third operating port connected to the lightly doped source region 8 is provided between two adjacent second spacers 7. Highly doped ions are implanted into the lightly doped source region 8 from the third operating port to form a heavily doped source region 9 of the first conductivity type. The depth of the heavily doped source region 9 is greater than the depth of the lightly doped source region 8 and less than the depth of the channel 5. 106) A third spacer 10 is provided inside the second spacer 7, and a fourth operating port is provided between two adjacent third spacers 10. The heavily doped source region 9 is etched through the fourth operating port. After etching, ion implantation is performed to form a plug region 11 of the second conductivity type, thereby obtaining a silicon carbide power device with a self-aligned region. 107) The depth of the plug region 11 of the second conductivity type is greater than or less than the depth of the P well 6, and the doping concentration of the plug region 11 of the second conductivity type is higher than the doping concentration of the P well 6. The depth of the plug area 11 of the second conductive type can be selected according to the required length.

[0028] In this embodiment, the insertion area 11 is strip-shaped or rectangular in the third dimension. The appropriate shape can be selected as needed; it can be strip-shaped or rectangular. In this embodiment, after removing the first mask 2, ion implantation is performed on the drift layer 101 without a mask to prepare a low-doped JFET region 13 of the first conductivity type. The width of the first spacer 4 in this invention is 1-800 nm; the width of the second spacer 7 is 1-200 nm; and the width of the third spacer 10 is 1-1000 nm. In the specific preparation process, the width can be adjusted according to the required width.

[0029] In this embodiment, the doping concentration of the lightly doped source region 8 is higher than that of the drift layer 101. In this embodiment, the doping concentration of the heavily doped source region 9 is higher than that of the lightly doped source region 8; During the formation of plug region 11, the heavily doped source region 9 can be precisely etched from the fourth operating port. This eliminates the need for excessive compensation through ion implantation. The heavily doped source region 9 is etched away first, and then ion implantation is performed with a lower dose to obtain plug region 11.

[0030] The specific preparation process of the first spacer 4 in this embodiment is as follows: a thin film is deposited at the first operating port of the first mask 2; the thin film is dry etched to form the first spacer 4 on the inner side of the first mask 2; a second operating port is provided between two adjacent first spacers 4; one side of the first spacer 4 is closely attached to the corresponding inner side of the first mask 2.

[0031] The specific preparation process of the second spacer 7 in this embodiment is as follows: a thin film is deposited at the second operating port; the thin film is dry etched to form the second spacer 7 inside the first spacer 4, a third operating port is provided between two adjacent second spacers 7, and one side of the second spacer 7 is closely attached to the inner side of the corresponding first spacer 4.

[0032] The specific preparation process of the third spacer 10 in this embodiment is as follows: a thin film is deposited at the third operating port; the thin film is dry etched to form the third spacer 10 inside the second spacer 7, and a fourth operating port is provided between two adjacent third spacers 10. One side of the third spacer 10 is closely attached to the inner side of the corresponding second spacer 7.

[0033] In some embodiments, the widths of the first spacer 4, the second spacer 7, and the third spacer 10 are equal. In other embodiments, the widths of the first spacer 4, the second spacer 7, and the third spacer 10 may be equal or unequal, depending on the specific circumstances.

[0034] Through the above-described design steps, this invention designs a first spacer 4, a second spacer 7, and a third spacer 10. When the first spacer 4 is set, a self-aligned structure is formed, providing a window for the formation of the P-well 6. When the second spacer 7 is set, a self-aligned structure is formed, providing a window for the formation of the lightly doped source region 8. When the third spacer 10 is set, a self-aligned structure is formed, providing a window for the formation of the plug region 11 of the second conductivity type. The lateral dimensions can be precisely controlled. The lightly doped source region 8 is used to better define the channel 5 of the second conductivity type and avoid scattering from the heavily doped source region 9. The heavily doped source region 9 is used for ohmic contacts.

[0035] This invention uses only one mask, and in conjunction with the first spacer 4, the second spacer 7 and the third spacer 10, it achieves staged implantation, realizes precise control of size, reduces mask misalignment caused by repeated photolithography masking steps, reduces errors, reduces costs, and can achieve precise control of channels and doped regions.

[0036] The method provided by the present invention can form a plug region 11 of a second conductivity type that is self-aligned with the source / well, which can reduce high field peaks in the gate oxide.

[0037] The first conductivity type dopant in this embodiment is an n-type dopant for SiC, which can be nitrogen.

[0038] The second conductivity type dopant in this embodiment is a p-type dopant, which can be aluminum.

[0039] The method provided by this invention is particularly advantageous for diffusion-limited SiC / wide bandgap devices that use injection + activation / drive annealing. The fewer photomasks required, the lower the cost and misalignment error from continuous mask windows, and the more precisely controllable the channel and doped region.

[0040] The first spacer 4, the second spacer 7, and the third spacer 10 can be made of silicon dioxide, silicon nitride, or other materials.

[0041] This invention provides a design with three spacers that can precisely set the lateral dimensions. The lightly doped source region 8 is used to well define the channel region and avoid scattering from the heavily doped source region 9, which is used for ohmic contacts.

[0042] The present invention provides a master mask and three spacers instead of three to four photomasks / windows to achieve phased implantation (channel, source, trap, plug region).

[0043] The proposed method is particularly advantageous for diffusion-limited SiC / wide bandgap devices that use injection + activation / drive annealing. Fewer photomasks result in lower costs and misalignment errors from continuous mask windows, and allow for precise control of channels and doped regions.

[0044] Example 2 like Figures 7 to 11 As shown in the figure, this embodiment provides a method for fabricating a silicon carbide power device with a self-aligned region, which includes the following steps: 201) A drift layer 101 of a first conductivity type layer is prepared on the upper surface of the substrate; 202) A first mask 2 is prepared on the upper end face of the drift layer 101, the first mask 2 is patterned, and a first operation port communicating with the drift layer 101 is formed after photolithography. Ion implantation is performed from the first operation port into the drift layer 101 to form a channel 5 of the second conductivity type. 203) A first spacer 4 is provided inside the first mask 2, and a second operating port communicating with the channel 5 is provided between two adjacent first spacers 4. Ion implantation is performed on the channel 5 through the second operating port to form a P-trap 6 of the second conductivity type. The depth of the P-trap 6 is ≥ the depth of the channel 5. 204) A second mask 12 is prepared above the P-well 6. An operating gap is provided between the two sides of the second mask 12 and the corresponding first spacer 4. Ions are implanted into the P-well 6 through the operating gap to form a lightly doped source region 8 of the first conductivity type. The depth of the lightly doped source region 8 is less than the depth of the P-well 6. 205) A second spacer 7 is provided inside the first spacer 4. A third operating port communicating with the lightly doped source region 8 is provided between the second spacer 7 and the adjacent second mask 12. Highly doped ions are implanted into the lightly doped source region 8 from the third operating port to form a heavily doped source region 9 of the first conductivity type. The depth of the heavily doped source region 9 is greater than that of the lightly doped source region 8 and less than that of the channel 5 of the second conductivity type. 206) Cover the heavily doped source region 9 with a third spacer 10, remove the second mask 12, etch at the location where the second mask 12 is removed, and after etching, perform ion implantation to form a plug region 11 of the second conductivity type, thereby obtaining a silicon carbide power device with a self-aligned region. 207) The depth of the plug region 11 of the second conductivity type is greater than or less than the depth of the P well 6, and the doping concentration of the plug region 11 of the second conductivity type is greater than the doping concentration of the P well 6. The depth of the plug area 11 of the second conductive type can be selected according to the required length.

[0045] In this embodiment, the insertion area 11 is strip-shaped or rectangular in the third dimension; In this embodiment, the width of the first spacer is 1-800 nm; the width of the second spacer is 1-200 nm; and the width of the third spacer is 1-1000 nm. The size can be selected as needed.

[0046] In this embodiment, the doping concentration of the lightly doped source region 8 is higher than that of the drift layer 101; the doping concentration of the heavily doped source region 9 is higher than that of the lightly doped source region 8. The specific preparation process of the first spacer 4 is as follows: a thin film is deposited at the first operating port of the first mask 2; the thin film is dry etched to form the first spacer 4 on the inner side of the first mask 2; a second operating port is provided between two adjacent first spacers 4; one side of the first spacer 4 is closely attached to the corresponding inner side of the first mask 2. The specific preparation process of the second spacer 7 is as follows: a thin film is deposited at the second operating port between the adjacent first spacer 4 and the second mask 12; the thin film is dry etched to form the second spacer 7 inside the first spacer 4, and a third operating port is provided between the second spacer 7 and the second mask 12. The specific preparation process of the third spacer 10 is as follows: a thin film is deposited at the third operating port to form the third spacer 10.

[0047] During the formation of the plug region 11, the heavily doped source region 9 is etched first, so that there is no need for excessive compensation through ion implantation. The heavily doped source region 9 is etched away first, and then ion implantation is performed with a lower dose to obtain the plug region 11.

[0048] This invention, through the design of the above steps, provides another method for fabricating silicon carbide power devices with self-aligned regions. It designs a first spacer 4, a second spacer 7, and a third spacer 10, using only a single masking technique. When the first spacer 4 is set, a self-aligned structure is formed, providing a window for the formation of the P-well 6. When the second spacer 7 is set, a self-aligned structure is formed, providing a window for the formation of the lightly doped source region 8. When the third spacer 10 is set, a self-aligned structure is formed, providing a window for the formation of the plug region 11 of the second conductivity type. This allows for precise setting of the lateral dimensions, reducing photolithography steps. The lightly doped source region 8 is used to better define the channel 5 of the second conductivity type and avoid scattering from the heavily doped source region 9. The heavily doped source region 9 is used for ohmic contacts.

[0049] This invention uses only one mask and combines it with three spacers, namely the first spacer 4, the second spacer 7 and the third spacer 10, to achieve staged implantation, achieve precise control of size, reduce mask misalignment caused by repeated photolithography masking steps, reduce errors, reduce costs, and achieve precise control of channels and doped regions.

[0050] The method provided by the present invention can form a plug region 11 of a second conductivity type that is self-aligned with the source / well, which can reduce high field peaks in the gate oxide.

[0051] Compared to Example 1, in this embodiment, the step of preparing the second mask 12 above the P-well 6 is designed so that the plug region 11 does not need to be overcompensated. This is because after the second mask 12 is covered, the covered area has no lightly doped source region 8 (in Example 1, the plug region 11 must be overcompensated for the lightly doped source region 8 that runs through the entire area).

[0052] The first spacer 4, the second spacer 7, and the third spacer 10 can be made of silicon dioxide, silicon nitride, or other materials.

[0053] This invention provides a design with three spacers that can precisely set the lateral dimensions. The lightly doped source region 8 is used to well define the channel region and avoid scattering from the heavily doped source region 9, which is used for ohmic contacts.

[0054] The present invention provides a master mask and three spacers instead of three to four photomasks / windows to achieve phased implantation (channel, source, trap, plug region).

[0055] Example 3 like Figures 12 to 14 As shown in the figure, this embodiment provides a method for fabricating a silicon carbide power device with a self-aligned region, which includes the following fabrication steps: 301) A drift layer 101 of a first conductivity type layer is prepared on the upper surface of the substrate; 302) A first mask 2 is prepared on the upper end face of the drift layer 101, the first mask 2 is patterned, and a first operation port communicating with the drift layer 101 is formed after photolithography. Ion implantation is performed at the first operation port to form a second conductivity type channel 5 on the drift layer 101. 303) A first spacer 4 is provided inside the first mask 2. A second operation port is provided on two adjacent first spacers 4 that communicate with the channel 5. The first mask 2 is removed, and ion implantation is performed on the substrate 1 at the position of the second operation port and the original first mask 2 to form a lightly doped source region 8 of the first conductivity type. The depth of the lightly doped source region 8 is less than the depth of the channel 5. 304) Cover the original first mask 2 position again, and implant ions into the lightly doped source region 8 from the second operation port to form a P-well 6 of the second conductivity type. The depth of the P-well 6 is greater than the depth of the channel 5. 305) A second spacer 7 is provided inside the first spacer 4, and a third operating port communicating with the P-well 6 is formed between two adjacent second spacers 7. Highly doped ions are implanted into the lightly doped source region 8 from the third operating port to form a heavily doped source region 9 of the first conductivity type. The depth of the heavily doped source region 9 is greater than the depth of the lightly doped source region 8 and less than the depth of the P-well 6 and the channel 5. 306) A third spacer 10 is provided inside the second spacer 7. A fourth operating port connected to the heavily doped source region 9 is formed between two adjacent third spacers 10. The heavily doped source region 9 is etched from the fourth operating port. After etching, ion implantation is performed to form a plug region 11 of the second conductivity type, thereby obtaining a silicon carbide power device with a self-aligned region. 307) The depth of the plug region 11 of the second conductivity type is greater than or less than the depth of the P well 6, and the doping concentration of the plug region 11 of the second conductivity type is greater than the doping concentration of the P well 6. The insertion area 11 is strip-shaped or rectangular in the third dimension; The width of the first spacer is 1-800 nm; the width of the second spacer is 1-200 nm; and the width of the third spacer is 1-1000 nm. The required size can be selected according to the requirements.

[0056] In this embodiment, the doping concentration of the lightly doped source region 8 is higher than that of the drift layer 101; the doping concentration of the heavily doped source region 9 is higher than that of the lightly doped source region 8.

[0057] The specific preparation process of the first spacer 4 in this embodiment is as follows: a thin film is deposited at the first operating port of the first mask 2; the thin film is dry etched to form the first spacer 4 on the inner side of the first mask 2. The first spacer 4 is closely attached to the inner side of the first mask 2, and a second operating port is provided between two adjacent first spacers 4. The specific preparation process of the second spacer 7 in this embodiment is as follows: a thin film is deposited at the second operating port between two adjacent first spacers 4; the thin film is dry etched to form the second spacer 7 inside the first spacer 4, and a third operating port is provided between two adjacent second spacers 7; The specific preparation process of the third spacer 10 in this embodiment is as follows: a thin film is deposited at the third operating port between the second spacers 7; the thin film is dry etched to form the third spacer 10 inside the second spacers 7, and a fourth operating port is provided between two adjacent third spacers 10.

[0058] In this embodiment, during the formation of the plug region 11, the heavily doped source region 9 is etched first, so that there is no need to make too much compensation through ion implantation. The heavily doped source region 9 is etched away first, and then ion implantation is performed with a lower dose to obtain the plug region 11.

[0059] The widths of the first spacer 4, the second spacer 7, and the third spacer 10 can be equal or unequal, depending on the specific circumstances.

[0060] Through the above-described design steps, this invention designs a first spacer 4, a second spacer 7, and a third spacer 10. When the first spacer 4 is set, a self-aligned structure is formed, providing a window for the formation of the P-well 6. When the second spacer 7 is set, a self-aligned structure is formed, providing a window for the formation of the lightly doped source region 8. When the third spacer 10 is set, a self-aligned structure is formed, providing a window for the formation of the plug region 11 of the second conductivity type. The lateral dimensions can be precisely set. The lightly doped source region 8 is used to better define the channel 5 of the second conductivity type and avoid scattering from the heavily doped source region 9. The heavily doped source region 9 is used for ohmic contact.

[0061] This invention uses only one first mask 2, along with the first spacer 4, the second spacer 7, and the third spacer 10, to achieve staged implantation, enabling precise control of dimensions, reducing mask misalignment caused by repeated photolithography masking steps, lowering errors, reducing costs, and enabling precise control of channels and doped regions.

[0062] The method provided by the present invention can form a plug region 11 of a second conductivity type that is self-aligned with the source / well, which can reduce high field peaks in the gate oxide.

[0063] Compared to Embodiment 1, in this embodiment, a lightly doped source region 8 is first formed in front of the P-well 6. The lightly doped source region 8 can be injected into the JFET region of the silicon carbide MOSFET and can better control the channel.

[0064] The first spacer 4, the second spacer 7, and the third spacer 10 can be made of silicon dioxide, silicon nitride, or other materials.

[0065] This invention provides a design with three spacers that can precisely set the lateral dimensions. The lightly doped source region 8 is used to well define the channel region and avoid scattering from the heavily doped source region 9, which is used for ohmic contacts.

[0066] The present invention provides a master mask and three spacers instead of three to four photomasks / windows to achieve phased implantation (channel, source, trap, plug region).

[0067] Example 4 like Figure 15 , Figure 16 As shown in the figure, the method for fabricating a silicon carbide power device with a self-aligned region provided in this embodiment includes the following steps: 401) A drift layer 101 of a first conductivity type layer is prepared on the upper surface of the substrate; 402) A first mask 2 is prepared on the upper end face of the drift layer 101, the first mask 2 is patterned, and a first operation port communicating with the drift layer 101 is formed after photolithography. The drift layer 101 is etched from the first operation port to form a V-shaped or U-shaped groove. Ion implantation is performed to form a second conductive channel 5 on the drift layer 101. 403) A first spacer 4 is prepared inside the first mask 2. The first spacer 4 is located on the side wall of the groove. A second operating window is formed between two adjacent first spacers 4. Ion implantation is performed from the second operating port to the drift layer 101 to form a P-well 6 of the second conductivity type. The depth of the P-well 6 is ≥ the depth of the channel 5. 404) Ion implantation is performed from the second operation port into the P-well 6 of the second conductivity type to form a lightly doped source region 8 of the first conductivity type, the depth of the lightly doped source region 8 being less than the depth of the P-well 6. 405) A second spacer 7 is prepared inside the first spacer 4, and a third operating port is formed between two adjacent second spacers 7. High doping is implanted into the lightly doped source region 8 from the third operating port to form a heavily doped source region 9 of the first conductivity type. The depth of the heavily doped source region 9 is greater than the depth of the lightly doped source region 8 and less than the depth of the P-well 6 and the channel 5. 406) A third spacer 10 is prepared inside the second spacer 7. A fourth operating port is provided between two adjacent third spacers 10. The heavily doped source region 9 is etched through the fourth operating port. After etching, ion implantation is performed to form a plug region 11 of the second conductivity type, thereby obtaining a silicon carbide power device with a self-aligned region. 407) The depth of the plug region 11 of the second conductivity type is greater than or less than the depth of the P well 6, and the doping concentration of the plug region 11 of the second conductivity type is greater than the doping concentration of the P well 6. In this embodiment, the insertion area 11 is strip-shaped or rectangular in the third dimension, and the shape in the three dimensions can be selected according to the preparation requirements.

[0068] In this embodiment, the width of the first spacer is 1-800 nm; the width of the second spacer is 1-200 nm; and the width of the third spacer is 1-1000 nm. The required size can be selected within the range according to the requirements.

[0069] In this embodiment, the doping concentration of the lightly doped source region 8 is higher than that of the drift layer 101; the doping concentration of the heavily doped source region 9 is higher than that of the lightly doped source region 8; the specific preparation process of the first spacer 4 is as follows: a thin film is deposited at the first operating port of the first mask 2; the thin film is dry etched to form the first spacer 4 on the inner side of the first mask 2, and a second operating port is provided between two adjacent first spacers 4, and one side of the first spacer 4 is closely attached to the corresponding inner side of the first mask 2.

[0070] The specific preparation process of the second spacer 7 in this embodiment is as follows: a thin film is deposited at the second operating port; the thin film is dry etched to form the second spacer 7 inside the first spacer 4, a third operating port is provided between two adjacent second spacers 7, and one side of the second spacer 7 is closely attached to the inner side of the corresponding first spacer 4.

[0071] The specific preparation process of the third spacer 10 in this embodiment is as follows: a thin film is deposited at the third operating port; the thin film is dry etched to form the third spacer 10 inside the second spacer 7, and a fourth operating port is provided between two adjacent third spacers 10. One side of the third spacer 10 is closely attached to the inner side of the corresponding second spacer 7.

[0072] In this embodiment, during the formation of the plug region 11, the heavily doped source region 9 is etched first, so that there is no need to make too much compensation through ion implantation. The heavily doped source region 9 is etched away first, and then ion implantation is performed with a lower dose to obtain the plug region 11.

[0073] Through the design of the above steps, this invention employs a single mask, combined with a first spacer 4, a second spacer 7, and a third spacer 10. When the first spacer 4 is set, a self-aligned structure is formed, providing a window for the formation of the P-well 6. When the second spacer 7 is set, a self-aligned structure is formed, providing a window for the formation of the lightly doped source region 8. When the third spacer 10 is set, a self-aligned structure is formed, providing a window for the formation of the plug region 11 of the second conductivity type. The lateral dimensions can be precisely set. The lightly doped source region 8 is used to better define the channel 5 of the second conductivity type and avoid scattering from the heavily doped source region 9. The heavily doped source region 9 is used for ohmic contacts.

[0074] The first mask 2 of this invention is used only once, and the others are designed with spacers, namely the first spacer 4, the second spacer 7 and the third spacer 10, to achieve staged implantation, achieve precise control of size, reduce mask misalignment caused by repeated photolithography masking steps, reduce errors, reduce costs, and achieve precise control of channels and doped regions.

[0075] The method provided by the present invention can form a plug region 11 of a second conductivity type that is self-aligned with the source / well, which can reduce high field peaks in the gate oxide.

[0076] Compared with Embodiment 1, the difference in this embodiment is that the drift layer 101 is etched from the operation port to form a V-shaped or U-shaped groove, so that the operation port provides a channel that is not on the same axis.

[0077] The materials of the first spacer 4, the second spacer 7, and the third spacer 10 in the above embodiments can be silicon dioxide or silicon nitride.

[0078] The first spacer 4, the second spacer 7, and the third spacer 10 can be made of silicon dioxide, silicon nitride, or other materials.

[0079] This invention provides a design with three spacers that can precisely set the lateral dimensions. The lightly doped source region 8 is used to well define the channel region and avoid scattering from the heavily doped source region 9, which is used for ohmic contacts.

[0080] The present invention provides a master mask and three spacers instead of three to four photomasks / windows to achieve phased implantation (channel, source, trap, plug region).

[0081] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method of fabricating a silicon carbide power device having a self-aligned region, the method comprising: The preparation steps include the following: ​ A drift layer (101) of the first conductivity type is prepared on the upper surface of the substrate. A first mask (2) is prepared on the upper surface of the drift layer (101), the first mask (2) is patterned, and a first operating port connected to the drift layer (101) is formed after photolithography. Ion implantation is performed at the first operating port to form a second conductive channel (5) on the drift layer (101). A first spacer (4) is provided inside the first mask (2). A second operating port communicating with the channel (5) is provided on two adjacent first spacers (4). The first mask (2) is removed. Ion implantation is performed on the substrate (1) at the position of the second operating port and the original first mask (2) to form a lightly doped source region (8) of the first conductivity type. The depth of the lightly doped source region (8) is less than the depth of the channel (5). The first mask (2) is covered again at the original position of the first mask (2), and ions are implanted into the lightly doped source region (8) from the second operation port to form a P-well (6) of the second conductivity type. The depth of the P-well (6) is greater than the depth of the channel (5). A second spacer (7) is provided inside the first spacer (4), and a third operating port connected to the P-well (6) is formed between two adjacent second spacers (7). Highly doped ions are implanted into the lightly doped source region (8) from the third operating port to form a heavily doped source region (9) of the first conductivity type. The depth of the heavily doped source region (9) is greater than the depth of the lightly doped source region (8) and less than the depth of the P-well (6) and the channel (5). A third spacer (10) is provided inside the second spacer (7), and a fourth operating port connected to the heavily doped source region (9) is formed between two adjacent third spacers (10). The heavily doped source region (9) is etched from the fourth operating port. After etching, ion implantation is performed to form a plug region (11) of the second conductivity type, thereby obtaining a silicon carbide power device with a self-aligned region.

2. The method for fabricating a silicon carbide power device with a self-aligned region according to claim 1, characterized in that: The depth of the plug region (11) of the second conductivity type is greater than or less than the depth of the P well (6), and the doping concentration of the plug region (11) of the second conductivity type is greater than the doping concentration of the P well (6). The insertion area (11) is strip-shaped or rectangular in the third dimension; The width of the first spacer is 1-800 nm; the width of the second spacer is 1-200 nm; the width of the third spacer is 1-1000 nm; The doping concentration of the lightly doped source region (8) is higher than that of the drift layer (101); The doping concentration of the heavily doped source region (9) is higher than that of the lightly doped source region (8); The specific preparation process of the first spacer (4) is as follows: A thin film is deposited at the first operating port of the first mask (2); Dry etching is performed on the thin film to form a first spacer (4) inside the first mask (2). The first spacer (4) is closely attached to the inner side of the first mask (2), and a second operation port is provided between two adjacent first spacers (4). The specific preparation process of the second spacer (7) is as follows: A thin film is deposited at the second operating port between two adjacent first spacers (4); Dry etching the thin film to form second spacers (7) inside the first spacers (4), and a third operation opening is arranged between two adjacent second spacers (7); The third spacers (10) are prepared as follows: Depositing a thin film at the third operation opening between the second spacers (7); Dry etching the thin film to form third spacers (10) inside the second spacers (7), and a fourth operation opening is arranged between two adjacent third spacers (10).

3. The method of claim 2, wherein: The first spacers (4), the second spacers (7) and the third spacers (10) have equal width.

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