Diamond-silicon carbide composite substrate, method for preparing the same and use thereof

Abstract

The application belongs to the technical field of semiconductor manufacturing, and relates to a diamond-silicon carbide composite substrate and a preparation method and application thereof. The preparation method comprises the following steps: coating SiC quantum dot sol on a silicon substrate and preparing a nucleation point array through pulse laser annealing, sequentially depositing a gradient buffer layer, a 3C-SiC film and a diamond layer, and polishing the surface of the 3C-SiC film to obtain the diamond-silicon carbide composite substrate; the gradient buffer layer is a SiGeC gradient buffer layer, and the thickness is 5-10 nm; the thickness of the 3C-SiC film is 0.5-5 microns. The application can realize stable combination of the ultrathin SiC layer with uniform thickness and smooth surface and the diamond under the premise of guaranteeing the interface bonding strength and structural integrity, and is beneficial to development and application of the high-performance diamond-silicon carbide composite substrate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor materials technology, specifically relating to a diamond-silicon carbide composite substrate, its preparation method, and its application. Background Technology

[0002] Silicon carbide (SiC), as a core material of third-generation semiconductors, is widely used in fields with extremely high power density and efficiency requirements, such as new energy vehicles, rail transportation, and smart grids, due to its excellent properties including wide bandgap, high breakdown field strength, high electron saturation drift velocity, and chemical stability. However, with the continuous miniaturization and integration of power electronic devices, the heat generated during operation is increasing dramatically, leading to increasingly prominent heat dissipation problems. Although SiC itself has a high thermal conductivity (490 W·m), - ¹·K - ¹), but under ultra-high power density conditions, its self-heating effect remains significant, causing the device junction temperature to rise rapidly, leading to performance degradation and decreased reliability. Effectively controlling the chip junction temperature has become the core driving force for the development of SiC devices to higher power levels.

[0003] Diamond is the material with the highest known thermal conductivity (theoretically up to 2200 W·m at room temperature). - ¹·K - ¹), and the composite substrate formed by combining it with SiC is considered an ideal solution to the heat dissipation problem of high-power devices. This structure can significantly reduce the thermal resistance of the device and improve the heat conduction efficiency from the active-oriented heat dissipation substrate, thereby significantly improving the operating stability and lifespan of the device. Theoretical studies have shown that the thickness of the SiC layer directly affects the heat dissipation performance of the composite substrate; the thinner the SiC layer, the shorter the heat conduction path and the higher the overall thermal conductivity. Therefore, reducing the SiC layer to the micrometer or even submicrometer level is a key approach to maximizing the heat dissipation performance of the composite substrate.

[0004] Although ultrathin SiC layers offer significant advantages in thermal management, the substantial differences in lattice constants and coefficients of thermal expansion between SiC and diamond lead to severe interfacial stress concentration when SiC layers are thinned to the micrometer or even submicrometer scale. This stress readily causes film cracking, warping, or delamination from the substrate, making the fabrication and processing of ultrathin SiC layers exceptionally difficult. Furthermore, existing fabrication methods struggle to achieve large-area, uniform, and stable ultrathin SiC / diamond composite structures while maintaining interfacial bonding quality and structural integrity, severely hindering the further development of high-performance power electronic devices. Summary of the Invention

[0005] The purpose of this invention is to provide a diamond-silicon carbide composite substrate, its preparation method, and its application, thereby overcoming the shortcomings of the prior art. By introducing a 3C-SiC buffer layer and optimizing the heterogeneous integration process, the overall performance and process stability of the diamond-silicon carbide composite substrate are significantly improved while achieving ultra-thin silicon carbide layers, which facilitates the large-scale preparation of large-size, uniform diamond-silicon carbide composite substrates.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows:

[0007] In a first aspect, the present invention provides a method for preparing a diamond-silicon carbide composite substrate, comprising the following steps: A nucleation dot array is obtained by coating SiC quantum dot sol on a silicon substrate and annealing it with pulsed laser. Then, a gradient buffer layer and a 3C-SiC thin film are deposited. A diamond layer is deposited on the 3C-SiC thin film, the silicon substrate and the gradient buffer layer are removed, and the surface of the 3C-SiC thin film is polished to obtain the final product.

[0008] The gradient buffer layer is a SiGeC gradient buffer layer with a thickness of 5-10 nm; the 3C-SiC thin film has a thickness of 0.5-5 μm.

[0009] This invention involves depositing a gradient buffer layer and a 3C-SiC thin film on a Si substrate, growing a diamond layer on the 3C-SiC thin film, removing the Si substrate through grinding, polishing, or etching, and then polishing the 3C-SiC thin film to remove the damaged layer, thereby obtaining an ultrathin 3C-SiC layer. Compared to traditional diamond-silicon carbide composite substrate preparation methods, this method can reduce the thickness of the silicon carbide layer, resulting in higher composite thermal conductivity and improved heat dissipation performance. Simultaneously, it avoids delamination issues caused by excessive thinning, thus yielding a complete composite substrate.

[0010] In some other embodiments, a single-crystal silicon substrate with a crystal orientation of (100) or (111) and a thickness of not less than 300 μm is used as the initial substrate; the surface of the silicon substrate is cleaned with a hydrofluoric acid (HF) solution to remove its natural oxide layer and form a hydrogen passivated surface, wherein the mass fraction of the HF solution is 1-2 wt%, preferably 1.5 wt%, and the cleaning time is 60 s. The surface of the silicon substrate is cleaned to remove the natural oxide layer and form the hydrogen passivated surface.

[0011] In some other embodiments, the gradient buffer layer is deposited as follows: At 600-700°C, a mixture of GeH4 and H2 gas is first introduced to pre-deposit a Ge seed layer with a thickness of 0.1-0.5 nm on the surface of a silicon substrate, wherein the GeH4 flow rate is controlled at 0.02-0.06 sccm and the H2 flow rate is 80-120 sccm; then, while maintaining a constant temperature, SiH4 and C2H2 gas are introduced to deposit a SiGeC gradient buffer layer on the Ge seed layer, wherein the SiH4 flow rate is 22-28 sccm and the C2H2 flow rate is 8-12 sccm.

[0012] Specifically, the gradient buffer layer is deposited at a temperature of 600, 650 or 700 °C, and the total thickness of the deposited gradient buffer layer is 5, 6, 7, 8, 9 or 10 nm.

[0013] More specifically, at a deposition temperature of 700°C, a mixture of GeH4 and H2 gas is introduced into the reaction chamber, wherein the flow rate of GeH4 is controlled at 0.02, 0.04, 0.05 or 0.06 sccm, and the flow rate of H2 is 80, 100 or 120 sccm, to pre-deposit a Ge atomic layer with a thickness of 0.2 nm on the surface of the silicon substrate. This ultrathin layer is used to suppress the diffusion of Si atoms in subsequent processes and to avoid island growth caused by excessive Ge thickness (e.g. ≥1 nm). Continuing Si-C layer deposition: After completing the Ge seed layer deposition, while maintaining a constant temperature, the original GeH4 / H2 gas is replaced with SiH4 and C2H2 gas, with a C2H2 flow rate of 10 sccm. By controlling the flow rate ratio of each gas and the deposition time, a SiGeC gradient buffer layer with a gradually changing chemical composition is deposited on the Ge seed layer. The SiGeC gradient buffer layer obtained through the above deposition process can gradually alleviate lattice mismatch and thermal mismatch between the substrate and the 3C-SiC epitaxial layer, suppressing the generation of dislocations and microcracks.

[0014] A gradient composition buffer layer from silicon to silicon carbide was constructed on a silicon substrate. This structure allows the lattice constant to smoothly transition from 5.43 Å in silicon to 4.36 Å in 3C-SiC, effectively alleviating the stress caused by approximately 20% of the lattice mismatch, avoiding the generation of interface dislocations and cracks, and laying a solid foundation for subsequent high-quality 3C-SiC thick film epitaxy.

[0015] In some other embodiments, the deposition method of 3C-SiC thin film is as follows: under conditions of 900-1200 °C and 100-500 mbar, SiH2Cl2, C2H2 and H2 are introduced as reactant gases, and a weak magnetic field (0.1-0.3 T) parallel to the substrate surface is applied simultaneously to improve the thickness uniformity or doping uniformity of the film in a specific direction, and to maintain the growth interface temperature difference at 500-600 °C.

[0016] In this process, SiH₂Cl₂ serves as a chlorinated silicon source, providing Si elements while simultaneously generating chlorides at high temperatures to suppress gas-phase nucleation and improve surface morphology. C₂H₂ acts as a carbon source to precisely control the C / Si ratio of the film. H₂, as both a carrier gas and a dilution gas, is continuously introduced at a high flow rate to stabilize the reaction environment and, in conjunction with the chlorides, to perform gentle in-situ etching of the growth surface. This achieves a high epitaxial growth rate while maintaining the flatness and density of the 3C-SiC film. This gas combination is used for 3C-SiC epitaxial growth under conditions where the back magnetic field and axial cooling system are activated, further improving plasma distribution and radial temperature uniformity, and reducing stress concentration caused by lattice / thermal mismatch.

[0017] Specifically, the 3C-SiC thin film is grown at temperatures of 900, 1000, 1100 or 1200 °C and pressures of 100, 150, 200, 250, 300, 350, 400, 450 or 500 mbar, by introducing SiH2Cl2, C3H8 and H2 reaction gases, while simultaneously applying a back magnetic field with an intensity of 0.2, 0.3 or 0.4 T, and maintaining the temperature difference at the growth interface at 500, 550 or 600 °C.

[0018] In some other embodiments, during the deposition of the 3C-SiC thin film, the introduction of reactive gas is interrupted every 1.5-2.5 μm of the 3C-SiC thin film thickness to perform an in-situ defect repair treatment. In-situ defect repair treatment employs a wavelength of 260-270 nm and an energy density of 0.3-0.6 J / cm². 2 The laser scans the growth surface while HCl is introduced simultaneously.

[0019] Specifically, when the 3C-SiC epitaxial layer grows to a thickness of 1.5, 2, or 2.5 μm, the reaction gas is interrupted, and an in-situ defect repair treatment is performed. The in-situ defect repair treatment uses wavelengths of 260, 265, or 270 nm and energy densities of 0.3, 0.4, 0.5, or 0.6 J / cm². 2A laser is used to scan the growth surface while HCl gas is simultaneously introduced. By controlling the number of growth and repair cycles, a 0.5-5 μm thick 3C-SiC single crystal film is finally obtained on a silicon substrate.

[0020] In some other embodiments, the spin-coating concentration of the SiC quantum dot sol is 10. 12 -10 13 cm -2 The laser wavelength for pulsed laser annealing is 350-360 nm, the pulse width is 3-6 ns, the annealing temperature is 1000-1200 ℃, and the annealing time is 30-60 s.

[0021] Specifically, the pulsed laser annealing uses a laser wavelength of 350, 355, or 360 nm, a pulse width of 3, 4, 5, or 6 ns, an annealing temperature of 1000, 1100, or 1200 °C, and an annealing time of 30, 40, 50, or 60 s. This process forms an array of SiC nucleation sites with a preferred {111} orientation on the surface of the silicon substrate.

[0022] In some other embodiments, the diamond layer is deposited by using a mixture of H2 and CH4 as the reaction gas source, wherein the CH4 volume concentration is 8%-12%, the substrate temperature is 800-1000 °C, the reaction pressure is 90-110 Torr, and the thickness of the diamond layer is 180-210 μm.

[0023] In some other embodiments, the surface can be treated with a nanodiamond particle suspension before diamond layer deposition to enhance nucleation density. Specifically, the 3C-SiC epitaxially grown substrate is placed in a suspension containing nanodiamond particles (0.1%–10% diamond powder of 1–2 micrometers by mass, 50%–80% pure water, and 6%–30% sodium hexametaphosphate dispersant) and ultrasonically treated; or the C-surface of SiC is first roughened with sandpaper and then placed in a nanodiamond suspension for 10–60 min to enhance the nucleation density of the subsequently deposited diamond layer.

[0024] In some other embodiments, the method for removing the silicon substrate is one of mechanical thinning-chemical etching, chemical etching, or electrochemical stripping.

[0025] Specifically, the mechanical thinning-chemical etching method involves first using precision mechanical grinding or polishing to uniformly thin the silicon substrate to approximately 60-75 μm; then using a selective etching solution to selectively remove the remaining silicon, with etching terminating at the 3C-SiC interface; the selective etching solution can be anisotropic etching using KOH with a concentration of 20-40%, or isotropic etching using a mixed solution of HNO3:HF:CH3COOH in a ratio of (5-7):1:1.

[0026] Chemical etching is used for silicon substrates with thin initial thickness or already patterned. It involves directly using KOH solution or a mixed etching solution with a volume ratio of HNO3:HF:CH3COOH of (5-7):1:1) to electrochemically etch the substrate, completely removing it in one go and avoiding damage that may be introduced by mechanical thinning.

[0027] Electrochemical stripping method: In a specific electrolyte (such as a mixed solution of HF:HC2H3O2:H2O), an anodic bias is applied to the silicon substrate to perform electrochemical etching. By taking advantage of the significant differences in electrochemical properties between 3C-SiC and silicon, the silicon layer can be stripped with high selectivity and high efficiency.

[0028] In some other embodiments, the thickness of the 3C-SiC layer in the diamond-silicon carbide composite substrate is 0.3-5 μm, and the surface roughness Ra < 0.2 nm.

[0029] Precision surface polishing: Precision chemical mechanical polishing (CMP) is performed on the exposed 3C-SiC thin film surface after removing the silicon substrate to remove surface damage layers, reduce surface roughness, and obtain an atomically smooth surface, providing a high-quality substrate for subsequent device fabrication. Either coarse polishing or fine polishing can be used. Coarse polishing involves initial mechanical polishing with diamond or alumina abrasive slurry to quickly remove larger surface undulations and damage layers. Fine polishing involves final precision chemical mechanical polishing with an alkaline polishing slurry of SiO2 or CeO2 colloidal suspension to control the surface roughness (Ra) below 0.2 nm, with a final roughness less than 0.5 nm.

[0030] To improve polishing efficiency, a slight reactive ion etching process using CF4 / O2 or Cl2 / BCl3 plasma can be performed before CMP to remove surface damage in advance, thereby reducing subsequent polishing time and consumable costs.

[0031] Post-treatment and planarization: To improve surface quality, high-temperature annealing smoothing and cleaning and drying processes can be employed. High-temperature annealing smoothing involves annealing at temperatures above 1000°C in a hydrogen or hydrogen-containing atmosphere. This utilizes the surface atomic migration effect to further reduce surface roughness and can be used as an auxiliary smoothing process after CMP. Cleaning and drying: After polishing, the wafer is thoroughly cleaned and dried using a cleaning machine and a rotary dryer to remove surface residues.

[0032] In a second aspect, the present invention provides a diamond-silicon carbide composite substrate, which is prepared by the diamond-silicon carbide composite substrate preparation method of the first aspect.

[0033] Thirdly, the present invention provides an application of the diamond-silicon carbide composite substrate of the second aspect in semiconductor devices.

[0034] The beneficial effects of this invention are: (1) The present invention introduces a 3C-SiC buffer layer and optimizes the preparation process, effectively thins and optimizes the interface of the 3C-SiC buffer layer, significantly improves the thermal conductivity of the composite substrate, which can reach up to 1700 W / (m·K), greatly enhances the heat dissipation capacity of the device under high power operation conditions, effectively suppresses the self-heating effect, thereby improving the power density, conversion efficiency and long-term reliability of the device.

[0035] (2) The 3C-SiC buffer layer effectively alleviates the lattice mismatch and thermal expansion difference between diamond and silicon carbide, significantly reduces the risk of cracking, warping or peeling of the ultrathin silicon carbide layer during preparation and subsequent processing, and improves the interfacial bonding strength and process yield of the composite structure.

[0036] (3) The preparation method of the present invention has a stable process route, good repeatability, and strong compatibility with existing semiconductor processes, providing a feasible technical path for the large-scale preparation of large-size, uniform diamond-silicon carbide composite substrates. Attached Figure Description

[0037] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0038] Figure 1 This is a schematic diagram of a novel method for preparing a diamond-silicon carbide composite substrate according to Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the Si substrate structure in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the structure after a gradient buffer layer is deposited on a Si substrate in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the structure after depositing a 3C-SiC single crystal thin film layer and growing a diamond layer on the gradient buffer layer in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the diamond-silicon carbide composite substrate after removing the Si substrate and gradient buffer layer in Embodiment 1 of the present invention; Figure 6 These are physical images of the diamond-silicon carbide composite substrates after substrate removal in Embodiment 1 and Comparative Example 3 of the present invention; wherein, a is an image of the diamond-silicon carbide composite substrate obtained in Embodiment 1, and b is an image of the diamond-silicon carbide composite substrate obtained in Comparative Example 3. in, Figures 2-5 The structure consists of: 1. a single-crystal silicon substrate, 2. a gradient buffer layer, 3. a 3C-SiC single-crystal thin film layer, and 4. a diamond layer. Detailed Implementation

[0039] Those skilled in the art will understand that the following embodiments are for illustrative purposes only and should not be construed as limiting the scope of the invention. Specific conditions not specified in the embodiments are performed under conventional conditions or conditions recommended by the manufacturer. Components whose manufacturers are not specified are all commercially available conventional products.

[0040] Example 1 This embodiment provides a diamond-silicon carbide composite substrate and its preparation method, the preparation method flow is as follows: Figure 1 As shown, the specific steps include: Step 1: The method for epitaxially growing 3C-SiC thin films on single-crystal silicon (Si) substrates comprises the following steps: S1. Substrate preparation and pretreatment: A single-crystal silicon substrate with a crystal orientation of (100) or (111) and a thickness of not less than 300 μm is used as the initial substrate (e.g., Figure 2 (As shown); the surface of the silicon substrate is cleaned with hydrofluoric acid (HF) solution to remove the native oxide layer and form a hydrogen-terminated passivated surface (H passivated surface).

[0041] S2. Preparation of nucleation point array: Spin-coating a concentration of 10 onto the H-passivated surface of the treated silicon substrate. 12 cm -2 The SiC quantum dot sol was then cured using a pulsed laser annealing process. The parameters of the pulsed laser annealing process were: laser wavelength 355 nm, pulse width 5 ns, annealing temperature 1100 ℃, and annealing time 45 s. This process formed an array of SiC nucleation points with a preferred orientation of {111} plane on the surface of the silicon substrate.

[0042] S3. Gradient Buffer Layer Deposition: A silicon substrate with a nucleation point array is placed in a chemical vapor deposition (CVD) reaction chamber. At a deposition temperature of 700°C, a mixture of GeH4 and H2 is introduced into the reaction chamber, with the GeH4 flow rate controlled at 0.05 sccm and the H2 flow rate at 100 sccm. A Ge atomic layer with a thickness of 0.2 nm is pre-deposited on the surface of the silicon substrate. This ultrathin layer is used to suppress the diffusion of Si atoms in subsequent processes and to avoid island growth caused by excessive Ge thickness (e.g., ≥1 nm). Continue depositing the Si-C layer: After completing the Ge seed layer deposition, while maintaining a constant temperature, replace the original GeH4 / H2 gas with SiH4 and C2H2 gas, where the C2H2 flow rate is 10 sccm. By controlling the flow rate ratio of each gas and the deposition time, continue depositing a SiGeC gradient buffer layer (8 nm thick) with a gradually changing chemical composition on the Ge seed layer. Figure 3(As shown). The SiGeC gradient buffer layer obtained by the above deposition process can gradually alleviate lattice mismatch and thermal mismatch between the substrate and the 3C-SiC epitaxial layer, and suppress the generation of dislocations and microcracks.

[0043] S4. Epitaxial growth and defect control of 3C-SiC thin films: After the gradient buffer layer deposition is completed, the temperature and pressure of the reaction chamber are maintained, and SiH2Cl2 (gas flow rate of 50 sccm), C2H2 (gas flow rate of 15 sccm) and H2 (gas flow rate of 20 sccm) are introduced as reaction gases to carry out the epitaxial growth of 3C-SiC thin films. During this growth period, a back magnetic field with an intensity of 0.3 T was applied simultaneously, and the axial cooling system was activated to maintain a temperature gradient of 550 °C at the growth interface. (T) When the growth thickness reaches 2 μm, the gas supply is interrupted, and an in-situ defect repair treatment is performed. This defect repair treatment uses a wavelength of 266 nm and an energy density of 0.5 J / cm². 2 The laser scans the growth surface, and HCl gas (flow rate 5 sccm) is introduced simultaneously. By controlling the number of growth and repair cycles, a 0.5 μm thick 3C-SiC single crystal film is finally obtained on the silicon substrate.

[0044] Step 2: The method for growing a highly thermally conductive diamond layer on a 3C-SiC thin film is as follows: S1. Substrate surface pretreatment: The 3C-SiC epitaxially grown substrate is placed in a suspension containing nanodiamond particles (composition as follows: 1.0 wt% diamond powder of 1-2 μm, 65.0 wt% pure water, and 30.0 wt% sodium hexametaphosphate dispersant) and ultrasonically treated; or the C-surface of SiC is roughened with sandpaper first, and then placed in the nanodiamond suspension and left to stand for 30 min to enhance the nucleation density of the subsequently deposited diamond layer.

[0045] S2. Depositing a diamond layer on the C-plane of a SiC substrate: The pretreated substrate is placed in a deposition apparatus, using a mixture of hydrogen and methane as the reaction gas source (where CH4 volume concentration is 10%), the substrate temperature is 900°C, and the reaction pressure is 100 Torr (approximately 133 mbar). A 200 μm thick polycrystalline diamond layer is grown on the 3C-SiC thin film using vapor deposition (e.g., ...). Figure 4 (As shown). Among them, the vapor deposition method can be microwave plasma chemical vapor deposition (MPCVD) or hot filament chemical vapor deposition (HFCVD).

[0046] Step 3: The method for removing the original Si substrate employs a combined mechanical and chemical approach to selectively remove the original silicon substrate, leaving only the epitaxial 3C-SiC thin film attached to the diamond layer, forming the final diamond-silicon carbide composite substrate (e.g., Figure 5 (As shown). The specific method for removing the original Si substrate can be mechanical thinning-chemical etching, with the following steps: First, the silicon substrate is uniformly thinned to about 75 μm using precision mechanical grinding or polishing; then, a selective etching solution is used to selectively remove the remaining silicon, with etching terminating at the 3C-SiC interface; the selective etching solution can be anisotropic etching using 30% KOH, or isotropic etching using a mixed solution of HNO3:HF:CH3COOH = 6:1:1.

[0047] Step 4: The method for precision polishing and post-processing of 3C-SiC thin film surface is as follows: S1. Precision Surface Polishing: Precision chemical mechanical polishing (CMP) is performed on the exposed 3C-SiC thin film surface after removing the silicon substrate to remove surface damage layers, reduce surface roughness, and obtain an atomically smooth surface, providing a high-quality substrate for subsequent device fabrication. Either coarse polishing or fine polishing can be used. Coarse polishing involves preliminary mechanical polishing using diamond or alumina abrasive slurry to quickly remove larger surface undulations and damage layers. Fine polishing involves final precision chemical mechanical polishing using an alkaline polishing slurry of SiO2 or CeO2 colloidal suspension to control the surface roughness (Ra) below 0.2 nm, with a surface roughness less than 0.5 nm.

[0048] To improve polishing efficiency, a slight reactive ion etching process using CF4 / O2 or Cl2 / BCl3 plasma can be performed before CMP to remove surface damage in advance, thereby reducing subsequent polishing time and consumable costs.

[0049] Post-treatment and planarization: To improve surface quality, high-temperature annealing smoothing and cleaning and drying processes can be employed. High-temperature annealing smoothing involves annealing at temperatures above 1000°C in a hydrogen or hydrogen-containing atmosphere. This utilizes the surface atomic migration effect to further reduce surface roughness and can be used as an auxiliary smoothing process after CMP. Cleaning and drying: After polishing, the wafer is thoroughly cleaned and dried using a cleaning machine and a rotary dryer to remove surface residues.

[0050] Ultimately, an ultrathin 3C-SiC single crystal film with a smooth surface and high crystal quality was obtained, with a final thickness of 0.3 μm. It was firmly attached to the high thermal conductivity diamond layer to form a high-performance diamond-silicon carbide composite substrate.

[0051] Example 2 Unlike Example 1, in step 1, the thickness of the deposited 3C-SiC single crystal film is 1 μm; in step 4, the thickness of the processed 3C-SiC single crystal film is 0.8 μm. Other preparation methods are the same as in Example 1.

[0052] Example 3 Unlike Example 1, in step 1, the thickness of the deposited 3C-SiC single crystal film is 5 μm; in step 4, the thickness of the processed 3C-SiC single crystal film is 4.7 μm. Other preparation methods are the same as in Example 1.

[0053] Comparative Example 1 A diamond with high thermal conductivity The specific steps for preparing SiC composite substrates are as follows: (1) After cleaning, the silicon carbide substrate with Ra < 0.2 nm was placed on the surface of the molybdenum stage. The surface temperature of the silicon carbide substrate was 950 °C, and etching was performed for 0.5 h in a hydrogen-oxygen plasma atmosphere (1% ≤ O2: H2 ≤ 4%). (2) Interfacial layer growth: Methane is used as the reactant gas, hydrogen is used as the carrier gas, and oxygen is used as the auxiliary gas. The amount of hydrogen is 300 sccm, the amount of methane is 5% of the amount of hydrogen, and the amount of oxygen is 0.1% of the amount of hydrogen. The growth temperature is 600℃ and the growth time is 2 h. The interfacial layer is obtained by growing on the silicon carbide substrate after etching by chemical vapor deposition. (3) Growth of polycrystalline diamond layer: Adjust the amount of methane, hydrogen and oxygen. The amount of hydrogen is 300 sccm, the amount of methane is 3% of the amount of hydrogen, and the amount of oxygen is 0.1% of the amount of hydrogen. In the process from step (2) to step (3), the temperature rise rate is 5 ℃ / min. The growth temperature reaches 950℃ and the growth continues. After the growth is completed, a polycrystalline diamond layer is obtained. The temperature is cooled at a rate of 2 ℃ / min to obtain a diamond-silicon carbide composite substrate with a diamond thickness of 200 μm and a silicon carbide thickness of 500 μm.

[0054] Comparative Example 2 Unlike Comparative Example 1, the silicon carbide substrate in the obtained diamond-silicon carbide composite substrate was thinned and polished to a silicon carbide thickness of 200 μm.

[0055] Comparative Example 3 Unlike Comparative Example 1, the silicon carbide substrate in the obtained diamond-silicon carbide composite substrate was thinned and polished to a silicon carbide thickness of 20 μm. However, peeling problems occurred during processing, resulting in damage to the silicon carbide layer.

[0056] Comparative Example 4 Unlike Example 1, in step 1, during the gradient buffer layer deposition process, the silicon substrate with the nucleation point array is placed in a chemical vapor deposition (CVD) reaction chamber. At a reaction chamber temperature of 700 °C, SiH4 (gas flow rate of 20 sccm) and C2H2 (gas flow rate of 5 sccm) reaction gases are introduced, thereby forming a gradient buffer layer with a total thickness of 8 nm on the substrate. Other preparation methods are consistent with Example 1.

[0057] Comparative Example 5 Unlike Example 1, in step 1, during the gradient buffer layer deposition process, the silicon substrate with the nucleation point array is placed in a chemical vapor deposition (CVD) reaction chamber. GeH4 (gas flow rate of 0.05 sccm) and H2 (gas flow rate of 5 sccm) reaction gases are introduced at a reaction chamber temperature of 700 °C, thereby forming a gradient buffer layer with a total thickness of 1 nm on the substrate. Other preparation methods are consistent with Example 1.

[0058] Comparative Example 6 Unlike Example 1, step 1 omits the preparation of the nucleation point array. Other preparation methods are the same as in Example 1.

[0059] Comparative Example 7 Unlike Example 1, in step 1, during the epitaxial growth and defect control of the 3C-SiC thin film, after the gradient buffer layer deposition is completed, the temperature and pressure of the reaction chamber are maintained, and the reaction gases are switched to C2H2 (gas flow rate of 15 sccm) and H2 (gas flow rate of 20 sccm) for the epitaxial growth of the 3C-SiC thin film. Other preparation methods are the same as in Example 1.

[0060] Comparative Example 8 Unlike Example 1, in step 1, during the epitaxial growth and defect control of the 3C-SiC thin film, after the gradient buffer layer deposition is completed, the temperature and pressure of the reaction chamber are maintained, and the reaction gases are switched to SiH2Cl2 (gas flow rate of 50 sccm) and H2 (gas flow rate of 20 slm) for the epitaxial growth of the 3C-SiC thin film. Other preparation methods are the same as in Example 1.

[0061] Comparative Example 9 Unlike Example 1, in step 1, the in-situ defect repair process is omitted in the epitaxial growth and defect control of the 3C-SiC thin film. Other preparation methods are the same as in Example 1.

[0062] Silicon carbide obtained in Examples 1-3 and Comparative Examples 1-9 The presence or absence of cracks in the diamond composite substrates was statistically analyzed. Then, the thermal conductivity of the uncracked composite substrates was tested using the laser flash method, following the ASTM E1461 standard or an equivalent test method. The test results are shown in Table 1.

[0063] Table 1. Thermal conductivity test results of the composite substrate.

[0064] In Table 1, " / " indicates that the sample was not detected or could not be detected.

[0065] Compared with Example 1, the thermal conductivity of the composite substrate obtained in Example 2 is slightly lower. This is because the deposition thickness and the thickness retained after processing of the 3C-SiC single crystal film in Example 2 are both higher than those in Example 1. As the thickness of the silicon carbide layer increases, the residual stress at the interface and the number of micro-defects increase accordingly, which has a certain scattering effect on phonon transmission, resulting in a decrease in the overall thermal conductivity.

[0066] Compared with Example 1, the thermal conductivity of the composite substrate obtained in Example 3 is further reduced. This is because the thickness of the 3C-SiC single crystal film is significantly increased in Example 3, the accumulated thermal mismatch stress and crystal defects inside the film are further increased, the interface thermal resistance is increased, and the phonon scattering is enhanced, which in turn has a more obvious adverse effect on the thermal conductivity of the composite substrate.

[0067] Compared with Example 1, Comparative Example 1 did not have a gradient component buffer layer and nucleation point array structure, making it difficult to effectively release interfacial thermal stress, resulting in a significant reduction in the thermal conductivity of the obtained composite substrate.

[0068] Compared with Example 1, although Comparative Example 2 reduced the thermal resistance to some extent by thinning the silicon carbide substrate, its thermal conductivity was still significantly lower than that of Example 1 due to the lack of a gradient buffer layer to regulate the interface stress.

[0069] Compared with Example 1, Comparative Example 3 experienced peeling and breakage during the further thinning of the silicon carbide substrate, and the composite substrate cracked, making it impossible to conduct thermal conductivity tests. This indicates that the structural stability of the composite substrate is significantly reduced when there is no gradient buffer layer and stress regulation structure.

[0070] Compared with Example 1, Ge element was not introduced into the gradient buffer layer of Comparative Example 4, and the interface lattice mismatch was not adequately alleviated, resulting in enhanced interface scattering and a significantly lower thermal conductivity than that of Example 1.

[0071] Compared with Example 1, Si element was not introduced into the gradient buffer layer of Comparative Example 5. The coherence matching between the buffer layer and the subsequent SiC epitaxial layer was insufficient, and the interface defect density was high, resulting in a lower thermal conductivity than that of Example 1.

[0072] Compared with Example 1, Comparative Example 6 omitted the preparation of the nucleation point array, which led to stress concentration during the subsequent epitaxial growth process, causing cracks in the composite substrate and making it impossible to obtain a complete structure.

[0073] Compared with Example 1, Comparative Example 7 uses C2H2 as a carbon source for 3C-SiC epitaxial growth, resulting in a relatively high defect density and enhanced phonon scattering, while its thermal conductivity is lower than that of Example 1.

[0074] Compared with Example 1, Comparative Example 8 used SiH2Cl2 as the silicon source for 3C-SiC epitaxial growth. The halogen-related defects introduced during the growth process had an adverse effect on thermal conductivity, and its thermal conductivity was lower than that of Example 1.

[0075] Compared with Example 1, Comparative Example 9 omitted in-situ defect repair during the 3C-SiC thin film epitaxy process, which led to defect accumulation and structural instability, causing cracking of the composite substrate.

[0076] Depend on Figure 6 As can be seen from 'a' in Example 1, the silicon carbide-diamond composite substrate prepared in Example 1 has a complete structure and no cracks were observed; while Figure 6 As can be seen in b, the silicon carbide-diamond composite substrate prepared in Comparative Example 1 showed cracking. This demonstrates that the present invention can achieve a high-strength bond between an ultrathin silicon carbide layer and diamond, resulting in a composite substrate with low interfacial thermal resistance and good structural integrity.

[0077] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for preparing a diamond-silicon carbide composite substrate, characterized in that, Includes the following steps: SiC quantum dot sol is coated on a silicon substrate and nucleation dot array is obtained by pulsed laser annealing. Gradient buffer layer, 3C-SiC film and diamond layer are deposited in sequence. The silicon substrate and gradient buffer layer are removed and the surface of 3C-SiC film is polished to obtain the final product. The deposition method of the gradient buffer layer is as follows: At 600-700℃, a mixed gas of GeH4 and H2 is first introduced to pre-deposit a Ge seed layer with a thickness of 0.1-0.5 nm on the surface of a silicon substrate, wherein the flow rate of GeH4 is 0.02-0.06 sccm and the flow rate of H2 is 80-120 sccm; then, while keeping the temperature constant, SiH4 and C2H2 gases are introduced to deposit a SiGeC gradient buffer layer on the Ge seed layer, wherein the flow rate of SiH4 is 22-28 sccm and the flow rate of C2H2 is 8-12 sccm. The deposition method of 3C-SiC thin film is as follows: SiH2Cl2, C2H2 and H2 are introduced as reaction gases at 900-1200 ℃ and 100-500 mbar, a magnetic field parallel to the substrate surface is applied simultaneously, and the temperature difference at the growth interface is maintained at 500-600 ℃, and the magnetic field strength is 0.1-0.3T. The gradient buffer layer is a SiGeC gradient buffer layer with a thickness of 5-10 nm. The thickness of the 3C-SiC thin film is 0.5-5 μm.

2. The method for preparing a diamond-silicon carbide composite substrate according to claim 1, characterized in that, During the deposition of 3C-SiC thin films, when the 3C-SiC thin film grows to a thickness of 1.5-2.5 μm, the reaction gas is interrupted and an in-situ defect repair treatment is performed. The in-situ defect repair treatment uses a wavelength of 260-270 nm and an energy density of 0.3-0.6 J / cm². 2 The laser scans the growth surface while HCl is introduced simultaneously.

3. The method for preparing a diamond-silicon carbide composite substrate according to claim 1, characterized in that, The spin-coating concentration of SiC quantum dot sol is 10. 12 -10 13 cm -2 ; The pulsed laser annealing uses a laser wavelength of 350-360 nm, a pulse width of 3-6 ns, an annealing temperature of 1000-1200 ℃, and an annealing time of 30-60 s.

4. The method for preparing a diamond-silicon carbide composite substrate according to claim 1, characterized in that, The method for depositing the diamond layer is as follows: a mixture of H2 and CH4 is used as the reaction gas source, wherein the volume concentration of CH4 is 8%-12%, the substrate temperature is 800-1000 °C, and the reaction pressure is 90-110 Torr; The thickness of the diamond layer is 180-210 μm.

5. The method for preparing a diamond-silicon carbide composite substrate according to claim 1, characterized in that, The method for removing the silicon substrate and gradient buffer layer is one of mechanical thinning-chemical etching, chemical etching, or electrochemical stripping.

6. The method for preparing a diamond-silicon carbide composite substrate according to claim 1, characterized in that, The thickness of the 3C-SiC layer in the diamond-silicon carbide composite substrate is 0.3-5 μm, and the surface roughness Ra < 0.2 nm.

7. A diamond-silicon carbide composite substrate, characterized in that, The diamond-silicon carbide composite substrate was prepared using the method described in any one of claims 1-6.

8. The application of the diamond-silicon carbide composite substrate of claim 7 in a semiconductor device.

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