Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a preparation method thereof, and relates to the technical field of integrated circuits, comprising: a substrate, the substrate comprising a first type of well region, a top surface of the well region comprising a gate oxide layer and a T-shaped conductive layer located on a side of the gate oxide layer facing away from the substrate; an outer sidewall and a bottom surface of the T-shaped conductive layer being covered with a work function layer; the T-shaped conductive layer comprising a horizontal portion and a protruding portion, the protruding portion sequentially contacting the top surface of the well region via the work function layer and the gate oxide layer; the horizontal portion being circumferentially surrounded by a sidewall; an air gap being included between the sidewall and the gate oxide layer; wherein a second type of source region / drain region is included in the well region outside the sidewall. At least the lateral breakdown voltage of the MOS device can be increased, the leakage current of the device can be reduced, and the reliability of the device can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit manufacturing technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the rapid development of semiconductor technology, the market demands higher and higher integration levels for integrated circuits, resulting in shorter and shorter channel lengths for MOS devices. This leads to problems such as increased leakage current, increased power consumption, and decreased performance in MOS devices.

[0003] Therefore, how to increase the lateral breakdown voltage of MOS devices, reduce the leakage current, and improve the reliability of MOS devices while shortening the channel is one of the technical problems that relevant researchers urgently need to solve. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems mentioned in the background art, which can at least increase the lateral breakdown voltage of the MOS device, reduce the leakage current of the device, and improve the reliability of the device while keeping the integration density unchanged and shortening the channel of the MOS device.

[0005] According to various embodiments of the present disclosure, a first aspect of the present disclosure provides a semiconductor structure including a substrate, the substrate including a first type well region, the top surface of the well region including a gate oxide layer and a T-type conductive layer located on the side of the gate oxide layer facing away from the substrate; the outer sidewall and bottom surface of the T-type conductive layer are covered with an active function layer; the T-type conductive layer includes a horizontal portion and a protrusion portion, the protrusion portion contacting the top surface of the well region sequentially via the active function layer and the gate oxide layer; the horizontal portion is circumferentially surrounded by a sidewall; an air gap is included between the sidewall and the gate oxide layer; wherein, the well region outside the sidewall includes a second type source / drain region.

[0006] In some embodiments, an air gap surrounds the gate oxide layer, such that the sidewalls are isolated from the protrusions via the air gap surrounding the gate oxide layer / protrusions in the circumferential direction, and that a portion of the horizontal portion is isolated from the channel via an air gap. By adding air gaps in both the lateral and longitudinal directions of the MOS device, the lateral and longitudinal capacitances can be reduced simultaneously, the RC delay can be reduced, and the gate control capability of the device can be improved.

[0007] In some embodiments, the ratio of the dimension of the horizontal portion along the first direction to the dimension of the gate oxide layer along the first direction is located in [1.17, 2], wherein the first direction is parallel to the top surface of the substrate. This avoids both reducing device reliability due to the gate oxide layer being too small along the first direction and reducing the size of the air gap due to the gate oxide layer being too large along the first direction.

[0008] In some embodiments, the substrate further includes a second type of well region, and the first type of well region and the second type of well region are isolated by a trench isolation portion; the protrusion in the first type of well region includes a first type of metal work function layer, a first etch stop layer and a second type of metal work function layer stacked sequentially in a direction away from the substrate; in the first type of well region, the first etch stop layer of the protrusion is located in the closed space enclosed by the first metal work function layer and the second metal work function layer.

[0009] In some embodiments, the protrusion in the second type well region includes a first metal work function layer of the second type, a first etch stop layer, and a third metal work function layer of the first type stacked sequentially along the direction away from the substrate; in the second type well region, the first etch stop layer of the protrusion is located within the closed space enclosed by the first metal work function layer and the third metal work function layer.

[0010] In some embodiments, a second aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0011] A substrate including a first type of well region is provided. The top surface of the well region includes a gate oxide layer and a sacrificial layer stacked sequentially in a direction away from the substrate. The orthogonal projection of the gate oxide layer onto the bottom surface of the sacrificial layer is located inside the bottom surface of the sacrificial layer.

[0012] Thermal oxidation forms a dielectric layer that covers the exposed surface of the sacrificial layer and the exposed surface of the trap region;

[0013] A sidewall material layer covering the dielectric layer is deposited; an air gap is formed between the sidewall material layer and the gate oxide layer.

[0014] Simultaneously remove the sidewall material layer and dielectric layer on the top surface of the sacrificial layer and the top surface of the well region; the remaining sidewall material layer constitutes the sidewall.

[0015] A type II source / drain region is formed in the well region surrounding the sidewalls, and a dielectric layer with its top surface flush with the top surface of the sacrificial layer is formed on the substrate;

[0016] Remove the T-shaped sacrificial layer to obtain the target groove;

[0017] After the functional layer is formed in the target groove, a T-shaped conductive layer is formed to fill the target groove.

[0018] In the semiconductor structure fabrication method described in the above embodiments, by setting the orthogonal projection of the gate oxide layer on the bottom surface of the sacrificial layer to be within the bottom surface of the sacrificial layer, a dielectric layer is formed by thermal oxidation to cover the exposed surface of the sacrificial layer and the exposed surface of the well region, making the remaining sacrificial layer T-shaped. A sidewall material layer covering the dielectric layer is deposited, forming an air gap between the sidewall material layer and the gate oxide layer. Simultaneously, the sidewall material layer and dielectric layer on the top surface of the sacrificial layer and the top surface of the well region are removed, and the remaining sidewall material layer constitutes the sidewall. After forming a second-type source / drain region in the well region outside the sidewall, a dielectric layer with its top surface flush with the top surface of the sacrificial layer is formed on the substrate. After removing the T-shaped sacrificial layer, the target trench is obtained. After forming a parabolic work function layer in the target trench, a T-shaped conductive layer filling the target trench is formed. The T-type conductive layer includes a horizontal portion and a protruding portion. The protruding portion sequentially connects to the top surface of the well region via the work function layer and the gate oxide layer. The horizontal portion is surrounded by sidewalls, and an air gap exists between the sidewalls and the gate oxide layer. This allows the outer wall and bottom surface of the T-type conductive layer to be covered with a parabolic work function layer, thereby increasing the lateral breakdown voltage of the MOS device. The addition of air gaps in both the lateral and vertical directions of the MOS device can simultaneously reduce the lateral and vertical capacitance, reduce RC delay, and improve the gate control capability of the device. A boss-shaped channel structure can be formed in the well region below the T-type conductive layer. This can reduce the leakage current of the device, increase the lateral breakdown voltage of the MOS device, and improve the reliability of the device, at least while maintaining the same integration density and shortening the channel of the MOS device.

[0019] In some embodiments, the ratio of the dimension of the sacrificial layer along the first direction to the dimension of the gate oxide layer along the first direction is located in [1.17, 2], wherein the first direction is parallel to the top surface of the substrate. This avoids both reducing device reliability due to the gate oxide layer being too small along the first direction and reducing the size of the air gap due to the gate oxide layer being too large along the first direction.

[0020] In some embodiments, the sacrificial layer includes polysilicon; the dielectric layer includes silicon oxide; the top surface of the silicon oxide at the bottom of the sacrificial layer is higher than the top surface of the gate oxide layer, so that after thermal oxidation to form a dielectric layer covering the exposed surface of the sacrificial layer and the exposed surface of the well region, the remaining sacrificial layer is T-shaped, so that after removing the T-shaped sacrificial layer, the target trench is obtained.

[0021] In some embodiments, the substrate further includes a second type well region, wherein the first type well region and the second type well region are isolated from each other via a trench isolation portion; after the sidewalls are formed and before the source / drain regions are formed, the substrate further includes:

[0022] A first patterned photoresist layer is formed on a substrate, and the first patterned photoresist layer exposes a second type well region;

[0023] A first-type extended region was formed in the second-type well region on the periphery of the sidewall using a first-stage light-doped drain ion implantation process.

[0024] After removing the first patterned photoresist layer, a second patterned photoresist layer is formed on the substrate, and the second patterned photoresist layer exposes the first type-well region.

[0025] A second type extended region is formed in the first type well region on the periphery of the sidewall using a second lightly doped drain ion implantation process.

[0026] Remove the second patterned photoresist layer.

[0027] In some embodiments, a success function layer is formed within the target slot, including:

[0028] After depositing dielectric material in the target trench, a type II first metal work function layer is deposited on the dielectric material;

[0029] A first etch stop layer is formed on the first metal work function layer using atomic layer deposition (ALD) technology.

[0030] A second type of second metal work function layer is deposited on the first etch stop layer; wherein, the portion of the first etch stop layer located at the bottom of the target trench is located within the sealed space enclosed by the first metal work function layer and the second metal work function layer;

[0031] After forming a sacrificial material layer that fills the target trench, a third patterned photoresist layer is formed on the sacrificial material layer;

[0032] Based on the third patterned photoresist layer and the sacrificial material layer, the sacrificial material layer in the target trench of the second type of well region is etched and removed.

[0033] Etch and remove the second metal work function layer within the target trench in the second type of well region;

[0034] Remove the third patterned photoresist layer and the remaining sacrificial material layer;

[0035] A third metal work function layer of the first type is deposited in the target trench using atomic layer deposition technology; wherein, a portion of the first etch stop layer located at the bottom of the target trench in the second type trap region is located within the sealed space enclosed by the first metal work function layer and the third metal work function layer.

[0036] In some embodiments, after forming the source / drain region and before forming the dielectric layer, the method further includes the step of forming electrical contacts within the source / drain region:

[0037] Plasma at a target temperature is generated using a fluorine- and ammonia-containing mixed gas under radio frequency power.

[0038] By utilizing plasma at the target temperature to react with silicon oxide on the substrate surface, a target compound that is easily sublimated is generated, thereby achieving pretreatment of the well region surface;

[0039] Nickel-platinum compound is deposited on the surface of the pretreated well region;

[0040] Titanium nitride is deposited on nickel-platinum compounds;

[0041] The first heat treatment involves titanium nitride and nickel-platinum compounds to form the first metal silicide.

[0042] The second heat treatment of the first metal silicide generates a second metal silicide with an impedance value lower than that of the first metal silicide. The deposited nickel is removed, and the second metal silicide is used to form an electrical contact.

[0043] The unexpected technical effects that can be produced by the embodiments of this disclosure include:

[0044] The T-type conductive layer includes a horizontal portion and a protruding portion. The protruding portion sequentially connects to the top surface of the well region via the work function layer and the gate oxide layer. The horizontal portion is surrounded by sidewalls, and an air gap exists between the sidewalls and the gate oxide layer. This allows the outer wall and bottom surface of the T-type conductive layer to be covered with a parabolic work function layer, thereby increasing the lateral breakdown voltage of the MOS device. The addition of air gaps in both the lateral and vertical directions of the MOS device can simultaneously reduce the lateral and vertical capacitance, reduce RC delay, and improve the gate control capability of the device. A boss-shaped channel structure can be formed in the well region below the T-type conductive layer. This can reduce the leakage current of the device, increase the lateral breakdown voltage of the MOS device, and improve the reliability of the device, at least while maintaining the same integration density and shortening the channel of the MOS device. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 The diagram shown is a flowchart illustrating a semiconductor structure fabrication method provided in one embodiment of this disclosure.

[0047] Figure 2 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a deep well region in step S10 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0048] Figure 3 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a trench isolation portion in step S10 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0049] Figure 4The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a first patterned photoresist layer in step S10 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0050] Figure 5 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a second patterned photoresist layer in step S10 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0051] Figure 6 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a sacrificial material layer in step S10 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0052] Figure 7 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after the gate oxide layer is formed in step S10 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0053] Figure 8 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a dielectric layer in step S20 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0054] Figure 9 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a sidewall material layer in step S30 of a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0055] Figure 10 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming an air gap in a semiconductor structure fabrication method provided in one embodiment of this disclosure.

[0056] Figure 11 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a first patterned photoresist layer in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0057] Figure 12 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a second patterned photoresist layer in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0058] Figure 13 The diagram shown is a longitudinal cross-sectional view of the semiconductor structure obtained after forming a second type extended region in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0059] Figure 14The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming the source / drain region in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0060] Figure 15 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming electrical contacts in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0061] Figure 16 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a dielectric layer in a semiconductor structure fabrication method provided in one embodiment of this disclosure.

[0062] Figure 17 The diagram shown is a longitudinal cross-sectional view of the semiconductor structure obtained after forming a first metal work function layer in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0063] Figure 18 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a second metal work function layer in a semiconductor structure fabrication method provided in one embodiment of this disclosure.

[0064] Figure 19 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a third patterned photoresist layer in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0065] Figure 20 The diagram shows a longitudinal cross-sectional view of the semiconductor structure obtained after forming a third metal work function layer in a semiconductor structure fabrication method provided in an embodiment of this disclosure.

[0066] Figure 21 The diagram shown is a schematic diagram of the longitudinal section of a semiconductor structure obtained after forming a T-type conductive layer in a semiconductor structure fabrication method provided in one embodiment of this disclosure.

[0067] 100. Substrate; 20. Deep well region; 101. Dielectric material; 102. First metal work function layer; 103. First etch stop layer; 104. Second metal work function layer; 301. Hard mask layer; PR31. Third patterned photoresist layer; 105. Third metal work function layer; 10. Work function layer; 200. Target trench; 30. Pad layer; 31. Gate oxide layer; 300. T-type conductive layer; 301. Horizontal portion; 302. Protrusion; 40. Trench isolation area; PR1. First patterned photoresist layer; PR2. Second patterned photoresist layer; 410. Sacrificial material layer; 41. Sacrificial layer; 50. Dielectric layer; 61. Sidewall material layer; 60. Sidewall; 70. Air gap; PR11. First patterned photoresist layer; NLDD. First type extended region; PR21. Second patterned photoresist layer; PLDD. Second type extended region; 80. Electrical contact; 90. Dielectric layer. Detailed Implementation

[0068] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0070] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0071] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0072] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0073] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0074] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0075] In the embodiments of this disclosure, "stacked" or "layered structure" can refer to one or more layers.

[0076] Please see Figure 1 In some embodiments, a method for fabricating a semiconductor structure is provided, comprising: steps S10-S70, wherein:

[0077] Step S10: Provide a substrate including a first type of well region. The top surface of the well region includes a gate oxide layer and a sacrificial layer stacked sequentially in a direction away from the substrate. The orthographic projection of the gate oxide layer on the bottom surface of the sacrificial layer is located inside the bottom surface of the sacrificial layer.

[0078] Step S20: Thermal oxidation forms a dielectric layer covering the exposed surface of the sacrificial layer and the exposed surface of the well region;

[0079] Step S30: Deposit to form a sidewall material layer covering the dielectric layer; form an air gap between the sidewall material layer and the gate oxide layer;

[0080] Step S40: Simultaneously remove the sidewall material layer and dielectric layer on the top surface of the sacrificial layer and the top surface of the well region; the remaining sidewall material layer constitutes the sidewall.

[0081] Step S50: Form a type II source / drain region in the well region surrounding the sidewalls, and form a dielectric layer on the substrate with its top surface flush with the top surface of the sacrificial layer;

[0082] Step S60: Remove the T-shaped sacrificial layer to obtain the target groove;

[0083] Step S70: After forming a functional layer in the target groove, a T-shaped conductive layer is formed to fill the target groove.

[0084] Please continue reading. Figure 1 By setting the orthogonal projection of the gate oxide layer on the bottom surface of the sacrificial layer to be inside the bottom surface of the sacrificial layer, thermal oxidation is used to form a dielectric layer covering the exposed surface of the sacrificial layer and the exposed surface of the well region, making the remaining sacrificial layer T-shaped. A sidewall material layer covering the dielectric layer is deposited, creating an air gap between the sidewall material layer and the gate oxide layer. Simultaneously, the sidewall material layer and dielectric layer on the top surface of the sacrificial layer and the top surface of the well region are removed, and the remaining sidewall material layer constitutes the sidewall. After forming a type II source / drain region in the well region outside the sidewall, a dielectric layer with its top surface flush with the top surface of the sacrificial layer is formed on the substrate. After removing the T-shaped sacrificial layer, the target trench is obtained. After forming a parabolic work function layer in the target trench, a T-shaped conductive layer filling the target trench is formed. The T-type conductive layer includes a horizontal portion and a protruding portion. The protruding portion sequentially connects to the top surface of the well region via the work function layer and the gate oxide layer. The horizontal portion is surrounded by sidewalls, and an air gap exists between the sidewalls and the gate oxide layer. This allows the outer wall and bottom surface of the T-type conductive layer to be covered with a parabolic work function layer, thereby increasing the lateral breakdown voltage of the MOS device. The addition of air gaps in both the lateral and vertical directions of the MOS device can simultaneously reduce the lateral and vertical capacitance, reduce RC delay, and improve the gate control capability of the device. A boss-shaped channel structure can be formed in the well region below the T-type conductive layer. This can reduce the leakage current of the device, increase the lateral breakdown voltage of the MOS device, and improve the reliability of the device, at least while maintaining the same integration density and shortening the channel of the MOS device.

[0085] Please see Figure 2 In some embodiments, the material of the substrate 100 provided in step S10 may include, but is not limited to, semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 100 is a semiconductor structure that provides mechanical support and electrical properties for fabricating a semiconductor structure. The substrate 100 may be a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a III / V semiconductor substrate or a II / VI semiconductor substrate. Those skilled in the art can select the type of substrate 100 according to the type of transistors formed on the substrate 100; therefore, the type of substrate 100 should not limit the scope of protection of this disclosure.

[0086] Please see Figure 2In some embodiments, in step S10, a spacer layer 30 may be grown on the top surface of the substrate 100 using a furnace tube process. The material of the spacer layer 30 may include silicon oxide. Then, an ion implantation process can be performed into the substrate 100 based on the spacer layer 30 to generate a deep well region 20. The thickness of the spacer layer 30 may be 50 angstroms to 60 angstroms. For example, the thickness of the spacer layer 30 may be 50 angstroms, 55 angstroms, or 60 angstroms. The spacer layer 30 can prevent damage to the substrate 100 during ion implantation to form the deep well region 20.

[0087] Please see Figure 3 In some embodiments, in step S10, a shallow trench (not shown) can be formed within the deep well region 20 using a dry etching process, with the bottom surface of the shallow trench higher than the bottom surface of the deep well region 20. After forming the shallow trench, an oxide material layer can be formed on the inner surface of the shallow trench using a furnace tube process to repair surface damage caused during the etching of the shallow trench. Then, a deposition process is used to fill the shallow trench with oxide material, and the top surface of the oxide material is planarized to obtain a trench isolation portion 40 with its top surface flush with the top surface of the pad layer 30. The oxide material may include silicon oxide.

[0088] Please see Figure 4 In some embodiments, in step S10, a first patterned photoresist layer PR1 is formed on the top surface of the pad layer 30. The first patterned photoresist layer PR1 includes a first opening pattern for defining parameters such as the shape, position, and size of the first type-well region. Based on the first patterned photoresist layer PR1 and the pad layer 30, an ion implantation process is performed on the deep well region 20 to form a first type-well region, such as an NW (N-Well), within the deep well region 20.

[0089] Please see Figure 5 In some embodiments, in step S10, a second patterned photoresist layer PR2 is formed on the top surface of the pad layer 30. The second patterned photoresist layer PR2 includes a second opening pattern for defining parameters such as the shape, position, and size of the second type well region. Based on the second patterned photoresist layer PR2 and the pad layer 30, an ion implantation process is performed on the deep well region 20 to form a second type well region, such as a PW (P-Well), within the deep well region 20.

[0090] Please see Figure 6 In some embodiments, in step S10, a sacrificial material layer 410 covering the pad layer 30 is formed. The sacrificial material layer 410 and the pad layer 30 are patterned to obtain an initial stack (not shown) located on the top surfaces of the first type well region and the second type well region, and spaced apart along a first direction. The initial stack includes the pad layer 30 and the sacrificial material layer 410 stacked sequentially along the direction away from the substrate 100.

[0091] Please see Figure 7In some embodiments, in step S10, the pad layer 30 can be selectively etched laterally using a wet process, and the remaining pad layer 30 forms the gate oxide layer 31. The orthographic projection of the gate oxide layer 31 onto the bottom surface of the sacrificial layer 41 is located within the bottom surface of the sacrificial layer 41.

[0092] Please continue reading. Figure 7 In some embodiments, the ratio of the dimension of the sacrificial layer 41 along a first direction parallel to the top surface of the substrate 100 to the dimension of the gate oxide layer 31 along the first direction can be set to [1.17, 2], where the first direction is parallel to the top surface of the substrate 100. For example, the ratio of the dimension of the sacrificial layer 41 along the first direction parallel to the top surface of the substrate 100 to the dimension of the gate oxide layer 31 along the first direction can be set to 1.17, 1.20, 1.27, 1.30, 1.38, 1.48, 1.58, 1.68, 1.78, 1.88, 1.98, or 2, etc. This avoids both reducing device reliability due to an excessively small dimension of the gate oxide layer 31 along the first direction and reducing the size of the air gap 70 due to an excessively large dimension of the gate oxide layer 31 along the first direction.

[0093] Please see Figure 8 In some embodiments, in step S20, a rapid thermal oxidation (RTP) process can be used to thermally oxidize and form a dielectric layer 50 covering the exposed surface of the sacrificial layer 41 and the exposed surface of the well region; the well region includes a first type well region and a second type well region.

[0094] Please continue reading. Figure 8 In some embodiments, the sacrificial layer 41 comprises polysilicon; the dielectric layer 50 comprises silicon oxide; the exposed sacrificial layer 41 is thermally oxidized, consuming a portion of the sacrificial layer 41, and silicon oxide is formed on the exposed outer surface of the sacrificial layer 41. The top surface of the silicon oxide formed on the exposed lower surface of the sacrificial layer 41 by thermal oxidation is higher than the top surface of the gate oxide layer 31, so that after the dielectric layer 50 covering the exposed surface of the sacrificial layer 41 and the exposed surface of the well region is formed by thermal oxidation, the remaining sacrificial layer 41 is T-shaped, and the target trench is obtained after removing the T-shaped sacrificial layer 41.

[0095] Please see Figure 9 In some embodiments, in step S30, a chemical vapor deposition (CVD) process can be performed at a low pressure of 0.1 Torr-5 Torr and a reaction temperature of 300°C-900°C to form a sidewall material layer 61 covering the dielectric layer 50. Low-pressure CVD offers high uniformity, high purity, and excellent step coverage, creating an air gap 70 between the sidewall material layer 61 and the gate oxide layer 31. The sidewall material layer 61 comprises silicon nitride.

[0096] Please see Figure 10 In some embodiments, step S40 may employ a dry etching process to simultaneously remove the sidewall material layer 61 and dielectric layer 50 from the top surface of the sacrificial layer 41 and the top surface of the well region. The remaining sidewall material layer 61 constitutes the sidewall 60. The dielectric layer 50 on the top surface of the well region can protect the well region from surface damage during the etching process to form the sidewall 60. The well region may include one or more of a first-type well region or a second-type well region.

[0097] Please continue reading. Figure 10 In some embodiments, the air gap 70 surrounds the gate oxide layer 31, so that the sidewall 60 is isolated from the gate oxide layer 31 via the air gap 70 surrounding the gate oxide layer 31 in a circumferential manner. This increases the effective volume of the air gap 70, which helps to reduce the lateral and longitudinal capacitances simultaneously, reduce RC delay, and improve the gate control capability of the device.

[0098] Please see Figures 11-12 In some embodiments, after the sidewall 60 is formed and before the source / drain region is formed, the method further includes:

[0099] Step S401: A first patterned photoresist layer PR11 is formed on the substrate 100, and the first patterned photoresist layer PR11 exposes the second type well region;

[0100] Step S402: A first-type extended region NLDD is formed in the second-type well region surrounding the sidewall 60 using a first light-doped drain ion implantation process;

[0101] Step S403: After removing the first patterned photoresist layer PR11, a second patterned photoresist layer PR21 is formed on the substrate 100, and the second patterned photoresist layer PR21 exposes the first type well region.

[0102] Step S404: A second type extended region PLDD is formed in the first type well region surrounding the sidewall 60 using a second lightly doped drain ion implantation process;

[0103] Step S405: Remove the second patterned photoresist layer PR21.

[0104] Please continue reading. Figure 11 In some embodiments, the first patterned photoresist layer PR11 precisely covers the first type-1 well region (i.e., the subsequent PMOS region), while exposing the second type-2 well region (i.e., the NMOS region). Using the first patterned photoresist layer PR11 as a mask, a first lightly doped drain ion implantation is performed, for example, using an N-type dopant, typically arsenic or phosphorus ions, at a medium-low energy (e.g., 5keV-20keV) and a medium-low dose (e.g., 1×10⁻⁶). 13 cm -2 –5×10 14 cm -2This ensures the formation of a shallow junction on the surface of the Type II well region surrounding the sidewall 60. A small-angle (e.g., 0 or 7 degrees) tilt injection is used to allow the dopant to extend below the gate edge, forming a Type I lightly doped extended region (NLDD). The Type I extended region NLDD, acting as a source / drain extension, smooths the electric field gradient between the channel and the heavily doped source / drain regions, significantly suppressing short-channel effects and device degradation caused by hot carrier injection.

[0105] Please continue reading. Figure 12 In some embodiments, the first patterned photoresist layer PR11 used in step S401 can be completely removed by ashing or wet stripping processes. The photoresist is then recoated, and a second patterned photoresist layer PR21 is formed by a second photolithography step. The second patterned photoresist layer PR21 covers the second type-2 well region (NMOS region) where the first type-1 lightly doped extended region NLDD implantation has been completed, while exposing the first type-1 well region (PMOS region). Using the second patterned photoresist layer PR21 as a mask, a second lightly doped drain ion implantation is performed, for example, using a P-type dopant, typically boron or boron fluoride, with appropriate energy and dose (e.g., boron energy 5keV-15keV, dose 1×10⁻⁶). 13 –5×10 14 cm -2 Using a small-angle tilt implantation, a second-type extended region PLDD is formed within the first-type well region surrounding the sidewall 60. The second patterned photoresist layer PR21 is then completely removed through a combination of dry ashing and wet cleaning. This prepares the site for subsequent processes (such as secondary deposition / etching of the sidewalls, or source / drain heavy doping implantation).

[0106] Please see Figure 13 In some embodiments, after completely removing the second patterned photoresist layer PR21, a silicon oxide layer and a silicon nitride layer can be deposited sequentially. Then, the silicon nitride layer and silicon oxide layer are etched using a self-aligned process. The remaining silicon oxide layer and silicon nitride layer constitute a protective wall located around the sidewall 60. A first-type source / drain region is formed within the first-type lightly doped extended region NLDD around the sidewall 60, and a second-type source / drain region is formed within the second-type extended region PLDD around the sidewall 60.

[0107] Please see Figures 14-15 In some embodiments, after forming the source / drain region and before forming the dielectric layer, the step of forming an electrical contact 80 within the source / drain region is further included:

[0108] Step S411: Use a fluorine- and ammonia-containing mixed gas to generate plasma at the target temperature under radio frequency power;

[0109] Step S412: The plasma at the target temperature reacts with the silicon oxide on the surface of the substrate 100 to generate a target compound that is easy to sublimate, thereby achieving pretreatment of the well region surface.

[0110] Step S413: Deposit a nickel-platinum compound on the surface of the pretreated well region;

[0111] Step S414: Deposit titanium nitride on the nickel-platinum compound;

[0112] Step S415: First heat treatment of titanium nitride and nickel-platinum compound to form the first metal silicide;

[0113] Step S416: The first metal silicide is heat-treated a second time to generate a second metal silicide with an impedance value lower than that of the first metal silicide. The deposited nickel is removed. The second metal silicide is used to form the electrical contact 80.

[0114] Please continue reading. Figures 14-15 In some embodiments, in step S411, a mixed gas containing fluorine (such as CF4, NF3) and ammonia (NH3) is used to generate plasma under radio frequency power. In step S412, the surface temperature of substrate 100 is brought to a target value (typically between 200°C and 400°C) by precisely controlling the radio frequency power, gas flow ratio, and cavity pressure. At this temperature, active free radicals in the plasma (such as fluorine radicals) react chemically with the natural silicon oxide on the surface of the source / drain region (typically silicon or silicon-germanium) to generate volatile byproducts (such as SiF4), thereby effectively removing the surface oxide layer. This not only achieves physicochemical cleaning of the well region surface but also forms dangling bonds on the silicon surface, providing a good interface state for subsequent metal deposition and ensuring low-resistance ohmic contact between the metal layer and the silicon substrate.

[0115] Please continue reading. Figures 14-15 In some embodiments, in step S413, two metal layers are sequentially deposited on the pretreated clean trap surface using a physical vapor deposition (PVD) process (such as magnetron sputtering): First, a nickel-platinum compound (Ni-Pt) is deposited: a uniform nickel alloy film containing a small amount of platinum (typically 5%-10% atomic percentage) is formed using co-sputtering or an alloy target. The incorporation of platinum can effectively suppress the agglomeration of nickel in subsequent high-temperature processes and improve the thermal stability of the silicide film.

[0116] Please continue reading. Figures 14-15 In some embodiments, in step S414, a titanium nitride (TiN) layer is deposited on the nickel-platinum layer as a capping layer. The TiN layer mainly serves to prevent the underlying nickel-platinum layer from being oxidized during heat treatment and to block the outward diffusion of metal.

[0117] Please continue reading. Figures 14-15 In some embodiments, in step S415, a first rapid thermal annealing (RTA1) is performed in a nitrogen atmosphere, typically at a temperature controlled between 250°C and 350°C. During this stage, the nickel-platinum layer reacts with the underlying monocrystalline silicon to preferentially form a first metal silicide with high resistivity, such as a metastable metal-rich phase silicide (e.g., Ni2Si).

[0118] Please continue reading. Figures 14-15 In some embodiments, in step S416, the first metal silicide undergoes a second rapid thermal annealing (RTA2), typically at a temperature controlled between 400°C and 550°C. Under a higher thermal budget, the initially formed high-resistivity phase (Ni2Si) further reacts with silicon, transforming into a thermodynamically stable second metal silicide with extremely low resistivity, for example, a single silicide phase (typically NiSi, or Ni(Pt)Si for Pt-doped systems). During this process, excess or unreacted nickel atoms precipitate from the silicide layer. Finally, wet etching using a chemical solution selectively corroding nickel (such as a hydrochloric acid / hydrogen peroxide mixture) removes the capping layer (TiN) and the nickel metal precipitated from the silicide and remaining on the field oxide or isolation structure, ensuring that only low-resistivity nickel-platinum silicide is formed in the source / drain regions as the final electrical contact 80.

[0119] Please see Figure 16 In some embodiments, in step S50, a dielectric layer 90 with its top surface flush with the top surface of the sacrificial layer 41 is formed on the substrate 100. For example, the dielectric layer 90 includes silicon oxide, and a silicon nitride layer may be deposited first, followed by filling the dielectric layer 90. After performing chemical mechanical polishing, a dielectric layer 90 with its top surface flush with the top surface of the sacrificial layer 41 is obtained.

[0120] Please see Figure 17 In some embodiments, in step S60, an etching process can be used to remove the T-shaped sacrificial layer 41 to obtain the target trench 200. The etching process must ensure that the underlying gate oxide layer 31 is not damaged. For example, etching can be performed in a vacuum chamber using a plasma containing fluorine gas (such as NF3, SF6, CF4). The reaction generates fluorine radicals, which react with silicon to generate volatile products (such as SiF4) that are then removed.

[0121] Please continue reading. Figure 17 In some embodiments, in step S60, an alkaline solution can be used for etching, such as tetramethylammonium hydroxide (TMAH) and ammonia (NH4OH) to selectively remove the sacrificial layer 41. After etching, the wafer can be immediately rinsed with a large amount of deionized water to terminate the reaction and thoroughly remove any residual chemical solution. Finally, the wafer is dried by methods such as spin drying.

[0122] Please continue reading. Figures 17-20 In some embodiments, step S70 includes:

[0123] Step S71: After depositing dielectric material 101 in the target trench 200, deposit a second type of first metal work function layer 102 on the dielectric material 101.

[0124] For example, please continue to refer to Figure 17 First, a dielectric material 101 with precisely controllable thickness (such as HfO2) is formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). Then, a first metal work function layer 102 with a second conductivity type (e.g., the high work function required for PMOS) is deposited using physical vapor deposition (PVD) or ALD. This layer is typically made of materials such as titanium nitride (TiN), tantalum nitride (TaN), or titanium aluminum carbon (TiAlC), and its thickness needs to be optimized according to the target threshold voltage, generally in the range of 2nm-10nm, such as 2nm, 3nm, 4nm, 6nm, 8nm, or 10nm. Good step coverage must be ensured during deposition to guarantee uniform thickness at the bottom and sidewalls of the target trench 200.

[0125] Step S72: An etch stop layer 103 is formed on the first metal work function layer 102 using an atomic layer deposition process.

[0126] For example, please continue to refer to Figure 18 To achieve subsequent selective etching, an ultrathin (typically 1nm-3nm), highly dense first etch stop layer 103 is deposited on the surface of the first metal work function layer 102 using ALD (Alternating Discharge Machining). The material of this layer must exhibit extremely high selectivity for subsequent etching processes; commonly used materials include titanium nitride, tantalum nitride, or aluminum oxide. The excellent conformality of the ALD process ensures that the etch stop layer can uniformly cover even within trenches with large aspect ratios, providing a reliable barrier for subsequent removal of part of the work function metal layer.

[0127] Step S73: Deposit a second type of second metal work function layer 104 on the first etch stop layer 103; wherein, the portion of the first etch stop layer 103 located at the bottom of the target trench 200 is located within the sealed space enclosed by the first metal work function layer 102 and the second metal work function layer 104.

[0128] For example, please continue to refer to Figure 18Above the first etch stop layer 103, a second metal work function layer 104 with the same conductivity type as the first metal work function layer 102 is deposited. Its material can be the same as or slightly different from the first metal work function layer 102 (e.g., using TiN with different compositions or adding elements such as Al and C) to achieve finer work function adjustment. The first etch stop layer 103 at the bottom of the target trench 200 is completely surrounded by the first metal work function layer 102 and the second metal work function layer 104, forming a "sandwich" structure. This design ensures that when the second metal work function layer 104 is removed, etching will stop at the first etch stop layer 103, thereby protecting the underlying first metal work function layer 102 and dielectric material 101.

[0129] Step S74: After forming a sacrificial material layer that fills the target trench 200, a third patterned photoresist layer PR31 is formed on the sacrificial material layer.

[0130] For example, please continue to refer to Figure 19 To distinguish between different well regions (such as NMOS and PMOS regions), a sacrificial material (such as spin-coated carbon SOC or organic dielectric material) is first spin-coated onto the wafer surface to fill the target trench 200, and the surface is planarized by etching back or chemical mechanical polishing (CMP). Subsequently, photoresist is coated, and after exposure and development, a third patterned photoresist layer PR31 is formed. The third patterned photoresist layer PR31 precisely covers the first type of well region (such as the PMOS region) while exposing the second type of well region (such as the NMOS region), preparing for subsequent selective removal.

[0131] Step S75: Based on the third patterned photoresist layer PR31 and the sacrificial material layer, etch and remove the sacrificial material layer in the target trench 200 within the second type of well region.

[0132] For example, please continue to refer to Figure 19 Using the third patterned photoresist layer PR31 as a mask, anisotropic dry etching (such as oxygen plasma ashing) is employed to precisely remove the sacrificial material in the exposed area (the second type-2 well region), exposing the underlying second metal work function layer 104. The etching process requires precise control of the endpoint to ensure complete removal of the sacrificial material without damaging the underlying metal layer. After this step, only metal stacking remains in the target trench 200 of the second type-2 well region, while the target trench 200 of the first type-2 well region remains filled with sacrificial material.

[0133] Step S76: Etch and remove the second metal work function layer 104 within the target trench 200 in the second type of well region.

[0134] For example, please continue to refer to Figures 19-20An etching process (such as wet etching or dry plasma etching) with high selectivity for the second metal work function layer 104 and extremely low etching rate for the first etch stop layer 103 is used to remove the exposed second metal work function layer 104 in the second type well region. Due to the presence of the first etch stop layer 103, the etching process automatically terminates on the surface of the first etch stop layer 103, thereby protecting the underlying first metal work function layer 102 and dielectric material 101 from damage. Thus, the metal stacking within the trench of the second type well region becomes a "first metal work function layer 102 / first etch stop layer 103" structure.

[0135] Step S77: Remove the third patterned photoresist layer PR31 and the remaining sacrificial material layer.

[0136] For example, please continue to refer to Figure 20 The residual third patterned photoresist layer PR31 and the sacrificial material layer still filling the first type-1 well region are completely removed by dry ashing combined with wet cleaning. At this point, the entire wafer surface is clean, and the top of each metal stack is exposed in the target trench 200: the first type-1 well region retains a complete stack of "first metal work function layer 102 / first etch stop layer 103 / second metal work function layer 104"; the second type-2 well region is a stack of "first metal work function layer 102 / first etch stop layer 103".

[0137] Step S78: A first type of third metal work function layer 105 is deposited in the target trench 200 using atomic layer deposition process; wherein, the first etch stop layer 103 located at the bottom of the target trench 200 in the second type well region is located in the closed space formed by the first metal work function layer 102 and the third metal work function layer 105.

[0138] For example, please continue to refer to Figure 20 A third metal work function layer 105 with a first conductivity type (e.g., the low work function required for NMOS) is deposited across the entire wafer surface using ALD. Commonly used materials include aluminum titanium alloy (TiAl), aluminum tantalum alloy (TaAl), or aluminum titanium nitride (TiAlN). The third metal work function layer 105 continues to cover the interior of the target trench 200: In the first type-well region (e.g., PMOS), the third metal work function layer 105 is deposited on top of the existing second metal work function layer 104, forming a composite work function stack. In the second type-well region (e.g., NMOS), the third metal work function layer 105 is deposited directly on top of the first etch stop layer 103 and may contact the sidewalls. At this point, the first etch stop layer 103 located at the bottom of the target trench 200 in the second type-well region is surrounded by the first metal work function layer 102 below and the third metal work function layer 105 above, forming a closed structure again, ensuring that different regions have independent and precisely controllable work function combinations.

[0139] In some embodiments, please refer to Figure 21 In step S70, after forming a functional layer within the target trench 200, a T-shaped conductive layer 300 filling the target trench 200 is formed, including:

[0140] Step S79: Deposit filler metal (such as tungsten, cobalt) to completely fill the target trench 200, and planarize it by CMP to finally form a metal gate structure suitable for transistors of different conductivity types.

[0141] In the above embodiments, by introducing an etch stop layer and selective removal, independent optimization of the work function metal layers of NMOS and PMOS is achieved on the same wafer. A low-resistance, large-contact-area gate electrode body is formed within the target trench 200 after the work function metal layer has been filled, significantly reducing the parasitic resistance (Rgate) of the gate electrode. This is crucial for improving the switching speed of the transistor and reducing RC delay. The flat and wide top provides an ideal landing platform for the subsequent formation of the gate contact hole (CB, i.e., the contact hole), ensuring reliable electrical connection.

[0142] In some embodiments, please refer to Figure 21 A semiconductor structure is provided, including a substrate 100, the substrate 100 including a first type well region (e.g., NW), the top surface of the well region including a gate oxide layer 31 and a T-type conductive layer 300 located on the side of the gate oxide layer 31 facing away from the substrate 100; the outer sidewall and bottom surface of the T-type conductive layer 300 are covered with an active function layer 10; the T-type conductive layer 300 includes a horizontal portion 301 and a protrusion 302, the protrusion 302 contacting the top surface of the well region sequentially via the active function layer 10 and the gate oxide layer 31; the horizontal portion 301 is circumferentially surrounded by a sidewall 60; an air gap 70 is included between the sidewall 60 and the gate oxide layer 31; wherein, the well region surrounding the sidewall 60 includes a second type source / drain region.

[0143] For example, please refer to Figure 21By setting a T-type conductive layer 300 including a horizontal portion 301 and a protruding portion 302, the protruding portion 302 sequentially contacts the top surface of the well region via a work function layer and a gate oxide layer 31. The horizontal portion 301 is surrounded by a sidewall 60, and an air gap 70 is included between the sidewall 60 and the gate oxide layer 31. Steps are included between regions A and B, and between regions B and C, so that the outer wall and bottom surface of the T-type conductive layer 300 can be covered with a parabolic work function layer to increase the lateral breakdown voltage of the MOS device. The air gaps 70 added in both the lateral and longitudinal directions of the MOS device can simultaneously reduce the lateral and longitudinal capacitance, reduce RC delay, and improve the gate control capability of the device. A boss-shaped channel structure can be formed in the well region below the T-type conductive layer 300, which can at least reduce the leakage current of the device, increase the lateral breakdown voltage of the MOS device, and improve the reliability of the device while keeping the integration density unchanged and shortening the channel of the MOS device.

[0144] In some embodiments, please refer to Figure 21 An air gap 70 surrounds the gate oxide layer 31, so that the sidewall 60 is isolated from the protrusion 302 via the air gap 70 surrounding the gate oxide layer 31 / protrusion 302 in the circumferential direction. This also isolates part of the horizontal portion 301 from the channel via the air gap 70. By adding air gaps 70 in both the lateral and longitudinal directions of the MOS device, the lateral and longitudinal capacitance can be reduced simultaneously, the RC delay can be reduced, and the gate control capability of the device can be improved.

[0145] In some embodiments, please refer to Figure 21 The ratio of the dimension of the horizontal portion 301 along the first direction to the dimension of the gate oxide layer 31 along the first direction is located in the range of [1.17, 2], where the first direction is parallel to the top surface of the substrate 100. For example, the ratio of the dimension of the sacrificial layer 41 along the first direction parallel to the top surface of the substrate 100 to the dimension of the gate oxide layer 31 along the first direction can be set to 1.17, 1.20, 1.27, 1.30, 1.38, 1.48, 1.58, 1.68, 1.78, 1.88, 1.98, or 2, etc. This avoids both reducing device reliability due to an excessively small dimension of the gate oxide layer 31 along the first direction and reducing the size of the air gap 70 due to an excessively large dimension of the gate oxide layer 31 along the first direction.

[0146] In some embodiments, please refer to Figure 21The substrate 100 also includes a second type well region, and the first type well region and the second type well region are isolated by a trench isolation portion 40; the protrusion 302 in the first type well region includes a second type first metal work function layer 102, a first etch stop layer 103 and a second type second metal work function layer 104 stacked sequentially in a direction away from the substrate 100; in the first type well region, the first etch stop layer 103 of the protrusion 302 is located in the closed space enclosed by the first metal work function layer 102 and the second metal work function layer 104.

[0147] In some embodiments, please refer to Figure 21 The protrusion 302 in the second type well region includes a first metal work function layer 102, a first etch stop layer 103 and a third metal work function layer 105 of the second type stacked sequentially along the direction away from the substrate 100; in the second type well region, the first etch stop layer 103 of the protrusion 302 is located in the closed space enclosed by the first metal work function layer 102 and the third metal work function layer 105.

[0148] Please continue reading. Figures 1-21 The unexpected technical effects that can be produced by the above-described embodiments include:

[0149] The T-type conductive layer 300 includes a horizontal portion 301 and a protruding portion 302. The protruding portion 302 contacts the top surface of the well region via the work function layer and the gate oxide layer 31. The horizontal portion 301 is circumferentially surrounded by a sidewall 60. An air gap 70 is included between the sidewall 60 and the gate oxide layer 31, so that the outer sidewall and bottom surface of the T-type conductive layer 300 can be covered with a parabolic work function layer to increase the lateral breakdown voltage of the MOS device. The air gaps 70 added in both the lateral and longitudinal directions of the MOS device can simultaneously reduce the lateral and longitudinal capacitance, reduce RC delay, and improve the gate control capability of the device. A boss-shaped channel structure can be formed in the well region below the T-type conductive layer 300, which can at least reduce the leakage current of the device, increase the lateral breakdown voltage of the MOS device, and improve the reliability of the device while keeping the integration density unchanged and shortening the channel of the MOS device.

[0150] In some embodiments, an electronic device is provided, including the semiconductor structure of any embodiment of this disclosure.

[0151] The aforementioned electronic devices include, but are not limited to, suitable types of electronic products such as consumer electronics, home electronics, automotive electronics, and financial terminals. Consumer electronics include mobile phones, tablets, laptops, desktop monitors, and all-in-one computers. Home electronics include smart locks, televisions, refrigerators, and wearable devices. Automotive electronics include car navigation systems and car DVD players. Financial terminals include ATMs and self-service terminals.

[0152] Please note that, for the sake of brevity, in the structural diagrams given in the following embodiments, unless a separate cross-sectional structural diagram is given, structural diagrams from different perspectives related to the inventive points of the embodiments of this disclosure can be referred to each other.

[0153] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0154] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a first type well region, the top surface of which includes a gate oxide layer and a T-type conductive layer located on the side of the gate oxide layer opposite to the substrate; The outer wall and bottom surface of the T-type conductive layer are covered with a parabolic work function layer; the T-type conductive layer includes a horizontal portion and a protruding portion, the protruding portion sequentially contacts the top surface of the well region via the work function layer and the gate oxide layer; the horizontal portion is circumferentially surrounded by a sidewall; the sidewall and the gate oxide layer include at least an air gap for isolating the horizontal portion and the substrate; a step is included between the work function layer directly above the air gap and the work function layer directly above the gate oxide layer; the protruding portion in the first type well region includes a second type of first metal work function layer, a first etch stop layer and a second type of second metal work function layer stacked sequentially in the direction away from the substrate; in the first type well region, the first etch stop layer of the protruding portion is located within the sealed space enclosed by the first metal work function layer and the second metal work function layer; wherein, the well region outside the sidewall includes a second type of source / drain region.

2. The semiconductor structure according to claim 1, characterized in that, The air gap surrounds the gate oxide layer.

3. The semiconductor structure according to claim 1, characterized in that, The ratio of the dimension of the horizontal portion along the first direction to the dimension of the gate oxide layer along the first direction is located in [1.17, 2], wherein the first direction is parallel to the top surface of the substrate.

4. The semiconductor structure according to claim 1, characterized in that, The substrate further includes a second type of well region, and the first type of well region and the second type of well region are isolated from each other via a trench isolation portion; The protrusion in the second type of well region includes a first metal work function layer of the second type, a first etch stop layer and a third metal work function layer of the first type stacked sequentially along the direction away from the substrate; Within the second type of trap region, the first etch stop layer of the protrusion is located within the sealed space enclosed by the first metal work function layer and the third metal work function layer.

5. A method for fabricating a semiconductor structure, characterized in that, include: A substrate including a first type of well region is provided, wherein the top surface of the well region includes a gate oxide layer and a sacrificial layer sequentially stacked in a direction away from the substrate, and the orthographic projection of the gate oxide layer on the bottom surface of the sacrificial layer is located inside the bottom surface of the sacrificial layer; Thermal oxidation forms a dielectric layer that covers the exposed surface of the sacrificial layer and the exposed surface of the well region; A sidewall material layer is deposited to cover the dielectric layer; an air gap is formed between the sidewall material layer, the remaining T-shaped sacrificial layer, and the gate oxide layer to isolate the T-shaped sacrificial layer and the substrate; Simultaneously remove the sidewall material layer and the dielectric layer from the top surface of the sacrificial layer and the top surface of the well region; the remaining sidewall material layer constitutes the sidewall. A second type of source / drain region is formed in the well region surrounding the sidewall, and a dielectric layer with its top surface flush with the top surface of the sacrificial layer is formed on the substrate; Remove the sacrificial layer of the T-shape to obtain the target groove; After forming a parabolic work function layer in the target trench, a T-shaped conductive layer is formed to fill the target trench. A step is included between the work function layer directly above the air gap and the work function layer directly above the gate oxide layer. The work function layer includes a first metal work function layer of type II, a first etch stop layer and a second metal work function layer of type II stacked sequentially in the direction away from the substrate. The first etch stop layer at the bottom of the target trench is located in the closed space enclosed by the first metal work function layer and the second metal work function layer.

6. The semiconductor structure fabrication method according to claim 5, characterized in that, The ratio of the dimension of the sacrificial layer along the first direction to the dimension of the gate oxide layer along the first direction is located in [1.17, 2], wherein the first direction is parallel to the top surface of the substrate.

7. The semiconductor structure fabrication method according to claim 5, characterized in that, The sacrificial layer comprises polycrystalline silicon; the dielectric layer comprises silicon oxide; The top surface of the silicon oxide at the bottom of the sacrificial layer is higher than the top surface of the gate oxide layer.

8. The semiconductor structure fabrication method according to claim 5, characterized in that, The substrate further includes a second type of well region, and the first type of well region and the second type of well region are isolated from each other via a trench isolation portion; After the sidewalls are formed, and before the source / drain regions are formed, the process further includes: A first patterned photoresist layer is formed on the substrate, the first patterned photoresist layer exposing the second type well region; A first-type extended region is formed in the second-type well region surrounding the sidewall using a first-lightly doped drain ion implantation process; After removing the first patterned photoresist layer, a second patterned photoresist layer is formed on the substrate, and the second patterned photoresist layer exposes the first type-well region; A second type extended region is formed in the first type well region outside the sidewall using a second lightly doped drain ion implantation process; Remove the second patterned photoresist layer.

9. The semiconductor structure fabrication method according to claim 8, characterized in that, A success function layer is formed within the target slot, including: After depositing dielectric material in the target trench, a second type of first metal work function layer is deposited on the dielectric material; A first etch stop layer is formed on the first metal work function layer using atomic layer deposition (ALD) technology. A second type of second metal work function layer is deposited on the first etch stop layer; wherein, the portion of the first etch stop layer located at the bottom of the target trench is located within the closed space enclosed by the first metal work function layer and the second metal work function layer; After forming a sacrificial material layer that fills the target trench, a third patterned photoresist layer is formed on the sacrificial material layer; Based on the third patterned photoresist layer and the sacrificial material layer, the sacrificial material layer in the target trench within the second type of well region is etched and removed; Etch and remove the second metal work function layer within the target trench in the second type of well region; Remove the third patterned photoresist layer and the remaining sacrificial material layer; An atomic layer deposition process is used to deposit a first type of third metal work function layer in the target trench; wherein, a portion of the first etch stop layer located at the bottom of the target trench in the second type trap region is located within the sealed space enclosed by the first metal work function layer and the third metal work function layer.

10. The semiconductor structure fabrication method according to claim 8, characterized in that, After forming the source / drain region and before forming the dielectric layer, the method further includes the step of forming electrical contacts within the source / drain region: Plasma at a target temperature is generated using a fluorine- and ammonia-containing mixed gas under radio frequency power. The target temperature plasma reacts with silicon oxide on the substrate surface to generate a target compound that is easily sublimated, thereby achieving pretreatment of the well region surface. Nickel-platinum compound is deposited on the surface of the pretreated well region; Titanium nitride is deposited on the nickel-platinum compound; The titanium nitride and the nickel-platinum compound are subjected to a first heat treatment to form a first metal silicide. The first metal silicide is subjected to a second heat treatment to generate a second metal silicide with an impedance value lower than that of the first metal silicide, and the deposited nickel is removed. The second metal silicide is used to form the electrical contact.

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