Back contact solar cells and their fabrication methods

Abstract

This invention discloses a back-contact solar cell and its fabrication method. The back-contact solar cell includes a silicon wafer, on which a doped polycrystalline silicon layer is disposed on the pyramidal base of the back side of the silicon wafer. The doped polycrystalline silicon layer includes a P-type doped region, an N-type doped region, and an isolation region separating the P-type and N-type doped regions. A doped region pattern is formed in the doped polycrystalline silicon layer. The ratio of the maximum size to the minimum size of the doped region pattern located in the N-type doped region is less than or equal to 1.5. The ratio of the maximum size to the minimum size of the doped region pattern located in the P-type doped region is less than or equal to 1.5.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically, to a back-contact solar cell and its fabrication method. Background Technology

[0002] Back-contact solar cells, especially interdigitated back-contact (IBC) solar cells and their derivatives combined with passivation contact technology (such as POLO-IBC, TBC, etc.), have become one of the mainstream technologies for next-generation high-efficiency photovoltaic cells due to their advantages such as no grid line obstruction on the front side, high short-circuit current density, and beautiful appearance.

[0003] Currently, the mainstream back-contact solar cell fabrication process usually adopts laser patterning technology. The typical process flow is as follows: global doping is performed on the back of the silicon wafer, then laser grooving is used to selectively remove the doped layer in some areas, a second doping is performed, and finally the slag and damage caused by laser grooving are cleaned by two alkaline polishing processes. However, this laser process has the following technical problems: (1) The high-temperature ablation of the laser will cause thermal damage to the pyramid base on the surface of the silicon wafer, resulting in microcracks and molten residue, and the boundary between the doped area and the isolation area will be severely jagged and blurred, and the heat-affected zone will overflow in a large area; (2) Although the subsequent two alkaline polishing processes are intended to remove the damaged layer, the alkaline solution will non-uniformly corrode the anisotropic pyramid textured surface structure, resulting in a rough pyramid base morphology, uneven surface, and extremely uneven grain size distribution in the N-type doped area, which is prone to poor metal contact; (3) The rough pyramid-shaped textured morphology is not conducive to the growth of a uniform and dense tunneling oxide layer on its surface, resulting in poor passivation effect and affecting the open circuit voltage and fill factor of the cell.

[0004] Therefore, developing a back-contact solar cell and its fabrication method that can avoid laser damage, obtain a doped region base with complete and smooth morphology, and thus improve battery performance, is of great practical significance.

[0005] In view of this, the present invention is proposed. Summary of the Invention

[0006] The purpose of this invention is to provide a back-contact solar cell and its fabrication method, which makes the boundary between the doped region and the isolation region clear, avoids the jaggedness and blurring of the boundary between the doped region and the isolation region caused by laser grooving, and avoids damage to the pyramid base.

[0007] This invention is implemented as follows:

[0008] In a first aspect, the present invention provides a back-contact solar cell, comprising:

[0009] A silicon wafer, wherein a doped polycrystalline silicon layer is disposed on the pyramid base on the back side of the silicon wafer, the doped polycrystalline silicon layer includes a P-type doped region, an N-type doped region and an isolation region separating the P-type doped region and the N-type doped region, and a doped region pattern is formed in the doped polycrystalline silicon layer;

[0010] The ratio of the maximum to the minimum size of the doped region pattern located in the N-type doped region is less than or equal to 1.5;

[0011] The ratio of the maximum to the minimum size of the doped region pattern located in the P-type doped region is less than or equal to 1.5.

[0012] In an optional embodiment, the doping region patterns of the N-type doped region and the P-type doped region have a tower-like shape.

[0013] In an optional embodiment, the average doped region pattern feature size of the N-type doped region is 1.2 to 2.0 times the average doped region pattern feature size of the P-type doped region.

[0014] And / or, the roughness of the line edges between the isolation region and the N-type doped region, and the line edges between the isolation region and the P-type doped region, is less than 0.5 μm;

[0015] And / or, the surface roughness of the P-type doped region and the N-type doped region is less than or equal to 50 nm, more preferably not greater than 30 nm;

[0016] And / or, the root mean square roughness of the P-type doped region and the N-type doped region is less than 20 nm.

[0017] In an optional embodiment, the average grain size of the N-type doped region is greater than the average grain size of the P-type doped region.

[0018] In an optional embodiment, the average grain size of the N-type doped region is 1.2 to 3 times that of the P-type doped region;

[0019] And / or, the average grain size of the N-type doped region is 100~500nm;

[0020] And / or, the average grain size of the P-type doped region is 50~200nm.

[0021] In an optional implementation, the P-type doped region is observed to have a polygonal grid structure with clear and continuous boundaries when viewed under 100x electron microscopy.

[0022] And / or, the projection pattern of the N-type doped region in the direction parallel to the substrate, observed under 100x electron microscopy, includes rectangles, hexagons, bars, and rhombuses;

[0023] And / or, when observed under 100x electron microscopy, the doped region pattern feature size of the N-type doped region is 10~30μm;

[0024] And / or, when observed under 100x electron microscopy, the doped region pattern feature size of the P-type doped region is 5~20 μm;

[0025] And / or, a tunneling oxide layer is further provided between the pyramid base of the silicon wafer and the doped polycrystalline silicon layer.

[0026] In an optional embodiment, the thickness of the tunneling oxide layer is 1~2.5 nm;

[0027] And / or, the thickness difference between different locations of the tunneling oxide layer is less than 0.3 nm;

[0028] And / or, when observing the N-type doped region under 100x magnification using an electron microscope, the area ratio of rectangles in the projection pattern parallel to the substrate direction is 40-70%, the area ratio of hexagons is 10-30%, the area ratio of bars is 10-30%, and the area ratio of rhombuses is 5-20%.

[0029] Secondly, the present invention provides a method for preparing a back-contact solar cell according to any one of the foregoing embodiments, comprising:

[0030] A masking material is deposited on the back of a silicon wafer with a pyramid base on the back to form a mask layer;

[0031] Photoresist is coated on the mask layer, and the electrode pattern is transferred to the photoresist by photolithography to form a photoresist pattern; then the photoresist pattern is transferred to the mask layer by etching to expose the first target doped region;

[0032] A first doped region is formed in the first target doped region;

[0033] Remove the remaining mask layer to expose the second target doped region;

[0034] A second doped region is formed in the second target doped region;

[0035] High-temperature annealing of silicon wafers;

[0036] A passivation layer is deposited on the back side of the silicon wafer, and metal electrodes are fabricated to form ohmic contacts with the first doped region and the second doped region, respectively.

[0037] Wherein, the first doped region is a P-type doped region and the second doped region is an N-type doped region, or the first doped region is an N-type doped region and the second doped region is a P-type doped region.

[0038] In an optional embodiment, the silicon wafer with a pyramid base on its back side is obtained by texturing and polishing the back side of the silicon wafer using an alkaline solution;

[0039] In an optional embodiment, the alkaline solution is a sodium hydroxide or potassium hydroxide solution with a mass fraction of 1% to 5%.

[0040] And / or, the alkaline solution further includes isopropanol, wherein the volume fraction of isopropanol in the alkaline solution is 2% to 8%;

[0041] And / or, the flocking temperature is 70~100℃, and the flocking time is 15~40min.

[0042] And / or, the thickness of the mask layer is 50~500nm;

[0043] And / or, the material of the mask layer is selected from at least one of silicon oxide, silicon nitride, and amorphous silicon;

[0044] And / or, the mask layer is prepared by plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition, with a deposition temperature below 600°C;

[0045] And / or, the photoresist thickness is 1~3μm, and the exposure dose for the photolithography step is 50~250mJ / cm. 2 ;

[0046] And / or, the etching process employs dry etching or wet etching;

[0047] And / or, the formation of the first doped region and / or the formation of the first doped region includes high-temperature thermal diffusion or the introduction of doping elements during the deposition of a polycrystalline silicon thin film;

[0048] And / or, also includes: forming a tunneling oxide layer on the first target doped region and the second target doped region by thermal oxidation, and then using low-pressure chemical vapor deposition to perform in-situ doping with a dopant while depositing a polycrystalline silicon layer, to form the first doped region and the second doped region respectively.

[0049] In an optional embodiment, the temperature of the thermal oxidation method is 600~750°C, the atmosphere is oxygen, and the thickness of the tunneling oxide layer is 1~2 nm.

[0050] And / or, the temperature of the low-pressure chemical vapor deposition is 550~650°C;

[0051] And / or, the thickness of the polycrystalline silicon layer is 50~300 nm.

[0052] And / or, the high-temperature annealing is carried out in an inert gas atmosphere, the annealing temperature is 800~1000℃, and the annealing time is 10~60min;

[0053] And / or, the passivation layer is selected from at least one of silicon nitride and aluminum oxide, and has a thickness of 80~120nm;

[0054] And / or, the metal electrode is selected from at least one of silver, silver alloys, copper, and copper alloys.

[0055] The present invention has the following beneficial effects:

[0056] The isolation region of the back-contact solar cell of this application is a continuous strip, clearly separated between the P-type and N-type doped regions. The boundary is straight and sharp, without obvious irregular undulations. The pyramid base pattern of the P-type and N-type doped regions near the isolation region is clear and uniform in size, without stacking of large and small bases. This achieves precise patterning of the doped and isolation regions, effectively preventing leakage risks between the P-type and N-type doped regions. At the same time, it provides an ideal dielectric interface for back-side optical reflection, improves the uniformity of the tunneling oxide layer thickness, and improves cell efficiency. Attached Figure Description

[0057] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 Schematic diagrams of N-type and P-type doped regions;

[0059] Figure 2 This is an enlarged schematic diagram of the doped and isolated regions of a back-contact solar cell.

[0060] Figure 3 This is a schematic diagram of the back side of the back contact solar cell prepared in Example 1, magnified 100 times (the upper blue area represents the P-type doped region, the lower blue area represents the N-type doped region, and the middle black area represents the isolation region).

[0061] Figure 4 This is a schematic diagram of the back side of the back contact solar cell prepared in Comparative Example 1, magnified 100 times (the upper blue area represents the P-type doped region, the lower blue area represents the N-type doped region, and the middle black area represents the isolation region).

[0062] Illustration: 100 - Silicon wafer; 200 - Pyramid base; 300 - Tunneling oxide layer; 400 - P-type doped region; 500 - N-type doped region; 600 - Isolation region; 700 - Metal electrode. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0064] This invention provides a back-contact solar cell, comprising:

[0065] A silicon wafer 100 has a doped polycrystalline silicon layer disposed on the pyramid base on the back side of the silicon wafer 100. The doped polycrystalline silicon layer includes a P-type doped region, an N-type doped region, and an isolation region separating the P-type doped region and the N-type doped region. A doped region pattern is formed in the doped polycrystalline silicon layer.

[0066] The ratio of the maximum to the minimum size of the doped region pattern located in the N-type doped region is less than or equal to 1.5;

[0067] The ratio of the maximum to the minimum size of the doped region pattern located in the P-type doped region is less than or equal to 1.5.

[0068] The doped region patterns of the N-type doped region and the P-type doped region have a tower-like shape. The ratio of the maximum to the minimum size of the doped region patterns of the N-type and P-type doped regions can characterize the uniformity of the doped region patterns: uniform doped region pattern size is beneficial to the consistent carrier collection ability of each doped unit; size fluctuations will lead to local current accumulation, increase resistance loss, and uneven distribution will also lead to a reduction in minority carrier lifetime, thereby affecting the battery conversion efficiency.

[0069] In an optional embodiment, the average doped region pattern feature size NL of the N-type doped region is 1.2 to 2.0 times the average doped region pattern feature size PL of the P-type doped region, for example, 1.2 times, 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.7 times, 1.8 times, 1.9 times, or 2 times. When the isolation region 600 is observed under electron microscopy at 20 to 50x magnification, the isolation region 600 appears as a continuous band.

[0070] When the isolation region is observed under electron microscopy at magnification of 20-50x, it appears as a continuous band, clearly separated between the P-type doped region and the N-type doped region. The boundary is straight and sharp, without obvious irregular undulations, effectively preventing the leakage risk between the P-type doped region 400 and the N-type doped region 500, while providing an ideal dielectric interface for back-side optical reflection.

[0071] In an optional implementation, when observed under electron microscopy at 30,000x magnification, no polycrystalline silicon grain structure was observed inside the isolation region. Only the tunneling oxide layer was retained covering the pyramid-shaped textured surface, thus achieving precise patterning of the doped region and the isolation region 600. This helps to prevent leakage risks between the P-type doped region 400 and the N-type doped region 500, while providing an ideal dielectric interface for back-side optical reflection.

[0072] In an optional embodiment, the roughness of the line edges of the isolation region 600 and the N-type doped region 500, as well as the line edges of the isolation region 600 and the P-type doped region 400, is less than 0.5 μm, for example, 0.1 μm, 0.14 μm, 0.18 μm, 0.22 μm, 0.26 μm, 0.30 μm, 0.34 μm, 0.38 μm, 0.42 μm, 0.46 μm, or 0.5 μm; this is beneficial for reducing interface scattering, improving carrier mobility, and suppressing leakage current.

[0073] And / or, the surface roughness of the P-type doped region 400 and the N-type doped region 500 is less than or equal to 50 nm, for example, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, more preferably not greater than 30 nm;

[0074] And / or, the root mean square roughness of the P-type doped region 400 and the N-type doped region 500 is less than 20 nm, for example, 5 nm, 6.7 nm, 8.3 nm, 10 nm, 11.7 nm, 13.3 nm, 15 nm, 16.7 nm, 18.3 nm, 20 nm.

[0075] Lower roughness is beneficial for improving the quality of the contact interface, reducing contact resistance, and enhancing the uniformity and interface stability of subsequent thin film deposition.

[0076] It should be noted that in this application, an atomic force microscope is used to scan the pyramid base surface of the N-type doped region 500 and the P-type doped region 400 to measure and calculate the surface roughness value, root mean square roughness value and line edge roughness value.

[0077] In an optional embodiment, the average grain size of the N-type doped region 500 is larger than that of the P-type doped region 400, which is beneficial to improving the carrier mobility and conductivity of the N-type doped region 500, while taking into account the doping activation efficiency and interface passivation quality of the P-type doped region 400.

[0078] In an optional embodiment, the average grain size of the N-type doped region 500 is 1.2 to 3 times that of the P-type doped region 400, for example, 1.2, 1.4, 1.6, 1.8, 2.0, 2.2, 2.4, 2.6, 2.8, 3.0.

[0079] And / or, the average grain size of the N-type doped region 500 is 100~500nm, for example 100 nm, 144 nm, 188 nm, 232 nm, 276 nm, 320 nm, 364 nm, 408 nm, 452 nm, 500 nm, and some grains extend along a specific crystal orientation, exhibiting anisotropic characteristics.

[0080] And / or, the average grain size of the P-type doped region 400 is 50~200 nm, for example 50 nm, 67 nm, 84 nm, 101 nm, 118 nm, 135 nm, 152 nm, 169 nm, 186 nm, 200 nm.

[0081] Meeting the above requirements for average grain size can optimize electrical transport characteristics.

[0082] In alternative implementations, such as Figure 1 As shown, under 100x magnification using an electron microscope, the P-type doped region 400 exhibits a polygonal grid structure with clear and continuous grain boundaries and no large-area domain distortion.

[0083] And / or, when the N-type doped region is observed under 100x electron microscopy, the projected pattern in the direction parallel to the substrate includes rectangles, hexagons, stripes, and rhombuses. When the N-type doped region is observed under 100x electron microscopy, the area ratio of rectangles is 40-70%, the area ratio of hexagons is 10-30%, the area ratio of stripes is 10-30%, and the area ratio of rhombuses is 5-20%.

[0084] And / or, when observed under 100x electron microscopy, the doped region pattern feature size L1 of the N-type doped region 500 is 10~30μm, for example 10 μm, 13 μm, 16 μm, 19 μm, 22 μm, 25 μm, 28 μm, 30 μm;

[0085] And / or, when observed under 100x magnification using an electron microscope, the doped region pattern feature size L2 of the P-type doped region 400 is 5~20 μm, for example 5 μm, 8 μm, 11 μm, 14 μm, 17 μm, 20 μm.

[0086] like Figure 1As shown, the P-type doped region 400 exhibits a uniform and fine grain mesh with similar sizes and continuous, clear grain boundary lines without significant interruptions. The N-type doped region 500 has a coarse grain mesh, consisting of regular polygons, with some grains elongated along specific directions. The intermediate isolation region 600 lacks any grain mesh. The small grain mesh of the P-type doped region 400 provides excellent lateral conductive channels, while the anisotropic structure of the large grains in the N-type doped region 500 facilitates vertical carrier transport. These two factors work synergistically to significantly improve the battery's fill factor and short-circuit current. It should be noted that under 100x electron microscopy magnification, the observation area can be divided into multiple regions with clear boundaries between adjacent regions; these boundaries define the doped region pattern.

[0087] And / or, a tunneling oxide layer 300 is further provided between the pyramid base 200 of the silicon wafer 100 and the doped polycrystalline silicon layer, which is beneficial to achieve selective tunneling transport of charge carriers and enhance the interface passivation effect.

[0088] In an optional embodiment, the thickness of the tunneling oxide layer 300 is 1~2.5 nm, for example 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2.0 nm, 2.2 nm, 2.4 nm, 2.5 nm; which can maintain good insulation barrier capability while ensuring a high tunneling probability;

[0089] And / or, the thickness difference between different locations of the tunneling oxide layer 300 is less than 0.3 nm, for example, 0 nm, 0.03 nm, 0.06 nm, 0.09 nm, 0.12 nm, 0.15 nm, 0.18 nm, 0.21 nm, 0.24 nm, 0.27 nm, or 0.3 nm; this is beneficial for ensuring the uniformity of the tunneling current and the consistency of the interface passivation quality.

[0090] Secondly, the present invention provides a method for preparing a back-contact solar cell according to any one of the foregoing embodiments, comprising:

[0091] A masking material is deposited on the back of a silicon wafer 100 with a pyramid base 200 on the back to form a masking layer.

[0092] Photoresist is coated on the mask layer, and the electrode pattern is transferred to the photoresist by photolithography to form a photoresist pattern; then the photoresist pattern is transferred to the mask layer by etching to expose the first target doped region;

[0093] A first doped region is formed in the first target doped region;

[0094] Remove the remaining mask layer to expose the second target doped region;

[0095] A second doped region is formed in the second target doped region;

[0096] Silicon wafer 100 is subjected to high-temperature annealing;

[0097] A passivation layer is deposited on the back side of silicon wafer 100, and metal electrodes 700 are fabricated to form ohmic contacts with the first doped region and the second doped region, respectively.

[0098] Wherein, the first doped region is a P-type doped region 400 and the second doped region is an N-type doped region 500, or the first doped region is an N-type doped region 500 and the second doped region is a P-type doped region 400.

[0099] This invention uses a masking process to replace laser grooving, thereby preparing a back-contact solar cell with a uniform pyramid base. This avoids thermal damage and makes the pyramid base smooth and complete. The polycrystalline silicon layer grown on this substrate has regular grains and clear grain boundaries. The fine and uniform grain structure of the P-type doped region 400 helps to reduce lateral resistance, while the coarse grains of the N-type doped region 500 reduce grain boundary recombination, thus synergistically improving carrier transport efficiency.

[0100] This invention achieves precise patterning of the doped region and the isolation region 600 through photolithography masking. The isolation region 600 is a continuous strip with straight boundaries and no obvious irregular undulations, which effectively prevents the leakage risk between the P-type doped region 400 and the N-type doped region 500, and at the same time provides an ideal dielectric interface for back-side optical reflection.

[0101] The back-contact solar cell prepared in this application has a smooth and complete microstructure at the pyramid base. The smooth and complete microstructure means that, under electron microscopy, the sharp edges of the physicochemical structure of the pyramid base are not damaged or smoothed, the base surface is flat and smooth, the doped polycrystalline silicon layer on it has fine and uniform grains, regular polygonal grids, and continuous and clear grain boundaries.

[0102] It should be noted that, through the design of the mask, the exposed opening pattern of the first conductivity type doped region has a small feature size, while the area covered by the mask layer corresponds to the second conductivity type doped region formed subsequently, which has a larger pattern size. The area that is not covered by photoresist and is not etched, i.e. the gap between the first doped region and the second doped region, will form the subsequent isolation region 600.

[0103] In an optional embodiment, the silicon wafer 100 with the pyramid base 200 on its back side is obtained by texturing and polishing the back side of the silicon wafer 100 using an alkaline solution.

[0104] In an optional embodiment, the side length of the pyramid base 200 is 1~10μm, for example, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm.

[0105] In an optional embodiment, the alkaline solution is a sodium hydroxide or potassium hydroxide solution with a mass fraction of 1% to 5%, such as 1%, 1.4%, 1.8%, 2.2%, 2.6%, 3.0%, 3.4%, 3.8%, 4.2%, 4.6%, or 5%.

[0106] In an optional embodiment, the alkaline solution further includes isopropanol, and the volume fraction of isopropanol in the alkaline solution is 2% to 8%, for example, 2%, 2.7%, 3.3%, 4.0%, 4.7%, 5.3%, 6.0%, 6.7%, 7.3%, or 8%.

[0107] In an optional embodiment, the flocking temperature is 70~100℃, for example 70℃, 73℃, 76℃, 79℃, 82℃, 85℃, 88℃, 91℃, 94℃, 97℃, 100℃; the flocking time is 15~40min, for example 15 min, 18 min, 21 min, 24 min, 27 min, 30 min, 33 min, 36 min, 39 min, 40 min.

[0108] Alkaline texturing and a suitable pyramid size ensure effective light capture.

[0109] In an optional embodiment, the thickness of the mask layer is 50~500nm, for example 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm.

[0110] In an optional embodiment, the material of the mask layer is selected from at least one of silicon oxide, silicon nitride, and amorphous silicon.

[0111] In an optional embodiment, the mask layer is prepared by plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition, with a deposition temperature below 600°C, such as 500°C, 511°C, 522°C, 533°C, 544°C, 555°C, 566°C, 577°C, 588°C, or 600°C.

[0112] In the fabrication method of the back-contact solar cell of this application, the mask layer deposited at low temperature balances pattern fidelity and silicon substrate integrity.

[0113] In an optional embodiment, the photoresist thickness is 1~3μm, for example 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2.0 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3.0 μm.

[0114] The exposure dose for the photolithography step is 50~250mJ / cm 2 For example, 50 mJ / cm 2 72 mJ / cm 2 94 mJ / cm 2 116mJ / cm 2 138 mJ / cm 2 160 mJ / cm 2 182 mJ / cm 2 204 mJ / cm 2 226 mJ / cm 2 250 mJ / cm 2 .

[0115] In an optional implementation, the etching process employs either dry etching or wet etching.

[0116] In the fabrication method of the back contact solar cell of this application, the photolithography and etching parameters are combined with the masking method to ensure sharp boundaries of the doped region.

[0117] In an alternative implementation, the formation of the first doped region and / or the formation of the first doped region includes high-temperature thermal diffusion or the introduction of dopant elements during the deposition of a polycrystalline silicon thin film.

[0118] In an optional embodiment, the method further includes: forming a tunneling oxide layer 300 on the first target doped region and the second target doped region using a thermal oxidation method, and then using a low-pressure chemical vapor deposition method to perform in-situ doping with a dopant while depositing a polycrystalline silicon layer, thereby forming the first doped region and the second doped region respectively.

[0119] In an optional embodiment, the temperature of the thermal oxidation method is 600~750℃, for example 600℃, 617℃, 634℃, 651℃, 668℃, 685℃, 702℃, 719℃, 736℃, 750℃; the atmosphere is oxygen; and the thickness of the tunneling oxide layer 300 is 1~2nm, for example 1.0 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2.0 nm.

[0120] In an optional embodiment, the temperature of the low-pressure chemical vapor deposition is 550~650°C, for example 550°C, 561°C, 572°C, 583°C, 594°C, 605°C, 616°C, 627°C, 638°C, or 650°C.

[0121] In an optional embodiment, the thickness of the polycrystalline silicon layer is 50~300 nm, for example 50 nm, 78 nm, 106 nm, 134 nm, 162 nm, 190 nm, 218 nm, 246 nm, 274 nm, 300 nm.

[0122] In the fabrication method of the back contact solar cell of this application, in-situ doping and thermal oxidation / annealing work together to achieve uniformity of the tunneling layer and activation of the doping.

[0123] In an optional embodiment, the high-temperature annealing is carried out in an inert gas atmosphere, and the annealing temperature is 800~1000℃, for example 800℃, 822℃, 844℃, 866℃, 888℃, 910℃, 932℃, 954℃, 976℃, 1000℃; the annealing time is 10~60min, for example 10 min, 16 min, 22 min, 28 min, 34 min, 40 min, 46 min, 52 min, 58 min, 60 min.

[0124] In an optional embodiment, the passivation layer is selected from at least one of silicon nitride and aluminum oxide, and has a thickness of 80~120 nm, such as 80 nm, 84 nm, 88 nm, 92 nm, 96 nm, 100 nm, 104 nm, 108 nm, 112 nm, 116 nm, and 120 nm.

[0125] In an optional embodiment, the metal electrode 700 is selected from at least one of silver, silver alloys, copper, and copper alloys.

[0126] In the fabrication method of the back contact solar cell of this application, the selection of passivation layer and metal electrode materials is beneficial to achieving high Voc and low Rs.

[0127] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0128] Example 1

[0129] This embodiment provides a method for fabricating a back-contact solar cell, including:

[0130] Substrate preparation and texturing: The back side of silicon wafer 100 is texturized and polished using an alkaline solution to obtain silicon wafer 100 with a pyramid base 200 on the back side; the alkaline solution is sodium hydroxide with a mass fraction of 3%, and the alkaline solution also includes isopropanol with a volume fraction of 5%, the texturing temperature is 85℃, the texturing time is 30min, and after polishing, the side length of the pyramid base 200 is 5μm;

[0131] Mask layer fabrication: A mask material is deposited on the back side of a silicon wafer 100 with a pyramid base 200 on the back side using plasma-enhanced chemical vapor deposition at a deposition temperature of 500℃ to form a mask layer with a thickness of 300nm. The material of the mask layer is silicon oxide.

[0132] Patterned mask layer: A 2μm thick photoresist is coated on the mask layer. The electrode pattern is transferred onto the photoresist by photolithography to form a photoresist pattern. The exposure dose is 150mJ / cm. 2 Next, the photoresist pattern is transferred to the mask layer by dry etching to expose the first target doped region;

[0133] The first doped region was formed by thermal oxidation to create a 1.5 nm thick tunneling oxide layer 300 on the first target doped region. Then, low-pressure chemical vapor deposition (LPCVD) was used to simultaneously deposit a polycrystalline silicon layer and perform in-situ doping with a dopant to form the first doped region, resulting in a 180 nm thick polycrystalline silicon layer. The thermal oxidation process was performed at 700 °C in an oxygen atmosphere, and the LCVD was conducted at 600 °C using diborane as the dopant at a concentration of 5 × 10⁻⁶. 19 cm -3 ;

[0134] Remove the remaining mask layer to expose the second target doped region; use a hydrofluoric acid solution (5% by volume) with a high etching rate for the mask layer material and a low etching rate for silicon and polysilicon to remove the remaining mask layer and expose the undoped second target doped region.

[0135] The second doped region was formed by using thermal oxidation to create a 1.5 nm thick tunneling oxide layer 300 on the second target doped region. Then, low-pressure chemical vapor deposition (LPCVD) was used to simultaneously deposit the polycrystalline silicon layer and perform in-situ doping with a dopant to form the second doped region, resulting in a 180 nm thick polycrystalline silicon layer. The thermal oxidation process was performed at 700°C in an oxygen atmosphere, and the LCVD was conducted at 600°C using phosphine (PH3) as the dopant with a doping concentration of 5 × 10⁻⁶. 19 cm -3 ;

[0136] Annealing activation: Silicon wafer 100 is annealed at high temperature in an inert gas atmosphere at 900℃ for 40 minutes.

[0137] Passivation layer and metal electrode 700 preparation: A passivation layer with a thickness of 100 nm is deposited on the back side of silicon wafer 100. The passivation layer is silicon nitride. Metal electrodes 700 are prepared to form ohmic contacts with the first doped region and the second doped region, respectively. The metal electrode 700 is selected from at least one of silver, silver alloy, copper and copper alloy.

[0138] The first doped region is a P-type doped region 400, and the second doped region is an N-type doped region 500.

[0139] The back-contact solar cell structure prepared in this embodiment is as follows: Figure 2 As shown, the device includes a silicon wafer 100, with a pyramidal base 200 disposed on the back side of the silicon wafer 100. A doped polycrystalline silicon layer is disposed on the pyramidal base 200 of the silicon wafer 100. The doped polycrystalline silicon layer includes P-type doped regions 400, N-type doped regions 500, and isolation regions 600 separating the P-type doped regions 400 and N-type doped regions 500. The P-type doped regions 400 and N-type doped regions 500 are arranged alternately in an interdigitated pattern. The isolation region 600 is observed under 100x electron microscopy, and the image obtained is shown below. Figure 3 As shown, the isolation region 600 is a continuous band with no observed grain structure inside. The roughness of the line edge between the isolation region 600 and the N-type doped region 500 is 0.28 μm, the roughness of the line edge between the isolation region 600 and the P-type doped region 400 is 0.24 μm, the surface roughness of the P-type doped region 400 is 23 nm, the surface roughness of the N-type doped region 500 is 27 nm, and the root mean square roughness of the P-type doped region 400 and the N-type doped region 500 is 12 nm.

[0140] The average grain size of the N-type doped region 500 is 1.67 times that of the P-type doped region 400; the average grain size of the N-type doped region 500 is 300 nm; and the average grain size of the P-type doped region 400 is 120 nm.

[0141] Under 100x magnification using an electron microscope, the P-type doped region 400 is observed to have a polygonal grid structure with clear and continuous boundaries, and the doped region pattern feature size of the P-type doped region 400 is 15 μm; the N-type doped region 500 is observed to have rectangular, hexagonal, strip, and rhomboid grain structures, and the doped region pattern feature size of the N-type doped region 500 is 25 μm.

[0142] Example 2

[0143] The main difference between the back contact solar cell in this embodiment and that in Embodiment 1 is that the average grain size of the N-type doped region 500 is 100 nm, the average grain size of the P-type doped region 400 is 90 nm, and the grain size of the N-region is basically the same as that of the P-region (the N-region grain size is only 1.1 times that of the P-region), and no significant difference in grain size is formed.

[0144] The main difference between the preparation method and Example 1 is that the low-pressure chemical vapor deposition temperature was adjusted to 500°C, the deposition rate was reduced, resulting in insufficient crystallinity of the polycrystalline silicon layer. At the same time, the annealing temperature was adjusted to 750°C, and the annealing time was shortened to 5 minutes, which failed to provide sufficient activation energy to promote grain growth.

[0145] Example 3

[0146] The main difference between the back contact solar cell in this embodiment and that in Embodiment 1 is that the average grain size of the N-type doped region 500 is 600 nm and the average grain size of the P-type doped region 400 is 120 nm. The grain size of the N-region is significantly larger than that of the P-region (the N-region grain size is about 5 times that of the P-region), exceeding the upper limit of the preferred range (1.2 to 3 times).

[0147] The main difference between the preparation method and Example 1 is that in the second doped region formation step, the deposition temperature of the N-type doped region is adjusted to 700℃, the annealing temperature is adjusted to 1050℃, and the annealing time is extended to 90 minutes. The excessively high thermal budget leads to excessive growth of the N-region polycrystalline silicon layer grains, with some grains exceeding 800 nm in size, and the grain size distribution is uneven, resulting in local abnormally large grains.

[0148] Example 4

[0149] The main difference between the back-contact solar cell in this embodiment and that in Embodiment 1 is that the P-type doped region 400 has a bar pattern, the N-type doped region 500 has a bar pattern, and the P-region and N-region are arranged in an alternating interdigitated bar pattern.

[0150] The main difference between the preparation method and Example 1 is that the design of the photomask is different. The rectangular grid pattern of the N region in Example 1 is changed to a bar pattern with a bar width of 600 μm and a bar spacing (corresponding to the width of the P region) of 250 μm. The area ratio of the N region is about 70%, which is basically the same as that of Example 1.

[0151] Example 5

[0152] The main difference between the back-contact solar cell in this embodiment and that in Embodiment 1 is that the P-type doped region 400 has a rectangular grid pattern with a doped region pattern feature size of 80 μm, the N-type doped region 500 has a rectangular grid pattern with a doped region pattern feature size of 150 μm, and the total projected area of ​​the N-region on the back side accounts for approximately 45%.

[0153] The main difference between the preparation method and Example 1 is that the design of the photomask in step 3 is different. The N-region pattern size (600μm) in Example 1 is reduced to 150μm, and the P-region pattern size (200μm) is reduced to 80μm. At the same time, the pattern arrangement density is adjusted so that the area ratio of the N-region is reduced from 70% to 45%.

[0154] Comparative Example 1

[0155] This comparative example provides a method for fabricating a back-contact solar cell, including:

[0156] Step 1: Substrate preparation and texturing. A silicon substrate is provided, and the back side of the silicon substrate is anisotropically etched using an alkaline solution to form a pyramidal texturing structure. After polishing, a pyramidal base is formed.

[0157] Step 2: Front masking and global doping. A protective mask is deposited on the front side of the silicon wafer, and global boron diffusion is performed on the back side to form a P-type doped layer. The diffusion temperature is 950℃, the diffusion time is 60min, and the sheet resistance is controlled at 80~100Ω.

[0158] Step 3: Laser grooving and patterning. A 355nm ultraviolet picosecond laser is used to perform laser grooving on the back side. The laser spot diameter is 40μm, the laser power is 8W, the scanning speed is 4m / s, and the grooving depth is 350nm. Laser ablation selectively removes some areas of the P-type doped layer and pyramid base, forming a patterned opening in the N-region to be doped. After laser grooving, a heat-affected zone appears at the grooving edge, and some of the pyramid base is melted and resolidified, damaging the surface morphology.

[0159] Step 4: Alkaline polishing and cleaning. A 3.5% potassium hydroxide solution is used to perform alkaline polishing on the back side to clean the slag and damaged layer generated by laser grooving. The treatment temperature is 70℃, and the treatment time is 6 minutes. During alkaline polishing, the laser-damaged area is preferentially corroded, resulting in obvious "V"-shaped corrosion pits in the grooved area, severely damaging the pyramid base.

[0160] Step 5: Phosphorus diffusion doping. Phosphorus diffusion doping is performed on the slotted area to form an N-type doped region. The diffusion temperature is 900℃, the diffusion time is 30min, and the sheet resistance is controlled at 60~80Ω / □.

[0161] Step 6: Annealing and activation. Annealing and activation are carried out in a nitrogen atmosphere at a temperature of 900℃ for 30 minutes.

[0162] Step 7: Passivation layer and metal electrode fabrication. A silicon nitride passivation layer with a thickness of 100 nm is deposited on the back side. Interdigitated silver electrodes are fabricated by screen printing, and ohmic contacts are formed after sintering. An electron microscope schematic diagram of the back side of the battery is shown below. Figure 4 As shown.

[0163] The performance of the back-contact solar cells prepared in the above embodiments and comparative examples was measured. The specific measurement methods are as follows, and the test results are shown in Table 1.

[0164] Interface defect density test: The interface quality between the silicon substrate and the tunneling oxide layer 300 was evaluated using the capacitance-voltage (CV) method, and the interface state density and fixed charge density were calculated (test temperature 25±2℃, test environment was dark and shielded).

[0165] Electrical performance (photovoltaic conversion efficiency, open-circuit voltage, series resistance, fill factor) tests were conducted. Under standard test conditions (STC: AM1.5 spectrum, 1000 W / m² irradiance, 25℃), the current-voltage characteristic curve of the battery was measured, and the above parameters were extracted.

[0166] Table 1

[0167]

[0168] In Table 1, Nmax / min is the ratio of the maximum to the minimum size of the doped region pattern located in the N-type doped region, and Pmax / min is the ratio of the maximum to the minimum size of the doped region pattern located in the P-type doped region.

[0169] The test results above show that the size uniformity (maximum / minimum) of the N-region in Examples 1-5 is between 1.08 and 1.27, and that of the P-region is between 1.14 and 1.31, both meeting the requirement of ≤1.5. In contrast, the N-region uniformity of the comparative examples is 1.56, and the P-region uniformity is 1.64, both exceeding 1.5, indicating that the pattern size fluctuation of the laser process is significantly greater than that of the mask process.

[0170] Example 1 of this invention exhibits the best performance, achieving a photoelectric conversion efficiency of 26.3%, an open-circuit voltage of 738 mV, and a fill factor of 84.6%, all significantly superior to other examples and comparative examples. Its interface defect state density (3.5 × 10⁻⁶) is also significantly higher. 10 cm -2 eV -1 ) and fixed charge density (2.3 × 10 11 cm - ²) The lowest value indicates that the smooth and complete pyramidal base texture provides an ideal interface for the growth of the tunnel oxide layer, resulting in the best passivation effect.

[0171] In Example 2, due to the excessively small N-region grain size (100 nm), grain boundary recombination increased, and the interface defect density rose to 8.2 × 10⁻⁶. 10 cm -2 eV -1 The efficiency dropped to 24.8%. In Example 3, due to excessive growth (600 nm) and uneven distribution of N-region grains, the interface quality decreased, and the efficiency was 25.1%. It can be seen that the grain size ratio needs to be controlled within the preferred range (1.2 to 3 times).

[0172] Example 4 uses a strip pattern, achieving an efficiency of 25.7%, slightly lower than Example 1, but with a simplified process. Example 5 suffers from a low N-region area ratio (45%), resulting in a decreased carrier collection efficiency of 25.2%. Comparative Example 1 uses a laser process, which severely damages the pyramid shape, leading to an interface defect density as high as 1.8 × 10⁻⁶. 11 cm -2 eV -1 The efficiency was only 23.6%, which verifies the technical advantages of the mask process of this invention.

[0173] In summary, this invention achieves precise patterning of the doped and isolated regions through a masking process. The isolated region is a continuous strip with sharp, straight boundaries, effectively preventing leakage risks between the P-type and N-type doped regions. Crucially, it achieves differentiated design of polycrystalline silicon grain sizes in the P- and N-type regions on the same back side of the cell: the P-type doped region exhibits a fine, uniform small-grain mesh structure, which helps reduce lateral resistance and improve conductivity uniformity; the N-type doped region forms a coarse, anisotropic grain structure, significantly reducing grain boundary recombination losses and optimizing the vertical carrier transport path. The synergistic effect of these two technologies, combined with a smooth and complete pyramidal base interface, comprehensively improves the passivation quality, contact characteristics, and photoelectric conversion efficiency of the cell.

[0174] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A back-contact solar cell, characterized in that, include: A silicon wafer, wherein a doped polycrystalline silicon layer is disposed on the pyramid base on the back side of the silicon wafer, the doped polycrystalline silicon layer includes a P-type doped region, an N-type doped region and an isolation region separating the P-type doped region and the N-type doped region, and a doped region pattern is formed in the doped polycrystalline silicon layer; The ratio of the maximum to the minimum size of the doped region pattern located in the N-type doped region is less than or equal to 1.5; The ratio of the maximum to the minimum size of the doped region pattern located in the P-type doped region is less than or equal to 1.

5.

2. The back-contact solar cell according to claim 1, characterized in that, The average doped region pattern feature size is 1.2 to 2.0 times that of the average doped region pattern feature size of the P-type doped region; the roughness of the line edges between the isolation region and the N-type doped region, as well as the line edges between the isolation region and the P-type doped region, is less than 0.5 μm; And / or, the surface roughness of the P-type doped region and the N-type doped region is less than or equal to 50 nm; And / or, the root mean square roughness of the P-type doped region and the N-type doped region is less than 20 nm.

3. The back-contact solar cell according to claim 1, characterized in that, The average grain size of the N-type doped region is greater than that of the P-type doped region.

4. The back-contact solar cell according to claim 3, characterized in that, The average grain size of the N-type doped region is 1.2 to 3 times that of the P-type doped region; And / or, the average grain size of the N-type doped region is 100~500nm; And / or, the average grain size of the P-type doped region is 50~200nm.

5. The back-contact solar cell according to claim 1, characterized in that, When observed under 100x electron microscopy, the P-type doped region exhibits a polygonal grid structure with clear and continuous boundaries. And / or, the projection pattern of the N-type doped region in the direction parallel to the substrate, observed under 100x electron microscopy, includes rectangles, hexagons, bars, and rhombuses; And / or, when observed under 100x electron microscopy, the doped region pattern feature size of the N-type doped region is 10~30μm; And / or, when observed under 100x electron microscopy, the doped region pattern feature size of the P-type doped region is 5~20 μm; And / or, a tunneling oxide layer is further provided between the pyramid base of the silicon wafer and the doped polycrystalline silicon layer.

6. The back-contact solar cell according to claim 5, characterized in that, The thickness of the tunneling oxide layer is 1~2.5 nm; And / or, the thickness difference between different locations of the tunneling oxide layer is less than 0.3 nm; And / or, when observing the N-type doped region under 100x magnification using an electron microscope, the area ratio of rectangles in the projection pattern parallel to the substrate direction is 40-70%, the area ratio of hexagons is 10-30%, the area ratio of bars is 10-30%, and the area ratio of rhombuses is 5-20%.

7. A method for preparing a back-contact solar cell as described in any one of claims 1 to 6, characterized in that, include: A masking material is deposited on the back of a silicon wafer with a pyramid base on the back to form a mask layer; Photoresist is coated on the mask layer, and the electrode pattern is transferred to the photoresist by photolithography to form a photoresist pattern; then the photoresist pattern is transferred to the mask layer by etching to expose the first target doped region; A first doped region is formed in the first target doped region; Remove the remaining mask layer to expose the second target doped region; A second doped region is formed in the second target doped region; High-temperature annealing of silicon wafers; A passivation layer is deposited on the back side of the silicon wafer, and metal electrodes are fabricated to form ohmic contacts with the first doped region and the second doped region, respectively. Wherein, the first doped region is a P-type doped region and the second doped region is an N-type doped region, or the first doped region is an N-type doped region and the second doped region is a P-type doped region.

8. The method for preparing a back-contact solar cell according to claim 7, characterized in that, The silicon wafer with a pyramid base on the back is obtained by texturing and polishing the back of the silicon wafer using an alkaline solution. And / or, the thickness of the mask layer is 50~500nm; And / or, the material of the mask layer is selected from at least one of silicon oxide, silicon nitride, and amorphous silicon; And / or, the mask layer is prepared by plasma-enhanced chemical vapor deposition or low-pressure chemical vapor deposition, with a deposition temperature below 600°C; And / or, the photoresist thickness is 1~3μm, and the exposure dose for the photolithography step is 50~250mJ / cm. 2 ; And / or, the etching is performed using dry etching or wet etching; And / or, the formation of the first doped region and / or the formation of the first doped region includes high-temperature thermal diffusion or the introduction of doping elements during the deposition of a polycrystalline silicon thin film; And / or, also includes: forming a tunneling oxide layer on the first target doped region and the second target doped region by thermal oxidation, and then using low-pressure chemical vapor deposition to perform in-situ doping with a dopant while depositing a polycrystalline silicon layer, to form the first doped region and the second doped region respectively. And / or, the high-temperature annealing is carried out in an inert gas atmosphere, the annealing temperature is 800~1000℃, and the annealing time is 10~60min; And / or, the passivation layer is selected from at least one of silicon nitride and aluminum oxide, and has a thickness of 80~120nm; And / or, the metal electrode is selected from at least one of silver, silver alloys, copper, and copper alloys.

9. The method for preparing a back-contact solar cell according to claim 8, characterized in that, The alkaline solution is a sodium hydroxide or potassium hydroxide solution with a mass fraction of 1% to 5%. And / or, the alkaline solution further includes isopropanol, wherein the volume fraction of isopropanol in the alkaline solution is 2% to 8%; And / or, the flocking temperature is 70~100℃, and the flocking time is 15~40min.

10. The method for preparing a back-contact solar cell according to claim 8, characterized in that, The thermal oxidation method is performed at a temperature of 600-750°C, in an oxygen atmosphere, and the thickness of the tunneling oxide layer is 1-2 nm. And / or, the temperature of the low-pressure chemical vapor deposition is 550~650°C; And / or, the thickness of the polycrystalline silicon layer is 50~300 nm.

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