Integrated circuits and their manufacturing methods

Abstract

This disclosure provides an integrated circuit and a method for manufacturing the same. A process forms alternating first and second metal lines in an interlayer dielectric layer. A first photolithography and etching process forms trenches in a patterned layer. A plurality of dielectric spacers are formed on the sidewalls of the trenches. A second photolithography and etching process forms a pattern of the first metal lines in a hard mask layer between the interlayer dielectric layer and the patterned layer based on the dielectric spacers. A third photolithography and etching process forms a pattern of the second metal lines in the hard mask layer based on the dielectric spacers. The pattern of the first and second metal lines is then transferred to the interlayer dielectric layer by an etching process, serving as trenches in the interlayer dielectric layer. The first and second sets of metal lines are then simultaneously formed by depositing a metal material in the trenches of the interlayer dielectric layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically to integrated circuits and methods of manufacturing thereof. Background Technology

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advancements in integrated circuit materials and design have yielded several generations of integrated circuits, each with smaller and more complex circuits than the previous one. In the development of integrated circuits, functional density (i.e., the number of interconnect devices per unit chip area) has typically increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing integrated circuits.

[0003] One aspect of integrated circuit manufacturing is forming metal lines in a dielectric layer. In scaling-down processes, it is desirable to reduce the width of the metal lines, thereby increasing their density. However, scaling-down processes present challenges when it comes to patterning and forming metal lines with progressively smaller widths and spacings. These challenges can lead to distortions in the metal lines. Such distortions can include undesirable widening of the metal lines, which can result in increased capacitance or even short circuits.

[0004] All topics discussed in the Background section are not necessarily prior art and should not be considered prior art solely because of their discussion in the Background section. Following this line of thought, any awareness of problems in the prior art discussed in the Background section or related to this topic should not be considered prior art unless explicitly stated otherwise. Instead, the discussion of any topic in the Background section should be considered as part of the inventor's solution to a particular problem and may itself be inventive. Summary of the Invention

[0005] In a first aspect, embodiments of the present disclosure provide a method comprising: forming a patterned layer over an interlayer dielectric layer of an integrated circuit; forming a plurality of first trenches in the patterned layer using a first photolithography process; conformally depositing a dielectric layer on the patterned layer and in the trenches; forming a plurality of spacers from the dielectric layer by removing the dielectric layer from a top surface of the patterned layer, each spacer lining a sidewall of a corresponding first trench; forming a plurality of first metal lines in the interlayer dielectric layer, each first metal line being laterally self-aligned with one of the spacers; and forming a plurality of second metal lines in the interlayer dielectric layer, the plurality of second metal lines being laterally staggered with the first metal lines, and each second metal line being laterally self-aligned with the gap between adjacent spacers.

[0006] In a second aspect, embodiments of the present disclosure provide a method comprising: forming a plurality of first trenches in a patterned layer above an interlayer dielectric layer using a first photolithography and etching process; forming a plurality of spacers, each spacer lining the sidewall of a corresponding first trench and spaced apart from each other; forming a plurality of second trenches in a hard mask layer below the patterned layer using a second photolithography process; and forming a plurality of third trenches in the hard mask layer that alternate laterally with the second trenches, the second trenches and third trenches being self-aligned laterally with the spacers.

[0007] In a third aspect, embodiments of this disclosure provide an integrated circuit, comprising: a plurality of transistors; an interlayer dielectric layer above the transistors; a plurality of first metal lines extending in a first lateral direction in the interlayer dielectric layer; and a plurality of second metal lines extending in the first lateral direction in the interlayer dielectric layer and alternating with the first metal lines in a second lateral direction perpendicular to the first lateral direction, wherein the first metal lines have a plurality of different end-to-end dimensions, and wherein the second metal lines have a plurality of different end-to-end dimensions. Attached Figure Description

[0008] Figures 1 to 13C These are cross-sectional and top views of integrated circuits at various process stages according to some embodiments.

[0009] Figure 14 This is a cross-sectional view of an integrated circuit according to some embodiments.

[0010] Figure 15A This is a layout of an integrated circuit according to some embodiments.

[0011] Figure 15B It is based on some implemented embodiments Figure 15A A top view of the layout of the integrated circuit.

[0012] Figure 16 This is a cross-sectional view of an integrated circuit according to some embodiments.

[0013] Figure 17 This is a cross-sectional view of an integrated circuit according to some embodiments.

[0014] Figure 18 This is a cross-sectional view of an integrated circuit according to some embodiments.

[0015] Figure 19 This is a flowchart of a method for forming an integrated circuit according to some embodiments.

[0016] Figure 20 This is a flowchart of a method for forming an integrated circuit according to some embodiments.

[0017] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, spatially related terms (e.g., "below," "under," "lower," "above," "higher," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). In addition to the orientations depicted in the figures, these spatially related terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly.

[0020] In the following description, certain specific details are set forth to provide a thorough understanding of various embodiments of this disclosure. However, those skilled in the art will understand that this disclosure may be practiced without these specific details. In other instances, well-known structures related to electronic components and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring the description of embodiments of this disclosure.

[0021] Unless the context otherwise requires, the word “comprising” and its variations, such as “including” and “containing”, shall be interpreted in an open, non-exclusive sense in the following description and claims, meaning “including, but not limited to”.

[0022] The use of ordinal numbers such as first, second, and third does not necessarily imply a sorting order, but may simply distinguish multiple instances of an action or structure.

[0023] References to “some embodiments” or “embodiments” throughout this specification mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases “in some embodiments” or “in an embodiment” appearing in various places throughout this specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0024] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include the plural referents unless the context clearly indicates otherwise. It should also be noted that, unless the content clearly indicates otherwise, the term “or” is generally used in its meaning including “and / or.”

[0025] As used herein, “light” generally refers to electromagnetic radiation of any wavelength unless a specific band or wavelength is specified. Therefore, unless otherwise stated, “light” means X-ray radiation, extreme ultraviolet (EUV) radiation, ultraviolet (UV) radiation, visible radiation, infrared radiation, or other bands, wavelengths, or categories of electromagnetic radiation. Furthermore, as used herein, “optical system” can include any system that receives / generates and utilizes electromagnetic radiation.

[0026] Embodiments of this disclosure provide a method for forming metal lines in an interlayer dielectric layer of an integrated circuit. The process forms a group of metal lines into a first set of metal lines and a second set of metal lines laterally intersecting the first set of metal lines. A patterned layer is formed over the interlayer dielectric layer. A first photolithography and etching process forms tracks in the patterned layer. Multiple dielectric spacers are formed on the sidewalls of the tracks, wherein the top surface of a hard mask layer is exposed at the bottom of the tracks. A second photolithography and etching process forms the pattern of the first set of metal lines in the hard mask layer based on the dielectric spacers. A third photolithography and etching process forms the pattern of the second set of metal lines in the hard mask layer based on the dielectric spacers. The patterns of the first and second sets of metal lines are then transferred to the interlayer dielectric layer as trenches in the interlayer dielectric layer by an etching process. The first and second sets of metal lines are then simultaneously formed by depositing metal material in the trenches.

[0027] The embodiments of this disclosure offer several benefits. First, separate photolithography and etching processes are eliminated to form breaks in the metal lines. Second, in the patterned layer, the trenches or windows for the first and second sets of metal lines are limited by dielectric spacers. This allows the two sets of metal lines to have multiple end-to-end dimensions or small dimensions (e.g., very small end-to-end distances). Excess line length and redundant metal are also significantly reduced. These lines do not have the characteristic of laterally expanding at unrestricted locations. This further results in better integrated circuit performance and fewer scrapped wafers.

[0028] Figures 1 to 13C These are cross-sectional and top views of an integrated circuit 100 at various process stages according to some embodiments. Figures 1 to 13C The formation of metal lines in the interlayer dielectric layer is shown. Regarding... Figures 1 to 13C The process shown efficiently and effectively forms metal wires with improved properties compared to other possible solutions. This process corresponds to a back-end processing (BEOL) process.

[0029] Figure 1 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 1 Interlayer dielectric layer 102 is shown. In some embodiments, the interlayer dielectric layer comprises a low-k dielectric material. In some embodiments, interlayer dielectric layer 102 comprises silicon oxide (e.g., SiO2). Interlayer dielectric layer 102 may comprise SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. Interlayer dielectric layer 102 may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) or other suitable deposition processes. Interlayer dielectric layer 120 has a thickness between 50 nm and 500 nm, but other thicknesses may be used without departing from the scope of this disclosure.

[0030] Although the interlayer dielectric layer 102 is shown as a single dielectric layer, in some embodiments, the interlayer dielectric layer 102 includes multiple dielectric layers stacked on top of each other.

[0031] In some embodiments, an interlayer dielectric layer 102 is formed over an active circuit region (not shown). The active circuit region includes a plurality of transistors. The transistors include PMOS transistors and NMOS transistors. In some embodiments, the transistors are core logic circuits. In some embodiments, the transistors form part of an SRAM array of integrated circuit 100.

[0032] In some embodiments, the active circuit region includes a semiconductor substrate. A channel region and a source / drain region of the transistor are formed together with the semiconductor substrate. A gate dielectric layer and a gate metal of the transistor are formed adjacent to the channel region. Gate contacts corresponding to conductive vias or conductive plugs extend downward to contact the gate region. Source / drain contacts corresponding to conductive vias or conductive plugs extend downward to contact the source / drain regions. Dielectric layers including gate spacers are formed on the transistor structure.

[0033] An interlayer dielectric layer 102 is formed on each structure of the active circuit region. Although not in Figure 1As shown, however, conductive vias can be formed in the lower part of the interlayer dielectric layer 102. Metal lines subsequently formed in the interlayer dielectric layer 102 can then contact the conductive vias at selected locations.

[0034] In some embodiments, the integrated circuit 100 includes a hard mask layer 104 over an interlayer dielectric layer 102. As will be explained in more detail below, the hard mask layer 104 corresponds to a layer that will ultimately be patterned with a pattern corresponding to the layout of metal lines to be formed in the interlayer dielectric layer 102. After patterning the hard mask layer 104, trenches can be formed in the interlayer dielectric layer 102 based on the patterned hard mask layer 104. Conductive material can then be deposited in the trenches in the interlayer dielectric layer 102 to form metal lines in the trenches.

[0035] In some embodiments, the hard mask layer 104 includes a plurality of hard mask sublayers. Figure 1 In this configuration, the hard mask layer 104 includes a first hard mask sublayer 106 on the interlayer dielectric layer 102. The hard mask layer 104 includes a second hard mask sublayer 108 on the first hard mask sublayer 106. The hard mask layer 104 includes a third hard mask sublayer 110 on the second hard mask sublayer 108.

[0036] In some embodiments, the first hard mask sublayer 106 comprises tetraethyl orthosilicate (TEOS). The first hard mask sublayer 106 can be deposited by CVD, ALD, or PVD. Other deposition processes and materials can be used for the first hard mask sublayer 106 without departing from the scope of this disclosure. The first hard mask sublayer 106 has a thickness between 20 nm and 28 nm, but other thicknesses can be used without departing from the scope of this disclosure.

[0037] In some embodiments, the second hard mask sublayer 108 comprises tungsten-doped carbon (tungsten-doped carbon). The second hard mask sublayer 108 can be deposited by CVD, ALD, or PVD. Other deposition processes and materials can be used for the second hard mask sublayer 108 without departing from the scope of this disclosure. The second hard mask sublayer 108 has a thickness between 10 nm and 15 nm, but other thicknesses can be used without departing from the scope of this disclosure.

[0038] In some embodiments, the third hard mask sublayer 110 comprises tetraethyl orthosilicate (TEOS). The third hard mask sublayer 110 can be deposited by CVD, ALD, or PVD. Other deposition processes and materials can be used for the third hard mask sublayer 110 without departing from the scope of this disclosure. The third hard mask sublayer 110 has a thickness between 7 nm and 12 nm, but other thicknesses can be used without departing from the scope of this disclosure.

[0039] In some embodiments, the integrated circuit 100 includes a patterned layer 112 on a hard mask layer 104. Figure 1 In the example, patterning layer 112 is located on the third hard mask sublayer 110. As will be explained in more detail below, patterning layer 112 serves as a layer that facilitates the transfer of patterns of the first and second sets of metal lines to hard mask layer 104. As will be explained in more detail below, tracks or trenches will be formed in patterning layer 112. Spacers will then be formed on the sidewalls of the tracks. The combination of spacers and patterning layer 112 will facilitate the transfer of patterns of the first and second sets of metal lines to hard mask layer 104.

[0040] In some embodiments, the patterned layer 112 comprises amorphous silicon, which has good etch selectivity relative to the dielectric layer 106 spacers, thereby achieving strong self-alignment. In some embodiments, the patterned layer 112 is deposited by PVD, ALD, or CVD. In some embodiments, the patterned layer 112 has a thickness between 35 nm and 50 nm. Other materials, thicknesses, and deposition processes may be used for the patterned layer 112 without departing from the scope of this disclosure.

[0041] According to some embodiments, the integrated circuit 100 includes a dielectric layer 114 on a patterned layer 112. In some embodiments, the dielectric layer 114 comprises amorphous carbon. In some embodiments, the dielectric layer is deposited by CVD, ALD, or PVD. In some embodiments, the dielectric layer 114 has a thickness between 10 nm and 50 nm. Other materials, deposition processes, and thicknesses may be used for the dielectric layer 114 without departing from the scope of this disclosure.

[0042] According to some embodiments, integrated circuit 100 includes a dielectric layer 116 on dielectric layer 114. In some embodiments, dielectric layer 116 includes SiOC. In some embodiments, the dielectric layer is deposited by CVD, ALD, or PVD. In some embodiments, dielectric layer 116 has a thickness between 10 nm and 50 nm. Other materials, deposition processes, and thicknesses may be used for dielectric layer 116 without departing from the scope of this disclosure.

[0043] exist Figure 1 In some embodiments, a photoresist layer 118 has been formed on a dielectric layer 116. The photoresist layer 118 comprises a material having a composition that changes upon exposure to photolithography. In some embodiments, the photoresist layer 118 comprises a material sensitive to extreme ultraviolet (EUV) radiation from about 13.5 nm. In some embodiments, the photoresist layer 118 comprises a positive photoresist. In some embodiments, the photoresist layer 118 comprises an organic photoresist.

[0044] exist Figure 2AIn this process, a photolithography process has been performed. The photolithography process involves exposing a photoresist layer 118 to photolithographic light, which includes a pattern of a photomask. After exposure, the exposed portion of the photoresist layer 118 is removed, thereby creating a pattern of trenches 120 in the photoresist layer 118. The pattern of the trenches 120 corresponds to the pattern of the photomask. As will be explained in more detail below, this pattern of the trenches 120 will be used to form a set of initial tracks in the patterning layer 112.

[0045] Figure 2B The integrated circuit 100 according to some embodiments is in Figure 2A A top view of the process stage shown. Figure 2A The cross-sectional view is along Figure 2B It was cut by the cutting line 2A. Figure 2B A top view shows rectangular trenches 120 formed in the photoresist layer 118. The top surface of the dielectric layer 116 is exposed in the trenches 120. Although Figure 2B The trench 120 is shown to have right-angled ends, but in some embodiments, the trench 120 has rounded ends.

[0046] Figure 3A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 3A In this process, an etching process is performed in the presence of a patterned photoresist layer 118. Specifically, a track 122 has been formed in the patterned layer 112. The track 122 has a pattern of trenches 120 in the photoresist layer 118. An etching process has been performed in the downward direction at the locations exposed by the trenches 120 to etch dielectric layers 114 and 116. The etching process continues, and the patterned layer 112 is also etched in the downward direction at the locations exposed by the trenches 120. Thus, the track 122 is formed in the patterned layer 112. The top surface of the hard mask sublayer 110 is exposed at the bottom of the track 122. The track 122 may also be referred to as a trench in the patterned layer 112.

[0047] In some embodiments, a single etching process is performed to etch through dielectric layers 116 and 114 and patterned layer 112. In some embodiments, multiple separate etching steps are performed to etch through dielectric layers 116 and 114 and patterned layer 112. The final etching step selectively etches the patterned layer 112 relative to the hard mask sublayer 110. Thus, the etching process stops at the top surface of the hard mask sublayer 110 without substantially etching the hard mask layer 110. The etching process may include one or more dry etching steps with anisotropic etching in the downward direction.

[0048] Figure 3B The integrated circuit 100 according to some embodiments is in Figure 3AA top view of the process stage shown. Figure 3A The cross-sectional view is along Figure 3B It was cut by the cutting line 3A. Figure 3B The top view shows tracks 122 formed in the patterned layer 112. The top surface of the hard mask sublayer 110 is exposed in the tracks 122. Although Figure 3B Track 122 is shown with right-angled ends, but in some embodiments, track 122 has rounded ends.

[0049] exist Figure 4 In some embodiments, a dielectric layer 124 has been deposited on the integrated circuit 100. The dielectric layer 124 is conformally deposited on the top surface of the patterned layer 112, the sidewalls of the patterned layer 112, and the top surface of the hard mask sublayer 110. In some embodiments, the dielectric layer 124 comprises a material that is selectively etchable relative to the materials of the patterned layer 112 and the hard mask sublayer 110. In some embodiments, the dielectric layer 124 comprises SiON, SiN, SiC, SiOC, SiOCN, SiO, or other suitable materials. The thickness of the dielectric layer 124 is between 8 nm and 15 nm, corresponding to the vertical thickness of the dielectric layer 124 on the top surface of the patterned layer 112 and the lateral thickness on the sidewalls of the patterned layer 112. The dielectric layer 124 can be deposited by CVD, ALD, or PVD. Other materials, thicknesses, and deposition processes may be used for the dielectric layer 124 without departing from the scope of this disclosure.

[0050] The dielectric layer 124 is a spacer layer. As will be described in more detail below, the dielectric layer 124 will be patterned to form spacers on the sidewalls of the track 122. The spacers will be used to form a pattern of a first set of metal lines and a second set of metal lines that intersect the first set of metal lines in the transverse direction.

[0051] Figure 5A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 5AIn this process, an etching process is performed in the presence of a patterned dielectric layer 124. Specifically, spacers 125 are formed from the dielectric layer 124 on the sidewalls of the patterned layer 112 (corresponding to the sidewalls of the track 122). The etching process is an anisotropic etching process that etches in the downward direction. The etching process is a timed etching process, the timing of which is selected to remove an amount of material corresponding to the vertical thickness of the dielectric layer 124 at the top surface of the patterned layer 112 and the hard mask sublayer 110. Since the vertical thickness of the dielectric layer 124 is smaller on the top surface of the patterned layer 112 and the hard mask sublayer 110 than on the sidewalls of the patterned layer 112, the dielectric layer 124 is completely removed from the central portion of the exposed top surface of the patterned layer 112 and the hard mask sublayer 110, without removing the dielectric layer 124 from the sidewalls of the patterned layer 112. Thus, spacers 125 are formed from the dielectric layer 124 on the sidewalls of the patterned layer 112. Some portions of the top surface of the hard mask sublayer 110 are exposed in the orbital 122.

[0052] The formation of spacer 125 defines the general pattern of a first set of metal lines and a second set of metal lines in the interlayer dielectric layer 102. Specifically, the first set of metal lines will be formed below the location of track 122. The second set of metal lines will be formed below the location of the remainder of patterned layer 112. This is entirely defined by the location of spacer 122.

[0053] Figure 5B The integrated circuit 100 according to some embodiments is in Figure 5A A top view of the process stage shown. Figure 5A The cross-sectional view is along Figure 5B It was cut by the cutting line 5A. Figure 5B The top view shows the inner track 122 and the spacer 125 that surrounds the track 122 laterally. The top surface of the hard mask sublayer 110 is exposed in the track 122.

[0054] from Figure 5B As can be seen in the top view, according to some embodiments, each spacer 125 surrounds a region corresponding to track 122. In some embodiments, the surrounded region is rectangular. In some embodiments, the surrounded region is elliptical. The surrounded region corresponds to a location below which a first set of metal lines will be formed in the interlayer dielectric layer 102. The region 123 between the surrounded regions corresponds to a location below which a second set of metal lines will be formed in the interlayer dielectric layer 102.

[0055] As described above, the area beneath each region surrounded by spacer 125 will be used to form a first metal line. However, in practice, multiple first metal lines separated from each other in the Y direction can be formed beneath each surrounded region, as will be described in further detail below. Similarly, multiple second metal lines separated from each other in the Y direction can be formed beneath each region 123 between adjacent spacers 125.

[0056] Figure 6 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 6 In this process, dielectric layer 128, dielectric layer 130, and photoresist layer 132 have been formed, preparing for the second photolithography process. The second photolithography process will be used to define the length (in the Y direction) and position of the first metal line.

[0057] A dielectric layer 128 is formed on the patterned layer 112, the spacer 125, and the exposed portion of the top surface of the hard mask sublayer 110. In some embodiments, the dielectric layer 128 comprises amorphous carbon. In some embodiments, the dielectric layer 128 is deposited by CVD, ALD, or PVD. In some embodiments, the dielectric layer 128 has a thickness between 10 nm and 50 nm. Other materials, deposition processes, and thicknesses may be used for the dielectric layer 128 without departing from the scope of this disclosure.

[0058] According to some embodiments, a dielectric layer 130 is formed on the dielectric layer 128. In some embodiments, the dielectric layer 130 comprises SiOC. In some embodiments, the dielectric layer 130 is deposited by CVD, ALD, or PVD. In some embodiments, the dielectric layer 130 has a thickness similar to that of the dielectric layer 116. Other materials, deposition processes, and thicknesses may be used for the dielectric layer 130 without departing from the scope of this disclosure.

[0059] According to some embodiments, a photoresist layer 132 has been formed on the dielectric layer 130. The photoresist layer 132 is... Figure 1 The photoresist layer 118 is made of the same material.

[0060] Figure 7A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 7A In this process, a photolithography process has been performed. The photolithography process includes exposing a photoresist layer 132 to photolithography light, which includes a pattern on a photomask. After exposure, the exposed portion of the photoresist layer 132 is removed, thereby creating a pattern of trenches 134 in the photoresist layer 132. The pattern of the trenches 134 corresponds to the pattern on the photomask.

[0061] Figure 7ATrench 134 is shown as having the same width as trench 122 in the X direction. However, in some embodiments, trench 134 is wider than trench 122. Trench 134 overlaps with spacer 125. Since the subsequent etching process does not etch spacer 125, there is some margin in the layout of trench 134. This can help to relax the alignment specifications of the trench 134 layout, as the subsequent trench will self-align with spacer 125 or trench 122.

[0062] Figure 7B The integrated circuit 100 according to some embodiments is in Figure 7A The cross-sectional view of the same process stage shown. Figure 7A The cross-sectional view is taken along the cutting line 7A, as shown below. Figure 7C The top view is shown. Figure 7B The cross-sectional view is taken along cutting line 7B, as shown below. Figure 7C The top view is shown. Figure 7C Includes the dashed line indicating the position of the track 122 below the photoresist layer 132.

[0063] Figure 7B and Figure 7C The groove 134 is shown not to extend the entire length of each track 122 in the Y direction. Instead, each groove 134 corresponds to a pattern of a single first metal wire. For the leftmost track 122, a single groove 134 is formed to correspond to a pattern of a single first metal wire. For the second track 122 from the left, two grooves 134 are formed, separated from each other in the Y direction, and correspond to patterns of two first metal wires. For the second track 122 from the right, a single groove 134 is formed to correspond to a pattern of a single first metal wire. For the rightmost track 122, a single groove 134 is formed to correspond to a pattern of a single first metal wire.

[0064] As will be explained in more detail below, the ends of each groove 134 (in the Y direction) are patterned without the need for separate masks to form cuts or breaks separating adjacent metal lines. Therefore, the ends of adjacent first metal lines can be placed very close together. Furthermore, the ends of the first metal lines can be positioned away from the ends of track 122 as needed. This results in less unnecessary or redundant metal. The first metal lines can be substantially as long (or short) as desired.

[0065] Figure 8A and Figure 8B This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 8C This is a top view of an integrated circuit 100 according to some embodiments. Figure 8A and Figure 8B The cross-sectional views are respectively along Figure 8CThe cutting lines 8A and 8B in the diagram were used to cut the material.

[0066] An etching process has been performed in the presence of a patterned photoresist layer 132. The etching process etches dielectric layers 130 and 128 at locations exposed by trench 134. The etching process also etches the hard mask sublayer 110 at locations exposed by trench 134. The etching process is an anisotropic etching process that selectively etches in the downward direction. In some embodiments, the etching process includes a single etching step that etches through dielectric layers 128 and 130 and the hard mask sublayer 110. In some embodiments, the etching process includes multiple etching steps to etch through the respective layers separately. The etching process selectively etches exposed portions of the layers while substantially omitting the spacer 125.

[0067] The final result of the etching process is the formation of trenches 136 in the hard mask sublayer 110 in the pattern of trenches 134 of the photoresist layer 132. Each trench 136 exposes the top surface of the hard mask sublayer 108. Each trench 136 corresponds to the pattern and location of a single first metal line to be formed in the interlayer dielectric layer 102. As previously discussed... Figures 7A to 7C As described, some tracks 122 correspond to the positions of multiple first metal lines that are separated from each other in the Y direction. Figure 8C This is shown as a trench 136 separated by the unetched portions of the pattern based on photoresist 132 of the hard mask sublayer 110. Figure 8C The location of the end of the groove 136 is also shown.

[0068] Figure 9 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 9 In this process, dielectric layer 140, dielectric layer 142, and photoresist layer 144 have been formed, preparing for the third photolithography process. The third photolithography process will be used to define the length (in the Y direction) and position of the second metal line.

[0069] A dielectric layer 140 is formed on the patterned layer 112, the spacer 125, the exposed sidewalls of the hard mask sublayer 110, and the exposed portion of the top surface of the hard mask sublayer 108. In some embodiments, the dielectric layer 140 comprises amorphous carbon. In some embodiments, the dielectric layer 140 is deposited by CVD, ALD, or PVD. In some embodiments, the dielectric layer 140 has a thickness between 10 nm and 50 nm. Other materials, deposition processes, and thicknesses may be used for the dielectric layer 140 without departing from the scope of this disclosure.

[0070] According to some embodiments, a dielectric layer 142 is formed on the dielectric layer 140. In some embodiments, the dielectric layer 142 comprises SiOC. In some embodiments, the dielectric layer 142 is deposited by CVD, ALD, or PVD. In some embodiments, the dielectric layer 142 has a thickness similar to that of the dielectric layer 116. Other materials, deposition processes, and thicknesses may be used for the dielectric layer 142 without departing from the scope of this disclosure.

[0071] According to some embodiments, a photoresist layer 144 has been formed on the dielectric layer 142. The photoresist layer 144 has a dielectric layer 142. Figure 1 The photoresist layer 118 is a material similar to that of the photoresist layer.

[0072] Figure 10A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 10A In this process, a photolithography process has been performed. The photolithography process includes exposing a photoresist layer 144 to photolithography light, which includes a pattern on a photomask. After exposure, the exposed portion of the photoresist layer 144 is removed, thereby creating a pattern of trenches 146 in the photoresist layer 144. The pattern of the trenches 146 corresponds to the pattern on the photomask.

[0073] Figure 10A The trench 146 is shown as having the same width in the X direction as the width of a portion 112 of the patterned layer 112 beneath the trench 146. However, in some embodiments, the trench 146 is wider than these portions of the patterned layer 112. The trench 146 overlaps with the spacer 125. Since the subsequent etching process does not etch the spacer 125, there is some margin in the layout of the trench 146. This can help to relax the alignment specifications of the trench 146 layout, as the subsequent trench will self-align with the spacer 125, or with the region 123 between the spacers 125.

[0074] Figure 10B The integrated circuit 100 according to some embodiments is in Figure 10A The cross-sectional view of the same process stage shown. Figure 10A The cross-sectional view is taken along the cutting line 10A, as shown below. Figure 10C The top view is shown. Figure 10B The cross-sectional view is taken along the cutting line 10B, as shown below. Figure 10C The top view is shown. Figure 10C Includes a dashed line indicating the location of region 123, which corresponds to the area between spacers 125 below the photoresist layer 144.

[0075] Figure 10B and Figure 10CIt is shown that the trench 146 does not extend through the entire length of each region 123 in the Y direction. Instead, each trench 146 corresponds to a pattern of a single second metal line. For the leftmost region 123, a single trench 146 is formed to correspond to a pattern of a single second metal line. For the middle region 123, a single trench 146 is formed to correspond to the position of a single second metal line. For the rightmost region 123, two trenches 146 are formed to be separated from each other in the Y direction and to correspond to patterns of two second metal lines.

[0076] As will be explained in more detail below, the ends of each trench 146 (in the Y direction) are patterned without the need for separate masks to form cuts or breaks separating adjacent metal lines. Therefore, the ends of adjacent second metal lines can be very close together. Furthermore, the ends of the second metal lines can be moved away from the ends of region 123 as needed. This results in less irrelevant or redundant metal. The second metal lines can be substantially as long (or short) as desired.

[0077] Figure 11A and Figure 11B This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 11C This is a top view of an integrated circuit 100 according to some embodiments. Figure 11A and Figure 11B The cross-sectional views are respectively along Figure 11C It was cut by cutting lines 11A and 11B.

[0078] An etching process has been performed in the presence of a patterned photoresist layer 144. The etching process etches dielectric layers 142 and 140 at locations exposed by trench 146. The etching process also etches patterned layer 112 and hard mask sublayer 110 at locations exposed by trench 146. The etching process is an anisotropic etching process that selectively etches in the downward direction. In some embodiments, the etching process includes a single etching step that etches through dielectric layers 140 and 142, patterned layer 112, and hard mask sublayer 110. In some embodiments, the etching process includes multiple etching steps to etch through each layer separately. The etching process selectively etches exposed portions of each layer while substantially omitting the spacer 125.

[0079] The final result of the etching process is the formation of trenches 137 in the hard mask sublayer 110 in the pattern of trenches 146 of the photoresist layer 144. Each trench 137 exposes the top surface of the hard mask sublayer 108. Each trench 137 corresponds to the pattern and location of a single second metal line to be formed in the interlayer dielectric layer 102. As previously discussed... Figures 10A to 10C As described, some regions 123 correspond to the positions of multiple second metal lines that are separated from each other in the Y direction. Figure 11CThis is shown as a trench 137 separated by the unetched portion of the patterned area 112 and the hard mask sublayer 110 based on the photoresist 144 pattern. Figure 11C The document also demonstrates how to select the position of the end of the groove 137 without using a separate mask for cutting or breaking.

[0080] Figure 12A and Figure 12B This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 12C This is a top view of integrated circuit 100. Figure 12A and Figure 12B The cross-sectional views are respectively along Figure 12C Cut by cutting lines 12A and 12B.

[0081] exist Figures 12A to 12C In some embodiments, an etching process has been performed. The hard mask layer 104 has been etched according to... Figures 11A to 11C The described trenches 136 and 137 are fully patterned. In other words, trenches 136 and 137 have extended completely through hard mask sublayers 108 and 106. The etching process also forms trench 148 in the interlayer dielectric layer 102 by extending trench 136 into the interlayer dielectric layer 102 in the pattern of trench 136. The etching process also forms trench 149 in the interlayer dielectric layer 102 by extending trench 137 into the interlayer dielectric layer 102 in the pattern of trench 137. The same etching process forms trenches 148 and 149. In some embodiments, the etching process includes multiple etching steps to etch through hard mask sublayers 108 and 106 and the interlayer dielectric layer 102. In some embodiments, a single etching step is used to etch through hard mask sublayers 108 and 106 and the interlayer dielectric layer 102.

[0082] Trench 148 corresponds to the pattern of trench 134 extending into the interlayer dielectric layer 102. Trench 148 corresponds to the location of the first metal line. Trench 149 corresponds to the pattern of trench 146 extending into the interlayer dielectric layer 102. Trench 149 corresponds to the location of the second metal line.

[0083] exist Figures 12A to 12C In this process, spacer 125 has been removed. Any remaining portion of patterned layer 112 has also been removed. This is accomplished through one or more etching steps. Therefore, in Figures 12A to 12C In this process, only the fully patterned hard mask layer 104 remains above the interlayer dielectric layer 102.

[0084] Figure 13A and Figure 13B This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 13C This is a top view of integrated circuit 100. Figure 13A and Figure 13B The cross-sectional views are respectively along Figure 13C Cut by cutting lines 13A and 13B.

[0085] exist Figures 13A to 13C In this process, the hard mask layer 104 has been completely removed. In some embodiments, the hard mask layer 104 is removed by performing one or more etching steps that selectively etch the material of the hard mask sublayer relative to the material of the interlayer dielectric layer 102. In some embodiments, the hard mask layer 104 is removed by performing a CMP process.

[0086] exist Figures 13A to 13C In this process, a first metal line 150 and a second metal line 151 have been formed in the interlayer dielectric layer 102. The first metal line 150 and the second metal line 151 are formed by depositing one or more metals in trenches 148 and 149. The one or more metals may comprise one or more liner layers lining the sidewalls and bottom of trenches 148 and 149. The one or more liner layers may comprise TiN, TaN, or other suitable materials. In some embodiments, the one or more metals comprise metals deposited on the liner layers and filling trenches 148 and 149. The metals may comprise W, Ti, Ta, Al, Cu, Au, or other suitable conductive materials. The metal layers may be deposited by PVD, ALD, or CVD. After depositing one or more metals, a CMP process is performed to remove excess metal material from the top surface of the interlayer dielectric layer 102. Thus, the first metal line 150 and the second metal line 151 are formed.

[0087] The first metal wire 150 corresponds to a group of first metal wires or a group of first metal wires. The second metal wire 151 corresponds to a group of second metal wires or a group of second metal wires. The metal wires 151 and 150 are intersected in the transverse direction.

[0088] Figures 13A to 13C The diagram shows that metal line 150 is wider than metal line 151 in the X direction. However, in some embodiments, metal lines 150 and 151 have the same width in the X direction. In some embodiments, metal lines 150 and 151 each have a width between 10 nm and 50 nm, but other dimensions may be used without departing from the scope of this disclosure. In some embodiments, metal lines 150 and 151 are spaced evenly apart from each other in the X direction. In some embodiments, the spacing between adjacent metal lines 150 and 151 in the X direction is between 5 nm and 50 nm, but other dimensions may be used without departing from the scope of this disclosure.

[0089] According to some embodiments, Figure 13C The top view helps to illustrate some of the benefits of the process used to form integrated circuit 100. From Figure 13CAs can be seen, the metal lines have different lengths in the Y direction. Since the lengths of the metal lines 150 / 151 in the Y direction can be chosen to be any length, the portion of the interlayer dielectric layer 120 beneath each track 122 or region 123 is not occupied by unrelated metal material. This is partly due to the use of the spacer 125, which allows for the avoidance of photolithography processes specifically designed to form breaks or cuts in the metal lines. Furthermore, due to the aforementioned process, the metal line 151 does not inappropriately widen in the X direction where there are no adjacent metal lines 150. This helps reduce parasitic capacitance and prevent short circuits.

[0090] Figure 14 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 14 The integrated circuit 100 includes an active circuit region 101, a first interlayer dielectric layer 102a above the active circuit region 101, and a second interlayer dielectric layer 102b above the first interlayer dielectric layer 102a.

[0091] According to some embodiments, a plurality of transistors 103 are formed in the active circuit region 101. The transistors 103 include PMOS transistors and NMOS transistors. In some embodiments, the transistors 103 are core logic circuits. In some embodiments, the transistors 103 form part of an SRAM array of integrated circuit 100.

[0092] In some embodiments, the active circuit region 101 includes a semiconductor substrate. Together with the semiconductor substrate, a channel region and a source / drain region of the transistor 103 are formed. A gate dielectric layer and a gate metal of the transistor are formed adjacent to the channel region. Gate contacts corresponding to conductive vias or conductive plugs extend downward to contact the gate region. Source / drain contacts corresponding to conductive vias or conductive plugs extend downward to contact the source / drain regions. Dielectric layers including gate spacers are formed on the transistor structure.

[0093] Interlayer dielectric layer 102a includes, according to, the following: Figures 1 to 13C The described process forms a first metal line 150a and a second metal line 151a. Prior to forming the metal lines 150a and 151a, a conductive via 154a is formed in the interlayer dielectric layer 102a. The metal lines 150a / 151a contact the conductive via 154a at selected contact areas according to the circuit layout. The conductive via 154a provides an electrical connection between the transistor 103 and the metal lines 150a / 151a.

[0094] Interlayer dielectric layer 102b includes, according to, the following: Figures 1 to 13CThe described process forms a first metal line 150b and a second metal line 151b. Prior to forming metal lines 150b and 151b, a conductive via 154b is formed in the interlayer dielectric layer 102b. The conductive via 154b contacts the metal lines 150a / 151a at selected contact locations according to the circuit layout. The metal lines 150b / 151b contact the conductive via 154b at selected contact areas according to the circuit layout. The conductive via 154b provides an electrical connection between the metal lines 150b / 151b and 150a / 151a. An additional interlayer dielectric layer and corresponding metal lines may be formed above the interlayer dielectric layer 102b.

[0095] Figure 15A This is a top view of a layout 160 of metal lines in an integrated circuit according to some embodiments. Layout 160 corresponds to a stored metal line design. Layout 160 shows the planned locations of metal lines 150 and 151 and contacts 162, which correspond to the locations where the metal lines will contact conductive vias.

[0096] Figure 15B This is a top view of integrated circuit 100, in which layout 160 has been achieved through the solid formation of metal lines 150 and 151 and contact 162. About Figures 1 to 13C The described process is used to form metal wires 150 and 151. Figure 15B The location of spacer 125 is also shown, but in reality, spacer 125 no longer exists after the metal lines 150 and 151 are formed. The use of spacer 125 makes it possible to utilize a larger contact window.

[0097] from Figure 15B As can be seen, layout 160 is accurately implemented in integrated circuit 100. Multiple end-to-end spacings exist. The metal lines have a uniform width and do not widen in the Y direction.

[0098] Figure 16 This is a top view of an integrated circuit 100 according to some embodiments. Figure 16 Two first metal lines 150 and two second metal lines 151 are shown. Figure 16 The first metal wire 150 and the second metal wire 151 are shown to have variable end-to-end distances, as indicated by the arrows. The end-to-end distance may correspond to the distance between adjacent metal wires 150 / 151 in the Y direction, or the distance between the end of metal wire 150 / 151 and the edge of the unit or track. Without the use of the restraining spacer 125, the metal wire 150 may have a finite end-to-end dimension.

[0099] Figure 17 This is a top view of an integrated circuit 100 according to some embodiments. Figure 17Two sets of three first metal wires 150 and one set of three second metal wires 151 are shown. Figure 17 It is shown that, using the above-described process, both the first metal line 150 and the second metal line 151 can have very small end-to-end spacing.

[0100] Figure 18 This is a top view of an integrated circuit 100 according to some embodiments. Figure 18 Three first metal wires 150 and three second metal wires 151 are shown. From Figure 18 As can be seen, the metal line 150 is not widened in the X direction, and there is no adjacent metal line 150. This is because the use of the restraining spacer 125 effectively prevents such widening. In some embodiments, Figure 18 The metal lines shown correspond to a portion of an SRAM cell, wherein one metal line 150 is a high power supply line supplying VDD and one metal line 151 is a low power supply line supplying GND.

[0101] Figure 19 This is a flowchart of a method 1900 for forming an integrated circuit according to some embodiments. Method 1900 can utilize... Figures 1 to 18 The process, components, and structure are described. At 1902, method 1900 includes forming a patterned layer on top of an interlayer dielectric layer of an integrated circuit. An example of an interlayer dielectric layer is... Figure 1 Interlayer dielectric layer 102. An example of a patterned layer is... Figure 1 The patterned layer 112. In 1904, method 1900 includes forming a plurality of first trenches in the patterned layer using a first photolithography process. An example of the first trenches is... Figure 3A The first trench 122. At 1906, method 1900 includes conformally depositing a dielectric layer on the patterned layer and in the trench. An example of the dielectric layer is... Figure 4 The dielectric layer 124. In 1908, method 1900 includes forming a plurality of spacers from the dielectric layer by removing the dielectric layer from the top surface of the patterned layer, each spacer being lined with the sidewall of a corresponding first trench. An example of a spacer is... Figure 5A The spacer 125. At 1910, method 1900 includes forming a plurality of first metal lines in the interlayer dielectric, each first metal line being laterally self-aligned with a spacer. An example of the first metal lines is... Figure 13A Metal wire 150. At 1912, method 1900 includes forming a plurality of second metal wires in an interlayer dielectric layer, the plurality of second metal wires being laterally staggered with the first metal wires, and the gaps between each second metal wire and adjacent spacers being laterally self-aligned. An example of the second metal wires is... Figure 13A Metal wire 151.

[0102] Figure 20 This is a flowchart of a method 2000 for forming an integrated circuit according to some embodiments. Method 2000 can utilize... Figures 1 to 18 The process, components, and structure are described. At 2002, method 2000 includes forming a plurality of first trenches in a patterned layer above an interlayer dielectric layer using a first photolithography process. An example of an interlayer dielectric layer is... Figure 1 Interlayer dielectric layer 102. An example of a patterned layer is... Figure 1 Patterned layer 112. An example of the first trench is... Figure 3A The first groove 122. At 2004, method 2000 includes forming a plurality of spacers, each spacer lined with the sidewall of a corresponding first groove and spaced apart from each other. An example of a spacer is... Figure 5A The spacer 125. In step 2006, method 2000 includes forming a plurality of second trenches in a hard mask layer beneath the patterned layer using a second photolithography process. An example of the hard mask layer is... Figure 1 The hard mask layer 110. An example of the second trench is... Figure 8A Trench 136. In 2008, method 2000 includes forming a plurality of third trenches in a hard mask layer that alternate laterally with the second trenches, the second and third trenches being laterally self-aligned with spacers. An example of the third trench is... Figure 11A Groove 137.

[0103] Embodiments of this disclosure provide a method for forming metal lines in an interlayer dielectric layer of an integrated circuit. The process forms a set of metal lines as a first set of metal lines and a second set of metal lines laterally intersecting the first set of metal lines. The process forms a patterned layer on the interlayer dielectric layer. A first photolithography and etching process forms tracks in the patterned layer. A plurality of dielectric spacers are formed on the sidewalls of the tracks, wherein the top surface of a hard mask layer is exposed at the bottom of the tracks. A second photolithography and etching process forms the pattern of the first set of metal lines in the hard mask layer based on the dielectric spacers. A third photolithography and etching process forms the pattern of the second set of metal lines in the hard mask layer based on the dielectric spacers. The patterns of the first and second sets of metal lines are then transferred to the interlayer dielectric layer by an etching process, serving as trenches in the interlayer dielectric layer. The first and second sets of metal lines are then simultaneously formed by depositing metal material in the trenches.

[0104] The embodiments of this disclosure offer several benefits. First, separate photolithography and etching processes are eliminated to form breaks in the metal lines. Second, in the patterned layer, the trenches or windows for the first and second sets of metal lines are limited by dielectric spacers. This allows the two sets of metal lines to have multiple end-to-end dimensions or small dimensions (e.g., very small end-to-end distances). Excess line length and redundant metal are also significantly reduced. These lines do not have the characteristic of laterally expanding at unrestricted locations. This further results in better integrated circuit performance and fewer scrapped wafers.

[0105] In some embodiments, the method includes: forming a patterned layer over an interlayer dielectric layer of an integrated circuit, and forming a plurality of first trenches in the patterned layer using a first photolithography process. The method includes: conformally depositing a dielectric layer on the patterned layer and in the trenches, and forming a plurality of spacers from the dielectric layer by removing the dielectric layer from a top surface of the patterned layer, each spacer lining the sidewalls of a corresponding first trench. The method includes forming a plurality of first metal lines in the interlayer dielectric, each first metal line being laterally self-aligned with a spacer, and forming a plurality of second metal lines in the interlayer dielectric layer, the plurality of second metal lines being laterally staggered with the first metal lines and the gaps between each second metal line and adjacent spacers being laterally self-aligned.

[0106] In some embodiments, a method includes forming a plurality of first trenches in a patterned layer above an interlayer dielectric layer using a first photolithography process, and forming a plurality of spacers, each spacer lining the sidewalls of a corresponding first trench and spaced apart from each other. The method also includes forming a plurality of second trenches in a hard mask layer below the patterned layer using a second photolithography process, and forming a plurality of third trenches in the hard mask layer that alternate laterally with the second trenches, the second and third trenches being laterally self-aligned with the spacers.

[0107] In some embodiments, the integrated circuit includes a plurality of transistors, an interlayer dielectric layer above the transistors, and a plurality of first metal lines extending in a first lateral direction in the interlayer dielectric layer. The integrated circuit also includes a plurality of second metal lines in the interlayer dielectric layer, the second metal lines extending in the first lateral direction and alternating with the first metal lines in a second lateral direction perpendicular to the first lateral direction. The first metal lines have a plurality of different end-to-end dimensions. The second metal lines have a plurality of different end-to-end dimensions.

[0108] Here are some specific examples.

[0109] Example 1. A method comprising:

[0110] A patterned layer is formed on top of the interlayer dielectric layer of the integrated circuit;

[0111] Multiple first trenches are formed in the patterned layer using a first photolithography process;

[0112] A dielectric layer is conventionally deposited on the patterned layer and in the trench;

[0113] A plurality of spacers are formed from the dielectric layer by removing the dielectric layer from the top surface of the patterned layer, each spacer being lined with the sidewall of a corresponding first trench;

[0114] Multiple first metal lines are formed in the interlayer dielectric layer, and each first metal line is laterally self-aligned with one of the spacers; and

[0115] Multiple second metal lines are formed in the interlayer dielectric layer, the multiple second metal lines intersect with the first metal lines in the lateral direction, and the gap between each second metal line and the adjacent spacer is self-aligned in the lateral direction.

[0116] Example 2. The method described in Example 1 includes:

[0117] In a hard mask layer between the patterned layer and the interlayer dielectric layer, a plurality of second trenches are formed in the hard mask layer below the first trench using a second photolithography process; and

[0118] Using a third photolithography process, a plurality of third trenches are formed in the hard mask layer based on the spacer, which are intersected laterally with the first trench.

[0119] Example 3. According to the method of Example 2, wherein each of the second trenches is below a first region surrounded by one of the spacers.

[0120] Example 4. The method according to Example 3, wherein each of the third grooves is below a second region between corresponding adjacent spacers.

[0121] Example 5. The method according to Example 2, wherein the second trench and the third trench extend partially into the hard mask layer.

[0122] Example 6. The method described in Example 2 includes:

[0123] Remove the spacer;

[0124] A fourth trench is formed in the interlayer dielectric layer using an etching process, in the pattern of the second trench; and

[0125] The fifth trench is formed in the interlayer dielectric layer using the etching process described above, in the pattern of the third trench.

[0126] Example 7. The method according to Example 6 includes forming the first metal line in the fourth trench and forming the second metal line in the fifth trench by depositing metal using a deposition process.

[0127] Example 8. The method according to Example 7, including performing a chemical mechanical planarization process after the deposition process.

[0128] Example 9. The method according to Example 1, wherein the patterned layer is amorphous silicon.

[0129] Example 10. The method according to Example 1, wherein the hard mask layer includes a first hard mask sublayer on the interlayer dielectric layer, a second hard mask sublayer on the first hard mask sublayer, and a third hard mask sublayer on the second hard mask sublayer.

[0130] Example 11. The method according to Example 10, wherein the first hard mask sublayer and the third hard mask sublayer are tetraethyl orthosilicate.

[0131] Example 12. A method comprising:

[0132] Multiple first trenches are formed in a patterned layer above the interlayer dielectric layer using a first photolithography and etching process;

[0133] Multiple spacers are formed, each spacer being lined with the sidewall of a corresponding first groove and spaced apart from each other;

[0134] A plurality of second trenches are formed in a hard mask layer beneath the patterned layer using a second photolithography process; and

[0135] A plurality of third trenches are formed in the hard mask layer, alternating laterally with the second trench, and the second trench and the third trenches are self-aligned laterally with the spacer.

[0136] Example 13. The method described in Example 12 includes:

[0137] A fourth trench is formed in the interlayer dielectric layer using a first etching process, in the pattern of the second trench;

[0138] Using the first etching process, a fifth trench is formed in the interlayer dielectric layer in the pattern of the third trench; and

[0139] A first metal wire is formed in the fourth trench; and

[0140] The metal is deposited using the aforementioned deposition process to form a second metal line in the fifth trench.

[0141] Example 14. The method according to Example 13, wherein the hard mask layer includes a first hard mask sublayer and a second hard mask sublayer on the first hard mask sublayer.

[0142] Example 15. According to the method described in Example 14, wherein:

[0143] Forming the second trench includes: etching the second hard mask sublayer using a second etching process prior to the first etching process, without etching the first hard mask layer; and

[0144] Forming the third trench includes etching the second hard mask sublayer using a third etching process between the second etching process and the first etching process, without etching the first hard mask sublayer.

[0145] Example 16. The method according to Example 15, wherein forming the fourth trench and the fifth trench includes: using a fourth etching process to extend the second trench and the third trench through the first hard mask sublayer.

[0146] Example 17. The method according to Example 16, wherein the first hard mask sublayer comprises tungsten-doped carbon, and wherein the second hard mask sublayer comprises tetraethyl orthosilicate.

[0147] Example 18. An integrated circuit, comprising:

[0148] Multiple transistors;

[0149] An interlayer dielectric layer above the transistor;

[0150] Multiple first metal lines extend in the interlayer dielectric layer in a first lateral direction; and

[0151] Multiple second metal lines extend in the interlayer dielectric layer in the first lateral direction and alternate with the first metal line in a second lateral direction perpendicular to the first lateral direction, wherein the first metal line has multiple different end-to-end dimensions, and wherein the second metal lines have multiple different end-to-end dimensions.

[0152] Example 19. An integrated circuit according to Example 18, wherein the first metal line and the second metal line are portions of an SRAM cell.

[0153] Example 20. The integrated circuit according to Example 19, wherein the first metal line and the second metal line are separated by a uniform spacing distance in the second lateral direction.

[0154] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made by those skilled in the art without departing from the spirit and scope of this disclosure.

Claims

1. A method comprising: A patterned layer is formed on top of the interlayer dielectric layer of the integrated circuit; A plurality of first trenches are formed in the patterned layer using a first photolithography process; A dielectric layer is conventionally deposited on the patterned layer and in the trench; A plurality of spacers are formed from the dielectric layer by removing the dielectric layer from the top surface of the patterned layer, each spacer being lined with the sidewall of a corresponding first trench; Multiple first metal lines are formed in the interlayer dielectric layer, and each first metal line is self-aligned in the lateral direction with one of the spacers. as well as Multiple second metal lines are formed in the interlayer dielectric layer, the multiple second metal lines intersect with the first metal lines in the lateral direction, and the gap between each second metal line and the adjacent spacer is self-aligned in the lateral direction.

2. The method according to claim 1, comprising: In the hard mask layer between the patterned layer and the interlayer dielectric layer, a plurality of second trenches are formed in the hard mask layer below the first trench using a second photolithography process; as well as Using a third photolithography process, a plurality of third trenches are formed in the hard mask layer based on the spacer, which are intersected laterally with the first trench.

3. The method according to claim 2, wherein, The second groove is located below the first region, which is surrounded by one of the spacers.

4. The method according to claim 3, wherein, The third grooves are each located below the second region between the corresponding adjacent spacers.

5. The method according to claim 2, wherein, The second trench and the third trench extend partially into the hard mask layer.

6. The method according to claim 2, comprising: Remove the spacer; A fourth trench is formed in the interlayer dielectric layer using an etching process, in the pattern of the second trench. as well as The fifth trench is formed in the interlayer dielectric layer using the etching process described above, in the pattern of the third trench.

7. The method of claim 6, further comprising forming the first metal wire in the fourth trench and forming the second metal wire in the fifth trench by depositing metal using a deposition process.

8. The method of claim 7, further comprising performing a chemical mechanical planarization process after the deposition process.

9. A method comprising: Multiple first trenches are formed in a patterned layer above the interlayer dielectric layer using a first photolithography and etching process; Multiple spacers are formed, each spacer being lined with the sidewall of a corresponding first groove and spaced apart from each other; Multiple second trenches are formed in the hard mask layer beneath the patterned layer using a second photolithography process; as well as A plurality of third trenches are formed in the hard mask layer, alternating laterally with the second trench, and the second trench and the third trenches are self-aligned laterally with the spacer.

10. An integrated circuit, comprising: Multiple transistors; The interlayer dielectric layer above the transistor; Multiple first metal lines extend in the interlayer dielectric layer in a first lateral direction; as well as Multiple second metal lines extend in the interlayer dielectric layer in the first lateral direction and alternate with the first metal line in a second lateral direction perpendicular to the first lateral direction, wherein the first metal line has multiple different end-to-end dimensions, and wherein the second metal lines have multiple different end-to-end dimensions.

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