Semiconductor package with vertically stacked transistors and its manufacturing method

Abstract

A semiconductor package includes a lead frame, a vertically stacked group of field-effect transistors (FETs), a source clip, a gate clip, and a molded package. The vertically stacked FET group includes a first FET and a second FET. The first FET is flip-floped. A method includes the steps of: providing a lead frame; mounting the vertically stacked FET group; mounting clips to form a molded package; and performing a dicing process.

Description

Technical Field

[0001] This invention generally relates to a semiconductor package and a method for manufacturing the same. More specifically, this invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) having vertically stacked transistors. Background Technology

[0002] Power control modules (PCMs) use multiple MOSFETs. MOSFETs have electrodes at both the top and bottom. One requirement is to maintain low resistance. Traditional PCMs contain a pair of MOSFETs side-by-side. To reduce resistance, thick metal (greater than 30 micrometers thick) is connected to this pair of side-by-side MOSFETs, increasing the size and cost of the PCM.

[0003] The semiconductor package disclosed in this invention comprises a pair of vertically stacked FETs, thereby contributing to a reduction in resistance (by 20%). Its horizontal dimensions are reduced by 35% (from 2 mm × 3.6 mm to 1.3 mm × 3.6 mm). Productivity, i.e., the number of products per hour (NPH), is also improved. Summary of the Invention

[0004] This invention discloses a semiconductor package including a lead frame, a vertically stacked FET group, a source clip, a gate clip, and a molded package. The vertically stacked FET group includes a first FET and a second FET. The first FET is flip-floped.

[0005] The present invention also discloses a method for manufacturing a semiconductor package. The method includes the steps of providing a lead frame, connecting vertically stacked FET groups, connecting clips, forming a molded package, and applying a dicing process. Attached Figure Description

[0006] Figure 1A This is a top perspective view of a semiconductor package in an embodiment of the present invention. Figure 1B This is a bottom perspective view. Figure 1C It is a decomposed diagram.

[0007] Figure 2 This is a side view of a vertically stacked FET group in an embodiment of the present invention.

[0008] Figure 3 This is a flowchart illustrating the process of manufacturing semiconductor packages in an embodiment of the present invention.

[0009] Figure 4A , 4B 4C, 4D, and 4E represent the process steps for manufacturing a semiconductor package in embodiments of the present invention.

[0010] Figure 5AThis is a top view of the lead frame strip in an embodiment of the present invention. Figure 5B This is a top view of the clip strip.

[0011] Figure 6 This diagram illustrates the process flow for manufacturing a vertically stacked FET group in an embodiment of the present invention.

[0012] Figure 7A , 7B 7C and 7D represent the process steps for manufacturing a vertically stacked FET group in an embodiment of the present invention. Detailed Implementation

[0013] Figure 1A This is a top perspective view of the semiconductor package 100 in an embodiment of the present invention. Figure 1B This is a bottom perspective view. Figure 1C It is a decomposed diagram. Figure 2 This is a side view of the vertically stacked FET group 250 in an embodiment of the present invention. In one embodiment, the semiconductor package 100 is a dual MOSFET. The semiconductor package 100 includes a lead frame 120, the vertically stacked FET group 250, a source clip 160, a gate clip 170, and a molded package 190. The lead frame 120 includes a chip pad 122, a side pad 124, a first gate pad 126, and a second gate pad 128.

[0014] The vertically stacked FET group 250 includes a first FET 260 and a second FET 280 connected back-to-back. The first FET 260 includes a source 262 and a gate 264 located on its front surface 261. The second FET 280 includes a source 282 and a gate 284 located on its front surface 281, which is opposite to the front surface 261 of the first FET 260. The drains 269 of the first FET 260 and the drains 289 of the second FET 280 are internally connected. The first FET 260 is flipped, with its source 262 connected to a chip pad 122 and its gate 264 connected to a first gate pad 126.

[0015] Source clip 160 electrically and mechanically connects the source 282 of the second FET 280 to the side pad 124 of the lead frame 120. Gate clip 170 electrically and mechanically connects the gate 284 of the second FET 280 to the second gate pad 128 of the lead frame 120.

[0016] The molded package 190 encapsulates the first FET 260, the second FET 280, the source clip 160, the gate clip 170, most of the first gate pad 126, most of the second gate pad 128, and most of the lead frame 120 (most of the chip pad 122, most of the side pad 124, most of the first gate pad 126, and most of the second gate pad 128). "Most" refers to more than 50%.

[0017] The bottom surface 123 of the chip pad 122, the bottom surface 125 of the side pad 124, the bottom surface 127 of the first gate pad 126, and the bottom surface 129 of the second gate pad 128 are exposed from the bottom surface 191 of the molded package 190.

[0018] In an embodiment of the invention, the source clip 160 is made of metal. In one embodiment, the source clip 160 is made of copper. In an embodiment of the invention, the gate clip 170 is made of metal. In one embodiment, the gate clip 170 is made of copper.

[0019] The source clip 160 includes a raised portion 162 and an inclined portion 164. The gate clip 170 includes a raised portion 172 and an inclined portion 174. In an embodiment of the present invention, the top surface of the raised portion 162 of the source clip 160 and the top surface of the raised portion 172 of the gate clip 170 are coplanar.

[0020] In an embodiment of the invention, the first FET 260 and the second FET 280 are formed on different substrates, and the vertically stacked FET group 250 includes the first FET 260 and the second FET 280 bonded back-to-back. An optional conductive bonding layer 270 bonds the drain 269 on the back side of the first FET 260 to the drain 289 on the back side of the second FET 280, forming a vertically stacked FET group 250 as a common-drain MOSFET. In one embodiment of the invention, the bonding layer 270 includes gold and serves as a common-drain region connecting the drain 269 of the first FET 260 and the drain 289 of the second FET 280.

[0021] In embodiments of the present invention, the first FET 260 and the second FET 280 are formed from the same semiconductor substrate (see U.S. Patent No. 10,446,545 to Lui et al. and U.S. Patent Application No. 2018 / 0006026 to Lui et al.). In embodiments of the present invention, the first FET 260 and the second FET 280 are monolithic structures.

[0022] Figure 3 This is a flowchart illustrating a semiconductor packaging process 300 in an embodiment of the present invention. Process 300 may begin at block 302. For simplicity, Figure 4A , 4B4C and 4D only show the process of manufacturing a single package. For the sake of simplicity, Figure 4E Only the process of manufacturing two semiconductor packages is shown. Figure 4A , 4B 4C, 4D, and 4E are along Figure 1C A cross-sectional view of line AA'.

[0023] In block 302, refer to Figure 4A A lead frame 420 is provided. The lead frame 420 includes chip pads 422 and side pads 424. Figure 1B First gate pad 126 and Figure 1A The second gate pad 128. In an embodiment of the invention, solder paste 421 is applied to the chip pad 422 of the lead frame 420. Block 302 may be followed by block 304.

[0024] In block 304, refer to Figure 4B A vertically stacked FET group 850 is mounted. In an embodiment of the invention, the vertically stacked FET group 850 is connected to solder paste 421. The vertically stacked FET group 850 includes a first FET 860 and a second FET 880. The first FET 860 is flipped and connected to the chip pad 422 via solder paste 421. The first FET 860 includes components located on its front surface 861. Figure 2 The source pole 262 and Figure 2 The gate 264. The second FET 880 is connected back-to-back to the first FET 860. The second FET 880 includes a gate 264 located on its front surface 881. Figure 2 The source pole 282 and Figure 2 Gate 284.

[0025] In an embodiment of the invention, the first FET 860 and the second FET 880 are formed on different substrates, and the vertically stacked FET group 850 includes the first FET 860 and the second FET 880 bonded back-to-back. An optional conductive bonding layer 870 bonds the drain on the back side of the first FET 860 to the drain on the back side of the second FET 880, forming a vertically stacked FET group 850 as a common-drain MOSFET. The optional conductive bonding layer 870 serves as a common-drain region connection. Figure 2 The drain of the first FET860 is 269 and Figure 2 The drain of the second FET 880 is 289.

[0026] In embodiments of the invention, the first FET 860 and the second FET 880 are formed from the same semiconductor substrate (see U.S. Patent No. 10,446,545 to Lui et al. and U.S. Patent Application No. 2018 / 0006026 to Lui et al.). In embodiments of the invention, the first FET 860 and the second FET 880 are monolithic structures. Block 304 may be followed by block 306.

[0027] In block 306, refer to Figure 4C Connecting clips. Source clip 460 will... Figure 2 The source 282 of the second FET 880 is electrically and mechanically connected to the side pad 424 of the lead frame 420. Figure 1A The gate clip 170 will Figure 2 The gate 284 of the second FET 880 is electrically and mechanically connected to ground. Figure 1A The second gate pad 128 of the lead frame 420. Figure 2 The gate 264 of the first FET 860 is connected to Figure 1B The first gate pad 126 of the lead frame 420.

[0028] In an embodiment of the invention, the source clip 460 is made of metal. In one embodiment, the source clip 460 is made of copper. In an embodiment of the invention, Figure 1A The gate clip 170 is made of metal. In one embodiment, Figure 1A The gate clip 170 is made of copper.

[0029] The source clip 460 includes a raised portion 462 and an inclined portion 464. Figure 1C The gate clip 170 includes Figure 1C The raised part 172 and Figure 1C The inclined portion 174. In an embodiment of the present invention, the top surface 461 of the raised portion 162 of the source clip 160 and Figure 1C The top surface of the raised portion 172 of the gate clamp 170 is coplanar. Block 306 can be followed by block 308.

[0030] In block 308, refer to Figure 4D This forms a molded package 490. The molded package 490 encapsulates the first FET 860, the second FET 880, and the source clip 460. Figure 1A The gate clip 170 and most of the lead frame 420 (most of the chip pad 422, most of the side pad 424, Figure 1B Most of the first gate pad 126 and Figure 1A (The majority of the second gate pad 128). "Most" means greater than 50%.

[0031] The bottom surface 423 of chip pad 422, and the bottom surface 425 of side pad 424. Figure 1B The bottom surface 127 of the first gate pad 126 and Figure 1A The bottom surface 129 of the second gate pad 128 is exposed from the bottom surface 491 of the molded package 490. Block 308 may be followed by block 310.

[0032] In block 310, refer to Figure 4E The dicing process is performed along dicing line 495. Semiconductor package 493 is separated from the adjacent semiconductor package 497. Although Figure 4E Only two semiconductor packages are shown, but the number of semiconductor packages separated in the same dicing process can vary. In an embodiment of the invention, semiconductor package 493 is a dual MOSFET.

[0033] In an embodiment of the present invention, block 302 includes providing Figure 5A A sub-block of the lead frame strip 510. The lead frame strip 510 includes a plurality of locking holes 517. In an embodiment of the invention, each locking hole 517 of the lead frame strip 510 is a first rectangular shape. Block 306 includes providing Figure 5B The clip strip 520 comprises a sub-block. The clip strip 520 includes a plurality of latches 527. In an embodiment of the invention, each latch 527 of the clip strip 520 is a second rectangular shape. The plurality of latches 527 of the clip strip 520 engage with a plurality of locking holes 517 of the lead frame strip 510. In an embodiment of the invention, the plurality of latches 527 of the clip strip 520 and the plurality of locking holes 517 of the lead frame strip 510 are used for locking and alignment.

[0034] In an embodiment of the present invention, block 304 includes Figure 6 The sub-block shown. For the sake of simplicity, Figure 7A , 7B Blocks 304 and 7C only show the process of manufacturing two vertically stacked FET groups. Block 304 can start from sub-block 602.

[0035] In sub-block 602, refer to Figure 7A A first wafer 710 is provided, which includes a plurality of first FETs, including a first FET 712. A second wafer 720 is also provided, which includes a plurality of second FETs, including a second FET 722. In embodiments of the invention, the first wafer 710 is flipped. Sub-block 602 may be followed by sub-block 604.

[0036] In sub-block 604, refer to Figure 7B Through eutectic bonding, transient liquid phase bonding, or metal hot pressing bonding processes, Figure 7A The bottom surface 719 of the first wafer 710 is bonded to Figure 7AThe bottom surface 729 of the second wafer 720. Although not shown here, optional conductive bonding layers such as layer 270 or layer 870 can be used to facilitate the wafer bonding process. Sub-block 604 can be followed by sub-block 606.

[0037] In sub-block 606, refer to Figure 7C The dicing process is performed along dicing line 795. The vertically stacked FET group 793 is separated from the adjacent vertically stacked FET group 797. Although Figure 7C Only two vertically stacked FET groups are shown, but the number of vertically stacked FET groups separated in the same dicing process can vary. Sub-block 606 can be followed by an optional sub-block 608 to form an embedded package 730.

[0038] In the optional sub-block 608 (shown by dashed lines), refer to Figure 7D This forms a molded package 790. The molded package 790 completely covers all surfaces of the vertically stacked FET group 793. Connection vias are formed from the bottom surface of the molded package 790 to reach the first FET, and connection vias are formed from the front surface of the molded package 790 to reach the second FET. Metallization processes such as electroplating are applied to form metal connections. Figure 7D As shown, the embedded package 730 includes a first gate metal portion 792g and a first source metal portion 792s disposed on the bottom surface of the molded package 790. The first gate metal portion 792g is connected to the gate of a first FET through a first gate connection via. The first source metal portion 792s is connected to the source of the first FET through a plurality of first source connection vias. A second gate metal portion 794g and a second source metal portion 794s are disposed on the front surface of the molded package 790. The second gate metal portion 794g is connected to the gate of a second FET through a second gate connection via. The second source metal portion 794s is connected to the source of the second FET through a plurality of second source connection vias. Each of the first gate metal portion 792g, the first source metal portion 792s, the second gate metal portion 794g, and the second source metal portion 794s preferably comprises a solderable metal, such as copper, gold, or silver.

[0039] In an embodiment of the invention, the embedded package 730 includes a vertically stacked FET group 793, which includes a first FET 712 and a second FET 722 formed on different substrates, and the first FET 712 and the second FET 722 are bonded together back-to-back. An optional conductive bonding layer, such as layer 270 or layer 870, bonds the drain on the back side of the first FET 712 to the drain on the back side of the second FET 722, forming a vertically stacked FET group 793 as a common-drain MOSFET. In one embodiment of the invention, the bonding layer includes gold and serves as a common-drain region connecting the drains of the first FET 712 and the second FET 722.

[0040] In an embodiment of the invention, the embedded package 730 includes a vertically stacked FET group 793, which includes a first FET 712 and a second FET 722 formed on the same semiconductor substrate (see U.S. Patent No. 10,446,545 to Lui et al. and U.S. Patent Application No. 2018 / 0006026 to Lui et al.). In an embodiment of the invention, the first FET 712 and the second FET 722 are monolithic structures.

[0041] Those skilled in the art will recognize that modifications can be made to the embodiments disclosed herein. For example, the heights of the inclined portion 164 and the inclined portion 464 can be varied. Other modifications may occur to those skilled in the art, and all such modifications are considered to fall within the scope of the invention as defined by the claims.

Claims

1. A semiconductor package, comprising: A lead frame, comprising: A chip pad, One side pad; A vertically stacked FET includes: A first field-effect transistor (FET) and a second FET are connected back to back. The first FET includes a source and a gate located on its front surface. The first FET is flip-mounted onto the chip pad. The second FET includes a source and a gate located on its front surface, which is opposite to the front surface of the first FET; A source clip connects the source of the second FET to the side pad of the leadframe; and A molded package that encloses most of the first FET, second FET, source clip, and lead frame.

2. The semiconductor package of claim 1 further comprises: A gate clip; The lead frame also includes: A first gate pad; and A second gate pad; The gate of the first FET is connected to the first gate pad of the lead frame; The gate clip connects the gate of the second FET to the second gate pad of the lead frame; and The molded package also encapsulates the gate clip, most of the first gate pad, and most of the second gate pad.

3. The semiconductor package of claim 2, wherein the bottom surface of the chip pad, the bottom surface of the side pad, the bottom surface of the first gate pad, and the bottom surface of the second gate pad are exposed from the bottom surface of the molded package.

4. The semiconductor package of claim 1 further includes a bonding layer as a common drain region connecting the drain of the first FET and the drain of the second FET.

5. The semiconductor package of claim 1, wherein the first FET and the second FET are formed from the same semiconductor substrate.

6. The semiconductor package of claim 1, wherein the semiconductor package is a bimetallic oxide semiconductor field-effect transistor (MOSFET).

7. A semiconductor package, comprising: A vertically stacked FET includes: A first field-effect transistor (FET) and a second FET are connected back-to-back. The first FET includes a source and a gate located on its front surface. The second FET includes a source and a gate located on its front surface, which is opposite to the front surface of the first FET; A molded package encapsulates a first FET and a second FET. The molded package includes: The bottom surface covering the front surface of the first FET; and The front side of the second FET front surface is covered; A first gate metal portion disposed on the bottom surface of the molded package is connected to the gate of the first FET through a first gate connection via; The first source metal portion disposed on the bottom surface of the molded package is connected to the source of the first FET through multiple first source connection vias; A second gate metal portion disposed on the front side of the molded package is connected to the gate of the second FET through a second gate connection via; and The second source metal portion disposed on the front side of the molded package is connected to the source of the second FET through multiple second source connection vias.

8. The semiconductor package of claim 7, wherein the first gate metal portion, the first source metal portion, the second gate metal portion, and the second source metal portion all comprise solderable metal.

9. The semiconductor package of claim 7 further includes a bonding layer as a common drain region connecting the drain of the first FET and the drain of the second FET.

10. The semiconductor package of claim 7, wherein the first FET and the second FET are formed from the same semiconductor substrate.

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