Bare chip leveling structure and preparation method thereof, pre-packaging module and preparation method thereof, and chip packaging structure and preparation method thereof

Abstract

The invention discloses a bare chip leveling structure and a preparation method thereof, a pre-packaging module and a preparation method thereof, and a chip packaging structure and a preparation method thereof, the bare chip leveling structure comprises a bare chip and a leveling silicon wafer, and the leveling silicon wafer is attached to the back surface of the bare chip to form an integral structure with a set thickness. According to the bare chip leveling structure, the leveling silicon wafer is mounted on the bare chip, and the overall thickness size of the bare chip leveling structure can be ensured by adjusting the thickness size of the leveling silicon wafer, so that the bare chips which need to be packaged together and have different thickness sizes can be prepared into the bare chip leveling structure with the set thickness, and even if the bare chips with different thicknesses are packaged, the packaging efficiency is greatly improved. And different bare chips can be kept coplanar in the packaging process, so that the problem of non-uniform pressure due to non-coplanar state is avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, specifically to a die leveling structure and its preparation method, a pre-packaged module and its preparation method, and a chip packaging structure and its preparation method. Background Technology

[0002] With the rapid development of applications such as artificial intelligence (AI), high-performance computing (HPC), 5G communication, and high-bandwidth memory (HBM), 2.5D and 3D packaging technologies have become key paths to achieve high-bandwidth interconnects, low latency, and heterogeneous integration. Correspondingly, the energy consumption and heat dissipation requirements of 2.5D packaging (silicon interposer / silicon bridge interconnect) and 3D packaging (TSV stacked interconnect) are increasing. Therefore, current chip packaging structures generally include heat sinks. Existing packaging processes first encapsulate the die with the substrate through an interposer, and then finally encapsulate the resulting overall structure with a heat sink. However, this process has the following drawbacks in actual production: Die thickness may vary, leading to non-coplanarity between the die and the interposer surface. When the heat sink is attached to the die surface with thermally conductive adhesive, uneven pressure occurs on dies of different thicknesses. Specifically, thicker dies and the corresponding interposer at those locations may be damaged due to excessive pressure, while thinner dies may have air gaps due to insufficient adhesion to the heat sink, significantly increasing local thermal resistance and affecting heat dissipation.

[0003] In addition, the silicon interposer is easily damaged by thermal stress (such as microcracks) during multiple die mounting hot pressing cycles. At the same time, due to the mismatch between the coefficient of thermal expansion (CTE) of the die and the silicon interposer material, the silicon interposer is prone to stress accumulation during multiple high-temperature processes, which may lead to warping problems. Summary of the Invention

[0004] This application aims to address one of the technical problems in related technologies to a certain extent. To this end, this application provides a die leveling structure and its fabrication method, a pre-packaged module and its fabrication method, and a chip packaging structure and its fabrication method.

[0005] To achieve the above objectives, this application adopts the following technical solution: a bare die leveling structure, comprising a bare die and a leveling silicon wafer, wherein the leveling silicon wafer is attached to the surface of the bare die to form an integral structure with a set thickness.

[0006] The application of this application has the following beneficial effects: for mounting and leveling silicon wafers on bare dies, the overall thickness of the bare die leveling structure can be ensured by designing the thickness of the leveling silicon wafer. This allows bare dies of different thicknesses that need to be packaged together to be prepared as bare die leveling structures with a set thickness. In this way, even if bare dies of different thicknesses are packaged, it can be ensured that the different bare dies remain coplanar during the packaging process, avoiding the problem of uneven pressure caused by non-coplanarity.

[0007] In addition, this application also provides a pre-packaged module, including a heat sink and at least two die leveling structures as described in the above technical solutions. The die leveling structures are attached to one side surface of the heat sink through the leveling silicon wafer to form an integral structure, and the active surfaces of the dies in all the die leveling structures are coplanar.

[0008] The application of this application has the following beneficial effects: Firstly, because the pre-packaged module adopts a die leveling structure, it ensures that the dies remain coplanar during the packaging process, avoiding uneven pressure caused by non-coplanarity. Secondly, compared with the prior art's operation of merging and bonding the heat sink cover to the die cover, the operation of bonding and fixing the die to the heat sink cover in this application is easier to align and more stable during the curing of thermally conductive adhesive, which can reduce the risk of chip damage and warpage, and improve product yield. In addition, regardless of the number of dies, the pre-packaged module can be flip-chip bonded to the interconnect interposer in one go, reducing the number of die-to-interconnect interposer mounting operations, thereby significantly reducing the duration of thermoforming cycles and reducing damage to the interconnect interposer, thus further improving yield.

[0009] Optionally, at least two of the bare sheet leveling structures may have different thickness dimensions for the bare sheets.

[0010] Optionally, the heat dissipation cover includes a cover plate portion and a bent portion formed by extending from the edge of the cover plate portion. The surface of the cover plate portion located inside the bent portion is the inner side surface of the cover plate portion. The bare die leveling structure is bonded and fixed to the inner side surface of the cover plate portion by a leveling silicon wafer.

[0011] Optionally, the arrangement of the plurality of bare plate leveling structures on the heat sink includes a straight line arrangement, a grid arrangement, and a radial arrangement from the center to the surrounding areas.

[0012] Optionally, at least two of the dies in the die leveling structures are manufactured using different semiconductor processes.

[0013] Optionally, the surface of the heat sink cover is provided with alignment marks for assisting in positioning the die leveling structure.

[0014] In addition, this application also provides a chip packaging structure, including a packaging substrate, an interconnect interposer disposed on the packaging substrate, and a pre-packaged module as described in any of the above technical solutions. The pre-packaged module is flip-chip mounted on the interconnect interposer, and the die in the pre-packaged module is electrically connected to the interconnect interposer.

[0015] The chip packaging structure provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned pre-packaged module, and will not be repeated here.

[0016] In addition, this application also provides a chip packaging structure, including a packaging substrate, a silicon bridge, and a pre-packaged module as described in any of the above technical solutions. The silicon bridge is bonded to at least two dies in the die leveling structure using a flip-chip process to form an integral structure. The packaging substrate is provided with a curing tank. The pre-packaged module and the silicon bridge, which form an integral structure, are integrally mounted on the packaging substrate using a flip-chip process. The chip is electrically connected to the packaging substrate, and the silicon bridge is at least partially accommodated in the curing tank.

[0017] The chip packaging structure provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned pre-packaged module, and will not be repeated here.

[0018] Furthermore, this application also provides a method for preparing a bare wafer leveling structure, the method comprising:

[0019] Offer bare dies or whole wafers;

[0020] A leveling silicon wafer is provided, and the thickness of the leveling silicon wafer is determined according to the thickness of the bare wafer or whole wafer and the target size of the bare wafer leveling structure.

[0021] The bare die or wafer is mounted onto the leveling silicon wafer with its surface facing the leveling silicon wafer to obtain an intermediate product.

[0022] Cutting the intermediate product yields a single bare sheet leveling structure.

[0023] The preparation method provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned bare wafer leveling structure, and will not be repeated here.

[0024] Furthermore, this application also provides a method for preparing a pre-packaged module, the method comprising:

[0025] Provide a heatsink cover;

[0026] Provide at least two bare die leveling structures as described in the above technical solutions, and all of the bare die leveling structures have the same thickness dimension;

[0027] The bare die leveling structure is attached to one side surface of the heat sink by leveling silicon wafer.

[0028] The preparation method provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned pre-packaged module, and will not be repeated here.

[0029] Optionally, providing at least two bare die leveling structures as described in the above technical solutions includes:

[0030] At least two of the aforementioned bare sheet leveling structures have different bare sheet thicknesses.

[0031] In addition, this application also provides a method for fabricating a chip packaging structure.

[0032] Provide a pre-packaged module as described in any of the above technical solutions;

[0033] A first packaging substrate with a first interconnect interposer layer is provided, and the pre-packaged module is mounted to the first interconnect interposer layer in one step using a flip-chip process, so that the bare die is electrically connected to the first interconnect interposer layer; or, a second interconnect interposer layer and a second packaging substrate are provided, and the pre-packaged module is mounted to the second interconnect interposer layer in one step using a flip-chip process, so that the bare die is electrically connected to the second interconnect interposer layer, to obtain an intermediate product, and then the intermediate product is mounted as a whole onto the second packaging substrate.

[0034] The preparation method provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned pre-packaged module, and will not be repeated here.

[0035] In addition, this application also provides a method for fabricating a chip packaging structure.

[0036] Provide a pre-packaged module as described in any of the above technical solutions;

[0037] Provide the required number of silicon bridges according to the number and arrangement of the die leveling structures in the pre-packaged module;

[0038] A packaging substrate is provided, and a curing groove adapted to the silicon bridge is formed on the surface of the packaging substrate;

[0039] The die leveling structure is interconnected by the silicon bridge using a flip-chip process, so that the silicon bridge and the pre-packaged module form an integral structure.

[0040] The silicon bridge, which is formed as an integral structure, and the pre-packaged module are integrally mounted to the packaging substrate in one step using a flip-chip process, so that the bare die in the pre-packaged module is electrically connected to the packaging substrate, and the silicon bridge extends at least partially into the curing tank;

[0041] The bottom filler material is filled into the curing tank and then cured.

[0042] The preparation method provided in this application is similar to the reasoning process of the beneficial effects of the aforementioned pre-packaged module, and will not be repeated here.

[0043] These features and advantages of this application will be disclosed in detail in the following specific embodiments and accompanying drawings. The best embodiments or means of this application will be shown in detail in conjunction with the accompanying drawings, but are not intended to limit the technical solutions of this application. In addition, each of these features, elements and components appearing in the following text and drawings is multiple and is labeled with different symbols or numbers for convenience, but all represent parts with the same or similar structure or function. Attached Figure Description

[0044] The following description, in conjunction with the accompanying drawings, further illustrates this application:

[0045] Figure 1 A schematic diagram of a bare die leveling structure provided for the first aspect of this application;

[0046] Figure 2 A schematic diagram of a pre-packaged module provided for the second aspect of this application;

[0047] Figure 3 This is a cross-sectional view of the pre-packaged module;

[0048] Figure 4 A schematic diagram of a chip packaging structure provided for the third aspect of this application;

[0049] Figure 5 for Figure 4 A schematic diagram of the intermediate product in the chip packaging structure during the manufacturing process;

[0050] Figure 6 This is a schematic diagram of a chip packaging structure in another embodiment;

[0051] Figure 7 for Figure 6 A schematic diagram of the intermediate product in the chip packaging structure during the manufacturing process.

[0052] Among them, 1. First die leveling structure; 10. First die; 100. First active surface; 11. First leveling silicon wafer; 2. Second die leveling structure; 20. Second die; 200. Second active surface; 21. Second leveling silicon wafer; 3. Heat sink; 30. Cover plate portion; 31. Bending portion; 4. First packaging substrate; 5. First interconnect interposer layer; 6. Third packaging substrate; 60. Curing tank; 7. Silicon bridge. Detailed Implementation

[0053] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described are intended to explain this application and should not be construed as limiting it.

[0054] The terms "an embodiment," "example," or "example" used in this specification refer to a particular feature, structure, or characteristic described in connection with the embodiment itself that may be included in at least one embodiment disclosed in this application. The phrase "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.

[0055] In the description of this application, it should be understood that the terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "a plurality of" means two or more, unless otherwise precisely specified.

[0056] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected," "linked," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a connection through an intermediary, or a connection within two elements or an interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0057] The first aspect of this application provides a bare die leveling structure, such as Figure 1 As shown, the die leveling structure includes a bare die and a leveling silicon wafer. The leveling silicon wafer is mounted on the surface of the bare die to form an integral structure with a predetermined thickness. To facilitate demonstration of the beneficial effects of this die leveling structure in application, Figure 1 The diagram illustrates two die leveling structures with different die thicknesses. For clarity, these structures are referred to as the first die leveling structure 11 and the second die leveling structure 22. The first die leveling structure 11 comprises a first die 10 and a first leveling structure, while the second die leveling structure 22 comprises a second die 20 and a second leveling structure. The first die 10 has a greater thickness than the second die 20, but through the cooperation of the first leveling wafer 11 and the second leveling wafer 21, the first active surface 100 on the first die 10 and the second active surface 200 on the second die 20 can be made coplanar.

[0058] For die mounting and leveling silicon wafers, the overall thickness of the die leveling structure can be ensured by designing the thickness of the leveling silicon wafer. This allows dies of different thicknesses that need to be packaged together to be prepared as die leveling structures with a set thickness. In this way, even when dies of different thicknesses are packaged, it can be ensured that the different dies remain coplanar during the packaging process, avoiding the problem of uneven pressure caused by non-coplanarity.

[0059] The preparation method of the above-mentioned bare wafer leveling structure is described, and the preparation method includes the following steps:

[0060] First, bare wafers are provided; to facilitate mass production, multiple bare wafers can be provided at once.

[0061] Then, a leveling silicon wafer is provided, and the thickness of the leveling silicon wafer is determined according to the thickness of the provided bare wafer and the target size of the bare wafer leveling structure; the leveling silicon wafer is a silicon wafer.

[0062] Secondly, the bare die is mounted on the leveling silicon wafer with its surface facing the leveling silicon wafer to obtain the intermediate product.

[0063] Finally, the intermediate products described above are cut to obtain individual bare sheet leveling structures.

[0064] The above preparation method can be used to obtain a die leveling structure with a set thickness. For multiple dies with different thicknesses that need to be packaged together, the above preparation method can be used to prepare the corresponding die leveling structures respectively.

[0065] In other alternative embodiments, the above-described preparation method can be improved. Specifically, instead of initially providing a bare wafer, a whole wafer is provided. Then, the thickness of the leveling silicon wafer is determined based on the thickness of the provided wafer and the target size of the bare wafer leveling structure, and a leveling silicon wafer of the corresponding thickness is provided. The wafer is then mounted on the leveling silicon wafer with its surface facing the leveling silicon wafer to obtain an intermediate product. Finally, the intermediate product is cut to obtain individual bare wafer leveling structures.

[0066] It is easy to understand that the active surface of the die refers to the functional surface of the circuit, which is both the interface for electrical signal input / output and the surface connected to the outside through wire bonding, flip-chip bonding, etc. in the package. The back surface of the die is the surface facing away from the active surface, mainly providing mechanical support and heat dissipation. Similarly, the active surface of the wafer refers to the side of the wafer on which active devices such as transistors, capacitors, and resistors, as well as multilayer metal interconnects, are fabricated. The back surface of the wafer is the surface facing away from the active surface, and the back surface of the wafer is unprocessed.

[0067] Combination Figure 2and Figure 3 As shown, a second aspect of this application provides a pre-packaged module, which includes a heat sink 3 and two die leveling structures (a first die leveling structure 11 and a second die leveling structure 22). The die leveling structures are mounted to one side surface of the heat sink 3 to form an integral structure by leveling silicon wafers, and the active surfaces of the dies in the two die leveling structures are coplanar. It is readily understood that in other alternative embodiments, three or more die leveling structures may also be provided.

[0068] On the one hand, because the pre-packaged module adopts a die leveling structure, it ensures that the dies remain coplanar during the packaging process, avoiding uneven pressure caused by non-coplanarity. On the other hand, compared with the existing technology of merging and bonding the heat sink cover 3 to the die cover, the operation of bonding and fixing the die to the heat sink cover 3 in this application is easier to align and more stable during the curing of thermally conductive adhesive, which can reduce the risk of chip damage and warpage and improve product yield. In addition, regardless of the number of dies, the pre-packaged module can be flip-chip bonded to the interconnect interposer in one go, reducing the number of die-to-interconnect interposer mounting operations, thereby significantly reducing the duration of thermo-pressing cycles and reducing damage to the interconnect interposer, thus further improving yield.

[0069] It should be noted that the pre-packaging module in this embodiment has two die leveling structures, wherein the first die 10 and the second die 20 have different thicknesses. In other optional embodiments, more die leveling structures can be provided, and at least two of the die leveling structures have different die thicknesses to achieve the effect of "avoiding uneven pressure due to non-coplanarity" provided by the pre-packaging module. Of course, in some optional embodiments, the die thicknesses in multiple die leveling structures can be designed to be the same, so that the pre-packaging module can still improve yield and packaging efficiency.

[0070] In this embodiment, the first die 10 and the second die 20 are heterogeneous dies of different types. Specifically, the first die 10 is an HBM die, and the second die 20 is a CPU die. In other optional embodiments, they can also be GPU dies or other dies. This design can meet the high-performance integration requirements of AI, HPC and other applications for dies with different functions. At the same time, it is easy to achieve tight interconnection of computing, storage and other units, reduce latency and improve bandwidth.

[0071] The heat sink 3 in this embodiment includes a cover plate portion 30 and a bent portion 31 extending from the edge of the cover plate portion 30. The surface of the cover plate portion 30 located inside the bent portion 31 is the inner side surface of the cover plate portion 30. The die leveling structure is bonded and fixed to the inner side surface of the cover plate portion 30 by a leveling silicon wafer. The above structural design facilitates the encapsulation of the heat sink 3 with the interlayer or substrate through the end face of the bent portion 31. In this embodiment, both the first die leveling structure 11 and the second die leveling structure 22 are bonded and fixed to the cover plate portion 30 by thermal adhesive (not shown in the figure), and the thickness of the thermal adhesive is about 20 μm.

[0072] In this embodiment, the first die leveling structure 11 and the second die leveling structure 22 are arranged in a straight line. In other optional embodiments, if the number of die leveling structures is greater, their arrangement can also be a grid pattern or a radial arrangement from the center outwards. Of course, a larger number of die leveling structures can also be arranged in a straight line. Specifically, the optimal layout can be selected based on the size, power consumption, and interconnection requirements of the dies in the die leveling structure to optimize the heat distribution and signal paths within the module.

[0073] Furthermore, in this embodiment, alignment marks for assisting in positioning the die are also provided on the surface of the heat sink 3. These alignment marks can be continuous or discontinuous etched lines, or color-coded area marks, etc. Using these alignment marks reduces the difficulty of alignment and improves the accuracy of alignment during the bonding process, thereby ensuring the positional accuracy of the die leveling structure on the heat sink 3, providing a good foundation for the high-precision flip-chip bonding of the pre-packaged module and the packaging substrate.

[0074] In this embodiment, the heat sink 3 is made of metal. For example, the heat sink 3 can be made of copper, which has a thermal conductivity of about 400 W / m·K, excellent thermal conductivity, and good strength. The heat sink 3 can also be made of aluminum, which has the advantages of being lightweight, low-cost, and strong, with a thermal conductivity generally between 160-220 W / m·K. In other optional embodiments, the heat sink 3 can also be made of a metal alloy, such as a copper alloy or an aluminum alloy, or it can be made of glass. Compared to the prior art where the chip is first bonded to the silicon interposer, in this embodiment, the first die 10 and the second die 20 are first bonded to one side surface of the heat sink 3, which has higher flatness and better rigidity. This makes alignment easier and ensures the stability of the first die 10 and the second die 20 relative to the heat sink 3 after bonding, reducing the probability of slight displacement during the curing process of the thermal adhesive.

[0075] The preparation method of the above-mentioned pre-packaged module is described, and the preparation method includes:

[0076] Provide heat sink 3;

[0077] A first bare die leveling structure 11 and a second bare die leveling structure 22 are provided, and the thickness of the first bare die leveling structure 11 and the thickness of the second bare die leveling structure 22 are the same.

[0078] The first die leveling structure 11 and the second die leveling structure 22 are respectively attached to one side surface of the heat sink 3 through the first leveling silicon wafer 11 and the second leveling silicon wafer 21.

[0079] The third aspect of this application provides a chip packaging structure, combined with Figure 4 and Figure 5 As shown, the chip packaging structure includes a packaging substrate, an interconnect interposer disposed on the packaging substrate, and the aforementioned pre-packaged module. The pre-packaged module is flip-chip mounted on the interconnect interposer, and the die in the pre-packaged module is electrically connected to the interconnect interposer.

[0080] As mentioned above, since the chip packaging structure uses the pre-packaged module provided in this application, regardless of the number of bare dies, the pre-packaged module can be flip-chipped with the interconnect interposer in one go, reducing the number of times the bare dies are mounted to the interconnect interposer, thereby significantly reducing the duration of the hot pressing cycle and reducing damage to the interconnect interposer, which can further improve the yield.

[0081] In other alternative implementations, silicon bridges 7 can be used instead of interconnect interposers to interconnect the die; specifically, in conjunction with... Figure 6 and Figure 7 As shown, another embodiment of the chip packaging structure includes a packaging substrate, a silicon bridge 7, and the aforementioned pre-packaged module. The silicon bridge 7 is bonded to the first die 10 and the second die 20 using a flip-chip process to form an integral structure. The packaging substrate is provided with a curing tank 60. The pre-packaged module and the silicon bridge 7, forming an integral structure, are integrally mounted on the packaging substrate using a flip-chip process. The chip is electrically connected to the packaging substrate, and the silicon bridge 7 is at least partially accommodated within the curing tank 60.

[0082] The fabrication method of the above-mentioned chip packaging structure is described below. Specifically, the fabrication process is as follows: Figure 4 The method for fabricating the chip packaging structure shown includes:

[0083] Provide the pre-packaged module as described above;

[0084] A first packaging substrate 4 having a first interconnect interposer layer 5 is provided;

[0085] The pre-packaged module is mounted onto the first interconnect interposer 5 in one step using a flip-chip process, thereby electrically connecting the bare die to the first interconnect interposer 5.

[0086] In the above scheme, the interconnect interposer is pre-installed on the packaging substrate as a whole. It is easy to understand that in some alternative embodiments, the interconnect interposer and the packaging substrate can be provided separately. Specifically, a second interconnect interposer and a second packaging substrate are provided. The pre-packaged module is first mounted onto the second interconnect interposer in one step using a flip-chip process, and the bare die is electrically connected to the second interconnect interposer to obtain an intermediate product (such as...). Figure 5 As shown in the figure, the intermediate product is then mounted onto the second packaging substrate.

[0087] The fabrication method using the above-described chip packaging structure can significantly reduce damage and warpage issues in the interconnect interposers, greatly improving yield. It can also significantly improve packaging efficiency and reduce production costs.

[0088] In addition, preparation such as Figure 6 The method for fabricating the chip packaging structure shown includes:

[0089] Provide the pre-packaged module as described above;

[0090] The required number of silicon bridges 7 are provided according to the number and arrangement of the die leveling structures in the pre-package module; in this embodiment, the pre-package module includes a first die leveling structure 11 and a second die leveling structure 22, and only one silicon bridge 7 needs to be set.

[0091] A third packaging substrate 6 is provided, and a curing groove 60 adapted to the silicon bridge 7 is formed on the surface of the third packaging substrate 6;

[0092] The die leveling structure is interconnected via silicon bridge 7 using a flip-chip process, making silicon bridge 7 and the pre-packaged module an integral structure (e.g.) Figure 7 (as shown)

[0093] The silicon bridge 7, which is formed as an integral structure, is attached to the pre-packaged module in one step using a flip-chip process, so that the bare die in the pre-packaged module is electrically connected to the third packaged substrate 6, and the silicon bridge 7 extends at least partially into the curing tank 60.

[0094] Fill the curing tank 60 with bottom filler material and cure it.

[0095] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Those skilled in the art should understand that this application includes, but is not limited to, the contents described in the accompanying drawings and the specific embodiments above. Any modifications that do not depart from the functional and structural principles of this application will be included within the scope of the claims.

Claims

1. A bare sheet leveling structure, characterized in that, It includes a bare die and a leveling silicon wafer, wherein the leveling silicon wafer is mounted on the surface of the bare die to form an integral structure with a set thickness.

2. A pre-packaged module, characterized in that, It includes a heat sink and at least two die leveling structures as described in claim 1, wherein the die leveling structures are attached to one side surface of the heat sink to form an integral structure by means of the leveling silicon wafers, and the active surfaces of the dies in all the die leveling structures are coplanar.

3. The pre-packaged module as described in claim 2, characterized in that, At least two of the aforementioned bare sheet leveling structures have different bare sheet thicknesses.

4. The pre-packaged module as described in claim 2, characterized in that, The heat dissipation cover includes a cover plate portion and a bent portion formed by extending from the edge of the cover plate portion. The surface of the cover plate portion located inside the bent portion is the inner side surface of the cover plate portion. The bare die leveling structure is bonded and fixed to the inner side surface of the cover plate portion by a leveling silicon wafer.

5. The pre-packaged module as described in claim 4, characterized in that, The arrangement of the multiple bare slab leveling structures on the heat sink includes a straight line arrangement, a grid arrangement, and a radial arrangement from the center to the surrounding areas.

6. The pre-packaged module as described in claim 4, characterized in that, At least two of the dies in the aforementioned die leveling structures are manufactured using different semiconductor process technologies.

7. The pre-packaged module as described in claim 4, characterized in that, The surface of the heat sink cover is provided with alignment marks to assist in positioning the die leveling structure.

8. A chip packaging structure, characterized in that, The package includes a packaging substrate, an interconnect interposer disposed on the packaging substrate, and a pre-packaged module as described in any one of claims 2 to 7, wherein the pre-packaged module is flip-chip mounted on the interconnect interposer, and the die in the pre-packaged module is electrically connected to the interconnect interposer.

9. A chip packaging structure, characterized in that, Includes a packaging substrate, a silicon bridge, and a pre-packaged module as described in any one of claims 2 to 7, wherein the silicon bridge is bonded to at least two dies in the die leveling structure using a flip-chip process to form an integral structure; The packaging substrate is provided with a curing tank. The pre-packaged module and silicon bridge, which are formed as an integral structure, are integrally mounted on the packaging substrate using a flip-chip process. The chip is electrically connected to the packaging substrate, and the silicon bridge is at least partially accommodated in the curing tank.

10. A method for preparing a bare wafer leveling structure, characterized in that, The preparation method includes: Offer bare dies or whole wafers; A leveling silicon wafer is provided, and the thickness of the leveling silicon wafer is determined according to the thickness of the bare wafer or whole wafer and the target size of the bare wafer leveling structure. The bare die or wafer is mounted onto the leveling silicon wafer with its surface facing the leveling silicon wafer to obtain an intermediate product. Cutting the intermediate product yields a single bare sheet leveling structure.

11. A method for preparing a pre-packaged module, characterized in that, The preparation method includes: Provide a heatsink cover; Provide at least two die leveling structures as described in claim 1, and all of the die leveling structures have the same thickness dimension; The bare die leveling structure is attached to one side surface of the heat sink by leveling silicon wafer.

12. The preparation method according to claim 11, characterized in that, The provision of at least two bare die leveling structures as described in claim 1 includes: At least two of the aforementioned bare sheet leveling structures have different bare sheet thicknesses.

13. A method for fabricating a chip packaging structure, characterized in that, Provide a pre-packaged module as described in any one of claims 2 to 7; A first packaging substrate with a first interconnect interposer layer is provided, and the pre-packaged module is mounted to the first interconnect interposer layer in one step using a flip-chip process, so that the bare die is electrically connected to the first interconnect interposer layer; or, a second interconnect interposer layer and a second packaging substrate are provided, and the pre-packaged module is mounted to the second interconnect interposer layer in one step using a flip-chip process, so that the bare die is electrically connected to the second interconnect interposer layer, to obtain an intermediate product, and then the intermediate product is mounted as a whole onto the second packaging substrate.

14. A method for fabricating a chip packaging structure, characterized in that, Provide a pre-packaged module as described in any one of claims 2 to 7; Provide the required number of silicon bridges according to the number and arrangement of the die leveling structures in the pre-packaged module; A packaging substrate is provided, and a curing groove adapted to the silicon bridge is formed on the surface of the packaging substrate; The die leveling structure is interconnected by the silicon bridge using a flip-chip process, so that the silicon bridge and the pre-packaged module form an integral structure. The silicon bridge, which is formed as an integral structure, and the pre-packaged module are integrally mounted to the packaging substrate in one step using a flip-chip process, so that the bare die in the pre-packaged module is electrically connected to the packaging substrate, and the silicon bridge extends at least partially into the curing tank; The bottom filler material is filled into the curing tank and then cured.

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