High vacuum room temperature bonding method

Abstract

This invention provides a high-vacuum, room-temperature bonding method, relating to the field of semiconductor device bonding technology. It includes: providing a chip and a wafer, wherein the chip has a first conductive structure and the wafer has a second conductive structure; and bonding under a vacuum degree ≤ 6 × 10⁻⁶. ‑6 Heatedless bonding of the chip and wafer is performed in the bonding chamber of Pa. Prior to bonding, the first and second conductive structures are reduced using a reducing gas to remove oxides from their surfaces. After the reduction treatment, the chip and wafer are transported to the bonding chamber in an oxygen-free environment, including a vacuum environment and / or an inert gas protective environment. This method enables heated metal bonding interconnection of the chip and wafer at room temperature.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device bonding technology, and more particularly to a high-vacuum room-temperature bonding method. Background Technology

[0002] Copper-to-copper interconnect (Cu-Cu TCB) is a core technology in advanced semiconductor packaging that enables solderless copper-to-copper direct diffusion connections between chips and substrates through thermocompression bonding. It is based on local heating, rapid temperature rise and fall, and high-precision alignment. By raising the copper to a set temperature and simultaneously applying pressure, copper atoms diffuse to form a stable connection. It is suitable for ultra-fine pitches of <10μm and supports high-density integration scenarios such as 3D-IC and Chiplet. It also has the advantages of low resistance, high reliability, and process compatibility.

[0003] The main limitation of TCB copper-copper interconnects lies in their narrow process window, requiring a balance between temperature, pressure, time, and alignment accuracy, making parameter optimization complex. Temperature, in particular, significantly impacts the chip; abnormal temperatures disrupt the controllable diffusion of copper atoms, either preventing metallurgical bonding due to insufficient diffusion or causing microstructure degradation due to excessive diffusion. This leads to derivative problems such as device thermal damage, structural deformation, and decreased process consistency. Temperature also causes thermal deformation, thermal stress, and system thermal drift in the chip, resulting in decreased alignment accuracy. In high-bump-density copper-copper interconnects, this can lead to bump misalignment, insufficient contact area, and ultimately interconnect failure. Summary of the Invention

[0004] This invention provides a high-vacuum room-temperature bonding method for performing heatless metal bonding interconnection between a chip and a substrate at room temperature.

[0005] To achieve this objective, the present invention adopts the following technical solution:

[0006] A high-vacuum room-temperature bonding method includes: providing a chip and a wafer, wherein the chip has a first conductive structure and the wafer has a second conductive structure;

[0007] Vacuum degree ≤ 9×10 -5 The bonding chamber of Pa performs heatless bonding of the chip to the wafer;

[0008] Before the bonding, the first conductive structure and the second conductive structure are reduced by reducing gas to remove oxides from the surfaces of the first conductive structure and the second conductive structure.

[0009] The surface roughness Ra of the first conductive structure and the second conductive structure after the reduction treatment is ≤2nm, including but not limited to 2nm, 1.5nm, 1nm, 0.5nm, and 0.2nm.

[0010] Preferably, after the reduction process, the chip and the wafer are transferred to the bonding chamber in an oxygen-free environment;

[0011] The oxygen-free environment includes a vacuum environment and / or an inert gas protective environment.

[0012] Preferably, a heat treatment of the bonded product is performed after the bonding; the bonded product includes a wafer and multiple chips bonded on the wafer.

[0013] Preferably, the heat treatment conditions include holding at 200-300°C for 5-120 minutes in a vacuum environment and / or an inert atmosphere, including but not limited to 5 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 60 minutes, 70 minutes, 80 minutes, 90 minutes, 100 minutes, 110 minutes, and 120 minutes.

[0014] Preferably, a mechanical pressure of 0.01-30 MPa is applied during the heat treatment process, including but not limited to 0.01 MPa, 1 MPa, 5 MPa, 10 MPa, 15 MPa, 20 MPa, 25 MPa, and 30 MPa.

[0015] Preferably, the vacuum level of the bonding chamber is 9 × 10⁻⁶. -5 Pa to 1×10 -9 Pa, including but not limited to 1×10 - 7 Pa, 5×10 -7 Pa, 1×10 -8 Pa, 5×10 -8 Pa, 1×10 -9 Pa.

[0016] Preferably, an inert gas is introduced into the bonding chamber during the bonding process, and the vacuum level of the bonding chamber is maintained at ≤9×10⁻⁶. -5 Pa;

[0017] Preferably, the inert gas is argon or nitrogen.

[0018] Preferably, the reducing gas includes at least one of hydrogen free radicals and hydrogen ions.

[0019] Preferably, the reducing gas is generated by the reaction of formic acid with a catalyst.

[0020] Preferably, the catalyst comprises a noble metal catalyst;

[0021] Preferably, the noble metal catalyst includes palladium, platinum, or nickel-based catalysts.

[0022] Preferably, the reducing gas is generated by plasma treatment of hydrogen.

[0023] Preferably, the first conductive structure and the second conductive structure are independently selected from at least one of gold, silver, copper, tin, copper-tin alloy, silver-tin alloy, and tin-silver-copper alloy, and the first conductive structure and the second conductive structure are homogeneous materials or a combination of heterogeneous materials.

[0024] Preferably, before the bonding, the first conductive structure and the second conductive structure are planarized.

[0025] The leveling process includes polishing or flattening.

[0026] The beneficial effects of this invention are:

[0027] This invention provides a high-vacuum room-temperature bonding method that enables heatless metal-to-chip interface bonding at room temperature. The method uses a reducing gas to remove the metal oxide layer on the bonding surface and completes the transfer and bonding operations entirely in an ultra-high vacuum environment. The ultra-high vacuum environment suppresses the secondary formation of the metal oxide layer, ensuring that the metal interface meets atomic diffusion conditions, ultimately forming a stable bonding interface. For scenarios requiring high bonding strength, the bonding strength can be further increased through overall heat treatment of the bonded product. This overall heat treatment of the bonded product avoids the problems associated with traditional TCB hot-press bonding.

[0028] This method solves a series of problems caused by high temperature in traditional TCB hot-press bonding: it avoids uncontrolled atomic diffusion caused by abnormal temperature (insufficient diffusion cannot effectively bond or excessive diffusion causes microstructure deterioration), eliminates defects such as chip thermal damage, structural deformation, system thermal drift and reduced process consistency caused by high temperature, and eliminates the loss of alignment accuracy caused by thermal deformation and thermal stress.

[0029] Furthermore, this method avoids the problems of plasma surface activation processes failing to effectively remove thick oxide layers and generating difficult-to-remove byproducts during the removal process. It effectively solves the interconnect failure risks such as bump misalignment and insufficient contact area in high bump density scenarios, significantly broadens the metal interconnect process window, reduces the difficulty of optimizing process parameters such as temperature and pressure, and ensures the connection reliability and process stability of ultra-fine pitch metal interconnects. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1This is a schematic diagram of the device structure used to perform one embodiment of the method of the present invention.

[0032] Figure label:

[0033] 1. Bonding chamber; 2. Transfer chamber; 3. Reduction chamber; 4. Transmission chamber; 5. Front-end module. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0035] The method in this embodiment can be achieved as follows: Figure 1 The equipment shown is complete. (As shown) Figure 1 As shown, the device includes a bonding chamber 1; a transfer chamber 2; a reduction chamber 3; a transit chamber 4; and a front-end module 5. The front-end module 5 is sealed to the transit chamber 4 via a vacuum valve, the transit chamber 4 is sealed to the transfer chamber 2 via a vacuum valve, and the transfer chamber 2 is sealed to the bonding chamber 1 via a vacuum valve. It is used for the transit storage of chips, wafers, and bonding products in an oxygen-free environment.

[0036] The reduction chamber 3 can release reducing gas to reduce the first conductive structure and the second conductive structure to remove oxides from the surfaces of the first conductive structure and the second conductive structure.

[0037] The bonding chamber 1 is equipped with a gantry platform, a pressing head module, a chip transfer mechanism, a wafer stage module, a chip transport module, and a vision alignment module. The gantry platform spans the interior of the bonding chamber 1, and the pressing head module is mounted on the gantry platform and can move in the XZ directions. The wafer stage module is located below the pressing head module and faces it. The chip transport module is located on one side of the wafer stage module and is used to supply chips. The chip transfer mechanism is located between the unloading position of the chip transport module and the picking position of the pressing head module, and is used to transfer chips. The pressing head module includes a driving section and a chip adsorption section, wherein the chip adsorption method is electrostatic adsorption. The driving section can drive the chip adsorption section to move in the Z direction, realizing the chip pickup and pressing action. The chip adsorption section is used to adsorb the chip at the picking position and press the chip onto the wafer surface.

[0038] Example 1

[0039] The system provides chips and wafers to be bonded. The chips are silicon-based chips that have undergone front-end processing and have a first conductive structure fabricated on their bonding surface. The chips include 100 chips mounted on a tray. The wafers are silicon wafers and have a second conductive structure fabricated on their bonding surface that precisely matches the position and size of the first conductive structure, ensuring that the two can be perfectly aligned during subsequent bonding. The time required to bond all 100 chips to the wafer is less than 30 minutes.

[0040] In this embodiment, both the first conductive structure and the second conductive structure use copper as the conductive material, which is compatible with the Cu-Cu interconnect process in advanced semiconductor packaging. The first conductive structure is a copper bump with a diameter of 10μm and a height of 5μm. The second conductive structure is a copper pad with a diameter of 10μm and a thickness of 5μm, and the bump spacing is 20μm.

[0041] In a preferred embodiment, the first conductive structure and / or the second conductive structure are planarized to ensure uniform height. The planarization process can be performed by chemical mechanical polishing or by flattening the conductive structure against a planarizing carrier.

[0042] As one implementation method, planarization can be used to bond the first or second conductive structure to a sapphire wafer with low roughness (e.g., roughness ≤ 2 nm), thereby making the first and second conductive structures highly consistent and with smooth surfaces. The surface roughness of the first and second conductive structures after planarization is 2 nm, providing a smooth interface for subsequent bonding and improving the diffusion efficiency of metal atoms.

[0043] Furthermore, the first and second conductive structures undergo surface cleaning to remove dust, oil, photoresist residue, and other impurities, preventing them from affecting the subsequent reduction process and bonding quality. Argon plasma cleaning is used, with a plasma power of 100W, a cleaning time of 30 seconds, and an argon flow rate of 30 sccm. After cleaning, nitrogen purging is employed to remove any residual plasma reaction products from the surface.

[0044] Furthermore, the cleaned chip and wafer are transferred to a separate reduction chamber, where a reducing gas is used to reduce the surfaces of the first and second conductive structures, removing the copper oxide film naturally formed on their surfaces. This prevents the oxide layer from hindering atomic diffusion between the conductive structures, ensuring stable metal bonding at room temperature. The reducing gas selectively reduces only the first and second conductive structures, without reacting with the silicon substrate of the chip and wafer, thus avoiding the adverse effects of sputtering difficult-to-remove byproducts on the silicon substrate through plasma activation.

[0045] In this embodiment, hydrogen free radicals are selected as the reducing gas. Hydrogen free radicals can be generated through a catalytic reaction of formic acid and noble metals, or through plasma generation of hydrogen gas. For example, high-purity hydrogen gas (purity ≥99.999%) is introduced into a radio frequency plasma generator, with the hydrogen flow rate controlled at 50 sccm and the plasma generation power at 150 W, generating highly reactive hydrogen free radicals as the reducing gas. Alternatively, formic acid (purity ≥99.5%) is heated to 80°C, vaporized, and then introduced into a reaction chamber containing a palladium-based catalyst. The formic acid undergoes a decomposition reaction under the catalysis of the palladium-based catalyst. Excess reaction products are removed by a gas filtration device (molecular sieve filtration) to obtain a pure hydrogen free radical reducing gas.

[0046] Before introducing the reducing gas into the reduction chamber, the chamber is first evacuated and then backfilled with inert gas to make the reduction chamber more conducive to the reduction reaction. After the reducing gas is introduced, it is kept for a certain period of time to remove the oxides on the surfaces of the first and second conductive structures. Then, the chamber is evacuated again and backfilled with inert gas. This effectively removes reaction impurities and makes the reduction chamber oxygen-free. The surface roughness of the first and second conductive structures after reduction treatment is 1.5 nm.

[0047] After the reduction process is completed, the chip and wafer are transported to the bonding chamber in an oxygen-free environment to prevent the clean surfaces of the first and second conductive structures from coming into contact with oxygen in the air and oxidizing again during the transport process, thus ensuring that the effect of the reduction process is not compromised.

[0048] In this embodiment, an oxygen-free environment is selected using a vacuum environment with inert gas protection. The reduction chamber and the bonding chamber are connected by a vacuum transfer channel, which is equipped with a vacuum manipulator for transferring the chip and wafer. Before transfer, the transfer channel is evacuated to a vacuum level of less than 1×10⁻⁶. -5 The vacuum level must be maintained at less than 9 × 10⁻⁶ Pa and backfilled with inert gas to ensure an oxygen-free environment during the transfer process. The transfer time should be controlled to be less than 30 seconds. If the transfer channel is not backfilled with inert gas, the vacuum level must be maintained at less than 9 × 10⁻⁶ Pa. -5 Pa minimizes the risk of surface contamination and secondary oxidation.

[0049] The reduced chip and wafer are then transferred to the bonding chamber under a vacuum of 1×10⁻⁶. -7 In an ultra-high vacuum environment of Pa, heatless bonding (i.e., room temperature bonding) of chips and wafers is performed without the need for additional heating equipment, fundamentally avoiding problems such as chip thermal damage, thermal deformation, and thermal stress accumulation caused by heating.

[0050] The bonding chamber is made of stainless steel with a low outgassing rate, and its inner wall is electropolished to reduce gas adsorption. The chamber is equipped with a multi-stage vacuum pump group (mechanical pump + molecular pump + ion pump) to achieve rapid evacuation from atmospheric pressure to ultra-high vacuum. A composite vacuum gauge is used to measure the vacuum level in the chamber in real time, ensuring that the vacuum level remains stable at 1×10⁻⁶ throughout the bonding process. -7 The requirements of Pa. An ultra-high vacuum environment can prevent impurities such as oxygen and moisture in the air from entering the bonding interface and prevent the conductive structure surface from oxidizing again.

[0051] Furthermore, during the bonding process, an inert gas, specifically argon gas with a purity ≥99.999%, is introduced into the bonding chamber at a flow rate of 20 sccm, while simultaneously maintaining a stable vacuum level of 1×10⁻⁶ in the bonding chamber. -7 Argon molecules can collide with and carry away trace amounts of gas released from the bonding interface, while also providing protection, further preventing oxidation of the conductive structure surface and reducing defects at the bonding interface.

[0052] During the bonding process, a high-precision optical alignment system is first used to control the alignment accuracy between the chip and the wafer, with an alignment error of ≤0.5μm. This ensures that the first conductive structure and the second conductive structure are precisely aligned, avoiding problems such as bump misalignment and insufficient contact area. After alignment, a uniform bonding pressure is applied using a pressure device. The bonding pressure is controlled at 20MPa to avoid impact damage to the conductive structure. The bonding pressure is maintained for 20s to ensure that copper atoms diffuse fully at room temperature and form a stable metal bond.

[0053] After bonding is completed, the bonded product undergoes heat treatment. The bonded product includes a wafer and multiple chips bonded to the wafer. The heat treatment conditions are: holding at 200-300℃ for 30 minutes in an inert atmosphere, with a mechanical pressure of 10MPa applied during the heat treatment process. After bonding is completed, the bonded components undergo comprehensive testing, and the bonding strength is measured using a shear strength tester. The measured shear strength reaches 25MPa, meeting the requirements for industrial applications.

[0054] For multi-chip bonding to wafers, if the total bonding time exceeds 30 minutes, the vacuum level of the bonding chamber can be further increased to ≤1×10⁻⁶. -7 Pa, to further prevent oxidation of the conductive structure.

[0055] Comparative Example 1:

[0056] Compared with Example 1, the difference is that the bonding chamber is not equipped with a vacuum environment, the bonding process is carried out in an atmospheric environment at normal pressure, and no inert gas is introduced for protection. During the bonding process, the reduced copper conductive structure (copper bumps, copper pads) comes into contact with oxygen in the air and is rapidly oxidized again to form a copper oxide film, which hinders the diffusion of copper atoms, resulting in the inability to form a stable metal bond at room temperature, and the chip and wafer cannot be effectively bonded.

[0057] Comparative Example 2:

[0058] Compared to Example 1, the difference lies in the reduced vacuum level of the bonding cavity to 5 × 10⁻⁶. -4 Pa. Due to insufficient vacuum in the bonding chamber, residual oxygen, moisture, and other impurities caused secondary oxidation of the conductive structure, hindering copper atom diffusion. Prolonged batch bonding without increasing vacuum led to the accumulation of impurity gases, exacerbating oxidation and increasing bonding defects, resulting in a significant decrease in yield. After bonding, the yield of 100 bonds was only 33%, with the remainder exhibiting bonding interface separation, low bonding strength, and other failures, failing to meet industrial application requirements.

[0059] Comparative Example 3:

[0060] Compared to Example 1, the difference lies in the control of the surface roughness of the conductive structure. After reduction, the surface roughness distribution of the first and second conductive structures is 3-5 nm, failing to meet the requirement of a surface roughness of less than 2 nm. The uneven surface leads to a significant reduction in the actual contact area between the first and second conductive structures, resulting in a significant decrease in the metal atom diffusion efficiency and the inability to form a uniform and stable metal bonding interface. After bonding, the tests showed that the shear strength of the bonded parts was generally lower than 10 MPa, and some bonded parts had problems with poor bonding interface contact and unstable resistivity, failing to meet the requirements of industrial applications.

[0061] The bonding method provided in this embodiment can achieve heatless bonding between metals through systematic control, solving a series of problems caused by high temperature in traditional hot-press bonding.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-vacuum room-temperature bonding method, characterized in that, include: A chip and a wafer are provided, the chip having a first conductive structure and the wafer having a second conductive structure; Vacuum degree ≤ 9×10 -5 The bonding chamber of Pa performs heatless bonding of the chip to the wafer; Before the bonding, the first conductive structure and the second conductive structure are reduced by reducing gas to remove oxides from the surfaces of the first conductive structure and the second conductive structure. The surface roughness Ra of the first conductive structure and the second conductive structure after the reduction treatment is ≤2nm.

2. The high-vacuum room-temperature bonding method according to claim 1, characterized in that, After the reduction process, the chip and the wafer are transferred to the bonding chamber in an oxygen-free environment; The oxygen-free environment includes a vacuum environment and / or an inert gas protective environment.

3. The high-vacuum room-temperature bonding method according to claim 1, characterized in that, Heat treatment of the bonded product is performed after the bonding process. The bonding product includes a wafer and multiple chips bonded to the wafer.

4. The high-vacuum room-temperature bonding method according to claim 1, characterized in that, During the bonding process, an inert gas is introduced into the bonding chamber, and the vacuum level of the bonding chamber is maintained at ≤9×10⁻⁶. -5 Pa; The inert gas is argon or nitrogen.

5. The high-vacuum room-temperature bonding method according to claim 1, characterized in that, The reducing gas includes at least one of hydrogen free radicals and hydrogen ions.

6. The high-vacuum room-temperature bonding method according to claim 1 or 5, characterized in that, The reducing gas is produced by the reaction of formic acid with a catalyst.

7. The high-vacuum room-temperature bonding method according to claim 6, characterized in that, The catalyst includes a noble metal catalyst; The noble metal catalyst includes palladium, platinum, or nickel-based catalysts.

8. The high-vacuum room-temperature bonding method according to claim 1 or 5, characterized in that, The reducing gas is generated by plasma treatment of hydrogen.

9. The high-vacuum room-temperature bonding method according to claim 1, characterized in that, The first conductive structure and the second conductive structure are independently selected from at least one of gold, silver, copper, tin, copper-tin alloy, silver-tin alloy, and tin-silver-copper alloy, and the first conductive structure and the second conductive structure are homogeneous materials or a combination of heterogeneous materials.

10. The high-vacuum room-temperature bonding method according to claim 1, characterized in that, Prior to the bonding, the first conductive structure and the second conductive structure are planarized. The leveling process includes polishing or flattening.

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