Group iii element nitride semiconductor substrate

Abstract

The present application provides a kind of III element nitride semiconductor substrate, it has first surface and second surface, for this III element nitride semiconductor substrate, first surface and second surface are easily distinguished by naked eye observation, end is easily detected using optical sensor, it can ensure that effective area (area that can be used for device production) is larger, warping of entire substrate is reduced.The III element nitride semiconductor substrate involved in the embodiment of the present application is a III element nitride semiconductor substrate with first surface and second surface, wherein the first surface is a mirror surface, the second surface has a second surface central region and a second surface peripheral region, the second surface central region is a mirror surface, and the second surface peripheral region is a non-mirror surface.

Description

[0001] This application is a divisional application of the invention patent application with application number 202180054548.2 (international application number PCT / JP2021 / 016074), application date April 20, 2021, entitled "Group III Element Nitride Semiconductor Substrate". Technical Field

[0002] This invention relates to group III nitride semiconductor substrates. More specifically, it relates to a group III nitride semiconductor substrate with mirror finish on both the front and back sides, the group III nitride semiconductor substrate having a first side and a second side, and wherein only the outer peripheral region of the second side is non-mirror finished. Background Technology

[0003] As substrates for various semiconductor devices, group III nitride semiconductor substrates such as gallium nitride (GaN) wafers, aluminum nitride (AlN) wafers, and indium nitride (InN) wafers are used (e.g., Patent Document 1).

[0004] The semiconductor substrate has a first surface and a second surface. When the first surface is designated as the main surface and the second surface as the back surface, the main surface is usually mirror-finished. On the other hand, the back surface is either mirror-finished or rough-finished depending on the application (e.g., Patent Documents 2-4).

[0005] When the back is mirror-finished, both the front and back surfaces are mirrored, making it difficult to distinguish between them with the naked eye. Therefore, in addition to forming the usual orientation flat, a sub-orientation flat is also formed, allowing the front and back surfaces to be distinguished by visual inspection.

[0006] However, if a sub-orientation flat is formed in addition to the usual orientation flat, the effective area of ​​the semiconductor substrate (the area available for device fabrication) is reduced.

[0007] Furthermore, in the automated manufacturing process of semiconductor substrates, optical sensors are used to detect the ends of the semiconductor substrate. In this case, if the semiconductor substrate is transparent and the back side has undergone mirror finishing, the following problem arises: the measuring light essentially passes through the semiconductor substrate. Therefore, the change between the amount of light output from the light source and the amount of light input to the detector is very small, and sometimes the optical sensor cannot detect it. As a result, detection errors at the ends of the semiconductor substrate are likely to occur, and the automated manufacturing process will stop.

[0008] On the other hand, when the back side undergoes roughing and finishing, it is easy to distinguish the main surface from the back side by visual inspection, and the detection errors at the optical sensor detection end, as mentioned above, are less likely to occur. However, this leads to a problem where the entire substrate is prone to warping. This is believed to be because the physical surface conditions of the main surface and the back side are different (e.g., Patent Documents 3 and 4). When using semiconductor substrates to fabricate various devices, from the viewpoint of suppressing malfunctions in the manufacturing process equipment, the less warping, the better. Here, malfunctions can be exemplified by: film thickness deviations in the film deposition equipment, focus shifts in the exposure equipment for semiconductor circuits, and poor adhesion in the transfer equipment.

[0009] Existing technical documents

[0010] Patent documents

[0011] Patent Document 1: Japanese Patent Application Publication No. 2005-263609

[0012] Patent Document 2: Japanese Patent Application Publication No. 2007-153712

[0013] Patent Document 3: Japanese Patent Application Publication No. 2007-297263

[0014] Patent Document 4: Japanese Patent No. 5796642 Summary of the Invention

[0015] The objective of this invention is to provide a group III element nitride semiconductor substrate having a first surface and a second surface, which are easily distinguishable by visual observation and whose ends are easily detected by an optical sensor, thereby ensuring a large effective area (the area that can be used to fabricate devices) and reducing the warpage of the entire substrate.

[0016] To address the challenges of this invention, a novel substrate design, unprecedented in previous designs, is required for a Group III nitride semiconductor substrate having a first surface and a second surface. When the first surface is designated as the main surface and the second surface as the back surface, to reduce warpage, designs are considered that make the physical surface conditions of the main surface and the back surface as similar as possible; specifically, designs where both the main surface and the back surface are mirrored. However, if the back surface is mirrored, detection errors at the optical sensor detection end are prone to occur. Furthermore, even with a design that makes the physical surface conditions of the main surface and the back surface as similar as possible, some distinguishing features need to be provided on the main surface and the back surface to facilitate visual differentiation. Conventionally, sub-orientation flats have been formed as these distinguishing features; however, this reduces the effective area (the area available for device fabrication), therefore, other distinguishing methods are needed.

[0017] The novel substrate design described above was studied, and it was found that: in a group III nitride semiconductor substrate having a first side and a second side, if the first side is set as the main side and the second side is set as the back side, focusing on the outer peripheral area of ​​the back side, only the outer peripheral area of ​​the back side is subjected to non-mirror finishing, resulting in a substrate with mirror finish on both the front and back sides. If such a substrate is used, the above-mentioned problems can be solved, thereby completing the present invention.

[0018] The group III nitride semiconductor substrate involved in the embodiments of the present invention is a group III nitride semiconductor substrate having a first side and a second side, wherein,

[0019] The first surface is a mirror.

[0020] The second surface has a central area and a peripheral area.

[0021] The central area of ​​the second surface is mirrored.

[0022] The outer perimeter of the second surface is non-mirror.

[0023] In one embodiment, the width of the outer peripheral region of the second surface is 5 mm or less.

[0024] In one embodiment, the width of the outer peripheral region of the second surface is 3 mm or less.

[0025] In one embodiment, the width of the outer peripheral region of the second surface is less than 1 mm.

[0026] In one embodiment, the surface roughness Ra of the outer peripheral region of the second surface is 100 nm or more.

[0027] In one embodiment, the surface roughness Ra of the central region of the second surface is less than 10 nm.

[0028] In one embodiment, the surface roughness Ra of the first surface is less than 1 nm.

[0029] In one embodiment, the outer peripheral region of the second surface is a light-shielding region that attenuates laser light with a wavelength of 650nm by more than 10%.

[0030] In one embodiment, the warpage of the substrate is less than 50 μm.

[0031] In one embodiment, the radius of curvature of the substrate is 30m or more.

[0032] In one embodiment, the group III nitride semiconductor substrate involved in the embodiments of the present invention does not have a secondary positioning edge.

[0033] In one embodiment, the diameter of the group III nitride semiconductor substrate involved in the embodiments of the present invention is 95 mm or more.

[0034] In one embodiment, the diameter of the group III nitride semiconductor substrate involved in the embodiments of the present invention is 145 mm or more.

[0035] Invention Effects

[0036] According to the present invention, a group III element nitride semiconductor substrate is provided, which has a first surface and a second surface. The first surface and the second surface are easily distinguishable by visual observation and the ends are easily detected by optical sensors, thereby ensuring a large effective area and reducing the warpage of the entire substrate. Attached Figure Description

[0037] Figure 1 This is a representative schematic cross-sectional view of a group III element nitride semiconductor substrate involved in the embodiments of the present invention.

[0038] Figure 2 In the diagram, (a) to (d) are group III nitride semiconductor substrates according to embodiments of the present invention, and their ends are... Figure 1 The diagram shows a schematic cross-sectional view of different implementation methods.

[0039] Figure 3 This is a schematic plan view of the group III nitride semiconductor substrate according to the embodiments of the present invention, viewed from the main plane direction.

[0040] Figure 4 This is a schematic plan view of the group III nitride semiconductor substrate according to an embodiment of the present invention, viewed from the back side.

[0041] Figure 5 This is a schematic diagram illustrating a method for manufacturing a group III nitride semiconductor substrate according to an embodiment of the present invention. Detailed Implementation

[0042] When the term "weight" is used in this specification, it can be replaced with "mass," which is the SI unit commonly used to represent quantity.

[0043] Typically, the group III nitride semiconductor substrate involved in the embodiments of the present invention is a self-standing substrate formed by crystallizing group III nitrides. In the description of the present invention, "self-standing substrate" refers to a substrate that will not deform or break due to its own weight during operation and can be operated in the form of a solid. Self-standing substrates can be used as substrates for various semiconductor devices such as light-emitting elements and power control elements.

[0044] Typically, the Group III nitride semiconductor substrate involved in the embodiments of the present invention is wafer-shaped (generally circular). When the Group III nitride semiconductor substrate involved in the embodiments of the present invention is wafer-shaped, its diameter is preferably 20 mm to 310 mm, with representative examples being 25 mm (approximately 1 inch), 45 to 55 mm (approximately 2 inches), 95 to 105 mm (approximately 4 inches), 145 to 155 mm (approximately 6 inches), 195 to 205 mm (approximately 8 inches), and 295 to 305 mm (approximately 12 inches). With such a size, the Group III nitride semiconductor substrate involved in the embodiments of the present invention can be easily applied to the manufacturing process of semiconductor packages. It should be noted that it can be processed into other shapes, such as rectangular shapes, as needed.

[0045] The thickness of the group III nitride semiconductor substrate involved in the embodiments of the present invention (the thickness of the maximum thickness portion when the thickness is not constant) is preferably 300 μm to 1000 μm.

[0046] Representative examples of group III nitrides include gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), or mixtures thereof. A single group III nitride can exist, or there can be two or more.

[0047] Specifically, the nitrides of group III elements are GaN, AlN, InN, and Ga. x Al 1－x N (1>x>0), Ga x In 1－x N(1>x>0), Al x In 1－x N (1>x>0), Ga x Al y In z N (1 > x > 0, 1 > y > 0, x + y + z = 1). These group III nitrides can be doped with various n-type or p-type dopants.

[0048] Representative examples of p-type dopants include beryllium (Be), magnesium (Mg), strontium (Sr), and cadmium (Cd). There can be only one p-type dopant or two or more.

[0049] Representative examples of n-type dopants include silicon (Si), germanium (Ge), tin (Sn), and oxygen (O). There can be only one type of n-type dopant, or there can be two or more types.

[0050] The surface orientation of a group III nitride semiconductor substrate can be a c-plane, a-plane, or a specific crystal plane inclined relative to the c-plane, a-plane, or m-plane. In particular, the effects of the present invention are more pronounced when the surface is set to the c-plane. Examples of specific crystal planes inclined relative to the c-plane, a-plane, or m-plane include so-called semi-polar surfaces such as the {11-22} plane and the {20-21} plane. Furthermore, as a surface orientation, not only are so-called positive planes perpendicular to the c-plane, a-plane, m-plane, or specific crystal planes inclined relative to these planes permissible, but also deflection angles within the range of ±5° are permissible.

[0051] The group III nitride semiconductor substrate involved in the embodiments of the present invention is a group III nitride semiconductor substrate having a first surface and a second surface, wherein the first surface is a mirror surface, the second surface has a central region of the second surface and a peripheral region of the second surface, the central region of the second surface is a mirror surface, and the peripheral region of the second surface is a non-mirror surface.

[0052] In the group III nitride semiconductor substrate according to the embodiments of the present invention, when the first surface is designated as the main surface and the second surface as the back surface, if the surface orientation of the group III nitride semiconductor substrate is c-plane, then the main surface is representative of the group III element polar surface, and the back surface is representative of the nitrogen polar surface. However, depending on the application, various devices are sometimes fabricated on the nitrogen polar surface, so the main surface can be designated as the nitrogen polar surface, or the back surface can be designated as the group III element polar surface. Various devices can be mounted on the main surface, and epitaxial crystal growth is also possible. The back surface is held by a substrate or the like, allowing for the transfer of the group III nitride semiconductor substrate according to the embodiments of the present invention.

[0053] In the description of the group III nitride semiconductor substrate according to the embodiments of the present invention, the first surface is referred to as the main surface and the second surface as the back surface. Therefore, in this specification, "main surface" can be referred to as "first surface" and "main surface" can also be referred to as "main surface"; "back surface" can be referred to as "second surface" and "back surface" can also be referred to as "back surface".

[0054] Figure 1 This is a representative schematic cross-sectional view of a group III element nitride semiconductor substrate involved in the embodiments of the present invention.

[0055] like Figure 1 As shown, in a representative embodiment of the present invention, the group III nitride semiconductor substrate 100 includes a main surface 10, a back surface 20, and a side surface 30, wherein the main surface 10 and the back surface 20 are in a surface and back surface relationship, the main surface 10 has a main surface central region 10a and a main surface outer peripheral region 10b, and the back surface 20 has a back surface central region 20a and a back surface outer peripheral region 20b.

[0056] Figure 1 In the middle, the main surface 10 has a central area 10a and an outer peripheral area 10b. However, it is possible that, unlike this, the main surface does not have a central area and an outer peripheral area.

[0057] It should be noted that the ends of the group III nitride semiconductor substrate involved in the embodiments of the present invention can adopt any suitable shape within the range of not compromising the effects of the present invention. That is, the end cross-sectional shape of the group III nitride semiconductor substrate involved in the embodiments of the present invention is not only... Figure 1 The rectangular shape shown can, for example, be a shape in which both the main face and the back face are chamfered to form a flat surface. Figure 2 (a) can also be a shape with a chamfered curved surface. Figure 2 (b) can also be used to chamfer the main face at only the ends to form a flat surface shape. Figure 2 (c) can also be used to chamfer the back side only at the ends to form a flat surface shape. Figure 2 (d)). Figure 2 In the group III nitride semiconductor substrate 100 of the embodiment of the present invention shown in (a), both the main surface side and the back surface side of the end are chamfered, and a main surface chamfered portion 11 and a back surface chamfered portion 21 are provided. Figure 2 (b) In the embodiment of the present invention shown, the group III nitride semiconductor substrate 100 has a main side chamfer 11 and a back side chamfer 21 that are chamfered into curved surfaces. The curved surfaces converge at the outer periphery and no flat side surfaces remain. Figure 2 (c) The group III nitride semiconductor substrate 100 of the embodiment of the present invention shown has a main surface chamfer 11 and no back surface chamfer. The main surface chamfer 11 is a flat surface, which is inclined relative to the main surface 10, the back surface 20 and the side surface 30. The side surface 30 is a flat surface. Figure 2 (d) The group III nitride semiconductor substrate 100 according to the embodiment of the present invention has a back side chamfer 21, while the main surface does not have a main surface chamfer. The back side chamfer 21 is a flat surface, which is inclined relative to the main surface 10, the back side 20, and the side surface 30. The side surface 30 is also a flat surface. Of course, the ends of the group III nitride semiconductor substrate according to the embodiment of the present invention are not limited to... Figure 2 (a) ~ Figure 2 The shape shown in (d).

[0058] The chamfered portion 11 on the main surface can be provided throughout the entire outer periphery region 10b of the main surface (the entire circumference), or it can be provided only in a part of the outer periphery region 10b of the main surface. From the viewpoint of suppressing notches in the semiconductor substrate, it is preferable to provide the chamfered portion 11 on the main surface throughout the entire outer periphery region 10b of the main surface (the entire circumference).

[0059] The back-side chamfer 21 can be provided on the entire back-side outer periphery region 20b (the entire circumference), or it can be provided only on a part of the back-side outer periphery region 20b. From the viewpoint of suppressing semiconductor substrate notches, it is preferable to provide the back-side chamfer 21 on the entire back-side outer periphery region 20b (the entire circumference).

[0060] In the group III nitride semiconductor substrates described in the embodiments of the present invention, the main surface is a mirror surface. That is, as shown... Figure 1 As shown, when the main surface 10 has a central region 10a and an outer peripheral region 10b, both the central region 10a and the outer peripheral region 10b are mirror surfaces.

[0061] In the group III nitride semiconductor substrate described in the embodiments of the present invention, the back side has a central region and an outer peripheral region, wherein the central region is mirrored and the outer peripheral region is non-mirrored. That is, Figure 1 In the middle, the central area 20a on the back is mirrored, and the outer peripheral area 20b on the back is non-mirrored.

[0062] The group III nitride semiconductor substrates involved in the embodiments of the present invention are, for example, such as... Figure 2 In the cases shown in (a), (b), and (d), where the back side chamfer is flat, the back side chamfer can be aligned with the outer periphery of the back side. That is, Figure 2 In (a), (b), and (d), the chamfered portion 21 on the back side can be consistent with the outer peripheral region 20b on the back side. In this case, since the outer peripheral region 20b on the back side is non-mirror, the chamfered portion 21 on the back side is also non-mirror.

[0063] As described above, in the group III nitride semiconductor substrate according to the embodiments of the present invention, the main surface is mirrored, the central region of the back surface is mirrored, and the outer peripheral region of the back surface is non-mirrored. That is, for the group III nitride semiconductor substrate according to the embodiments of the present invention, only the outer peripheral region of the back surface is non-mirrored, while the others are mirrored. The group III nitride semiconductor substrate according to the embodiments of the present invention is a group III nitride semiconductor substrate with mirrored surfaces on both the front and back surfaces, in which only the outer peripheral region of the back surface has been non-mirrored. This makes it easy to distinguish the main surface and the back surface by visual inspection, easy to detect the ends by optical sensors, and reduces the warpage of the entire substrate. In addition, since the main surface and the back surface are easily distinguishable by visual inspection, it is not necessary to form a sub-orientation flat, which ensures a larger effective area of ​​the semiconductor substrate (the area that can be used to fabricate devices).

[0064] A mirror finish refers to a surface that has undergone mirror polishing. After mirror polishing, the surface roughness and undulations are reduced to a level where light reflection is so strong that an object's reflection can be visually observed and confirmed. In other words, the roughness and undulations of the mirror-polished surface are reduced to a level that is negligible relative to the wavelength of visible light. Epitaxial crystal growth can then proceed sufficiently on a mirror-polished surface.

[0065] As a method for mirror finishing, any suitable method can be employed within the scope of not compromising the effects of the present invention. Examples of such methods include: mirror finishing using one or a combination of a grinding apparatus using a grinding belt, a fine grinding apparatus using diamond abrasive grains, and a CMP (Chemical Mechanical Polish) apparatus using a slurry such as colloidal silica and a non-woven abrasive pad.

[0066] Non-mirror surfaces are those that have not undergone mirror finishing; a typical example is a rough surface obtained through roughening.

[0067] As a method for roughening the surface, any suitable method can be employed within the scope of not compromising the effects of the present invention. Examples of such methods include: laser texturing, etching using various chemicals and gases, physical or chemical coating, and texturing using mechanical processing.

[0068] The surface roughness Ra of the outer peripheral region of the back side is preferably 100 nm or more, more preferably 200 nm to 1500 nm, and even more preferably 500 nm to 1000 nm. By adjusting the surface roughness Ra of the outer peripheral region of the back side to the above range, it is easier to distinguish the main surface and the back side by visual observation, and it is easier to detect the end by optical sensors. However, if the surface roughness Ra of the outer peripheral region of the back side is too large, the damage to the semiconductor substrate will increase, becoming a cause of cracks, which is undesirable.

[0069] The surface roughness Ra of the central region on the back side is preferably less than 10 nm, more preferably 0.1 nm to 2 nm, even more preferably 0.1 nm to 1 nm, and particularly preferably 0.1 nm to 0.5 nm. By adjusting the surface roughness Ra of the central region on the back side to the above range, it is easier to distinguish the main surface and the back side by visual observation, easier to detect the end by optical sensors, and also to suppress warping of the semiconductor substrate.

[0070] The surface roughness Ra of the main surface is preferably less than 2 nm, more preferably less than 1 nm, further preferably 0.1 nm to 0.5 nm, and particularly preferably 0.1 nm to 0.2 nm. By adjusting the surface roughness Ra of the main surface to the above range, it is easier to distinguish the main surface and the back surface by visual observation, and it is easier to detect the end by optical sensors.

[0071] In embodiments of the present invention, the physical surface states of the main and back surfaces of the group III nitride semiconductor substrate are similar. Therefore, the warpage of this substrate is small, preferably less than 50 μm, more preferably less than 40 μm, and even more preferably less than 30 μm. If the warpage of the substrate is greater than 50 μm, manufacturing defects may sometimes occur when using the semiconductor substrate to fabricate various devices due to film thickness deviations in the film deposition apparatus or focus offsets in the exposure apparatus for semiconductor circuits.

[0072] In the embodiments of the present invention, the physical surface states of the main and back surfaces of the group III nitride semiconductor substrate are similar. Therefore, the warpage of the substrate is small, and the radius of curvature is preferably 30 m or more, more preferably 50 m or more, further preferably 70 m or more, and particularly preferably 100 m or more. If the radius of curvature is less than 30 m, when using the semiconductor substrate to manufacture various devices, it is sometimes impossible to fix the substrate by adsorption inside the process equipment or on the transport equipment, resulting in manufacturing defects due to substrate detachment, etc.

[0073] The group III nitride semiconductor substrates involved in the embodiments of the present invention are easily distinguishable from the back side by visual inspection. Therefore, it is not necessary to form a sub-orientation flat, which ensures a large effective area of ​​the semiconductor substrate (the area that can be used to fabricate devices). That is, the group III nitride semiconductor substrates involved in the embodiments of the present invention preferably do not have a sub-orientation flat.

[0074] Figure 3 This is a schematic plan view of the group III nitride semiconductor substrate according to the embodiments of the present invention, viewed from the main plane direction.

[0075] like Figure 3 As shown, a chamfered portion 11 can be provided on the main surface. Typically, the chamfered portion 11 is a region provided in the outer peripheral region 10b of the main surface, extending from the outer peripheral end 12 towards the inner side of the main surface 10 to a distance of width D1. The width D1 of the chamfered portion is the distance from the outer peripheral end 12, and is the distance in the normal direction of the tangent at the outer peripheral end 12 in the direction towards the inner side of the main surface 10. Preferably, the width D1 of the chamfered portion is constant throughout the entire chamfered portion 11.

[0076] Figure 4 This is a schematic plan view of the group III nitride semiconductor substrate according to an embodiment of the present invention, viewed from the back side.

[0077] like Figure 4 As shown, a back-side chamfer 21 may be provided on the back side. Typically, the back-side chamfer 21 is a region provided in the outer peripheral region 20b of the back side, extending from the outer peripheral end 22 towards the inner side of the back side 10 to a distance of width D2. The width D2 of the back-side chamfer is the distance from the outer peripheral end 22, and is the distance in the normal direction of the tangent at the outer peripheral end 22 in the direction towards the inner side of the back side 20. Preferably, the width D2 of the back-side chamfer is constant throughout the entire back-side chamfer 21.

[0078] like Figure 4 As shown, typically, the outer peripheral region 20b of the back surface is: the region extending from the outer peripheral end 22 towards the inner side of the back surface 20 when viewed from a planar direction, up to a distance of width d2. Figure 4 As shown, the width d2 of the outer periphery region of the back surface is the distance from the outer periphery end 22, and is the distance in the normal direction of the tangent at the outer periphery end 22 in the direction towards the inner side of the back surface 20. The width d2 of the outer periphery region of the back surface is preferably constant throughout the entire outer periphery region 20b of the back surface.

[0079] The width d2 of the outer peripheral region of the back side can be any suitable size within the range that does not impair the effects of the present invention, such as the size of the group III nitride semiconductor substrate involved in the embodiments of the present invention. In terms of further demonstrating the effects of the present invention, the width d2 of the outer peripheral region of the back side is preferably 5 mm or less, more preferably 3 mm or less, and even more preferably 1 mm or less. In terms of further demonstrating the effects of the present invention, the lower limit of the width d2 of the outer peripheral region of the back side is preferably 0.2 mm or more, more preferably 0.5 mm or more.

[0080] In the group III nitride semiconductor substrates described in the embodiments of the present invention, the back-side chamfer can coincide with the outer peripheral region of the back side. For example, Figure 4 In this case, the chamfered portion 21 on the back side can be aligned with the outer peripheral region 20b on the back side. Figure 4 In the middle, the width D2 of the chamfered part on the back side is the same as the width d2 of the outer peripheral area on the back side.

[0081] In the group III nitride semiconductor substrate according to the embodiments of the present invention, the outer peripheral region 20b of the back side is preferably a light-shielding region that attenuates laser light in the range of 450 nm to 1100 nm. Because the outer peripheral region 20b of the back side is a light-shielding region that attenuates laser light in the range of 450 nm to 1100 nm, the main surface and the back side can be easily distinguished by visual observation, and the end can be easily detected by an optical sensor. In the group III nitride semiconductor substrate according to the embodiments of the present invention, the outer peripheral region 20b of the back side is more preferably a light-shielding region that attenuates laser light with a wavelength of 650 nm by more than 10%.

[0082] In embodiments of the present invention, the warpage of the group III nitride semiconductor substrate is preferably 50 μm or less. The measurement of warpage will be described below.

[0083] The radius of curvature of the group III nitride semiconductor substrate involved in the embodiments of the present invention is preferably 30 m or more, more preferably 40 m or more, and even more preferably 50 m or more. The measurement of the radius of curvature will be described below.

[0084] The group III nitride semiconductor substrates involved in the embodiments of the present invention can be fabricated using any suitable method within the scope of not compromising the effects of the present invention.

[0085] For the group III nitride semiconductor substrates involved in the embodiments of the present invention, typically, such as Figure 5As shown in (a), a seed film 2 is formed on the main surface 1a of the substrate 1, and a group III element nitride layer 3 is formed on the group III element polar surface 2a of the seed film 2. Next, the group III element nitride layer (seed film 2 + group III element nitride layer 3), which will become a self-standing substrate, is separated from the substrate 1 to obtain a self-standing substrate 100' having a main surface 10' and a back surface 20'. The group III element nitride layer can be separated by laser ablation from the back surface 1b side of the substrate 1, as shown by arrow A, using a laser lift-off method. Figure 5 (b) shows the self-standing substrate 100'. Alternatively, the self-standing substrate 100' can be obtained by spontaneous separation using the difference in thermal shrinkage during cooling after the formation of the III element nitride layer 3, or by slicing the III element nitride layer 3 using a wire saw or the like.

[0086] The substrate material can be any suitable material without compromising the effects of the present invention. Examples of suitable materials include: sapphire, crystalline oriented alumina, gallium oxide, and Al. x Ga 1－x N (0≤x≤1), GaAs, SiC.

[0087] As the material for the seed film, any suitable material can be used within the range that does not impair the effects of the present invention. Examples of such materials include: Al. x Ga 1－x N (0 ≤ x ≤ 1), In x Ga 1－x N (0≤x≤1), preferably gallium nitride. As the material for the seed film, gallium nitride that can be confirmed by fluorescence microscopy to produce a yellow emission effect is more preferred. Yellow emission refers to a peak (yellow emission (YL) or yellow band (YB)) appearing in the range of 2.2 to 2.5 eV, excluding the exciton transitions from the band to the band (UV).

[0088] As a method for forming the seed film, any suitable method can be used within the range that does not impair the effects of the present invention. Examples of such methods include vapor phase growth, with preferred methods including: Metal-Organic Chemical Vapor Deposition (MOCVD), Hydride Vapor Phase Growth (HVPE), Pulse Excitation Deposition (PXD), MBE, and sublimation. Among these methods, Metal-Organic Chemical Vapor Deposition (MOCVD) is more preferred. The growth temperature is preferably 950–1200°C.

[0089] As the cultivation direction for crystallizing group III element nitrides, any suitable cultivation direction can be adopted within the scope of not compromising the effects of the present invention. Examples of such cultivation directions include: the normal direction of the c-plane of the wurtzite structure, the normal directions of the a-plane and m-plane, and the normal directions of the planes inclined relative to the c-plane, a-plane, and m-plane, respectively.

[0090] As for the preparation of the group III element nitride layer, any suitable preparation method can be adopted within the scope of not compromising the effects of the present invention. Examples of such preparation methods include: metal-organic chemical vapor deposition (MOCVD), hydride vapor deposition (HVPE), pulse-induced deposition (PXD), MBE, sublimation, and other gas-phase methods; and ammonothermal methods, flux methods, and other liquid-phase methods.

[0091] Next, the outer periphery of the self-supporting substrate is ground to adjust it into a circle of the desired diameter.

[0092] The size of the self-supporting substrate can be any suitable size within the range that does not impair the effects of the present invention. Examples of such sizes include 25 mm (about 1 inch), 45-55 mm (about 2 inches), 95-105 mm (about 4 inches), 145-155 mm (about 6 inches), 195-205 mm (about 8 inches), and 295-305 mm (about 12 inches).

[0093] Next, the nitrogen-polar side of the circular self-standing substrate is attached to the processing platform. During attachment, the wax thickness is changed by adjusting the load applied to the self-standing substrate, or a tool is clamped between the self-standing substrate and the processing platform, thereby changing the surface shape of the self-standing substrate.

[0094] Next, the polar surfaces of group III elements are removed through grinding, fine grinding, and lapping processes, thereby thinning the substrate to the desired thickness and flattening the surface of the polar surfaces of group III elements, resulting in a self-standing substrate with mirror-finished polar surfaces of group III elements.

[0095] Next, the group III element polar facet of the self-standing substrate, which has been mirrored, is attached to the processing platform. During attachment, the wax thickness is changed by adjusting the load applied to the self-standing substrate, or a tool is clamped between the self-standing substrate and the processing platform, thereby changing the surface shape of the self-standing substrate.

[0096] Next, the nitrogen polar surface is removed through grinding, fine lapping, and polishing processes, thereby thinning the substrate to the desired thickness and planarizing the surface of the nitrogen polar surface, resulting in a self-standing substrate with a mirror-finished nitrogen polar surface. It should be noted that in this embodiment, the nitrogen polar surface is mirror-finished after the group III element polar surface is mirror-finished; however, the order can be reversed.

[0097] The thickness of the self-standing substrate after grinding (the thickness of the thickest part when the thickness is not constant) is preferably 300μm to 1000μm.

[0098] Next, the outer periphery of the self-standing substrate is chamfered by grinding, and finally, the group III nitride semiconductor substrate 100 involved in the embodiments of the present invention is obtained.

[0099] In the group III nitride semiconductor substrates involved in the embodiments of the present invention, chamfering can be performed using any suitable chamfering method within the scope of not compromising the effects of the present invention. Examples of such chamfering methods include: grinding using diamond grinding stones, grinding using abrasive belts, and CMP (Chemical Mechanical Polishing) using a slurry such as colloidal silica and a nonwoven abrasive pad.

[0100] Next, a roughening process is performed on the outer periphery of the nitrogen polar surface, and finally, the group III element nitride semiconductor substrate 100 according to the embodiments of the present invention is obtained.

[0101] As a method for roughening the surface, any suitable method can be employed within the scope of not compromising the effects of the present invention. Examples of such methods include: laser texturing, etching treatment using various chemicals or gases, physical or chemical coating treatment, and texturing using mechanical processing.

[0102] The obtained group III nitride semiconductor substrate 100 allows for epitaxial growth of crystals on its main surface (group III polar surface) 10, such as... Figure 5 As shown in (c), the functional layer 4 is deposited to obtain the functional element 5. 20 is the back side (nitrogen polar side).

[0103] It should be noted that if the warpage of the main face (the polar face of group III elements) differs from that of the back face (the polar face of nitrogen), a total thickness variation (TTV) occurs on the self-contained substrate. However, even with this thickness variation, the main face (the polar face of group III elements) will not exhibit a significant distribution during the epitaxial growth of the functional layer on the self-contained substrate. This is because the high thermal conductivity of the group III nitride crystals constituting the self-contained substrate is utilized. As a result, no morphological anomalies occur during functional layer deposition, and deviations in emission wavelength and voltage-current characteristics are effectively suppressed.

[0104] Examples of epitaxial crystals grown on a obtained group III element nitride semiconductor substrate include gallium nitride, aluminum nitride, indium nitride, or mixtures thereof. Specifically, examples of such epitaxial crystals include GaN, AlN, InN, and Ga... x Al 1－x N (1>x>0), Ga x In 1－x N(1>x>0), Al x In 1－x N (1>x>0), Ga x Al y In z N (1 > x > 0, 1 > y > 0, x + y + z = 1). In addition to the light-emitting layer, functional layers disposed on the obtained group III nitride semiconductor substrate can include rectifier layers, switching elements, power semiconductor layers, etc. Furthermore, after disposing of the functional layer on the group III polar surface of the obtained group III nitride semiconductor substrate, processing the nitrogen polar surface, such as grinding or polishing, can also reduce the thickness and thickness distribution of the self-contained substrate.

[0105] Example

[0106] The present invention will now be specifically described through examples; however, the present invention is not limited to these examples in any way. It should be noted that the testing and evaluation methods in the examples are as follows. It should be noted that when a quantity is described as "parts," unless otherwise specified, it refers to "parts by weight"; when a quantity is described as "%," unless otherwise specified, it refers to "% by weight."

[0107] <Determination of Surface Roughness Ra>

[0108] For the surface of a group III nitride semiconductor self-standing substrate, a non-contact surface shape measuring instrument (Zygo, New View 7000, 5x objective lens, MetroPro 9.0.10 software) was used to calculate the surface roughness (arithmetic mean roughness) Ra with an observation field of 1.4 mm × 1.05 mm. Ra was measured at the center of the substrate's main surface and the central region of the back surface. With the width of the outer peripheral region of the back surface set as d2, Ra was measured at a position equivalent to d2 / 2 from the boundary between the central region and the outer peripheral region of the back surface. When the width d2 of the outer peripheral region of the back surface was narrower than the 1.4 mm × 1.05 mm observation field, the observation field was appropriately narrowed before measurement.

[0109] <Evaluation criteria for distinguishing the front and back by visual inspection>

[0110] Using a white fluorescent lamp as the light source, and in an indoor environment with a luminous intensity of 817–893 LX, the front and back surfaces of the wafer were distinguished by naked-eye observation. A YOKOGAWA 510LUX METER was used as the photometer. The entire mirrored surface was designated as the front surface, and the non-mirrored outer periphery was designated as the back surface. Situations where the wafer could be distinguished without special observation were categorized as "easy," situations where it could be distinguished with observation were categorized as "able," and situations where it could not be clearly distinguished even with observation were categorized as "difficult." Here, "observation" refers to observing for more than 10 seconds while changing the angle.

[0111] <Evaluation Criteria for Detecting End Units Using Optical Sensors>

[0112] A transmissive photoelectric sensor was used to perform detection tests on the substrate edge. An Omron ZX-GT28S (wavelength 650nm) light source and detector were used. The binarization level of the measured values ​​was set to 50%, and the attenuation rate at 650nm was evaluated. It should be noted that a laser power sensor (Ophiropt 3A) was used to confirm that the transmissive photoelectric sensor could achieve the required laser intensity at the edge.

[0113] 〇: Able to attenuate laser light with a wavelength of 650nm by more than 10% (sensor judgment: pass).

[0114] ×: Unable to attenuate 650nm laser wavelength by more than 10% (sensor judgment: failing).

[0115] <Determination of Warpage>

[0116] The warpage of the main surface is measured, and the radius of curvature is calculated based on the warpage. A laser displacement meter can be used to measure the warpage. A laser displacement meter is a device that measures the displacement of each surface by irradiating it with a laser beam. With the laser wavelength set to 655nm, the measurement method can be determined based on the surface roughness, using confocal measurement, triangulation, or optical interference.

[0117] Excluding a 3mm width range measured from the substrate end, the waveform was obtained. Next, an approximate curve for this waveform was obtained using the least squares method of a quadratic function. The difference between the highest and lowest values ​​of this approximate curve was measured on the substrate surface along two orthogonal axes, and the average of the two values ​​was set as the warp S. Furthermore, based on this warp value, the radius of curvature R was calculated using the following formula. D is the substrate diameter.

[0118] R=D 2 / (8·S)

[0119] (The units for radius of curvature R, substrate diameter D, and warpage S here are [m].)

[0120] [Example 1]

[0121] A 2μm thick gallium nitride film is formed on a 6-inch c-plane sapphire wafer using the MOCVD method to create a seed substrate.

[0122] The seed substrate was placed in an alumina crucible with a diameter of 200 mm inside a glove box under a nitrogen atmosphere. Next, metallic gallium and metallic sodium were filled into the crucible at a ratio of Ga / Ga+Na (mol%) = 15 mol%, and the crucible was covered with an alumina plate. The crucible was placed in a stainless steel inner container, and then placed in a stainless steel outer container to accommodate it, and the container was closed with a lid attached to a nitrogen inlet tube. The outer container was placed on a rotating stage in the heating section of a pre-vacuum-baked crystallization apparatus, and the pressure vessel was sealed with a lid.

[0123] Next, the pressure vessel was evacuated to below 0.1 Pa using a vacuum pump. Then, the upper, middle, and lower heaters were adjusted to heat the heating space to 870°C, while simultaneously introducing nitrogen gas from a nitrogen cylinder to 4.0 MPa, causing the outer container to rotate clockwise and counterclockwise around its central axis at a speed of 20 rpm in a specific cycle. This state was maintained for 40 hours. Afterward, it was allowed to cool naturally to room temperature, and the pressure was reduced to atmospheric pressure. The lid of the pressure vessel was then opened, and the crucible was removed. The solidified metallic sodium in the crucible was removed, and the gallium nitride crystal grown on the seed substrate was recovered.

[0124] Ultraviolet laser light is irradiated from the sapphire wafer side, thereby decomposing the gallium nitride crystal on the seed substrate and separating the grown gallium nitride crystal from the sapphire wafer. The warpage of the separated gallium nitride crystal is 50 μm.

[0125] Using a diamond grinding wheel, the outer periphery of the gallium nitride crystal was ground to adjust the diameter to 150mm.

[0126] Next, gallium nitride crystals were bonded to a ceramic processing platform, and the Ga polar surface was ground and polished using a grinding and finishing device. Finally, a mirror finish was achieved using diamond abrasive grains with a diameter of 0.1 μm.

[0127] The gallium nitride crystal was then fixed onto a ceramic machining platform, and the nitrogen polar surface was similarly ground and polished. A final mirror finish was achieved using diamond abrasive grains with a diameter of 0.1 μm.

[0128] Protective materials are applied to the surface and back of the gallium nitride (GaN) crystal. A beveling apparatus is used to shape the outer periphery of the wafer. For the Ga polar facet, a tilted grinding stone (20-degree angle) is used for chamfering. The chamfer width D1 is set to 150 μm. For the Nitrogen polar facet, laser texturing is used to roughen the outer periphery. A 355 nm wavelength, 3 W output ultraviolet laser is used to scan and focus the laser beam onto a 70 μm diameter area, thereby creating a textured surface on the outer periphery. The roughening area d2 is set to 3 mm from the outer periphery.

[0129] The surface and back sides of the obtained group III element nitride semiconductor wafer can be easily distinguished by visual inspection. In addition, the warpage of the wafer is 40 μm.

[0130] The results are shown in Table 1.

[0131] [Example 2]

[0132] The back-side roughening process, d2, was set to 5 mm from the outer perimeter. Otherwise, the process was performed in the same manner as in Example 1 to fabricate a Group III nitride semiconductor wafer. The surface and back sides of the resulting Group III nitride semiconductor wafer were easily distinguishable by visual inspection. Furthermore, the wafer warpage was 48 μm.

[0133] The results are shown in Table 1.

[0134] [Example 3]

[0135] The back-side roughening process, d2, was set to 1 mm from the outer perimeter. Otherwise, the process was performed in the same manner as in Example 1 to fabricate a Group III nitride semiconductor wafer. The surface and back sides of the resulting Group III nitride semiconductor wafer were distinguishable by visual inspection. Furthermore, the wafer warpage was 28 μm.

[0136] The results are shown in Table 1.

[0137] [Comparative Example 1]

[0138] The back side was roughened and finished, and otherwise the process was carried out in the same manner as in Example 1 to fabricate a Group III nitride semiconductor wafer. The surface and back side of the resulting Group III nitride semiconductor wafer could be easily distinguished by visual inspection. Furthermore, the wafer warpage was 105 μm.

[0139] The results are shown in Table 1.

[0140] [Comparative Example 2]

[0141] The back-side roughening process, d2, was set to 10 mm from the outer perimeter. Otherwise, the process was performed in the same manner as in Example 1 to fabricate a Group III nitride semiconductor wafer. The surface and back sides of the resulting Group III nitride semiconductor wafer were easily distinguishable by visual inspection. Furthermore, the wafer warpage was 59 μm.

[0142] The results are shown in Table 1.

[0143] [Comparative Example 3]

[0144] The entire back side was mirror-finished, and otherwise the process was performed in the same manner as in Example 1 to fabricate a group III nitride semiconductor wafer. The surface and back side of the resulting group III nitride semiconductor wafer were indistinguishable to the naked eye. Furthermore, the wafer warpage was 21 μm.

[0145] The results are shown in Table 1.

[0146] [Table 1]

[0147]

[0148] Industrial availability

[0149] The group III nitride semiconductor substrates involved in the embodiments of the present invention can be used as substrates for various semiconductor devices.

[0150] Symbol Explanation

[0151] 100 Group III nitride semiconductor substrates

[0152] 100' free standing baseboard

[0153] 1. Substrate

[0154] 1a Main surface of substrate 1

[0155] 1b Back side of substrate 1

[0156] 2. Seed film

[0157] 2a Group III element polar surface of seed film 2

[0158] 3 Group III nitride layers

[0159] 4. Functional Layer

[0160] 5 Functional Components

[0161] 10 Main side

[0162] 10' Main side

[0163] 10a Main surface central area

[0164] 10b Main surface outer perimeter area

[0165] 11. Beveled edge of the main face

[0166] 12. Outer peripheral end

[0167] 20 Back

[0168] 20' Back

[0169] 20a Central area on the back

[0170] 20b Reverse outer perimeter area

[0171] 21. Back side chamfer

[0172] 22. Outer peripheral end

[0173] 30 Side View

Claims

1. A group III element nitride semiconductor substrate, having a first surface and a second surface, The characteristic of the group III nitride semiconductor substrate is that... The first surface is a mirror. The second surface has a central area and a peripheral area. The central area of ​​the second surface is mirrored. The outer perimeter of the second surface is non-mirror.

2. The group III nitride semiconductor substrate according to claim 1, characterized in that, The width of the outer peripheral region of the second surface is less than 5 mm.

3. The group III nitride semiconductor substrate according to claim 2, characterized in that, The width of the outer peripheral region of the second surface is less than 3 mm.

4. The group III nitride semiconductor substrate according to claim 3, characterized in that, The width of the outer periphery of the second surface is less than 1 mm.

5. The group III nitride semiconductor substrate according to any one of claims 1 to 4, characterized in that, The surface roughness Ra of the outer peripheral region of the second surface is above 100 nm.

6. The group III nitride semiconductor substrate according to any one of claims 1 to 5, characterized in that, The surface roughness Ra of the central region of the second surface is less than 10 nm.

7. The group III nitride semiconductor substrate according to any one of claims 1 to 6, characterized in that, The surface roughness Ra of the first surface is less than 1 nm.

8. The group III nitride semiconductor substrate according to any one of claims 1 to 7, characterized in that, The outer peripheral region of the second surface is a light-shielding area that attenuates laser light with a wavelength of 650nm by more than 10%.

9. The group III nitride semiconductor substrate according to any one of claims 1 to 8, characterized in that, The warpage of the substrate is less than 50 μm.

10. The group III nitride semiconductor substrate according to any one of claims 1 to 9, characterized in that, The radius of curvature of the substrate is 30m or more.

11. The group III nitride semiconductor substrate according to any one of claims 1 to 10, characterized in that, It does not have a secondary positioning edge.

12. The group III nitride semiconductor substrate according to any one of claims 1 to 11, characterized in that, The diameter is 95mm or more.

13. The group III nitride semiconductor substrate according to any one of claims 1 to 12, characterized in that, The diameter is 145mm or more.

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