Method and apparatus for handling chip test limits
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI OPTICAL COMMUNICATIONS CORP
- Filing Date
- 2024-11-27
- Publication Date
- 2026-05-29
Smart Images
Figure CN122109774A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing, and in particular to a method and apparatus for processing chip testing limits. Background Technology
[0002] For chip quality testing, Automatic Test Equipment (ATE) can be used to perform parameter testing on the chip. The parameter testing process mainly involves comparing the chip's tested parameters with the corresponding limit values to determine whether the chip is a qualified product.
[0003] In the prior art, a fixed test limit value corresponding to the tested parameter is obtained by fitting the chip parameter test results to a normal distribution or a log-normal distribution, and the chip is then judged to be qualified by using the fixed test limit value.
[0004] However, chips exhibit varying operating efficiencies at different turn-on voltages, leading to significant fluctuations in the measured parameters under different operating efficiencies. Therefore, simply setting a fixed test limit to determine chip quality has the drawback of either rejecting qualified products or allowing unqualified products to pass the test. Summary of the Invention
[0005] In a first aspect, this application provides a method for processing chip test limits, the method being applied to a computer device, comprising:
[0006] Obtain test values corresponding to multiple test parameters of multiple chips under test;
[0007] Based on the multiple measured parameters, a parameter coordinate system is constructed;
[0008] The test value is added to the parameter coordinate system to obtain the first fitted data point in the parameter coordinate system;
[0009] The first fitted data points are preprocessed to obtain a second fitted data point that meets preset conditions;
[0010] Perform data fitting processing on all the second fitted data points to generate a first relationship line of the measured parameter in the parameter coordinate system;
[0011] The first relational line is moved in the coordinate system according to a preset method to obtain a second relational line in the coordinate system for the test limit value of the measured parameter.
[0012] Output the second relationship line.
[0013] In one possible implementation, the preprocessing of the first fitted data points to obtain second fitted data points that meet preset conditions further includes:
[0014] Obtain the theoretical upper limit value for each measured parameter;
[0015] Each coordinate value of each first fitted data point is compared with the theoretical upper limit value of the corresponding measured parameter, where the coordinate value is the test value of the corresponding measured parameter.
[0016] In response to the fact that at least one coordinate value of the first fitted data point is greater than the theoretical upper limit value of the corresponding measured parameter, the first fitted data point is deleted from the parameter coordinate system;
[0017] In response to the fact that all coordinate values of the first fitted data point are less than or equal to the theoretical upper limit value of the corresponding measured parameter, the first fitted data point is retained in the parameter coordinate system;
[0018] Each first fitted data point retained in the parameter coordinate system is used as a second fitted data point that meets the preset conditions.
[0019] In one possible implementation, the step of performing data fitting processing on all the second fitted data points to generate a first relationship line of the measured parameter in the parametric coordinate system further includes:
[0020] Determine the expected value, slope, and preset random variables of the regression line corresponding to all processed fitted data points;
[0021] The first measured parameter is taken as the dependent variable, and the remaining measured parameters are taken as independent variables.
[0022] The product of each independent variable and the slope is obtained respectively, and the sum of each product and the expected value and the random variable is used as the dependent variable to obtain the first relationship equation of the measured parameter;
[0023] The first relational equation is fitted to the data in the parameter coordinate system to generate the first relational line of the measured parameter.
[0024] In one possible implementation, the second relational line, which moves the first relational line in the coordinate system according to a preset method to obtain the test limit value of the measured parameter in the coordinate system, further includes:
[0025] Obtain the standard deviation of the test value of the first measured parameter corresponding to each second fitted data point;
[0026] Add the first relational equation to a preset multiple of the standard deviation to obtain a second relational equation for the test limit of the measured parameter;
[0027] The second relational equation is fitted to the parameter coordinate system to obtain a second relational line for the test limit of the measured parameter.
[0028] In one possible implementation, the output of the second relational line further includes:
[0029] The relationship line of the test limit is sent to the test equipment so that the test equipment can determine whether the chip under test is qualified based on the second relationship line and generate a judgment result.
[0030] In one possible implementation, the method further includes:
[0031] Obtain the judgment result;
[0032] Based on the judgment results, obtain the product information for each damaged chip;
[0033] The product information of the damaged chip is sent to the user terminal to identify the damaged chip.
[0034] Secondly, this application provides an electronic device, comprising:
[0035] Memory stores the instructions executed by the computer;
[0036] The processor is configured to execute computer execution instructions stored in the memory, causing the electronic device to perform the method described above.
[0037] Thirdly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method described above. Attached Figure Description
[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0039] Figure 1 This is a schematic diagram of a scenario using existing technologies;
[0040] Figure 2 This is a schematic diagram of a scenario corresponding to an embodiment of this application;
[0041] Figure 3 A flowchart illustrating the chip test limit processing method provided in this application. Figure 1 ;
[0042] Figure 4 A flowchart illustrating the chip test limit processing method provided in this application. Figure 2 ;
[0043] Figure 5 A flowchart illustrating the chip test limit processing method provided in this application. Figure 3 ;
[0044] Figure 6 A schematic diagram of the first relationship line of the measured parameters as an example;
[0045] Figure 7 A flowchart illustrating the chip test limit processing method provided in this application. Figure 4 ;
[0046] Figure 8 A schematic diagram of the second relationship line for example test limits;
[0047] Figure 9 A flowchart illustrating the chip test limit processing method provided in this application. Figure 5 ;
[0048] Figure 10 A schematic diagram of the structure of the electronic device provided in this application.
[0049] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0050] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.
[0051] Figure 1 This is a schematic diagram of a scenario using existing technologies, such as... Figure 1 As shown in the schematic diagram of this application, the scenario includes ① a computer device, an automatic testing device, and a chip under test. The computer device can be a server, and there can be multiple chips under test. The automatic testing device performs parameter tests on the required parameters of each chip under test to obtain test results. The test results are the test values for each parameter corresponding to each chip under test. The automatic testing device sends the test results to the computer device. The computer device performs normal distribution fitting or log-normal distribution fitting on the test results to obtain a fixed test limit for the measured parameter, and sends the obtained fixed test limit back to the automatic testing device. The automatic testing device determines whether each chip under test is qualified based on the obtained test limit.
[0052] However, chips exhibit varying operating efficiencies at different turn-on voltages, leading to significant fluctuations in the measured parameters under different operating efficiencies. Therefore, simply setting a fixed test limit to determine chip quality has the drawback of either rejecting qualified products or allowing unqualified products to pass the test.
[0053] Figure 2 This is a schematic diagram of a scenario corresponding to an embodiment of this application, such as... Figure 2 As shown in the schematic diagram, the scenario includes ① a computer device, an automatic testing device, and a chip under test. The execution entity of this application embodiment is the computer device shown in the schematic diagram. This application differs from existing technologies in that: the computer device constructs a parameter coordinate system based on test results, adds the test values corresponding to multiple test parameters of each chip under test to the parameter coordinate system, obtains fitting data points corresponding to each chip under test, preprocesses the fitting data points to obtain processed fitting data points that meet preset conditions, performs data fitting processing on all processed fitting data points to generate a relationship line of the test parameters in the parameter coordinate system, moves the relationship line of the test parameters in the coordinate system according to a preset method to obtain a relationship line of the test limit values of the test parameters in the coordinate system, and outputs the second relationship line. The method provided in this application provides a range of test limit relationship lines. These lines are obtained based on the fitting of data points. Therefore, the test limit relationship lines can be adaptively adjusted according to the specific distribution of the fitted data points to obtain appropriate test limits for the fitted data points. Using appropriate test limits to determine whether the chip is qualified can improve the accuracy of determining whether the chip is qualified.
[0054] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.
[0055] Figure 3 A flowchart illustrating the chip test limit processing method provided in this application. Figure 1 ,like Figure 3 As shown, it includes:
[0056] S301. Obtain the test values corresponding to multiple test parameters of multiple chips under test.
[0057] The execution subject of this embodiment is Figure 2 Computer devices in the context can be implemented through computer programs.
[0058] Based on the scenario example, the number of chips under test and the parameters to be tested can be determined according to the actual situation. There must be at least two parameters to be tested, and these parameters are related to the operating performance of the chips under test. Taking two parameters as an example, if the chip under test integrates multiple devices, including a ring oscillator, then the parameter to be tested can be the logarithm of the ring oscillator's frequency and leakage current value.
[0059] S302. Construct a parameter coordinate system based on the multiple measured parameters.
[0060] In a scenario example, if there are two measured parameters, one can be used as one coordinate axis and the other as another to construct a two-dimensional parameter coordinate system. If there are more than two measured parameters, each measured parameter can be used as an axis to construct a multi-dimensional parameter coordinate system. Taking the measured parameters as the frequency of a ring oscillator and the logarithm of the leakage current as an example, the frequency of the ring oscillator can be used as the horizontal axis and the logarithm of the leakage current as the vertical axis to establish a parameter coordinate system.
[0061] S303. Add the test value to the parameter coordinate system to obtain the first fitted data point in the parameter coordinate system.
[0062] Taking a scenario example, using a parameter coordinate system established by the frequency of the ring oscillator and the logarithm of the leakage current as the measured parameters, if the frequency of the ring oscillator is taken as the horizontal axis and the logarithm of the leakage current is taken as the vertical axis, then for each chip under test, the measured value of the frequency of the ring oscillator is taken as the horizontal axis in the parameter coordinate system, and the measured value of the logarithm of the leakage current is taken as the vertical axis in the parameter coordinate system. This yields the fitted data point of each chip under test in the parameter coordinate system, which can be taken as the first fitted data point.
[0063] S304. Preprocess the first fitted data points to obtain a second fitted data point that meets the preset conditions.
[0064] Based on the scenario example, the preprocessing of the first fitted data points is mainly based on the screening of the first fitted data points according to preset conditions. The first fitted data points that meet the preset conditions are retained, and the first fitted data points that do not meet the preset conditions are deleted from the parameter coordinate system. The first fitted data points that meet the preset conditions can be used as the second fitted data points.
[0065] S305. Perform data fitting processing on all the second fitted data points to generate a first relationship line of the measured parameter in the parameter coordinate system.
[0066] Based on the scenario example, according to the distribution of all second-fit data points in the parameter coordinate system, the distribution trend and distribution area of the second-fit data points in the parameter coordinate system are obtained by fitting the regression equation, and the image of the regression equation in the parameter coordinate system is used as the first relationship line of the measured parameter.
[0067] S306. Move the first relational line in the coordinate system according to a preset method to obtain a second relational line for the test limit of the measured parameter in the coordinate system.
[0068] In the context of the scenario, the first relationship line of the measured parameters characterizes the distribution trend and distribution area of the fitted data points in the parameter coordinate system. In other words, most of the fitted data points are distributed on both sides of the first relationship line. The test limits are used to judge the quality of the measured parameters of the product under test. Therefore, the first relationship line should be moved to a suitable position so that most of the fitted data points are distributed on one side of the relationship line, and the moved relationship line should be used as the second relationship line of the test limits.
[0069] S307, Output the second relationship line.
[0070] Based on the scenario example, the second relationship line of the obtained test limit is finally output so that the second relationship line can be put into use to judge the quality of the chip.
[0071] The second relationship line of the test limit obtained in this embodiment can be adaptively adjusted according to the specific distribution of the fitted data points to obtain a suitable test limit for the fitted data points. Using a suitable test limit to determine whether the chip is qualified can improve the accuracy of determining whether the chip is qualified.
[0072] Optional, Figure 4 A flowchart illustrating the chip test limit processing method provided in this application. Figure 2 ,like Figure 4 As shown, S304 includes:
[0073] S401. Obtain the theoretical upper limit value of each measured parameter.
[0074] Taking a scenario example, with the measured parameters being the frequency of a ring oscillator and the logarithm of its leakage current, we can obtain the theoretical upper limit of the ring oscillator's frequency and the upper limit of the logarithm of its leakage current.
[0075] S402. Compare each coordinate value of each first fitted data point with the theoretical upper limit value of the corresponding measured parameter, wherein the coordinate value is the test value of the corresponding measured parameter.
[0076] In a scenario example, if the theoretical upper limit of the ring oscillator's frequency is *m*, and the upper limit of the logarithm of the leakage current is *n*, and if the ring oscillator's frequency is the horizontal axis of the parametric coordinate system, and the logarithm of the leakage current is the vertical axis, then the horizontal coordinate value of each first fitted data point is compared with *m*, and the vertical coordinate value of each first fitted data point is compared with *n*. The horizontal coordinate of the first fitted data point represents the measured value corresponding to the frequency of the ring oscillator of the chip under test, and the vertical coordinate of the first fitted data point represents the measured value corresponding to the logarithm of the leakage current of the chip under test.
[0077] S403. In response to the fact that at least one coordinate value of the first fitted data point is greater than the theoretical upper limit value of the corresponding measured parameter, the first fitted data point is deleted from the parameter coordinate system.
[0078] Based on the scenario example, for any first fitted data point, if the x-coordinate value is greater than m, or the y-coordinate value is greater than n, then the first fitted data point can be deleted from the parameter coordinate system.
[0079] S404. In response to the fact that all coordinate values of the first fitted data point are less than or equal to the theoretical upper limit value of the corresponding measured parameter, the first fitted data point is retained in the parameter coordinate system.
[0080] Based on the scenario example, for any first fitted data point, if the x-coordinate value is no greater than m and the y-coordinate value is no greater than n, then the first fitted data point can be retained in the parametric coordinate system.
[0081] S405. Each first fitted data point retained in the parameter coordinate system is taken as a second fitted data point that meets the preset conditions.
[0082] Based on the scenario example, if the preset conditions are that the x-coordinate value is no greater than m and the y-coordinate value is no greater than n, then all the first fitted data points retained in the parameter coordinate system are second fitted data points that meet the constraint conditions. Therefore, the first fitted data points retained in the parameter coordinate system can be used as second fitted data points.
[0083] Based on the method provided in this embodiment, relatively discrete points in the parametric coordinate system can be deleted, while points with a more concentrated distribution can be retained, which can more accurately reflect the distribution trend of the fitted data points in the parametric coordinate system.
[0084] Optional, Figure 5 A flowchart illustrating the chip test limit processing method provided in this application. Figure 3 ,like Figure 5 As shown, S305 includes:
[0085] S501. Determine the expected value, slope, and preset random variables of the regression line corresponding to all processed fitted data points.
[0086] In the example scenario, the expected value is the intercept of the regression directly on the vertical axis, denoted as . The slope of the regression line is denoted as The preset random variable is denoted as ε, which is the random variable of the error term.
[0087] S502. Take the first measured parameter as the dependent variable and the remaining measured parameters as independent variables.
[0088] For example, taking the measured parameters as the frequency of the ring oscillator and the logarithm of the leakage current as an example, the logarithm of the leakage current can be used as the first measured parameter Y, and the frequency of the ring oscillator can be used as the independent variable X.
[0089] S503. Obtain the product of each independent variable and the slope, and use the sum of each product, the expected value, and the random variable as the dependent variable to obtain the first relational equation of the measured parameter.
[0090] Based on the scenario example, the relationship equation of the measured parameters is: Y = β0 + β1X + ε, where β0 and β1 are unknown and can be used. and Replacement. and The value can be calculated using the least squares method, for example, by minimizing the sum of squared errors between the observed and estimated values of the dependent variable. and Specifically:
[0091]
[0092] When the minimum is reached, the following can be obtained. and According to the least squares method, we can obtain:
[0093]
[0094] S504. Fit the first relational equation to the parameter coordinate system to generate the first relational line of the measured parameter.
[0095] Combined with scenario examples, Figure 6 This is a schematic diagram of the first relationship line of the measured parameter as an example. Figure 6 As can be seen, each fitting point in the parametric coordinate system is located on both sides of the first relationship line. Based on the method provided in this embodiment, the first relationship line of the measured parameter can be generated.
[0096] Optional, Figure 7 A flowchart illustrating the chip test limit processing method provided in this application. Figure 4 ,like Figure 7 As shown, S306 includes:
[0097] S701. Obtain the standard deviation of the test values of the first measured parameter corresponding to each second fitted data point.
[0098] Combined with the scenario example and the above embodiments, if the first measured parameter is the logarithm of the leakage value, obtain the test values corresponding to the logarithms of the leakage values of each measured chip, and calculate the standard deviation with the test values corresponding to the logarithms of the leakage values of each measured chip as samples.
[0099] S702. Add the first relationship equation and a preset multiple of the standard deviation to obtain a second relationship equation for the test limit of the measured parameter.
[0100] Combined with the scenario example, taking the first measured parameter as an example, the test limit of the first measured parameter is used to determine the quality of the measured chip. Taking the test limit of the first measured parameter as the upper limit, the relationship line of the test limit should be above the relationship line of the measured parameter. First, based on the first relationship equation of the measured parameter, add 3 times the standard deviation of the test values corresponding to the logarithm of the leakage value, denoted as 3σ, to obtain the second relationship equation of the test limit: Y = β0 + β1X + ε + 3σ.
[0101] S703. Perform data fitting on the second relationship equation in the parameter coordinate system to obtain a second relationship line for the test limit of the measured parameter.
[0102] Combined with the scenario example Figure 8 For the schematic diagram of the second relationship line of the test limit as an example, as can be seen from 8, the second relationship line of the test limit is above most of the fitted data points. Based on the method provided in the embodiment, the second relationship line of the test limit can be generated.
[0103] Optionally, S207 includes:
[0104] Send the relationship line of the test limit to the automatic test equipment, so that the automatic test equipment determines whether the measured chip is qualified based on the second relationship line and generates a judgment result.
[0105] Combined with the scenario example, send the obtained second relationship line of the test limit to the automatic test equipment. The automatic test equipment will use the second relationship line of the test limit as the test basis. If the fitted data point corresponding to the measured chip in the parameter coordinate system is below the second relationship line of the test limit, the judgment result is qualified; otherwise, if the fitted data point corresponding to the measured chip in the parameter coordinate system is above the second relationship line of the test limit, the judgment result is unqualified. Based on the method provided in this embodiment, a test basis for the measured chip can be provided for the automatic test equipment to improve the accuracy of the automatic test equipment for detecting the quality of the measured chip.
[0106] Optional, Figure 9 A flowchart illustrating the chip test limit processing method provided in this application. Figure 5 ,like Figure 9 As shown, it also includes:
[0107] S901. Obtain the judgment result.
[0108] Based on the scenario examples, each chip under test has its own corresponding judgment result, which is the conclusion of whether the chip under test is qualified.
[0109] S902. Based on the judgment result, obtain the product information of each damaged chip.
[0110] Based on the scenario example, each chip under test carries a unique identification code after it is manufactured, such as the serial number. Therefore, the product information can be the identification code of the chip under test. The identification codes of each damaged chip are collected and recorded.
[0111] S903. Send the product information of the damaged chip to the user terminal to identify the damaged chip.
[0112] Based on scenario examples, the product information of each damaged chip is sent to the staff's user terminal, such as sending the product information of each damaged chip to the staff's mobile device. The staff can then use the product information of the damaged chip to locate and recycle it, or take other actions to deal with the damaged chip according to the actual situation, so as to prevent the damaged chip from being put into use.
[0113] Based on the method provided in this application, the second relationship line of the obtained test limit can be adaptively adjusted according to the specific distribution of the fitted data points to obtain a suitable test limit for the second fitted data points. Using a suitable test limit to determine whether the chip is qualified can improve the accuracy of determining whether the chip is qualified.
[0114] Figure 10 A schematic diagram of the structure of the electronic device provided in this application. Figure 10 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus 504.
[0115] In a specific implementation, at least one processor 501 is configured to execute computer execution instructions stored in memory 502, causing at least one processor 501 to perform the above-described method.
[0116] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.
[0117] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules within the processor.
[0118] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.
[0119] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0120] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.
[0121] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.
[0122] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.
[0123] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.
[0124] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0125] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0126] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0127] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.
[0128] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.
Claims
1. A method for processing chip test limits, characterized in that, include: Obtain test values corresponding to multiple test parameters of multiple chips under test; Based on the multiple measured parameters, a parameter coordinate system is constructed; The test value is added to the parameter coordinate system to obtain the first fitted data point in the parameter coordinate system; The first fitted data points are preprocessed to obtain a second fitted data point that meets preset conditions; Perform data fitting processing on all the second fitted data points to generate a first relationship line of the measured parameter in the parameter coordinate system; The first relational line is moved in the coordinate system according to a preset method to obtain a second relational line in the coordinate system for the test limit value of the measured parameter. Output the second relationship line.
2. The method according to claim 1, characterized in that, The step of preprocessing the first fitted data points to obtain second fitted data points that meet preset conditions further includes: Obtain the theoretical upper limit value for each measured parameter; Each coordinate value of each first fitted data point is compared with the theoretical upper limit value of the corresponding measured parameter, where the coordinate value is the test value of the corresponding measured parameter. In response to the fact that at least one coordinate value of the first fitted data point is greater than the theoretical upper limit value of the corresponding measured parameter, the first fitted data point is deleted from the parameter coordinate system; In response to the fact that all coordinate values of the first fitted data point are less than or equal to the theoretical upper limit value of the corresponding measured parameter, the first fitted data point is retained in the parameter coordinate system; Each first fitted data point retained in the parameter coordinate system is used as a second fitted data point that meets the preset conditions.
3. The method according to claim 1, characterized in that, The step of performing data fitting processing on all the second fitted data points to generate a first relationship line of the measured parameter in the parameter coordinate system further includes: Determine the expected value, slope, and preset random variables of the regression line corresponding to all processed fitted data points; The first measured parameter is taken as the dependent variable, and the remaining measured parameters are taken as independent variables. The product of each independent variable and the slope is obtained respectively, and the sum of each product and the expected value and the random variable is used as the dependent variable to obtain the first relationship equation of the measured parameter; The first relational equation is fitted to the data in the parameter coordinate system to generate the first relational line of the measured parameter.
4. The method according to claim 3, characterized in that, The second relational line, which moves the first relational line in the coordinate system according to a preset method to obtain the test limit value of the measured parameter in the coordinate system, further includes: Obtain the standard deviation of the test value of the first measured parameter corresponding to each second fitted data point; Add the first relational equation to a preset multiple of the standard deviation to obtain a second relational equation for the test limit of the measured parameter; The second relational equation is fitted to the parameter coordinate system to obtain a second relational line for the test limit of the measured parameter.
5. The method according to claim 1, characterized in that, The output of the second relationship line further includes: The relationship line of the test limit is sent to the test equipment so that the test equipment can determine whether the chip under test is qualified based on the second relationship line and generate a judgment result.
6. The method according to claim 5, characterized in that, The method further includes: Obtain the judgment result; Based on the judgment results, obtain the product information for each damaged chip; The product information of the damaged chip is sent to the user terminal to identify the damaged chip.
7. An electronic device, characterized in that, include: Memory stores the instructions executed by the computer; A processor configured to execute computer execution instructions stored in the memory, causing the electronic device to perform the method as described in any one of claims 1-6.
8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-6.