Method, storage medium, and device for performing instantaneous power failure recovery processing

Abstract

The present application relates to a method, a storage medium and an apparatus for performing a transient power loss recovery process. The method is performed by a processing unit of a flash controller, comprising: after regaining power, performing operations required for the transient power loss recovery process; and performing a reduced garbage collection process. The execution time of the transient power loss recovery process and the reduced garbage collection process is limited within a default time that a host waits for the flash controller to complete the transient power loss recovery process.

Description

Technical Field

[0001] This invention relates to storage devices, and more particularly to a method, computer-readable storage medium, and apparatus for performing instantaneous power failure recovery processing. Background Technology

[0002] Flash memory is generally divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device; the central processing unit (Host) can provide any address to access NOR flash memory on the address pins and promptly retrieve the data stored at that address from the data pins of NOR flash memory. Conversely, NAND flash memory is not random access but serial access. Unlike NOR flash memory, NAND flash memory cannot access any random address. Instead, the Central Processing Unit (CPU) needs to write serial bytes of values ​​into the NAND flash memory to define the type of request command (e.g., read, write, erase, etc.) and the address used for that command. The address can point to a page (the smallest data block in flash memory for a write operation) or a block (the smallest data block in flash memory for an erase operation). Improving the access performance of NAND flash memory has always been an important issue for NAND flash memory devices. Summary of the Invention

[0003] In view of this, how to mitigate or eliminate the deficiencies in the aforementioned related fields is a problem that needs to be solved.

[0004] The present invention relates to a method for performing momentary power failure recovery processing, executed by a processing unit of a flash memory controller, comprising: performing operations required for momentary power failure recovery processing after power is restored; and performing simplified garbage collection processing.

[0005] The present invention also relates to a computer-readable storage medium for storing program code that can be loaded and executed by a processing unit of a flash memory controller, wherein the program code, when executed by the processing unit, implements the method for performing instantaneous power failure recovery processing as described above.

[0006] The present invention also relates to an apparatus for performing momentary power outage recovery processing, comprising: a processing unit. The processing unit is configured to perform operations required for momentary power outage recovery processing after power is restored; and to perform streamlined waste collection processing.

[0007] The execution time for instantaneous power failure recovery processing and simplified garbage collection is limited to a default time on the host side while waiting for the flash controller to complete the instantaneous power failure recovery processing.

[0008] One of the advantages of the above embodiments is that by adding the simplified waste recycling process described above to the instantaneous power outage recovery process, the execution efficiency of the device can be improved.

[0009] Other advantages of the present invention will be explained in more detail below with reference to the accompanying drawings. Attached Figure Description

[0010] The accompanying drawings, which are provided to further illustrate this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application.

[0011] Figure 1 This is a system architecture diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 This is a schematic diagram of a flash memory module according to an embodiment of the present invention.

[0013] Figure 3 This is a partial hardware architecture diagram of a NAND flash memory cell according to an embodiment of the present invention.

[0014] Figure 4 This is a schematic diagram of an example (n=3, k=6) low-density parity check code according to an embodiment of the present invention.

[0015] Figure 5 This is a flowchart of an optimized Sudden Power Off Recovery (SPOR) process according to an embodiment of the present invention.

[0016] Figure 6 This is a flowchart illustrating a method for reading a batch of valid pages in general waste recycling processing, based on some implementation methods.

[0017] Figure 7 This is a flowchart illustrating a method for reading a batch of valid pages in a streamlined waste recycling process according to an embodiment of the present invention.

[0018] The annotations in the attached figures are explained as follows:

[0019] 10: Electronic devices

[0020] 110: Host side

[0021] 130: Flash memory controller

[0022] 131: Host Interface

[0023] 132: Bus Architecture

[0024] 134: Processing Unit

[0025] 136: Random Access Memory

[0026] 137: Software decoder

[0027] 138: RAID Engine

[0028] 139: Flash Memory Interface

[0029] 150: Flash memory module

[0030] 151: Interface

[0031] 153#0~153#15: NAND flash memory cells

[0032] CH#0~CH#3: Channels

[0033] CE#0~CE#3: Start signal

[0034] 300: Storage Block

[0035] 310: Floating gate transistor

[0036] BL1~BL3: Bit lines

[0037] WL0~WL5: Word lines

[0038] 500: Streamline waste recycling and processing

[0039] S510~S550: Method Steps

[0040] S610~S690: Methods and Procedures

[0041] S700, S750~S770: Method Steps Detailed Implementation

[0042] The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals denote the same or similar components or method flows.

[0043] The following provides various aspects and embodiments of this specification. Some embodiments can be implemented independently, while others can be combined and implemented by those skilled in the art where readily apparent. The following description is for illustrative purposes only, and specific details are provided to enable a complete understanding of various aspects of the present invention. However, it will be apparent that these embodiments are not necessarily to be carried out in such a detailed and complete manner. The accompanying drawings and description are not intended to limit the scope of the invention.

[0044] The following description is merely illustrative and is not intended to limit the scope, application, or setting of this specification. Rather, the examples provided are intended to offer implementations that can be carried out by those skilled in the art. It should be understood that the function and arrangement of the elements may be changed without departing from the scope and spirit of the claims.

[0045] refer to Figure 1Electronic device 10 includes a host side 110, a flash memory controller 130, and a flash memory module 150, which can be collectively referred to as the device side. Electronic device 10 can be implemented in peripheral storage devices, personal computers, laptop PCs, tablet computers, mobile phones, digital cameras, digital camcorders, smart TVs, smart refrigerators, automotive electronic systems, and other electronic products. The host interface 131 of the host side 110 and the flash memory controller 130 can communicate with each other using communication protocols such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Storage (UFS), and Embedded Multi-Media Card (eMMC). The flash interface 139 of the flash controller 130 and the flash module 150 can communicate with each other using a Double Data Rate (DDR) communication protocol, such as Open NAND Flash Interface (ONFI), DDR Toggle, or other communication protocols. The flash controller 130 includes a processing unit 134, which can be implemented in various ways, such as using general-purpose hardware (e.g., a single processor, a microcontroller unit, a multiprocessor with parallel processing capabilities, a graphics processor, or other processors with computing power), and provides the functions described later when executing software and / or firmware instructions. The processing unit 134 receives host commands, such as write commands and read commands, through the host interface 131, schedules and executes these commands.The flash memory controller 130 also includes random access memory (RAM) 136, which can be implemented as dynamic random access memory (DRAM), static random access memory (SRAM), or a combination of the two. This RAM is used to configure space as a data buffer, storing user data (also referred to as host data) read from the host 110 and about to be written to the flash memory module 150, as well as user data read from the flash memory module 150 and about to be output to the host 110. The RAM 136 can also store data required during execution, such as variables, data tables, data structures, host-to-flash / H2F tables, flash-to-host / F2H tables, etc. The flash interface 139 includes a NAND Flash Controller (NFC) that provides the functions required to access the flash module 150, such as a command sequencer and low-density parity check (LDPC).

[0046] The flash controller 130 includes a configurable bus architecture 132 for coupling components to each other to transmit data, addresses, control signals, etc. These components include, but are not limited to, the host interface 131, the processing unit 134, RAM 136, a software decoder 137, a Redundant Array of Independent Disks (RAID) engine 138, and a flash interface 139. Direct Memory Access (DMA) circuits within the components can migrate data between components via the bus architecture 132 according to instructions or control signals. For example, the DMA circuits in the host interface 131 or the flash interface 139 can move data from a specific data buffer to a specific address in RAM 136, or move data from a specific address in RAM 136 to a specific data buffer.

[0047] Flash module 150 provides a large storage space, typically hundreds of gigabytes (GB) or even multiple terabytes (TB), for storing large amounts of user data, such as high-resolution images and videos. Flash module 150 includes control circuitry and a memory array. The memory cells in the memory array can be configured as Single Level Cells (SLCs), Multiple Level Cells (MLCs), Triple Level Cells (TLCs), Quad-Level Cells (QLCs), or any combination thereof. Processing unit 134 writes user data to a specified address (destination address) in flash module 150 and reads user data from a specified address (source address) in flash module 150 via flash interface 139. Flash interface 139 uses multiple electronic signals to coordinate data and command transmission between flash controller 130 and flash module 150, including data lines, clock signals, and control signals. Data lines can be used to transmit commands, addresses, read data, and write data; control signal lines can be used to transmit control signals such as Chip Enable (CE), Address Latch Enable (ALE), Command Latch Enable (CLE), and Write Enable (WE).

[0048] refer to Figure 2 The interface 151 in the flash memory module 150 may include four input / output channels (I / O channels, hereinafter referred to as channels) CH#0 to CH#3, each channel connecting four NAND flash memory cells. For example, channel CH#0 connects NAND flash memory cells 153#0, 153#4, 153#8, and 153#12. Each NAND flash memory cell may be packaged as an independent die. The flash memory interface 139 can send one of the start signals CE#0 to CE#3 through the interface 151 to start NAND flash memory cells 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15. Then, user data is read from the started NAND flash memory cell or written to the started NAND flash memory cell in parallel.

[0049] refer to Figure 3The local hardware architecture of a NAND flash memory cell. Each NAND flash memory cell may contain memory blocks 300, and memory blocks 300 contain multiple memory cells, such as floating gate transistors 310 or other charge trap devices. The structure of memory blocks 300 includes multiple bit lines and multiple word lines. For simplicity, Figure 3 Only bit lines BL1 to BL3 and word lines WL0 to WL5 are labeled. For example, the floating gate transistor on each of word lines WL0 to WL5 can be used to store one or more pages of data.

[0050] Each NAND flash memory cell can contain multiple data planes, and each data plane can contain multiple physical blocks. To improve data write and read efficiency, physical pages in multiple data planes of multiple NAND flash memory cells can be organized into a super page (SP). For example, in... Figure 2In the example setup shown, each flash cell contains four data planes, and each data plane contains a 4-kilobyte (KB) physical page. A superpage can store 256 KB of user data (= 4 channels × 4 CEs × 4 data planes × 4 KB). Multiple superpages can form a superblock (SB). In some embodiments, any superblock can be configured as a Single Level Cell (SLC) superblock, where each superpage in the SLC SB is an SLCSP. In other embodiments, any superblock can be configured as a Multiple Level Cell (MLCSB) superblock, where each superpage in the MLC SB can be a Most Significant Bit (MSB) superpage or a Least Significant Bit (LSB) superpage. In other embodiments, any superblock may be configured as a Triple Level Cell (TLC SB), where each superpage in the TLC SB may be an MSB SP, a Center Significant Bit (CSB SP), or an LSB SP. In other embodiments, any superblock may be configured as a Quad-Level Cell (QLC SB), where each superpage in the QLC SB may be a Top Significant Bit (TSB Page), an MSB SP, a CSB SP, or an LSB SP.

[0051] In some embodiments, a Logical Block Address (LBA) managed by host 110 may represent 512 bytes (B) of user data, and each physical page may be further divided into eight 512-byte sections. The LBA number can be referred to as the logical address managed by host 110. Superblocks, physical pages, and sections can be identified using Super-block Numbers, Physical Page Numbers, and Section Numbers, respectively, and the combination of these numbers can be referred to as the physical address of flash memory module 150. In other embodiments, a Host Page Number managed by host 110 may represent 4KB of user data, and each physical page does not need to be further subdivided into sections. The Host Page Number can be referred to as the logical address managed by host 110. Superblocks and physical pages can be identified using Super-block Numbers and Physical Page Numbers, respectively, and the combination of these numbers can be referred to as the physical address of flash memory module 150.

[0052] Each superblock can be divided into a data block or a current block according to its function. Processing unit 134 can select an empty superblock as the current block to prepare for writing user data received from host 110. Processing unit 134 can maintain an F2H table for each current block in RAM 136, containing multiple records that store information about which logical address each physical address in the current block is associated with (or mapped to) by the user data. Logical addresses can be represented using LBA numbers, main page numbers, or other methods and are managed by host 110. After all physical pages in a current block are filled with user data, or after the remaining pages in a current block are filled with dummy values, processing unit 134 can drive flash interface 139 to write the corresponding F2H table in RAM 136 to the data portion of a specified physical page in the current block. For example, a current block can be divided into multiple banks, and the record in the F2H table corresponding to a bank of the current block can be written to the last physical page of that bank. Once all records of the corresponding F2H table have been written to the flash memory module 150, the current block becomes a data block, and the user data stored in the data block will not change. Next, the processing unit 134 can select another empty superblock as the new current block.

[0053] To achieve data fault tolerance, a dedicated circuit in the processing unit 134 or flash interface 139 can execute an encoding algorithm to generate an error correcting code (ECC) based on each page of user data. The user data, along with the error correcting code, is then written to the flash module 150, enabling future correction of user data containing erroneous bits read from the flash module 150. The error correcting code can be a low-density parity check code (LDPC), a BCH code (Bose–Chaudhuri–Hocquenghem Code), or other types of encoding. For example, per 1KB of user data, a BCH code can provide correction for up to 72 error bits, while an LDPC code can provide correction for up to 128 error bits.

[0054] For example, LDPC codes are linear error correction codes, and the generation of LDPC codes can be expressed using the following formula:

[0055] MSG 1xn ⊙PCM nx(n+m) =CW 1x(n+m)

[0056] Among them, MSG 1xn PCM is a 1-column, n-row matrix representing user data. nx(n+m) Represents an n-column, (n+m)-row parity check matrix, CW 1x(n+m) This represents a 1-column, (n+m)-row matrix containing the final codeword, where ⊙ represents modulo 2 multiplication. The parity check matrix can contain a quasi-cyclic (QC) structure, and CW... 1x(n+m) The value of the first n bits in MSG is equal to 1xn The value of CW 1x(n+m) The last m bits of the code are called the LDPC code. An example is shown below:

[0057]

[0058] Those skilled in the art know that known parity check matrices and efficient algorithms can be used to generate LDPC codes, such as two-stage encoding.

[0059] Processing unit 134 can drive software decoder 137 to verify the codeword (containing user data and LDPC code) read from a specific page of flash memory module 150 via flash memory interface 139 and determine whether the codeword contains error bits. If an error bit is found in the codeword, processing unit 134 can further drive software decoder 137 to attempt to recover the correct codeword and obtain user data from it. If, after a predetermined number of attempts, the correct codeword cannot be recovered, software decoder 137 determines that the codeword is an uncorrectable codeword. For more information on LDPC decoding, see [reference needed]. Figure 4 The example shown is an LDPC code (n=3, k=6). Blocks 43#0 to 43#5 represent variable nodes, and blocks 41#0 to 41#2 represent check nodes. The bits in variable nodes 43#0 to 43#5 form a codeword, consisting of user data and LDPC code, and the bits must satisfy the graphical constraints. Specifically, all lines connected to a variable node have the same value, and the sum of all lines connected to a check node must have a remainder of 0 when divided by two (that is, the sum is even, or has an even number of odd values). Check nodes 41#0 to 41#2 are also called the synthesizers.

[0060] The soft decoder 137 includes two important circuits: a check-node calculation circuitry and a variable-node calculation circuitry. The check-node calculation circuitry performs modulo-2 squares on the hard bits or variable nodes, and the parity check matrix to calculate the checksum. The variable-node calculation circuitry performs a known bit-flipping algorithm based on the soft bits corresponding to the hard bits or variable nodes, and the checksum, to generate new variable nodes, and uses a known formula to calculate the soft bits of the new variable nodes. RAM 136 is a configurable space for storing hard bits and variable nodes, and the soft bits corresponding to the hard bits and variable nodes. The codeword initially read from a designated page of the flash memory module 150 represents the hard bits. In some embodiments, the flash memory interface 139 may include a soft-bit calculation circuitry for calculating the soft bits for each hard bit in the codeword when reading the codeword from the flash memory module 150. It should be noted that the software decoder 137 takes some time to perform multiple iterations of processing in an attempt to recover the correct codeword.

[0061] In other embodiments, those skilled in the art can implement the algorithms executed by the check node calculation circuit and the change node calculation circuit in the dedicated software decoder 137 as software program code, which can then be loaded and executed by the processing unit 134. It should be noted that the time required to complete the above functions using software program code is typically longer than the runtime of the dedicated software decoder 137.

[0062] When the user data read from a page contains more error bits than the error correction code can correct, the software decoder 137 cannot recover the correct codeword. To improve the fault tolerance of the device, the flash memory controller 130 can form a page group with a default number of pages and generate a parity page based on the user data of the page group. For example, seven pages P#0 to P#6 form a page group, each page containing 4096 bits of user data, and generating a 128-bit ECC accordingly. For example, the error correction code for page P#0 is ECC#0, the error correction code for page P#1 is ECC#1, and so on. The processing unit 134 can drive the RAID engine 138 to execute the RAID encoding algorithm to generate parity page data based on the user data and ECC in pages P#0 to P#6. The parity page data can be generated using formula (1):

[0063] P j =d p0,j ⊕d p1,j ⊕d p2,j ⊕d p3,j ⊕d p4,j ⊕d p5,j ⊕d p6,j ,

[0064] Where j is any integer from 0 to 4223, p0 represents the 0th page, p1 represents the 1st page, p2 represents the 2nd page, and P j d represents the value of the j-th bit in the parity check page. p0,j d represents the value of the j-th bit in the 0th page. p1,j d represents the value of the j-th bit in the first page. p2,jThis represents the value of the j-th bit in the second page. When the error correction code of a page cannot correct the error bits of the user data, the processing unit 134 can discard this page and drive the RAID engine 138 to generate the corrected user data for this page using a mutual exclusion OR operation based on the contents of other pages in the page group and the parity check page. If the error bits of the user data in the first page cannot be corrected using the corresponding error correction code, the error page can be recovered using formula (2):

[0065] d p1,j =d p0,j ⊕d p2,j ⊕d p3,j ⊕d p4,j ⊕d p5,j ⊕d p6,j ⊕P j .

[0066] The parity check code on the parity check page, based on its function, is also known as the Redundant Array of Independent Disks (RAID ECC) error correction code. It's important to note that the RAID 138 engine involves reading multiple pages during the error page recovery process, which takes some time.

[0067] In other embodiments, those skilled in the art can implement the algorithms executed by the RAID engine 138 as software program code, which can then be loaded and executed by the processing unit 134. It should be noted that the time required to perform the above functions using software program code is typically longer than the runtime of the dedicated RAID engine 138.

[0068] A sudden power outage, whether caused by natural or man-made events, may interrupt the write operation of the flash memory module 150. Upon power restoration, the processing unit 134 executes a Sudden Power Off Recovery (SPOR) process to detect the last correctly written page of the flash memory module 150 in the current block before the power outage and rebuilds the H2F table to reflect the status of all correctly written pages of the flash memory module 150 in the current block before the power outage. The H2F table contains multiple records, storing information in logical address order about which logical address the user data is actually stored at.

[0069] After a momentary power outage and subsequent restoration of power, the host 110 typically waits for a default period of time, for example, any time between 0.8 seconds and 1 second, without issuing any host commands to the device, to wait for the device (specifically, the flash controller 130) to complete the SPOR process. The host may issue a query request to the flash controller 130, including information to write "1" to the "fDeviceInit" flag, to notify the flash controller 130 to begin device initialization. Then, after waiting for the default period, it issues another query request to the flash controller 130, including information to read the "fDeviceInit" flag. If the device has completed device initialization, the flash controller 130 issues a query response to the host 110, with the "fDeviceInit" flag set to "0". If the device has not yet completed device initialization, the "fDeviceInit" flag is set to "1" in the query response. However, the device side only needs approximately 300 to 500 milliseconds (ms) to complete the SPOR process. To effectively utilize this time spent waiting for the SPOR process on the host side, this embodiment of the invention performs both SPOR processing and reduced garbage collection (GC) processing. The execution of both SPOR processing and reduced GC processing is limited to the default timeframes described above.

[0070] After multiple accesses, a physical block may contain valid and invalid pages (also known as expired pages). Valid pages store valid user data, while invalid pages store invalid (old) user data. In typical garbage collection (GC) processing, processing unit 134 drives flash interface 139 to issue a read command, instructing flash module 150 to read and collect user data from valid pages in several data blocks (referred to as source blocks). Then, it drives flash interface 139 to issue a write command, instructing flash module 150 to rewrite the collected valid user data to the current block (referred to as the destination block). The source block, containing only invalid pages, can then provide new data storage space after erasure. Compared to typical GC processing, simplified GC processing primarily reduces the time required to read and collect user data from valid pages in source blocks; its technical details will be explained in the following paragraphs.

[0071] In one respect, reference Figure 5 The flowchart shown illustrates the method. When loading and executing the bootloader's program code, processing unit 134 executes the optimized SPOR method. Detailed explanation follows:

[0072] Step S510: Perform the operations required for SPOR processing as described above.

[0073] After the SPOR processing is completed, the simplified GC processing 500 is executed. Simplified GC processing 500 consists of a loop comprising steps S520, S530, S540, and S550. Within a default timeframe, simplified GC processing 500 collects user data from valid pages in multiple source blocks and writes the collected user data to physical pages in the destination block. At the beginning of simplified GC processing 500, the bootloader may start a timer, counting from 0.

[0074] Step S520: Collect user data from multiple valid pages from the source block.

[0075] Step S530: Determine if a read failed or if the execution time of the thin GC process has exceeded the default time. For example, a read failure could mean that the source block has been marked as a bad block. If so, the process ends and exits the SPOR process. Otherwise, the process continues to the operation in step S540.

[0076] Step S540: Write the collected user data into the specified physical page in the destination block.

[0077] Step S550: Determine if the execution time of the simplified GC process has exceeded the default time. If so, the process ends and exits the SPOR process. Otherwise, the process continues to the operation of step S520.

[0078] The default time in steps S530 and S550 can be any time from 400ms to 500ms.

[0079] In steps S530 and S550, specifically, the boot program determines whether the timer count has exceeded the default time. If so, it means that the execution time of the simplified GC process has exceeded the default time. In other words, the timer count indicates the execution time of the simplified GC process in step S530 or S550.

[0080] In general GC processing, refer to Figure 6The flowchart shown illustrates the method. Processing unit 134 reads a batch of valid pages when loading and executing the Firmware Translation Layer (FTL) program code. It's important to note that after SPOR processing, processing unit 134 enters Runtime Mode and loads and executes the FTL program code to execute host commands received from host 110, and during the execution of host commands or during idle periods, performs background processing to improve device performance, such as general garbage collection (GC).

[0081] Detailed explanation is as follows:

[0082] Step S610: Read user data and the corresponding ECC code from the specified valid page in the source block, and (if necessary) correct the erroneous bits in the user data according to the corresponding ECC code. The operation of step S610 can be called the Hard Decoding Process.

[0083] Step S620: Determine whether the hard decoding process was successful. If yes, the process continues to step S690; otherwise, the process continues to step S630.

[0084] Step S630: Perform a read retry process. In some embodiments, the manufacturer of the flash memory module 150 provides a re-read voltage table, which records multiple sets of re-read voltages, in addition to providing a suggested set of read voltages. In other embodiments, the re-read voltage table provided by the manufacturer of the flash memory module 150 records multiple sets of offset values, allowing the processing unit 134 to obtain the re-read voltage of the corresponding set based on the suggested read voltage and the offset value of the corresponding set. The read retry process is executed repeatedly in a loop until the user data read from the page is correct, or all sets of re-read voltages have been tried.

[0085] Step S640: Determine whether the read retry process was successful. If yes, the process continues to step S690; otherwise, the process continues to step S650.

[0086] Step S650: Perform the soft decoding process. In some embodiments, the FTL drives the soft decoder 137 to complete the soft decoding process. In other embodiments, the FTL calls and executes the program code of the soft decoding function program, which includes the algorithms executed by the check node calculation circuit and the change node calculation circuit in the soft decoder 137 to complete the soft decoding process.

[0087] Step S660: Determine whether the software decoding process was successful. If yes, the process continues to step S690; otherwise, the process continues to step S670.

[0088] Step S670: Perform RAID decoding processing. In some embodiments, the FTL drives the RAID engine 138 to complete the RAID decoding processing. In other embodiments, the FTL calls and executes the program code of the RAID decoding function program, which includes the algorithm executed in the RAID engine 138, to complete the RAID decoding processing.

[0089] Step S680: Determine whether the RAID decoding process was successful. If yes, the process continues to step S690; otherwise, the process continues to step S685.

[0090] Step S685: Mark this valid page as an uncorrectable ECC (UECC page).

[0091] Step S690: Determine whether the reading of this batch is complete. If yes, the process ends; otherwise, the process continues to the operation of step S610. A batch of reading includes reading operations of multiple specified valid pages in the source block.

[0092] However, Figure 6 The method shown may take a considerable amount of time to read user data from valid pages, which is not conducive to incorporating general GC processing within the default waiting time for SPOR processing on the host side 110. Therefore, in one aspect, embodiments of the present invention propose as follows: Figure 7 The flowchart shown illustrates the method in simplified GC processing. Processing unit 134 executes a method for reading a valid page from a source block when loading and executing the boot program code.

[0093] Unlike Figure 6 The flowchart shown is for the method. Figure 7 The method shown removes steps S650, S660, S670, S680, and S685 to save time in performing software decoding and RAID decoding. Step S700 is added before step S610. Steps S750, S760, and S770 are added after the "No" path in step S640. Detailed explanation follows:

[0094] Step S700: Since the simplified GC process can conditionally reference part of the general GC process program code, the functions of software decoding and RAID decoding are disabled to avoid the execution of steps S650, S660, S670, S680, and S685.

[0095] Step S750: After determining that the read retry process has failed, mark this valid page as a potential UECC page. After entering real-time execution mode, FTL will attempt to use software decoding and RAID decoding to retrieve the user data from this potential UECC page.

[0096] Step S760: Determine whether the number of potential UECC pages exceeds a threshold. If yes, the process continues to step S770; otherwise, the process continues to step S690. This threshold can be set to the number of valid pages of this source block (e.g., 90% or more).

[0097] Step S770: Mark this source block as a bad block, and then end the process.

[0098] Although the present invention has been described and illustrated herein with reference to specific embodiments, it is not intended to be limited to the details shown. Rather, various modifications to the details may be made within the scope and equivalents of the claims without departing from the invention. It should be understood that the above description is illustrative and should not be construed as limiting the invention. Various modifications, applications, and / or combinations of the embodiments will be apparent to those skilled in the art without departing from the scope of the invention as defined by the claims.

[0099] It will be readily understood by those skilled in the art that the invention discussed above can be implemented using different configurations of hardware elements than those disclosed. Therefore, although the invention has been described based on these preferred embodiments, certain modifications, variations, and alternative constructions will be apparent to those skilled in the art, and are also within the scope of the invention.

[0100] It must be understood that the terms "comprising" and "including" used in this specification are used to indicate the presence of specific technical features, values, method steps, operation processes, parts and / or components, but do not preclude the addition of more technical features, values, method steps, operation processes, components, parts, or any combination thereof.

[0101] In this invention, terms such as "first," "second," and "third" are used to modify components in the claims and are not used to indicate a priority order, a prior relationship, or that one component precedes another, or the chronological order of the execution of method steps. They are only used to distinguish components with the same name.

[0102] It's important to understand that when a component is described as "connected" or "coupled" to another component, it can be a direct connection or coupling to other components, potentially involving intermediate components. Conversely, when a component is described as "directly connected" or "directly coupled" to another component, there are no intermediate components. Other terms used to describe relationships between components can be interpreted similarly, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," and so on.

[0103] The terms "device" or "module" are not limited to one or a specific number of physical objects (e.g., a smartphone, a controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that performs at least some of the functions of the invention disclosed herein. While the description and examples use the terms "device" or "module" to describe various aspects of the invention, the terms "device" or "module" are not limited to a particular configuration, type, or number of objects. Furthermore, the terms "system" or "module" are not limited to multiple components or a particular orientation. For example, a system may be implemented on one or more printed circuit boards or other substrates and may have movable or static components. While the description and examples use the term "system" to describe various aspects of the invention disclosed herein, the term "system" is not limited to a particular configuration, type, or number of objects.

[0104] Specific details are provided in the above description to aid in a thorough understanding of various aspects of the invention. However, those skilled in the art will understand that these aspects can be implemented without these specific details. For clarity of explanation, in some instances, the technology may be presented as comprising individual functional blocks, including devices, device components, steps or subroutines embodied in software methods, or combinations of hardware and software. Other additional components, different from those shown in the figures and / or described herein, may also be used. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form to avoid obscuring these aspects with unnecessary detail. In other instances, to avoid obscuring these aspects with unnecessary detail, known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail.

[0105] Some aspects can be described as processes or methods in the text, and can be shown as flowcharts, data flow diagrams, structure diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, multiple operations can be executed in parallel or simultaneously. Furthermore, the order of these operations can be rearranged. The process terminates when an operation is completed, but there may be other steps not included in the diagram. A process can correspond to a method, function, program, subroutine, subroutine, etc. When a process corresponds to a function, its termination can correspond to the function returning to the calling function or the main function.

[0106] All or part of the steps in the method described in this invention can be implemented by a computer program, such as a firmware translation layer (FTL) in the device, a driver for specific hardware, etc. Furthermore, it can also be implemented in other types of programs as shown above. Those skilled in the art can write the methods of the embodiments of this invention into program code, which will not be described further for the sake of brevity. The computer program implementing the method according to the embodiments of this invention can be stored on a suitable computer-readable storage medium or placed on a network server accessible via a network (e.g., the Internet, or other suitable media).

[0107] Computer-readable storage media include volatile and non-volatile, removable and non-removable media that store information, such as computer-readable instructions, data structures, program modules, or other data, using any method or technique. Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory, CD-ROM, DVD, Blu-ray disc or other optical storage media, magnetic cards, magnetic tape, hard disks or other magnetic storage media, or other carriers that can be used to store information required and accessed by an instruction execution system. It should be noted that computer-readable storage media can be paper or other suitable media used to print program code, enabling the program code to be accessed electrically, such as by optical scanning of the paper or other media, and then, if necessary, compiled, interpreted, or otherwise processed, and then stored in the memory of an electronic device.

[0108] The program code can be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such a processor can be configured to perform any of the techniques described in this disclosure. A general-purpose processor may be a microprocessor; however, in alternative instances, the processor may be any conventional processor, controller, microprocessor, or state machine. A processor may be implemented as a combination of multiple computing devices, such as a DSP and a microprocessor, multiple microprocessors, one or more microprocessors paired with a DSP core, or any other similar configuration. Accordingly, the term "processor" as used herein may refer to any of the foregoing structures, any combination of the foregoing structures, or any other structure or device suitable for implementing the counts described herein.

[0109] The various illustrative logic blocks, modules, engines, circuits, and algorithm steps described in conjunction with the inventive aspects disclosed herein can be implemented as electronic hardware, computer software, firmware, or any combination thereof. To clearly illustrate the interchangeability of hardware and software, the various illustrative components, blocks, modules, engines, circuits, and steps have been generally described above in terms of their functionality. Whether these functions are implemented in hardware or software depends on the specific application scenario and the design constraints imposed on the overall system. Those skilled in the art can implement the described functions in different ways for each specific application scenario, but such implementation decisions should not be construed as departing from the scope of this application.

[0110] Although Figures 1 to 3 It includes the components described above, but does not preclude the use of other additional components to achieve better technical results without violating the spirit of the invention. Furthermore, although... Figures 5 to 7 The flowchart describes the steps in a specified order. However, those skilled in the art can modify the order of these steps to achieve the same effect without departing from the spirit of the invention. Therefore, the present invention is not limited to using only the order described above. Furthermore, those skilled in the art can integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention should not be limited thereto.

[0111] The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Those skilled in the art can make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the content defined in the claims of this application.

Claims

1. A method for performing instantaneous power failure recovery processing, executed by the processing unit of a flash memory controller, characterized in that, The method for performing instantaneous power outage recovery includes: After power is restored, perform the operations required for the instantaneous power outage recovery process; and Implement streamlined waste recycling and disposal. The execution time of the instantaneous power failure recovery process and the simplified garbage collection process is limited to a default time during which the host waits for the flash memory controller to complete the instantaneous power failure recovery process.

2. The method for performing instantaneous power outage recovery processing according to claim 1, characterized in that, The streamlined waste recycling process includes a recurring cycle, which includes: Collect user data from multiple valid pages from the source block; After collecting the user data from the multiple valid pages from the source block, it is determined whether the reading failed, or whether the first execution time of the simplified garbage collection process exceeded the default time; If a read fails or the first execution time of the simplified garbage collection process exceeds the default time, the instantaneous power outage recovery process ends. If the read is successful and the first execution time of the simplified garbage collection process does not exceed the default time, the user data is written to the physical page of the destination block; After writing the user data to the physical page in the destination block, it is determined whether the second execution time of the thin garbage collection process exceeds the default time; When the second execution time of the simplified waste recycling process exceeds the default time, the instantaneous power outage recovery process ends; and If the second execution time of the simplified garbage collection process does not exceed the default time, continue to the next iteration.

3. The method for performing instantaneous power outage recovery processing according to claim 2, characterized in that, include: At the beginning of the streamlined waste recycling process, a timer is started, counting from 0. The timer's count value indicates either the first execution time or the second execution time of the streamlined waste recycling process.

4. The method for performing instantaneous power outage recovery processing according to claim 2, characterized in that, The default time is any time between 400ms and 500ms.

5. The method for performing instantaneous power outage recovery processing according to claim 1, characterized in that, The execution time for the instantaneous power outage recovery process and the simplified waste recycling process is limited to any time between 0.8 seconds and 1 second.

6. The method for performing instantaneous power outage recovery processing according to claim 1, characterized in that, In the simplified garbage collection process, the functions of software decoding and independent hard disk redundant array decoding are disabled.

7. The method for instantaneous power outage recovery according to claim 6, characterized in that, The soft decoding process is the user data in the error page. Based on the soft bits corresponding to the hard bits or the change nodes, and the checksum, a bit flipping algorithm is performed to generate new change nodes, and the soft bits of the new change nodes are calculated using a formula. The independent hard disk redundancy array decoding process generates user data in the error page based on user data from other pages in the page group and data from the parity check page.

8. A computer-readable storage medium for storing program code executable by a processing unit of a flash memory controller, characterized in that, When the program code is executed by the processing unit, it implements the method for instantaneous power failure recovery processing according to any one of claims 1 to 7.

9. A device for performing instantaneous power failure recovery processing, characterized in that, include: The processing unit is configured to perform the operations required for the instantaneous power outage recovery process after power is restored. And implement streamlined waste recycling and processing. The execution time of the instantaneous power outage recovery process and the simplified waste recycling process is limited to a default time during which the host waits for the device to complete the instantaneous power outage recovery process.

10. The apparatus for performing instantaneous power failure recovery processing according to claim 9, characterized in that, The streamlined waste recycling process includes a recurring cycle, which includes: Collect user data from multiple valid pages from the source block; After collecting the user data from the multiple valid pages from the source block, it is determined whether the reading failed, or whether the first execution time of the simplified garbage collection process exceeded the default time; If a read fails or the first execution time of the simplified garbage collection process exceeds the default time, the instantaneous power outage recovery process ends. If the read is successful and the first execution time of the simplified garbage collection process does not exceed the default time, the user data is written to the physical page of the destination block; After writing the user data to the physical page in the destination block, it is determined whether the second execution time of the thin garbage collection process exceeds the default time; When the second execution time of the simplified waste recycling process exceeds the default time, the instantaneous power outage recovery process ends; and If the second execution time of the simplified garbage collection process does not exceed the default time, continue to the next iteration.

11. The apparatus for performing instantaneous power failure recovery processing according to claim 10, characterized in that, The processing unit is configured to start a timer at the beginning of the streamlined waste recycling process, counting from 0, wherein the count value of the timer indicates the first execution time or the second execution time of the streamlined waste recycling process.

12. The apparatus for performing instantaneous power failure recovery processing according to claim 10, characterized in that, The default time is any time between 400ms and 500ms.

13. The apparatus for performing instantaneous power failure recovery processing according to claim 9, characterized in that, The execution time for the instantaneous power outage recovery process and the simplified waste recycling process is limited to any time between 0.8 seconds and 1 second.

14. The apparatus for performing instantaneous power failure recovery processing according to claim 9, characterized in that, The processing unit is configured to disable the software decoding process and the independent hard disk redundant array decoding process in the simplified garbage collection process.

15. The apparatus for performing instantaneous power failure recovery processing according to claim 14, characterized in that, The soft decoding process is the user data in the error page. Based on the soft bits corresponding to the hard bits or the change nodes, and the checksum, a bit flipping algorithm is performed to generate new change nodes, and the soft bits of the new change nodes are calculated using a formula. The independent hard disk redundancy array decoding process generates user data in the error page based on user data from other pages in the page group and data from the parity check page.

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