Data reading method, device, apparatus and storage medium

Abstract

The application provides a data reading method and device, equipment and a storage medium, and relates to the technical field of storage. The method is applied to a processor, and the processor comprises a plurality of cores. The data reading method comprises the following steps: receiving a data reading request sent by a first core in the plurality of cores, the data reading request being used for requesting to read target data; after receiving the data reading request, performing a listening operation on at least one target cache, the listening operation being used for detecting whether the target data is stored in the target cache, and the target cache being a preset cache; if the target data is stored in the target cache, reading the target data from the target cache, and sending the target data read from the target cache to the first core. The method improves the data reading speed.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a data reading method, apparatus, device, and storage medium. Background Technology

[0002] With the development of storage technology, modern processors include multiple cores. For any given core, the target data required when executing a task may be stored in its own cache or in the caches of other cores.

[0003] In related technologies, when a first core (which can be understood as any core) initiates a read request for target data, the system queries a directory unit, which records the storage location information of at least one piece of data. Based on the retrieved storage location information of the target data, the system obtains the target data and returns it to the first core.

[0004] However, because the data storage location information needs to be obtained from the directory unit, the data reading speed is relatively slow. Summary of the Invention

[0005] This application provides a data reading method, apparatus, device, and storage medium. The technical solutions provided by this application are as follows.

[0006] According to one aspect of the embodiments of this application, a data reading method applied in a processor is provided, the processor including multiple cores, the method comprising: Receive a data read request sent by the first core among the plurality of cores, the data read request being used to request the reading of target data; After receiving the data read request, a listening operation is performed on at least one target cache. The listening operation is used to detect whether the target data is stored in the target cache, which is a pre-defined cache. If the target data is stored in the target cache, the target data is read from the target cache and sent to the first core.

[0007] According to one aspect of the embodiments of this application, a data reading device for use in a processor is provided, the processor including multiple cores, the device comprising: The receiving module is used to receive a data read request sent by the first core among the plurality of cores, wherein the data read request is used to request the reading of target data; A listening module is used to perform a listening operation on at least one target cache after receiving the data read request. The listening operation is used to detect whether the target data is stored in the target cache, and the target cache is a pre-set cache. The reading module is configured to read the target data from the target cache if the target data is stored in the target cache, and send the target data read from the target cache to the first core.

[0008] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-described data reading method.

[0009] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and the computer program is loaded and executed by a processor to implement the above-described data reading method.

[0010] According to one aspect of the embodiments of this application, a chip is provided, the chip including programmable logic circuits and / or program instructions, which, when the chip is running, are used to implement the above-described data reading method.

[0011] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program, the computer program being loaded and executed by a processor to implement the above-described data reading method.

[0012] The technical solution provided in this application can bring the following beneficial effects: By receiving a data read request from the first core among multiple cores, a listening operation is directly performed on at least one target cache to detect whether the target data is stored in the target cache. If the target data is stored in the target cache, it is read from the target cache and sent to the first core, providing a shorter path to obtain the target data. This technical solution can directly provide data when the target data is stored in the target cache, reducing additional query overhead and latency, thereby accelerating the data reading speed. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a multi-core processor provided in one possible implementation of related technologies; Figure 2 This is a schematic diagram of a multiprocessor system provided in one possible implementation of related technologies; Figure 3 This is a schematic diagram of a data reading method provided in one possible implementation of the related technology; Figure 4 This is a flowchart of a data reading method provided in one possible implementation of this application; Figure 5 This is a schematic diagram of a directory unit provided in one possible implementation of this application; Figure 6 This is a schematic diagram of a data reading method provided in one possible implementation of this application; Figure 7 This is a structural block diagram of a data reading device provided in one possible implementation of this application; Figure 8 This is a structural block diagram of a computer device provided in one possible implementation of this application. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0016] Before introducing the technical solution proposed in this application, the relevant technical background and related technologies will be briefly described below.

[0017] This application relates to multi-core processor architecture. With the development of semiconductor technology, multi-core processors have become the mainstream architecture for improving computer system performance. A multi-core processor refers to a processor that integrates two or more cores within a single physical package (e.g., a single chip), each capable of executing instructions independently. Each core typically contains its own cache for temporarily storing frequently accessed data, reducing latency caused by accessing slower memory (e.g., DRAM). Furthermore, in current computer systems, besides multi-core processor architectures within a single chip, there are also system architectures composed of multiple processors, such as multi-processor servers and multi-processor workstations. In these multi-processor system architectures, each processor typically also has its own cache, and different processors can be connected via system-level inter-chip interconnect networks (e.g., QPI (Quick Path Interconnect), UPI (Ultra Path Interconnect)). In summary, whether it's a multi-core processor architecture or a multi-processor system architecture, each core and / or each processor's corresponding cache may contain data at the same memory address. Because each cache is independent and can perform read and write operations concurrently, the lack of a coordination mechanism can lead to inconsistencies in the data stored at the same memory address in different caches, resulting in program errors or system anomalies. Therefore, regardless of the specific architecture, caches must meet the cache coherency requirement, which guarantees that at any given time, data at the same memory address should remain consistent across all caches and memory, and that access to that data should follow a predetermined state protocol.

[0018] For example, please refer to Figure 1 , Figure 1 This is a schematic diagram of a multi-core processor provided in one possible implementation of related technologies. For example... Figure 1 As shown, the basic architecture of a multi-core processor may include: 1. Cores and Caches: The processor integrates multiple cores (such as core 0 to core n), and each core has a corresponding cache (such as cache 0 to cache n). The cache is used to temporarily store frequently accessed data to reduce the latency of accessing main memory.

[0019] 2. On-chip interconnect: The core communicates with the cache, consistency agent unit, directory unit and memory through the on-chip interconnect to realize the transmission of data and control signals.

[0020] 3. Consistency Proxy Unit and Directory Unit: The consistency proxy unit is responsible for maintaining cache consistency. It obtains data location information by querying the directory unit and coordinates data read and replace operations. The directory unit records the current location of data (e.g., in a core's cache or in memory) and is a key structure for achieving cache consistency. Furthermore, when data is loaded into the cache or replaced, the consistency proxy unit can update the location information of that data recorded in the directory unit to maintain cache consistency.

[0021] 4. Memory: Used to store large amounts of data and instructions, it is the largest storage medium in the processor but has a relatively slow access speed. When the core needs to access certain data, if the data is not in its corresponding cache (i.e., a cache miss), it needs to be read from memory and loaded into the cache for subsequent fast access.

[0022] Figure 1 In actual operation, not all cores of the multi-core processor shown are at full load (cores under load are called loaded cores). Related technologies utilize the caches of idle cores (called idle cores) to temporarily store data that the caches of loaded cores cannot store. In this way, when a core in the processor needs to use the data, it can quickly read it from the cache instead of from memory. Specifically, the above process can include the following two stages: 1. Cache Replacement Phase: When a load-bearing core needs more data to execute tasks and its corresponding cache is full, a cache replacement will be performed, and the replaced data will be sent to the consistency broker unit. The consistency broker unit can write this data into the cache of a specified idle core according to the register configuration. For example... Figure 1 As shown, assuming the working core is core 0 (corresponding to cache 0) and the idle cache is cache 1 (corresponding to cache 1), when replacing data, cache 0 of core 0 can send the data to the consistency broker unit through the on-chip interconnect network, and then the consistency broker unit writes it into cache 1, thus completing the temporary storage of data in the idle core cache.

[0023] 2. Data Reading Phase: Due to the spatial locality of the program, the load core is highly likely to reread previously replaced data during subsequent execution. At this time, the read request issued by the load core can be sent to the consistency proxy unit. The consistency proxy unit learns from the directory unit that the data is currently located in cache 1, and then initiates a listening operation to retrieve the data from cache 1 and return it to the load core, thereby avoiding the high latency caused by direct memory access.

[0024] For example, please refer to Figure 2 , Figure 2This is a schematic diagram of a multiprocessor system provided in one possible implementation of related technologies.

[0025] Figure 2 The multiprocessor system 200 shown includes multiple independent processors (i.e., processors 210, 220, 230, etc. in the figure), a cache corresponding to each processor (i.e., cache 211, cache 221, cache 231, etc. in the figure), a consistency proxy unit, and a directory unit, and communicates through an inter-chip interconnection network. In some embodiments, Figure 1 The core mechanisms illustrated (i.e., the cache replacement phase and data read phase described above) are also applicable in multiprocessor systems, but extended to cross-processor collaboration scenarios. Specifically, in a multiprocessor environment, each processor has its own cache and coherence proxy unit, and data may be shared or copied across the caches of multiple processors. When a processor needs to replace data, its coherence proxy unit needs to collaborate with the coherence proxy units of other processors to ensure cached data consistency. In this scenario, the cache replacement phase and data read phase still apply, but cross-processor communication is required via an inter-chip interconnect network. For example, in a multiprocessor system, when processor 210's cache 211 is full and needs to replace data, its coherence proxy will migrate the data to the cache of another idle processor (e.g., processor 220's cache 221) according to register configuration. It is noteworthy that this process requires cross-processor communication via an inter-chip interconnect network, rather than just data transfer between cores within a single chip; during the data read phase, when processor 210 needs to read data from the caches of other processors, it sends a request to the coherence proxy unit. The consistency proxy unit can query the directory unit to find out that the data is currently stored in the cache 221 of the processor 220, and then initiate a listening operation through the inter-chip interconnect network to retrieve the data from the cache 221.

[0026] In summary, regardless of multi-core processors (such as...) Figure 1 (as shown) or in a multiprocessor system (such as...) Figure 2 As shown in the diagram, any technical solution that utilizes the cache of idle cores or processors to temporarily store data from the loaded cores or processors, and then quickly retrieves that data during subsequent accesses via a listening mechanism, is applicable. The core principle is to reduce direct memory access and improve data access efficiency by temporarily storing potentially reused data in the idle cache, while maintaining cache consistency.

[0027] It is worth noting that the related technologies and the technical solutions of this application are all illustrated using data reading in a multi-core processor environment as an example. The technical solutions and related technologies of this application are also applicable to multi-processor systems, but to avoid repetition, the specific implementation details in the multi-processor system environment will not be repeated.

[0028] For example, please refer to Figure 3 , Figure 3 This is a schematic diagram of a data reading method provided in one possible implementation of related technologies.

[0029] In related technologies, regarding the data reading phase, specifically when the target data to be read does not exist in the core's local cache, how can... Figure 3 The data reading method shown acquires the target data. Specifically, it may include at least one of the following steps: 1. The first core initiates a request to read the target data.

[0030] 2. The consistency proxy unit receives read requests. The consistency proxy unit can receive read requests for target data initiated by the first core through the on-chip interconnect network.

[0031] 3. Parallel execution of directory unit queries and memory read operations: Consistent agent units can query directory units or read memory in parallel to determine the cache for temporarily storing target data or to directly retrieve target data from memory.

[0032] 4. Send target data to the first core: Once the target data is found (whether from the cache or memory), it will be returned to the first core.

[0033] It is worth noting that querying the directory unit is typically faster than reading data directly from memory. In practice, if the directory query hits the cache, the cache containing the target data can be quickly located; if the query misses, it is still necessary to fall back to reading data from memory. Therefore, in related technologies, querying the directory unit is a necessary step in the data reading phase. On the other hand, the consistency proxy unit and the directory unit are physically two independent modules. In a real chip layout, communication between them often requires a latency of tens of nanoseconds, and this latency will fluctuate due to the varying distances between the directory unit and the consistency proxy unit.

[0034] Therefore, the relevant technologies have the following problems: First, directory unit lookup is a necessary step in the data reading phase; that is, regardless of whether the cache is hit, the storage location of the target data must first be confirmed through the directory unit. Second, the physical independence of the directory unit and the consistency proxy unit leads to a significant latency in their communication. In summary, because the directory unit needs to be queried, latency is inevitably introduced into the data reading process, ultimately slowing down the data reading speed.

[0035] To address the aforementioned issues, this application provides a data reading method for use in a processor. It is worth noting that the processor includes multiple cores.

[0036] In one aspect of this embodiment, a processor refers to a hardware unit with complete or partial computational and control functions, such as instruction fetching, decoding, execution, memory access, and control flow management, capable of completing program tasks independently or in a multi-core collaborative mode. A core refers to a basic computational unit within the processor capable of independently executing instruction flows. It may possess necessary components such as an independent PC (Program Counter), register set, control unit, and ALU (Arithmetic Logic Unit), and can execute different threads or tasks in parallel and / or serially under a certain scheduling mechanism. A processor may consist of one or more cores, and the cores can communicate and cooperate with each other through shared cache, bus, interconnection network, etc. Exemplarily, the form of the processor and cores may vary depending on factors such as architecture and application scenario. Specifically, it may include, but is not limited to, the following forms: 1. Single-chip multi-core processor: Multiple cores can be integrated on the same silicon chip, such as a multi-core CPU (Central Processing Unit). The CPU cores can share resources such as on-chip cache and memory controller.

[0037] 2. Heterogeneous multi-core processors: Different types of cores are integrated within the same processor chip, such as a combination of high-performance cores and high-efficiency cores, or a CPU core plus a GPU (Graphics Processing Unit) core, a DSP (Digital Signal Processing) core, an AI (Artificial Intelligence) acceleration core, etc., to balance performance and power consumption.

[0038] 3. Multi-Chip Module (MCM) processor: Multiple cores can be distributed on different chips and interconnected at the package level (such as silicon interposer, organic substrate) to form a single logic processor. It is commonly found in high-end server or accelerator products.

[0039] 4. Distributed multiprocessor system: Multiple independent processors (each processor may contain a single core or multiple cores) can be connected through an interconnect network or a dedicated interconnect structure (such as PCI-Express (peripheral component interconnect express, a high-speed serial computer expansion bus standard) or NoC (network-on-chip) to present a multi-core / multiprocessor environment at the operating system level.

[0040] 5. Multi-core subsystem in SoC (System on Chip): In a system on a chip, the processor can exist as a subsystem of the SoC, containing multiple cores and working in conjunction with other modules such as GPU and ISP (Internet Service Provider).

[0041] 6. Mapping of logical cores and physical cores in a virtualized environment: In processors that support hardware virtualization, one physical core can be represented as multiple logical cores, allowing multiple virtual machines or processes to share execution resources.

[0042] It is worth noting that regardless of the specific form in which the processor and cores are implemented, as long as they meet the basic characteristic that "a processor contains multiple cores capable of independently executing instruction streams," and each core can participate in data reading, instruction execution, and control flow management under the unified coordination or independent scheduling of the processor, they all fall within the scope of "a processor including multiple cores" as defined in this application. The scope of protection of this application is not limited to a specific number of cores, arrangement, integration process, or interconnection architecture, nor is it limited to the physical or logical organization of the processor and cores. Any hardware structure and related methods capable of realizing multi-core concurrent or cooperative execution functions fall within the scope of protection of this application.

[0043] For example, please refer to Figure 4 , Figure 4 This is a flowchart of a data reading method provided in one possible implementation of this application. The data reading method may include at least one of the following steps 410 to 430.

[0044] Step 410: Receive a data read request sent by the first core among multiple cores. The data read request is used to request the reading of target data.

[0045] In one aspect of this embodiment, the first core refers to the core among the multiple cores included in the processor that is currently executing a task and needs to read target data. The first core may have an independent PC, register set, control unit, and arithmetic unit, and can independently complete the execution of the instruction stream under the scheduling of the processor, and cooperate with other cores through shared resources or interconnection networks.

[0046] In one aspect of this embodiment, target data refers to the data content that the first core needs to access during the execution of the current task. Its specific form can be scalar data, vector data, structure, array elements, or any information that can be loaded into registers or used in calculations. For example, the storage location of the target data can include: 1. Directly stored in the cache corresponding to the first core; 2. Temporarily stored in the cache of other cores during the cache replacement phase: when a cache coherence protocol exists between multiple cores, the target data may be stored in the cache of other cores due to replacement or migration; 3. Stored only in memory: if the target data is not hit by any core cache, it is stored only in memory. Here, memory refers to a persistent or non-persistent storage medium accessible to the processor. Specifically, the form of memory can include, but is not limited to: 1. ROM (Read Only Memory), where data stored in ROM can only be read and not written, and the data will not be lost even if the machine is powered off; 2. RAM (Random Access Memory), where data can be read from and written to. When the machine power is turned off, the data stored in it will be lost; 3. DRAM (Dynamic RAM), DRAM has a simpler structure and higher integration, and is usually used to manufacture memory chips in memory modules. It is worth noting that the above description of the specific types, characteristics and application scenarios of memory is only illustrative and is not intended to limit the scope of protection of this application. Any memory unit that can be used to store data and can complete data transfer and access in a multi-core processor through the processor's memory access path, cache coherency mechanism or interconnection network, or other memory media that can be directly or indirectly accessed by the processor core, falls within the scope of protection of this application.

[0047] In one aspect of this embodiment, during specific execution, when the first core needs to read target data, it typically follows a local-first-external search strategy, that is, it first attempts to read the target data from its own cache; if the target data is not found in the cache (i.e., cache miss), the first core generates a data read request and sends it to the controller. It is worth noting that the specific content of the data read request can vary depending on the system design and consistency protocol. For example, it may include at least one or more of the following information: 1. The memory address of the target data: The memory address is the identifier of the target data's storage location in memory. By carrying the memory address of the target data in the request, the controller can directly locate the memory or determine whether the target data is temporarily stored in a core's cache; 2. Identification information of the target data: For example, the target data's tag, hash value, or other key fields that can be used for matching in the cache directory or memory mapping table. The above form can achieve querying in scenarios that do not expose the physical address and is suitable for address abstraction, security isolation, or multi-tenant environments; 3. Optional additional metadata: such as timestamps, transaction sequence numbers, priority markers, etc., which can assist in sorting, deduplication, or debugging tracing in multi-core high-concurrency environments. In summary, the specific form of a data read request can at least include a request sent based on the memory address of the target data. This method has high positioning accuracy because the address and data storage location correspond one-to-one. Furthermore, it can include the target data's identification information and possible additional metadata to meet the needs of different system architectures and consistency protocols. It is worth noting that any data read request containing valid information that can be used to locate or query the target data, and sent by the first core to the controller when its own cache misses, falls within the protection scope of this application.

[0048] In one aspect of this embodiment, the aforementioned controller refers to a hardware module and / or logic unit for receiving data read requests sent by the core. Exemplarily, the unit capable of receiving data read requests may include, but is not limited to: 1. Memory controller: The memory controller is responsible for managing data transfer and address mapping between the processor and system memory, and can receive data read requests from the core; 2. Interconnect arbitrator: In the interconnect structure of a multi-core or multi-processor system, the interconnect arbitrator is used to receive and arbitrate access requests from different cores or modules, including data read requests, and forward them to the target node; 3. Bus Interface Unit (BIU): The BIU is a module connected to the system bus, responsible for sending and receiving bus transactions, and has the ability to receive data read requests from the core; 4. Consistency proxy unit: In a cache consistency protocol, the consistency proxy unit can receive data read requests issued by the core and parse and forward them; 5. DMA (Direct Memory Access) controller: The DMA controller can receive transfer requests from the core or peripherals, including data read requests sent by the first core.

[0049] It is worth noting that the specific implementation of the aforementioned controller can vary depending on the processor architecture, interconnection method, and system design, and can also be composed of multiple sub-modules. In this embodiment, a consistency proxy can be used as the controller to receive the first core data read request, but any module capable of receiving data read requests can serve as the aforementioned controller. Any hardware module or logic unit capable of receiving data read requests, regardless of its specific implementation, location, or cooperation method with other functional units, falls within the protection scope of this application as long as it has the ability to receive the aforementioned requests.

[0050] Step 420: After receiving a data read request, perform a listening operation on at least one target cache. The listening operation is used to detect whether the target cache stores the target data. The target cache is a pre-defined cache.

[0051] In one aspect of this embodiment, the target cache is a pre-defined cache. The target cache is characterized in that its selection and determination do not rely on querying directory units, mapping tables, or other intermediate units after receiving a data read request; instead, it can be directly obtained and used as a listening object upon receiving the request. Specifically, the target cache can be determined based on static and / or dynamic information configured by the processor during operation. This information can be directly provided to the unit performing the listening operation when a data read request arrives, thereby avoiding additional query processes. Exemplarily, the aforementioned information may include, but is not limited to: 1. Register Configuration Information: During the cache replacement phase, the processor can designate a core's cache as a temporary storage location for data based on configuration information pre-written into specific registers. This register configuration information can be updated during system initialization or runtime and can be directly read by the execution unit of the listening operation to immediately determine one or more target caches to be listened to upon receiving a data read request.

[0052] 2. Pre-defined target cache information: The execution unit of the listening operation can pre-store the identifiers and / or address ranges of certain core-related caches during the design or configuration phase, so that these caches can be directly included in the listening scope without querying when a data read request arrives. For example, caches that frequently participate in data sharing can be set as target caches.

[0053] 3. Other directly available determination methods: such as fixed mapping relationships written by firmware or boot code during system construction, fixed associated cache sets determined by hardware connections, or candidate cache lists directly derived from task scheduling information. These methods also allow the unit performing the listening operation to directly know the target cache after receiving a data read request, without having to query modules such as the directory unit.

[0054] Therefore, the above-described method for determining the target cache ensures that the unit performing the listening operation can immediately execute the listening operation upon receiving a data read request, without first querying other units. This reduces access latency and avoids the additional control overhead and delay caused by the query process. It is worth noting that the above-described method for determining the target cache is merely an illustrative example; any cache that can be directly used as the listening object after receiving a data read request falls within the protection scope of this application.

[0055] In one aspect of this embodiment, the listening operation is used to detect whether target data is stored in the target cache. Essentially, it is a judgment process; it does not directly read the target data from the target cache, but rather confirms whether the target data exists in the target cache. For example, the above judgment process can employ one or more of the following execution methods based on the information carried in the data read request and the organization method of the target cache: 1. Memory Address Based: When a data read request includes the memory address of the target data, the unit performing the listening operation can send an address matching signal to the target cache or perform parallel comparisons in the tag array of the target cache. The target cache typically stores address tags corresponding to the data it contains. A match can be determined by comparing these address tags with the memory address in the data read request. If a match is found, it is determined that the target cache stores the target data; otherwise, it is determined that the data does not exist.

[0056] 2. Based on target data identification information: If the data read request carries the target data's identification information (such as data tags, hash values, etc.), the listening operation can search for records matching the aforementioned identification information in the target cache's directory or index structure. This method can be used in systems that do not expose physical addresses (such as virtualized or securely isolated environments) to determine whether data is temporarily stored in the target cache through identifier matching.

[0057] 3. Cache State Broadcasting and Response: In consistency protocols (such as MESI (Modified, Exclusive, Shared, Invalid) and MOESI (Modified, Owned, Exclusive, Shared, Invalid)), a snooping operation can broadcast a request for information (such as an address or identifier) ​​to the target cache via the interconnection network. The target cache can then return a "hit" or "miss" response based on its stored data. This process is a typical snooping mechanism that can quickly collect the status of each cache at the hardware level without polling each entry individually.

[0058] 4. Hybrid approach: The above methods can be combined. For example, first, the tags can be quickly matched locally based on the data reading request. If no match is found, then consistent listening can be performed through interconnect broadcast to improve the detection success rate while also considering efficiency.

[0059] It is worth noting that any process that can directly perform a judgment on the target cache to detect whether the target data is stored therein after receiving a data read request falls within the protection scope of this application.

[0060] In one aspect of this embodiment, the unit performing the listening operation refers to a hardware module or logical function block that can perform a listening operation on the target cache after receiving a data read request. Exemplarily, the above-mentioned unit may exist in forms including, but not limited to: 1. A consistency proxy unit: In a cache consistency protocol, the consistency proxy unit has the ability to receive data read requests and can also perform a listening operation on the target cache to determine whether the target data is stored in these caches. In this case, the consistency proxy unit can perform both request receiving and listening functions, thereby reducing cross-module interaction and lowering access latency; 2. Bus listening logic: In a bus-based architecture system, the bus listening logic is distributed throughout the bus and can listen for address or identification information on the bus and perform corresponding listening operations; 3. Other dedicated or integrated logic: For example, a listening function module integrated into an interconnect router, consistency engine, or on-chip network controller can also directly perform a listening operation on the target cache after receiving a data read request. In this embodiment, the consistency proxy unit can perform both request receiving and listening operations, or it can be performed by an independent or integrated listening control unit. It is worth noting that the unit that performs the listening operation can be any hardware module or logical function block that performs the listening operation on the cache. As long as the hardware module or logical unit that can perform the listening operation on the target cache falls within the protection scope of this application.

[0061] Step 430: If the target cache contains target data, then read the target data from the target cache and send the target data read from the target cache to the first core.

[0062] In one aspect of this embodiment, when the monitoring result indicates that target data is stored in one or more target caches, the execution unit needs to have a corresponding mechanism to ensure that correct and consistent target data is sent to the first core. Specifically, if target data is obtained from only one target cache, it can be directly sent to the first core, since a single source does not involve cross-cache consistency issues; if target data is obtained from multiple target caches, the execution unit needs to determine the final data source to be sent to the first core to avoid the first core obtaining incorrect or expired target data due to data inconsistency.

[0063] For example, the above mechanism can be implemented based on factors such as cache status information, data version information, or predefined priority strategies. Specifically, different execution units can adopt different judgment methods, such as: 1. The consistency proxy unit can determine which target cache holds the latest or has the highest privileges for the target data based on the status field of the cache consistency protocol. For example, it can prioritize target data in the modified state or target data in the exclusive state, and then send it to the first core; 2. The cache controller can select the target data that has been recently written or has not been marked as invalid for reading and sending when it receives target data from multiple target caches, based on the cache replacement order or recent use information recorded locally; 3. The bus interface unit can select target data that meets the permission and consistency requirements from the target data returned by multiple target caches and send it to the first core based on the bus transaction priority or the initiator's access permissions; 4. The processing unit in the first core can also independently complete the judgment and selection for different data sources after receiving target data from multiple target caches, and provide the finally selected target data to the first core. In summary, the unit that reads and sends target data can be any hardware module or logical function block capable of performing the above actions, and its specific form depends on the system architecture and consistency protocol.

[0064] It is worth noting that any hardware module or logic unit capable of reading target data and sending it to the first core when the target data is stored in the target cache falls within the protection scope of this application.

[0065] By directly performing a listening operation on at least one target cache after receiving a data read request from the first core among multiple cores, to detect whether the target data is stored in the target cache, and if the target data is stored in the target cache, reading the target data from the target cache and sending it to the first core, a shorter path to obtain the target data is provided, reducing additional query overhead and latency, thereby speeding up the data reading speed.

[0066] In some embodiments, the data of the first core is stored in at least one target cache based on register configuration information. The register configuration information is used to indicate at least one target cache.

[0067] In one aspect of this embodiment, the processor can store the data of the first core into at least one target cache based on register configuration information. Specifically, when the first core needs to cache data, the cache controller can first attempt to store the data into the first core's local cache (i.e., the cache corresponding to the first core). If the local cache is not full and / or there are still available entries, it can be directly stored in the local cache. However, if the local cache is full, the cache line is locked, or the cache consistency policy prohibits writing to the current cache entry, causing the relevant data of the first core to be unable to be directly written to the local cache, the cache controller can determine other caches available for storage, i.e., target caches, based on the register configuration information.

[0068] In one aspect of this embodiment, the core function of the register configuration information is to indicate at least one target cache. Its specific content and format can be flexibly defined according to the system design, as long as this function can be achieved. For example, the register configuration information may include the target cache's identification information (e.g., cache index, cache number, or mapping relationship with physical / logical cache units) and the target cache's attribute information (e.g., cache level, core to which it belongs). In other implementations, the register configuration information may also include the target cache's grouping information or policy parameters. By parsing this information, the set of caches that can be used as target caches can be indirectly determined. After reading the register configuration information, the cache controller can determine one or more target caches that are allowed to be written to. Subsequently, the cache controller can send information carrying the data address (i.e., the data's memory address or other related address) and an instruction to write to the control logic where the target cache resides via the on-chip interconnect network. Upon receiving the message, the control logic where the target cache resides can trigger a read request for the data, read the data from the local cache or memory of the first core, and store the read data into its own cache array. The above process is equivalent to migrating data from the first core to the target cache specified by the register configuration information during the cache replacement phase, thereby realizing temporary storage or multiple copy distribution of data (i.e., data with the same memory address is stored in multiple caches).

[0069] In one aspect of this embodiment, register configuration information can be written by software or firmware into the corresponding registers and the unit used to perform the listening operation (such as the aforementioned consistency proxy unit) during system initialization or runtime. This allows the aforementioned unit to directly obtain relevant information about the target cache by reading the register configuration information. The methods for obtaining the register configuration information may include register access mechanisms such as directly reading the register address or accessing the register image region through the internal bus. On the other hand, in addition to the identifier and attributes of the aforementioned target cache, the register configuration information may also include optional storage strategy parameters, such as whether multi-location storage is allowed, or whether to prioritize writing to a specific target cache, so as to flexibly adjust data distribution and consistency behavior in specific scenarios.

[0070] It is worth noting that regardless of the specific form of indication content contained in the register configuration information, as long as it can be used to indicate at least one target cache, the function protected by the embodiments of this application is achieved. Therefore, any implementation that indicates at least one target cache based on register configuration information falls within the protection scope of this application.

[0071] On the one hand, since the data that needs to be temporarily stored in other core caches during the cache replacement phase is executed based on register configuration information, the target cache stores a large amount of data from other cores. Furthermore, due to spatial locality, the cores are highly likely to access this data again during subsequent execution. On the other hand, register configuration information can be stored in the unit executing the listening operation during system initialization or runtime. This allows the unit to directly perform a listening operation on the target cache after receiving a data read request, even without querying the directory unit. Based on this mechanism, the listening operation can maintain a high probability of successful data reads without querying the directory unit, thereby improving data read speed while ensuring data read accuracy.

[0072] In some embodiments, if the target cache stores target data and the target data is in an exclusive state, then the target data is read from the target cache and sent to the first core. Here, "exclusive state" means that the target data is stored in only one cache.

[0073] In one aspect of this embodiment, if the target cache stores target data and the target data is in an exclusive state, the target data is read from the target cache and sent to the first core. Here, the exclusive state refers to the state where the target data is stored in only one cache. In this state, data modification and access do not require synchronous broadcasting with other cores. Specifically, in typical consistency protocols (such as MESI, MOESI, etc.), the states of data in the cache typically include exclusive, shared, modified, and invalid states. The exclusive state indicates that the data exists only in a single cache and is consistent with the main memory; the core holding the exclusive state can directly modify the data without notifying other cores. The shared state indicates that the data may exist in multiple caches simultaneously; any modification to the data must be broadcast synchronously through a consistency protocol to ensure that all sharing parties have access to the data. Figure 1The fundamental reason why the target data can only be directly read and returned when it is in an exclusive state in this application embodiment is that the listening operation in this application embodiment is essentially an expectation of the exclusive state of the data—that is, it hopes to directly obtain the target data that exists only in a single cache through the listening operation, so as to avoid the overhead and latency caused by directory unit query and / or multi-core synchronization. Conversely, the target data in the shared state cannot support the above listening operation. The fundamental reason is that the current consistency processing logic cannot correctly complete the state transition in the shared state. Specifically, the shared state involves broadcast synchronization between multiple cores (the target data may be held by multiple caches at the same time), while the listening mechanism is only designed for the exclusive state (the target data exists only in a single cache) and does not have the complex synchronization and conflict resolution capabilities required to handle the shared state. If the listening operation is rashly executed in the shared state, it may cause the first core to read the expired target data or cause a consistency error.

[0074] In this embodiment, the determination of data status can be collaboratively completed by the cache controller. The cache controller is a functional unit in a multi-core processor responsible for managing cache data access and consistency control. Specifically, the cache controller may exist in forms including, but not limited to: 1. Each cache is independently equipped with a cache controller, achieving a one-to-one correspondence between the cache and the controller; 2. Multiple caches share a single cache controller, which uniformly schedules the access and status maintenance of each cache; 3. A centralized cache controller is set up at the processor level to centrally manage and monitor the status of all caches in the system. It is worth noting that regardless of the specific implementation, there is a management and managed relationship between the cache controller and the cache: the cache controller can receive access or other requests from the core and / or other functional units (e.g., units that receive data read requests), and perform operations such as data read / write, status updates, and consistency responses based on the internal storage status and status identifier of the cache. In this embodiment, the cache controller can be used to determine the data status of target data. For example, if the target data is stored in the target cache and its data status is exclusive, the cache controller can invalidate the target data in the target cache and return the target data to the first core that initiated the data read request, thereby completing a fast read. Conversely, if the target data is not in an exclusive state, the cache controller can return a read failure signal, thereby triggering the system to use the original data read process for processing.

[0075] It is worth noting that the cache controller in the above embodiments is merely an illustrative example and is not intended to limit the scope of protection of this application. In fact, any functional unit capable of determining the data state of target data, regardless of its specific hardware implementation, name, or deployment method, should be considered within the scope of the cache controller described in this application. For example, this functional unit can be an independent hardware module, control logic integrated within the cache, a state monitoring circuit within the processor, a state determination component in a distributed listening node, or a determination logic implemented collaboratively by software and hardware. As long as it can achieve the technical solution of detecting the data state in the embodiments of this application and directly returning the data when the data state is exclusive, it falls within the scope of protection of this application.

[0076] By further detecting whether the target data is in an exclusive state when it is stored in the target cache, the validity of the target data can be directly determined. Since an exclusive state means the target data is stored only in one target cache and is consistent with the data content in memory, this target cache can directly send the target data to the first core without worrying about the target data being modified or invalidated in other cores. Based on this mechanism, the system does not need to rely on subsequent units to perform additional screening and validity verification on the returned target data, avoiding corresponding processing overhead and latency, thereby significantly improving data reading efficiency.

[0077] In some embodiments, after reading target data from the target cache and sending the target data read from the target cache to the first core, the method further includes: changing the data state of the target data from an exclusive state to a non-exclusive state. Here, the non-exclusive state refers to a state where the target data is stored in at least two caches.

[0078] In one aspect of this embodiment, the non-exclusive state refers to the state in which the target data is stored in at least two caches. In the cache coherence protocol, the non-exclusive state is used to indicate that there are multiple valid copies of data at the same memory address in the system. These copies are stored in different caches, and any modification or access to the data must follow the synchronization and broadcast rules specified in the coherence protocol to ensure that the copies in each cache (i.e., the data at the same memory address) remain consistent.

[0079] In one aspect of this embodiment, the data state of the target data is modified because after the target data is sent from the target cache to the first core, the target data actually exists in at least two caches—that is, both the original target cache and the first core's cache hold the data, and its storage range has changed. Therefore, the data state should naturally change from exclusive to non-exclusive. On the other hand, after receiving the target data, the first core may read, modify, or perform other operations on it, causing the copy of the data in the original target cache to no longer represent the latest valid data. In this embodiment, in order to read data directly from the target cache without querying a directory unit, specific data state conditions must be met, namely, the data must be stored in only a single cache and not held by other caches, to ensure that the read data is the latest and only available data. For example, once the target data is sent to the first core, the above conditions no longer hold. Specifically, the target data is no longer solely stored in the original target cache and may generate new data due to the processing of the first core. If, while the target data's data state is still exclusive, other cores subsequently attempt to access the original target cache through the path without querying a directory unit, inaccurate target data may be read, leading to runtime errors and other problems.

[0080] In one aspect of this embodiment, after the target data read from the target cache is sent to the first core, as long as the target data no longer meets the condition of being read through a path without querying a directory unit, the data state of the target data can be changed to any suitable state, such as a non-exclusive state, an invalid state, or other data states indicating that the data can no longer be directly accessed through that path. For example, the target data can be marked as invalid, so that any subsequent access to the data must go through a directory unit query or other consistency confirmation process, thereby avoiding directly reading potentially outdated or inconsistent data. On the other hand, the unit performing the above state change operation is not limited to the cache controller. Any functional unit that can modify the data state to prevent subsequent reading of the original data through a path without querying a directory unit after data transmission, based on the current data storage status and access requirements, can achieve the technical effect of this application. The aforementioned functional unit can be a controller independent of the cache, logic circuits integrated within the cache, a state management module within the processor, a state update component in a distributed consistency node, or a judgment and modification logic implemented by hardware and software collaboration. As long as it can implement the technical solution proposed in this application, it falls within the protection scope of this application.

[0081] By changing the data state from exclusive to non-exclusive after reading data from the target cache and sending it to the first core, the system can accurately reflect the current actual storage status of the data—that is, the data already exists in at least two caches. On the one hand, this mechanism avoids reading old data that may have been held or modified by other cores during subsequent data reads. On the other hand, it ensures that during subsequent data reads, relevant units can correctly identify the data as non-exclusive, thereby triggering necessary synchronization or verification processes, ensuring the accuracy of data reads and cache consistency in multi-core processor architectures.

[0082] In some embodiments, after receiving a data read request, the directory unit is queried to determine the storage location of the target data. The directory unit records the storage location of at least one piece of data. The target data is read according to its storage location. If no target data is detected in the target cache, the target data read from the directory unit is sent to the first core.

[0083] In one aspect of this embodiment, the directory unit is used to centrally record the distribution of data across multiple caches and / or memory. The core function of the directory unit is to store the storage location information of at least one piece of data, so that when data access or consistency maintenance is required, it can be determined which caches or storage entities currently hold the data. Specifically, the information recorded by the directory unit may include, but is not limited to: 1. Data identifier: Used to identify the memory address, tag, or key value of data so that read requests can be mapped to the corresponding directory entries.

[0084] 2. Cache list: Used to record which caches currently contain copies of data, and may include cache number, cache index, or association identifier with the cache controller.

[0085] 3. Data status information: such as the exclusive state, shared state, invalid state, etc., are used to describe the consistency status of data in each cache to determine the access strategy and synchronization method.

[0086] 4. Storage location details: In addition to cache-related indications, it may also include indications of whether the data resides in memory, disk or other storage units to support cross-level access.

[0087] 5. Timestamp information: can identify the update order or storage time of data in cache and / or memory.

[0088] 6. Access permissions: Used to indicate whether data is being used by a single core or is being read, in order to avoid cache inconsistency issues caused by concurrent access from multiple cores.

[0089] For example, please refer to Figure 5 , Figure 5 This is a schematic diagram of a directory unit provided in one possible implementation of this application. Figure 5 The directory unit 500 shown stores data storage location information in the form of entries. Specifically, the directory unit 500 records the following three types of information: 1. Data Address: The data address is used to record the address of the data in memory (i.e., the memory address), which is used to determine the source or original storage location of the data. For example, if the data is stored at memory address 0x1000, then this field should be filled with 0x1000.

[0090] 2. Temporary Storage Location: The temporary storage location is used to record the cache number or identifier currently storing the data, which is used to identify the cache location of the data. For example, if cache 1 (numbered 1) holds the data, then this field is filled with 1; if the data is held by both cache 1 and cache 2, it may need to be expanded into multiple fields or multiple entries.

[0091] 3. Data Status: Data status indicates the consistency state of the data (e.g., exclusive, shared, invalid, etc.) and is used to determine the access strategy or synchronization method. For example, if the data is currently in an exclusive state, enter EXCLUSIVE; if it is in a shared state, enter SHARED.

[0092] It is worth noting that, Figure 5 The directory unit shown is merely an illustrative example. Its specific structure and stored information can be adjusted according to actual needs. For example, a timestamp field can be added for conflict detection or consistency verification. It can also be expanded into a multi-level directory to support larger-scale multi-core processor architectures, and can be optimized into a compressed format to reduce storage overhead. The definition of a directory unit is that as long as a component can record the storage location information of at least one piece of data, regardless of its specific format or additional information, it meets the definition of a directory unit in this application. For example, hardware-implemented register groups or lookup tables, software-managed hash tables or databases, and consistency protocol modules in distributed systems can all serve as directory units that implement this function and fall within the protection scope of this application.

[0093] In one aspect of this embodiment, the storage location of the target data can be determined by querying the directory unit, and the target data can be read using various methods based on the aforementioned storage location information. For example, it can be done using... Figure 5Taking the directory unit shown as an example: by querying the data address field, the address of the target data in memory can be directly obtained, thus enabling direct reading of the data from memory; by querying the temporary storage location field, it can be directly determined which caches store the target data, and combined with the data status field, it can be determined whether the data meets the requirements for direct reading under the current cache consistency protocol. If the requirements are met, the target data can be directly read from the corresponding cache, and the corresponding temporary storage location and data status information in the directory unit are updated to reflect the distribution after reading. It is worth noting that the above two data reading paths are only illustrative examples. The actual data reading method is not limited to reading from memory through the data address or reading from the cache through the temporary storage location. Other location information or additional fields recorded in the directory unit (such as timestamps, multi-level directory indexes, etc.) can also be used to determine the storage level and holder of the data, and accordingly select to read the target data from remote nodes or other consistency domains. The specific reading strategy and subsequent consistency processing flow can also be determined by combining data status and permission information. In summary, any technical solution that successfully reads target data by querying a directory unit and based on the storage location information of the target data recorded in that directory unit, regardless of the specific path, level, or additional judgment conditions used, falls within the protection scope of this application.

[0094] In one aspect of this embodiment, regarding the data reading method independent of querying the directory unit proposed in the above embodiment, when the unit responsible for performing the listening operation listens to all target caches and does not detect that the target data is stored in the target cache, it indicates that the target data has not been stored in the target cache. Based on the above condition, the cache controller and / or the unit responsible for performing the listening operation can return a read failure message to the system and continue to execute the path based on the querying directory unit, that is, determine the storage location of the target data through the querying directory unit and obtain the target data based on the storage location. It is worth noting that the above logical process from the listening operation missing to the return of the read failure message, and then to the switch to the directory unit for reading, is only used to illustrate that there can be multiple data reading paths in the system. In the specific implementation process, there is no strict dependency or sequential relationship between the data reading paths in terms of logic and timing. The design purpose is to ensure the reliability and data availability of the system under various operating conditions, and does not mean that the directory unit query will only be started when the target cache is missed. Specifically, different strategies such as serial, parallel, or prefetching can be flexibly selected to arrange the execution mode of each data reading path according to design requirements. For example, this may include, but is not limited to: 1. Initiating queries on directory units in parallel while performing a listening operation on the target cache, thereby improving the response speed and success rate of data reading. In the above case, when the listening operation misses, the query results of the directory units that have been started in parallel can be quickly used, thereby ensuring that the reading of target data is not blocked due to the delay of a single path; 2. Starting queries on directory units serially after a listening operation misses; 3. Pre-preparing the results of directory unit queries in advance through a prediction or pre-fetching mechanism to shorten the overall response time. In summary, as long as the target data is ultimately used based on the query of the directory unit when no target data is detected in the target cache, and the target data is sent to the first core, regardless of whether the timing of the listening operation and the query of the directory unit is serial, parallel, or any other strategy during the specific execution process, it falls within the protection scope of this application.

[0095] By reading the target data obtained from the query directory unit and sending it to the first core when no target data is detected in the target cache, the execution path of the data reading method proposed in this application embodiment is improved in the above-mentioned abnormal situation. This not only does not affect the overall data reading speed, but also avoids reading interruption or failure due to the target cache not storing target data. This ensures the integrity and stability of the above-mentioned data reading method, so that regardless of whether the target cache stores target data, valid target data can be obtained through the established mechanism and sent to the first core, ensuring the reliability and continuity of the data reading process.

[0096] In some embodiments, after receiving a data read request, the directory unit is queried to determine the storage location of the target data. The directory unit records the storage location of at least one piece of data. Based on the storage location of the target data, the target data is read. If the target data is detected to be stored in the target cache, and the data state of the target data is non-exclusive, the target data read based on the directory unit is sent to the first core. Here, non-exclusive state refers to the state where the target data is stored in at least two caches.

[0097] In one aspect of this embodiment, if target data is detected to be stored in the target cache and the data state of the target data is non-exclusive, the target data can still be obtained by querying the directory unit and sent to the first core. Here, non-exclusive state refers to the state where the target data is stored in at least two caches. In the above case, even if target data exists in the target cache, because it is in a multi-cache shared state, the target data is still obtained by querying the directory unit and delivered to the first core to ensure the consistency and controllability of the reading process. It is worth noting that regarding the data reading method proposed in this embodiment, various possibilities in timing and logic during execution can be found in the above embodiments, and will not be repeated here.

[0098] By successfully retrieving the target data and sending it to the first core even when the target data is in a non-exclusive state, the read uncertainty caused by multiple cache sharing is avoided, thereby improving the integrity and stability of the data reading method proposed in this application in the shared state scenario and ensuring reliable reading of the target data.

[0099] For example, please refer to Figure 6 , Figure 6 This is a schematic diagram of a data reading method provided in one possible implementation of this application. For example... Figure 6 As shown, the above data reading method is applied to a processor including multiple cores. After the first core initiates a data reading request for target data, the reading and sending of the target data can be completed through multiple parallel and / or on-demand calling paths. For example, the data reading method proposed in this embodiment may include at least one of the following data reading paths: 1. Perform a listening operation on the target cache: After receiving a data read request from the first core, a listening operation can be performed on at least one target cache. This listening operation is used to detect whether the target data is stored in the target cache. Specifically: If the target data is detected to be stored in the target cache, and it is determined that the data state of the target data is exclusive (i.e., the target data is stored in only one cache), then the target data is directly read from that target cache and sent to the first core. After this read is completed, the data state of the target data can be changed from exclusive to non-exclusive to maintain consistency when accessed by other cores. The core purpose of the above path is to achieve low-latency direct reads, while ensuring data consistency in a multi-core environment by updating the data state.

[0100] 2. Querying the Directory Unit: After receiving a data read request, the directory unit can be queried to determine the storage location of the target data. This directory unit is used to record the storage location of at least one piece of data (see reference). Figure 5 The target data can be read from the directory unit shown, based on the found storage location. Conversely, if no target data is detected in the target cache, the target data read from the directory unit can be sent to the first core. Furthermore, even if target data is detected in the target cache, but the data state of that target data is non-exclusive (i.e., the target data is stored in at least two caches), the target data read from the directory unit can still be sent to the first core. The above path design aims to improve the reading mechanism under abnormal conditions and / or when the target data is in a shared state, ensuring that the data reading method proposed in this embodiment can stably acquire data, thereby guaranteeing the integrity and reliability of the entire data reading method.

[0101] 3. Memory Read: During the process of querying directory units and / or performing listening operations on the target cache, target data can also be read directly from memory. It is worth noting that the memory read path is the slowest of the three data read paths mentioned above.

[0102] The three types of paths described above logically constitute a parallel or conditional branching relationship. Specifically, when the read path performing the listening operation on the target cache fails to meet the read conditions, it can be processed according to the original path, which refers to the path of querying the directory unit and / or directly reading memory, to continue to complete the acquisition of the target data. In actual implementation, the execution sequence of the above three paths can be flexibly arranged by the system design—it can be designed as a serial sequence (e.g., listening first, and querying the directory unit or reading memory if a miss occurs), or it can be designed as parallel execution (e.g., initiating the query of the directory unit and memory reading at the same time as initiating the listening on the target cache). Pre-judgment, pre-fetching, or other optimization strategies can also be introduced to prepare the directory unit query results or memory data in advance to shorten the response time. Importantly, these three types of paths do not depend on each other in actual execution. Their triggering and execution can be carried out independently, and they do not need to wait for each other to complete. However, when the first core finally receives the target data, its data source may be the cache hit, the query result of the directory unit, or the result of reading directly from memory. The logical order of events does not limit the actual timing arrangement of the hardware or software. As long as the triggering conditions of each path are met and the technical solution can ultimately read target data and send it to the first core based on the above three paths, it falls within the protection scope of this application. In addition, the data reading method of this embodiment may also include the step of storing the data of the first core to at least one target cache based on register configuration information, which is used to indicate the target cache, thereby providing a basis for performing the listening operation.

[0103] It is worth noting that, Figure 6 The data reading method illustrated is merely an illustrative example used to aid in understanding the data reading method and related supplementary paths proposed in this application. In actual implementation, besides... Figure 6 In addition to the listening operation path, query directory unit path, and memory read path shown in the application, there may be other forms or combinations of data read paths and logic. As long as they contain the core mechanism of directly performing listening operations on the target cache to detect the target data and completing the reading and sending under the corresponding conditions, no matter what additional read paths or optimization logic are introduced in the specific implementation, they all fall within the protection scope of this application.

[0104] The data reading method provided in this application provides a more concise path for obtaining target data by directly performing a listening operation on at least one target cache after receiving a data reading request from a first core among multiple cores. This is done to detect whether the target cache stores target data, and if so, reads the target data from the target cache and sends it to the first core. In summary, the data reading method provided in this application can directly provide data when the target cache stores target data, reducing additional query overhead and latency, thereby accelerating the data reading speed.

[0105] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0106] For example, please refer to Figure 7 , Figure 7 This is a structural block diagram of a data reading device provided in one possible implementation of this application. It is worth noting that the data reading device 700 is applied in a processor, which includes multiple cores, and the processor and cores are... Figure 7 The above data reading device 700 includes: a receiving module 710, a listening module 720, and a reading module 730. (Not shown in the image.)

[0107] The receiving module 710 is used to receive a data read request sent by the first core among multiple cores. The data read request is used to request the reading of target data.

[0108] The listening module 720 is used to perform a listening operation on at least one target cache after receiving a data read request. The listening operation is used to detect whether the target cache stores target data. The target cache is a pre-defined cache.

[0109] The read module 730 is used to read target data from the target cache if the target cache contains target data, and then send the target data read from the target cache to the first core.

[0110] In some embodiments, the reading module 730 is further configured to read the target data from the target cache if the target cache stores the target data and the data state of the target data is exclusive, and then send the target data read from the target cache to the first core. Here, exclusive state refers to the state where the target data is stored in only one cache.

[0111] In some embodiments, the data reading device 700 further includes a status changing module ( Figure 7(Not shown in the image). The state change module is used to change the data state of the target data from exclusive to non-exclusive. The non-exclusive state refers to the state where the target data is stored in at least two caches.

[0112] In some embodiments, the data reading device 700 further includes a query module ( Figure 7 (Not shown in the image).

[0113] The query module, upon receiving a data read request, queries the directory unit to determine the storage location of the target data. The directory unit records the storage location of at least one piece of data.

[0114] The reading module 730 is also used to read the target data according to the storage location of the target data.

[0115] The reading module 730 is also used to send the target data read based on the directory unit to the first core if no target data is detected stored in the target cache.

[0116] In some embodiments, the reading module 730 is further configured to send the target data read based on the directory unit to the first core if it detects that target data is stored in the target cache and the data state of the target data is non-exclusive. Here, non-exclusive state refers to the state in which the target data is stored in at least two caches.

[0117] In some embodiments, the data reading device further includes a storage module ( Figure 7 (Not shown in the image).

[0118] A storage module is used to store the data of the first core into at least one target cache based on register configuration information. The register configuration information is used to indicate at least one target cache.

[0119] The data reading device provided in this application provides a shorter path for obtaining target data by directly performing a listening operation on at least one target cache after receiving a data reading request from a first core among multiple cores. This allows the device to detect whether target data is stored in the target cache. If target data is stored in the target cache, the device reads the target data from the target cache and sends it to the first core. In summary, the data reading device provided in this application can directly provide data when target data is stored in the target cache, reducing additional query overhead and latency, thereby accelerating the data reading speed.

[0120] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0121] For example, please refer to Figure 8 , Figure 8 This is a structural block diagram of a computer device provided in one possible implementation of this application. The computer device 800 can be any electronic device with data calculation, processing, and storage functions. The computer device 800 can be used to implement the data reading method provided in the above embodiments.

[0122] Typically, computer device 800 may include a processor 810 and a memory 820.

[0123] Processor 800 may include one or more processing cores, such as a quad-core processor or an octa-core processor. Processor 800 may be implemented using at least one hardware form selected from DSP, FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 810 may also include a main processor and a coprocessor. The main processor, also known as the CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 810 may integrate a GPU, which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 810 may also include an AI processor, which is used to handle computational operations related to machine learning.

[0124] The memory 820 may include one or more computer-readable storage media, which may be non-transitory. The memory 820 may also include high-speed random access memory and NVM (Non-Virtual Machine). Volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage medium in memory 820 is used to store a computer program configured to be executed by one or more processors to implement the data reading method described above.

[0125] Those skilled in the art will understand that Figure 8The structure shown does not constitute a limitation on the computer device 800, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0126] In an illustrative embodiment, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor of a computer device, implements the aforementioned data reading method. Optionally, the computer-readable storage medium may be a ROM, RAM, CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk, or optical data storage device, etc.

[0127] In an exemplary embodiment, a chip is also provided, the chip including programmable logic circuitry and / or program instructions, the programmable logic circuitry and / or program instructions being stored in a computer-readable storage medium. A processor of a computer device reads the programmable logic circuitry and / or program instructions from the computer-readable storage medium, and the processor executes the programmable logic circuitry and / or program instructions, causing the computer device to perform the data reading method described above.

[0128] In an exemplary embodiment, a computer program product is also provided, which includes a computer program that is loaded and executed by a processor to implement the data reading method described above.

[0129] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0130] The above are merely exemplary embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims

1. A data reading method applied in a processor, characterized in that, The processor includes multiple cores, and the method includes: Receive a data read request sent by the first core among the plurality of cores, the data read request being used to request the reading of target data; After receiving the data read request, a listening operation is performed on at least one target cache. The listening operation is used to detect whether the target data is stored in the target cache, which is a pre-defined cache. If the target data is stored in the target cache, the target data is read from the target cache and sent to the first core.

2. The method according to claim 1, characterized in that, If the target data is stored in the target cache, then reading the target data from the target cache and sending the target data read from the target cache to the first core includes: If the target data is stored in the target cache and the target data is in an exclusive state, then the target data is read from the target cache and sent to the first core; wherein, the exclusive state means that the target data is stored in only one cache.

3. The method according to claim 2, characterized in that, After reading the target data from the target cache and sending the target data read from the target cache to the first core, the method further includes: Change the data state of the target data from the exclusive state to the non-exclusive state; wherein, the non-exclusive state refers to the state in which the target data is stored in at least two caches.

4. The method according to claim 1, characterized in that, The method further includes: Upon receiving the data read request, the directory unit is queried to determine the storage location of the target data; wherein, the directory unit is used to record the storage location of at least one piece of data; Read the target data according to its storage location; If the target data is not detected to be stored in the target cache, the target data read from the directory unit is sent to the first core.

5. The method according to claim 1, characterized in that, The method further includes: Upon receiving the data read request, the directory unit is queried to determine the storage location of the target data; wherein, the directory unit is used to record the storage location of at least one piece of data; Read the target data according to its storage location; If the target data is detected to be stored in the target cache and the data status of the target data is non-exclusive, then the target data read based on the directory unit is sent to the first core; wherein, the non-exclusive status refers to the state in which the target data is stored in at least two caches.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: Based on register configuration information, the data of the first core is stored in the at least one target cache; wherein the register configuration information is used to indicate the at least one target cache.

7. A data reading device for use in a processor, characterized in that, The processor includes multiple cores, and the device includes: The receiving module is used to receive a data read request sent by the first core among the plurality of cores, wherein the data read request is used to request the reading of target data; A listening module is used to perform a listening operation on at least one target cache after receiving the data read request. The listening operation is used to detect whether the target data is stored in the target cache, and the target cache is a pre-set cache. The reading module is configured to read the target data from the target cache if the target data is stored in the target cache, and send the target data read from the target cache to the first core.

8. The apparatus according to claim 7, characterized in that, The reading module is further configured to read the target data from the target cache if the target data is stored in the target cache and the data state of the target data is exclusive, and send the target data read from the target cache to the first core; wherein, the exclusive state refers to the state in which the target data is stored in only one cache.

9. The apparatus according to claim 8, characterized in that, The device further includes: The state change module is used to change the data state of the target data from the exclusive state to the non-exclusive state; wherein, the non-exclusive state refers to the state in which the target data is stored in at least two caches.

10. The apparatus according to claim 7, characterized in that, The device also includes a query module; The query module is used to query the directory unit after receiving the data read request to determine the storage location of the target data; wherein, the directory unit is used to record the storage location of at least one piece of data; The reading module is further configured to read the target data according to the storage location of the target data; The reading module is further configured to send the target data read from the directory unit to the first core if the target data is not detected to be stored in the target cache.

11. The apparatus according to claim 7, characterized in that, The device also includes a query module; The query module is used to query the directory unit after receiving the data read request to determine the storage location of the target data; wherein, the directory unit is used to record the storage location of at least one piece of data; The reading module is further configured to read the target data according to the storage location of the target data; The reading module is further configured to send the target data read from the directory unit to the first core if it detects that the target data is stored in the target cache and the data status of the target data is non-exclusive; wherein, the non-exclusive status refers to the state in which the target data is stored in at least two caches.

12. The apparatus according to any one of claims 7 to 11, characterized in that, The device further includes: A storage module is configured to store the data of the first core into the at least one target cache based on register configuration information; wherein the register configuration information is used to indicate the at least one target cache.

13. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the method as claimed in any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the method as described in any one of claims 1 to 6.

15. A chip, characterized in that, The chip includes programmable logic circuitry and / or program instructions, which, when the chip is running, are used to implement the method as described in any one of claims 1 to 6.

16. A computer program product, characterized in that, The computer program product includes a computer program that is loaded and executed by a processor to implement the method as described in any one of claims 1 to 6.

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