LUT selection data addition verification circuit, electronic device and verification method

Abstract

The application relates to the field of semiconductor integrated circuits, in particular to an LUT selection data addition verification circuit, an electronic device and a verification method, which comprise an input port module, a plurality of selectors, a NOT control module, a MAC-ECC module, a compensation vector preprocessing module and an adder. The input port module outputs a selection signal to the selectors, the NOT control module processes the output of the selectors and outputs a NOT signal, the MAC-ECC module performs addition verification on the NOT signal, the compensation vector preprocessing module outputs a compensation vector based on the input port module, and finally, the adder combines the verification result and the compensation vector to obtain a final result. Thus, the problem that data cannot be bit-inverted and verified under the condition that the LUT is compressed in the related art is solved, the applicability of addition verification is improved, and the area and power consumption of the ECC circuit with the LUT are reduced.

Images