Heterogeneous computing systems and methods for computers

Abstract

This application discloses a heterogeneous computing system and method for computers, relating to the field of supercomputer technology. The heterogeneous computing system includes: a register unit, used to determine the computing core and its corresponding target configuration register based on the physical address of the data to be computed corresponding to the heterogeneous computing task of the processing device, and to allocate the data to be computed to the target configuration register; and a data read / write unit, used to allocate the data to be computed to the corresponding memory layers among multiple memory layers based on the target configuration register through a first crossbar switch, so as to drive the computing unit to execute computing tasks according to the data to be computed corresponding to the multiple memory layers. This solves the problems of large data transmission latency and low memory utilization in related technologies' heterogeneous acceleration systems, achieving the technical effects of fully utilizing memory resources in heterogeneous platforms, improving the performance of data transmission between different computing units, and reducing data migration latency.

Description

Technical Field

[0001] This application relates to the field of supercomputer technology, and in particular to a heterogeneous computing system and heterogeneous computing method for computers. Background Technology

[0002] In related technologies, with the development of heterogeneous computing platforms, in heterogeneous computing platforms based on CPU (Central Processing Unit) + FPGA (Field Programmable Gate Array), when offloading computationally intensive tasks to the FPGA for execution, the computing functions are usually piped and parallelized. Multiple computing IP cores (Intellectual Property cores, referring to pre-designed, verified, and reusable hardware functional modules) are instantiated to work in parallel to achieve acceleration. To improve the efficiency of front-end data transmission and back-end computation result writing to memory and result feedback, FPGAs integrate more and more memory layers to support the parallel operation of multiple computing IP cores.

[0003] However, in related technologies, when multiple computing IP cores work in parallel using the memory layer inside the FPGA, the memory management methods of traditional heterogeneous computing platforms often only target the use of a single type of memory (memory layer), lack unified scheduling of mixed memory, and mostly adopt static data placement strategies, which cannot be dynamically adjusted according to application access patterns, resulting in low memory resource utilization and failure to fully leverage the performance advantages of heterogeneous memory, which urgently needs to be addressed. Summary of the Invention

[0004] This application provides a heterogeneous computing system and method for computers, which at least solves the problems in the related technologies where, when multiple computing IP cores work in parallel using the memory layer inside the FPGA, the memory management methods of traditional heterogeneous computing platforms often only target the use of a single type of memory, lack unified scheduling of mixed memory, and cannot dynamically adjust according to the application access mode, resulting in low memory resource utilization and failure to fully leverage the performance advantages of heterogeneous memory.

[0005] This application provides a heterogeneous computing system for a computer, including a processing device and a programmable logic device. The programmable logic device includes a register unit, a data read / write unit, and a computing unit. The register unit is used to determine a computing core based on the physical address of the data to be computed corresponding to the heterogeneous computing task of the processing device, and to determine a target configuration register based on the physical address and the computing core, and to allocate the data to be computed to the target configuration register. The data read / write unit is used to allocate the data to be computed to corresponding memory layers among multiple memory layers through a first crossbar switch based on the target configuration register, so as to drive the computing unit to execute the heterogeneous computing task according to the data to be computed corresponding to the multiple memory layers. Each memory layer has different physical characteristics, and each memory layer is communicatively connected to the target configuration register through the first crossbar switch.

[0006] This application also provides a heterogeneous computing method for a computer, employing the aforementioned heterogeneous computing system. The method includes the following steps: reading memory resources corresponding to multiple memory layers in a programmable logic device; encoding the memory resources to obtain multiple virtual addresses corresponding to the memory resources; wherein the multiple memory layers include a random access memory layer, a high-bandwidth memory layer, and a dual data rate synchronous dynamic random access memory layer; detecting the task type of the computing task; and when the task type is a heterogeneous computing task, allocating the data to be computed corresponding to the heterogeneous computing task to the multiple memory layers based on the multiple virtual addresses and the programmable logic device; executing the heterogeneous computing task according to the data to be computed in the multiple memory layers; and generating the computation result of the heterogeneous computing task.

[0007] This application also provides a heterogeneous computing device for a computer, employing the aforementioned heterogeneous computing system, comprising: an addressing module, configured to read memory resources corresponding to multiple memory layers in a programmable logic device, and to perform address encoding on the memory resources to obtain multiple virtual addresses corresponding to the memory resources, wherein the multiple memory layers include a random access memory layer, a high-bandwidth memory layer, and a dual data rate synchronous dynamic random access memory layer; and a computing module, configured to detect the task type of a computing task, and when the task type is a heterogeneous computing task, to allocate the data to be computed corresponding to the heterogeneous computing task to the multiple memory layers based on the multiple virtual addresses and the programmable logic device, so as to execute the heterogeneous computing task according to the data to be computed in the multiple memory layers and generate the computing result of the heterogeneous computing task.

[0008] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described heterogeneous computing methods of a computer.

[0009] This application also provides a non-volatile computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described heterogeneous computing methods.

[0010] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described heterogeneous computing methods for computers.

[0011] This application enables a heterogeneous computing system, comprising processing devices and programmable logic devices, to store data to be computed in multiple different memory layers and efficiently invoke them during heterogeneous computing tasks. It addresses the technical problem in related technologies where, when multiple computing IP cores work in parallel using the memory layers within an FPGA, traditional heterogeneous computing platforms often manage memory only for a single type of memory, lacking unified scheduling of mixed memory and the ability to dynamically adjust based on application access patterns. This results in low memory resource utilization and an inability to fully leverage the performance advantages of heterogeneous memory. The application achieves efficient coordination of cache resources on the heterogeneous computing platform, dynamically allocating and scheduling data to be computed based on its characteristics (size and throughput) in a time-sharing and hierarchical manner. This fully utilizes the characteristics of each memory resource while avoiding resource waste, effectively improving the performance of the heterogeneous computing system, reducing latency during data movement between different memory resources, increasing data transmission efficiency, and fully utilizing memory resources while leveraging the performance advantages of heterogeneous memory. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of a heterogeneous computing system for a computer according to an embodiment of this application; Figure 2 This is a hardware architecture diagram of a heterogeneous computing system in one embodiment of this application; Figure 3 This is a schematic diagram of the structure of a cascaded unit according to an embodiment of this application; Figure 4 This is a schematic diagram of a crossbar switch network according to an embodiment of this application; Figure 5 This is a flowchart illustrating heterogeneous computing in a computer according to an embodiment of this application; Figure 6 This is a schematic diagram of the 64-bit virtual address space partitioning according to an embodiment of this application; Figure 7 This is a schematic diagram of a heterogeneous acceleration system with unified management of multi-level caches according to an embodiment of this application; Figure 8 This is a flowchart of heterogeneous computing according to one embodiment of this application; Figure 9 This is a schematic diagram of the structure of a heterogeneous computing device for a computer according to an embodiment of this application.

[0014] Figure label: Among them, 10-heterogeneous computing system; 100-processing device; 200-programmable logic device; 201-register unit; 202-data read / write unit; 203-computing unit; 20-heterogeneous computing device of computer; 300-addressing module; 400-computing module. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0016] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0017] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] Before explaining the heterogeneous computing system 10 in the embodiments of this application, the technical principles of heterogeneous computing and other technologies involved in the embodiments of this application will be explained first.

[0019] As will be understood by those skilled in the art, heterogeneous computing refers to a computing method that uses systems composed of computing units with different types of instruction sets and architectures, such as CPU+GPU (Graphics Processing Unit) and CPU+FPGA heterogeneous computing platforms. Heterogeneous computing can effectively meet the computing needs of computationally intensive fields such as artificial intelligence, high-performance data analysis, and financial analysis, and can effectively meet the task types that general-purpose computing in computers is not good at.

[0020] To improve efficiency in traditional heterogeneous computing systems, acceleration systems based on heterogeneous devices offload acceleration tasks to heterogeneous accelerator cards based on the type of computing task and hardware support. First, the data to be computed is transferred to the host memory via the disk DMA (Direct Memory Access) controller. Then, the FPGA accelerator card is configured and task started via the registers mapped by the PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) BAR (Base Address Register). Upon receiving a task request, the accelerator card starts its internal DMA controller to transfer the data from the host memory to the accelerator's device memory. Next, it starts the logic resources for computation. After the computation is complete, it notifies the CPU of the completion via an interrupt, allowing it to retrieve the result or initiate the next computation task. Alternatively, data transmission can utilize P2P (Peer-to-Peer) direct transfer technology to transfer the data to be computed directly from the disk to the device memory in the FPGA accelerator before starting the computation. After computation, some results that do not need to be returned to the CPU can be directly written to the disk, while others need to be returned to the CPU via DMA to complete the computation task.

[0021] The above is a commonly used heterogeneous acceleration architecture. In FPGA-based heterogeneous computing platforms, traditional heterogeneous computing systems utilize the parallel computing capabilities of FPGAs. When offloading computationally intensive tasks to FPGAs for execution, the computing functions are usually piped and parallelized, and multiple computing IP cores are instantiated to work in parallel to achieve acceleration.

[0022] With continuous improvements in FPGA chip manufacturing technology, the number of programmable logic units within a single chip is constantly increasing, enabling more and more functionalities. The more IP cores that can be integrated within it, the stronger its parallel processing computing capabilities become. However, without improving the efficiency of front-end data transmission and the writing of back-end computation results to memory and the return of results, simply increasing computing power cannot further enhance the acceleration effect. Therefore, HBM (High Bandwidth Memory, a new memory technology for high-performance computing that provides a higher data transfer rate than traditional DDR (Double Data Rate) memory) emerged.

[0023] With the advent of HBM, this problem has been partially alleviated because HBM can support concurrent access, meaning that multiple parallel computing IP cores can access HBM simultaneously, thereby achieving true parallel computing.

[0024] However, after using HBM, traditional heterogeneous computing systems cannot fully utilize the DDR in the accelerator card. This is because the memory management methods of traditional heterogeneous computing systems are usually designed for the use of a single type of memory, lacking unified scheduling for mixed memory. At the same time, they adopt a static data placement strategy, which cannot be dynamically adjusted according to application access patterns and lacks a cross-memory level collaborative optimization mechanism. As a result, DDR will be idle, memory resource utilization will be low, and the performance advantages of heterogeneous memory cannot be fully utilized.

[0025] Therefore, this application proposes a heterogeneous computing system based on hierarchical memory management that can dynamically schedule the migration of data between FPGA on-chip RAM (Random Access Memory), HBM, and DDR according to memory characteristics, application access patterns, and resource status. It can schedule and use different memory resources according to the characteristics of different types of memory, make full use of the resources on the platform, and enable the acceleration platform to achieve the maximum computing effect through reasonable scheduling and control. This provides an effective solution for improving the performance of heterogeneous acceleration platforms and effectively improves the overall performance of the memory system.

[0026] The embodiments of this application provide a heterogeneous computing system, and the heterogeneous computing system is described in detail in conjunction with its structure.

[0027] Specifically, Figure 1 This is a schematic diagram of the structure of a heterogeneous computing system 10 of a computer according to an embodiment of this application.

[0028] like Figure 1As shown, the system includes a processing device 100 and a programmable logic device 200. The programmable logic device 200 includes a register unit 201, a data read / write unit 202, and a computing unit 203. The register unit 201 is used to determine the computing core based on the physical address of the data to be computed corresponding to the heterogeneous computing task of the processing device 100, and to determine the target configuration register based on the physical address and the computing core, and to allocate the data to be computed to the target configuration register. The data read / write unit 202 is used to allocate the data to be computed to the corresponding memory layer among multiple memory layers through a first crossbar switch based on the target configuration register, so as to drive the computing unit 203 to execute the heterogeneous computing task according to the data to be computed corresponding to the multiple memory layers. Each memory layer has different physical characteristics, and each memory layer is communicatively connected to the target configuration register through the first crossbar switch.

[0029] As one possible implementation, this application embodiment designs a heterogeneous computing system 10, which includes a processing device 100 and a programmable logic device 200.

[0030] Here, the processing device 100 can be understood as the CPU in the heterogeneous computing system 10 composed of a CPU and an FPGA, and the programmable logic device 200 can be understood as the FPGA in the heterogeneous computing system 10 composed of a CPU and an FPGA.

[0031] Furthermore, the programmable logic device 200 in this embodiment includes, but is not limited to, a register unit 201, a data read / write unit 202, and a calculation unit 203, depending on the data flow direction.

[0032] Figure 2 This is a hardware architecture diagram of a heterogeneous computing system 10 according to one embodiment of this application. Figure 2 As shown, the hardware architecture in this application embodiment is mainly FPGA-side. Figure 2 The functional implementation framework inside the FPGA is demonstrated.

[0033] Among them, register unit 201 (and Figure 2 (The register path identifier in the same way) After receiving a heterogeneous computing task sent by the CPU (here referring to a heterogeneous computing task offloaded from the CPU to the FPGA accelerator, not a complete heterogeneous computing task issued by the user: because in general, some computing tasks issued by the user, such as machine learning inference, video transcoding, financial risk analysis, etc., need to be completed in conjunction with a general-purpose CPU and an FPGA accelerator. The task usually contains complex logic control suitable for CPU processing and data-intensive parts suitable for large-scale parallel computing by FPGA / GPU), the heterogeneous computing task can be parsed to obtain the data to be computed and its physical address corresponding to the heterogeneous computing task.

[0034] Among them, the data to be computed corresponding to the heterogeneous computing task obtained after parsing contains different physical addresses allocated by the processing device 100. Based on the physical addresses corresponding to different data in the data to be computed, it can be determined which configuration registers, i.e. target configuration registers, should be allocated to the different data in the data to be computed.

[0035] Specifically, the data to be computed contains different computational contents in heterogeneous computing tasks (generally transmitted in data packets). Different computational contents (data packets) correspond to different computing cores (computing IP cores, such as compression, decompression, convolution computing cores, etc.). The corresponding computing core can be determined based on the data to be computed, and each computing IP core has a corresponding configuration register.

[0036] Among them, the computing IP core (and Figure 2 The identifiers for computation unit 1, computation unit 2, computation unit 3, ..., computation unit n in the FPGA / on-chip system have the same function. Here, they can be understood as pre-packaged, reusable hardware functional modules that are hardware units that perform specific computational tasks.

[0037] Therefore, the target configuration register can be understood here as the configuration register corresponding to different computing IP cores, for example, Figure 2 The configuration registers for computing unit 1, computing unit 2, computing unit 3, ..., computing unit n are hardware register sets that are built into each computing IP core and can be accessed by the host device (CPU / FPGA hard core) through bus addressing. They are also the only interactive control entry point between the host device and a single IP core. All configuration, control, and status reading operations of the host device for each computing IP core are completed by writing / reading the configuration register set of this computing IP core. For example, operations such as starting a computing unit, allocating memory access addresses, and configuring computing parameters are essentially writing specified values ​​to the corresponding bits / addresses of this configuration register set.

[0038] In simple terms, the master device can precisely control the working status of each computing IP core, set its working parameters, and read its current running status by operating the configuration register of each computing IP core through the bus.

[0039] Each computing IP core has its own dedicated address range for its configuration register. These computing IP cores correspond to different data packets in different data to be computed. Therefore, by using the physical addresses of different data packets (corresponding to different computing cores) in the data to be computed, the target configuration register corresponding to the computing IP core for different data in the data to be computed can be determined.

[0040] To achieve faster data reading and further improve the acceleration effect of heterogeneous computing platforms, the data read / write unit 202 (and...) is set within the FPGA in this embodiment of the application. Figure 2 The data read / write path identifiers in the same way have the same function. This includes the first crossbar switch (such as...). Figure 2 The first crossbar switch (selected in this embodiment) connects each memory layer and the configuration register. Based on the target configuration register corresponding to each piece of data to be computed, it can allocate the data to be computed to the corresponding memory layer among multiple memory layers, thereby driving the computing unit 203 (and...). Figure 2 (The computing path identifier has the same function) Based on the data to be computed corresponding to multiple memory layers, the CPU transfers heterogeneous computing tasks, thereby realizing the execution of heterogeneous computing tasks on the basis of maximizing the utilization of resources in these memory layers.

[0041] In this context, the memory layer can be understood as the cache memory resources set up within the FPGA, such as DDR, HBM, etc. Since each memory layer has different physical characteristics (such as latency, bandwidth, capacity, etc.), this embodiment can allocate the data to be computed to different memory layers according to the data utilization during the execution of the computation task. Furthermore, each memory layer can communicate with the configuration register through a first crossbar switch.

[0042] This application embodiment can achieve intelligent offloading of computing tasks and dynamic scheduling of hierarchical memory through the collaborative design of processing device 100 and programmable logic device 200. While supporting efficient communication and task allocation between CPU and FPGA, it can reasonably allocate data to different levels such as RAM, HBM and DDR according to memory characteristics (such as latency, bandwidth and capacity), thereby significantly improving memory resource utilization, reducing data migration latency, and ultimately achieving efficient parallel execution of computing tasks and optimization of overall system performance.

[0043] Optionally, in one embodiment of this application, the register unit 201 includes: a register configuration management module, which parses the data to be calculated to obtain the data type of the data to be calculated; and a cascading unit, which allocates the data to be calculated to the target configuration register according to the data type and the base address of the register.

[0044] In actual implementation, data transmission and parsing between the processing device 100 (CPU) and the programmable logic device 200 (FPGA) of this application can be, but is not limited to, through a PCIe interface module (such as...). Figure 2 The high-speed serial computer expansion bus interface module is implemented in the system.

[0045] This application allows for the configuration of a PCIe interface module between the CPU and the FPGA. This module can perform the functions of the PHY (Physical Layer) and data link layer in PCIe communication, receiving and parsing heterogeneous computing tasks sent by the CPU. The parsed data to be computed is then processed through the Completer Request / Completer Completion interface (CQ / CC) to obtain the physical addresses of multiple BAR address windows corresponding to the data to be computed. Based on the different addresses of the BAR (Base Address Register, an address window on the PCIe device), the data to be computed can be routed (transmitted) to the register configuration management module or the hybrid memory address extension module.

[0046] The register configuration management module needs to parse the data packet content of the data to be calculated in order to obtain the data type (computation unit type) of the data packet, and then initiate a register read / write request based on the data type of the data packet. The backend module of the register configuration management module will respond to the register read / write request.

[0047] Furthermore, the register unit 201 in this embodiment also includes a cascading unit. Figure 3 This is a schematic diagram of the structure of a cascaded unit according to an embodiment of this application. Figure 3 As shown, the cascaded unit can allocate the data to be calculated to the configuration register corresponding to its computing core according to the data type of the data packet and the base address of the register.

[0048] Simply put, such as Figure 3 As shown, in order to distinguish different types of register submodules (configuration registers), the cascading unit can, but is not limited to, connect 1 Master (master device / master interface) to multiple back-end Slave (slave device / slave interface) in a cascading manner, so that the address decoder can route the data to be calculated to the corresponding register submodule (configuration register) according to the base address of the register.

[0049] Furthermore, this design theoretically allows for the control of the registers of any number of computing IP cores on the software side, enabling the configuration of computing unit startup, allocation of memory access addresses for computing IP cores, and other related information.

[0050] And, such as Figure 3As shown, in this embodiment of the application, the interface output by the register configuration management module can be, but is not limited to, designed as an AXI-Lite (a simplified version of the Advanced eXtensible Interface bus protocol, mainly used for communication between low-bandwidth, low-latency processors and peripherals) type, and the interface of the address decoder connected to the back end of the register configuration management module can be connected to it as a Slave interface.

[0051] This application embodiment can intelligently parse the data type of the data to be calculated by introducing a register configuration management module and cascading units, and achieve precise routing by combining the register base address. This allows different types of data packets to be automatically assigned to the corresponding configuration registers, greatly improving configuration flexibility and response speed, and laying a solid control foundation for the efficient execution of subsequent computing tasks. It is especially suitable for complex scenarios with multiple types of concurrent computing tasks.

[0052] Optionally, in one embodiment of this application, the cascading unit further includes: an address decoder, used to allocate the data to be computed to at least one slave interface according to the data type and the base address of the register; and at least one second cross switch, used to allocate the data to be computed to the configuration register corresponding to the computing core based on the at least one slave interface and the number of computing cores.

[0053] In some embodiments, the cascading unit in this application includes, but is not limited to, an address decoder and at least one second cross switch (e.g., Figure 3 (Cross switch 1, cross switch 2, etc. in the middle).

[0054] In this embodiment, the address decoder is mainly used to allocate the data to be calculated to at least one slave interface according to the data type of different data packets and the base address of the register.

[0055] At least one second cross switch is primarily used to allocate the data to be computed to the target configuration register corresponding to the computing core corresponding to its different data packets, based on at least one slave interface and the number of computing cores.

[0056] Specifically, such as Figure 2 Register paths and Figure 3 As shown: The address decoder in the first stage of the cascaded unit can route multiple slave interfaces (at least one slave interface, such as...) based on the type of computing unit. Figure 3 (e.g., slave device 0 interface, slave device 1 interface, slave device 2 interface, etc.), for example, computation cluster 1 is compression computation, computation cluster 2 is decompression computation, computation cluster 3 is convolution computation, etc. In a cascaded unit, at least one secondary cross switch (one or more second cross switches) can route multiple slave interfaces based on the number of computing IP cores, so as to allocate the data to be computed to the target configuration register corresponding to the computing core corresponding to its different data packets based on at least one slave interface and the number of computing cores.

[0057] For example, the AXI_Lite_S0 interface (and) Figure 3 The slave module's "read-only RAM register" (which has the same function as the slave device 0 identifier) ​​is the same as the slave module's "read-only RAM register" (e.g., ...). Figure 3 The base address of the random access memory register (RAM) is 0x00000000, and the addresses of its various internal configuration registers can be, but are not limited to, set to this base address plus an offset address: AXI_Lite_S1 (and) Figure 3 The base address of the slave module of the interface (which has the same function as the slave device 1 interface identifier) ​​is 0x00010000. If its backend computing cluster 1 has 8 IP cores (such as computing cluster 1-0 to computing cluster 1-7), then the secondary addresses of the IP cores are 0x00010000, 0x00011000, 0x00012000, and so on; while the register address in IP1 is 0x00010000 + offset address; AXI_Lite_S2 (and Figure 3 (The base address of the interface is 0x00020000, which is the same as the function of the interface identifier of the slave device 2.) The secondary address of the backend IP2 computing cluster is the same as above.

[0058] The embodiments of this application can adopt a cascaded architecture of address decoder and second cross switch to achieve efficient concurrent configuration and management of multiple computing IP cores. It realizes dynamic expansion of the number of slave interfaces according to the number of computing cores, supports independent configuration and status control of large-scale parallel computing IP cores, effectively enhances the scalability and parallel processing capability of the system, and avoids configuration conflicts and resource contention.

[0059] Optionally, in one embodiment of this application, the address decoder is connected to at least one second cross switch, and the at least one second cross switch is connected to at least one configuration register.

[0060] Based on the relevant descriptions in other embodiments, it can be understood that, in order to distinguish different types of register sub-modules (configuration registers), the embodiments of this application may, but are not limited to, use a cascading approach to connect the Master with multiple backend Slaves.

[0061] In actual implementation, the address decoder in this application is connected to at least one second cross switch, and the at least one second cross switch is connected to at least one configuration register.

[0062] It should be noted that the number of second cross switches needs to be determined by the data type (computation unit type) of the data to be calculated in the actual calculation process. This application embodiment is only an illustrative example and does not provide a specific example.

[0063] Therefore, by combining an address decoder and at least one second cross switch capable of enabling 1 Master to multiple Slaves, data can be routed to the corresponding submodule based on the base address of the register.

[0064] The embodiments of this application can clearly define the physical connection relationship between the address decoder and the second cross switch, and between the second cross switch and the configuration register. This structured cascade design simplifies the hardware routing logic, reduces addressing complexity, improves the stability and reliability of system configuration, and facilitates hardware implementation and expansion.

[0065] Optionally, in one embodiment of this application, the data read / write unit 202 includes: multiple request interfaces, multiple controllers, and multiple computing core read / write modules; a first cross switch is connected to the multiple request interfaces, multiple controllers, and multiple computing core read / write modules respectively, wherein each controller is connected to the corresponding memory layer, and each computing core is connected to the corresponding target configuration register; the first cross switch is connected to the random access memory layer, the high bandwidth memory layer, and the dual data rate synchronous dynamic random access memory layer.

[0066] Based on the relevant descriptions in other embodiments, it can be understood that after the data to be computed is allocated to the corresponding target configuration register, the data read / write unit can allocate the data to be computed to the corresponding memory layer among multiple memory layers through the first cross switch based on the target configuration register, so as to drive the final computing unit to perform heterogeneous computing tasks according to the data to be computed corresponding to the multiple memory layers.

[0067] In order to realize this series of data transmission and data utilization, in some embodiments, the data read and write unit of this application also includes, but is not limited to, multiple request interfaces, multiple controllers and multiple computing core read and write modules.

[0068] In this application embodiment, the multiple request interfaces include, but are not limited to, a hybrid memory address extension module, a DMA control management module, and a data mover module. These request interfaces can be connected to the CPU side through, but are not limited to, RQ (Requester Quester) / RC (Requester Completion) interfaces, and can determine how to utilize each memory layer and the data to be computed.

[0069] In addition, multiple controllers, including but not limited to RAM controllers, HBM controllers, and DDR controllers, are connected to the corresponding random access memory layer (on-chip RAM layer), high bandwidth memory layer (HBM memory layer), and dual data rate synchronous dynamic random access memory layer (DDR memory layer) respectively, so as to control the random access memory layer, high bandwidth memory layer, and dual data rate synchronous dynamic random access memory layer respectively. Therefore, each controller is connected to its corresponding memory layer.

[0070] Multiple compute core read / write modules (such as) Figure 2 The memory read / write modules of computing unit 1, ..., computing unit n, etc., can be connected to the target configuration register to read and write the data to be calculated. Therefore, each computing core read / write module is connected to the corresponding target configuration register.

[0071] Furthermore, such as Figure 2 As shown, in order to enable the first cross switch to utilize each memory layer and its data to be computed, the first cross switch in this embodiment can be connected to the multiple request interfaces, multiple controllers and multiple computing core read / write modules respectively.

[0072] By connecting the first crossbar switch to multiple controllers and the memory layers corresponding to the multiple controllers, the connection between the first crossbar switch and the random access memory layer, the high bandwidth memory layer, and the dual data rate synchronous dynamic random access memory layer is realized.

[0073] For example, such as Figure 2 As shown: In this application embodiment, the Switch data direction selection module can be used as the first cross switch, but is not limited to: For the RAM, HBM, or DDR of the Slave, there are four Masters that may initiate data access requests. The first is the mixed memory address interface module, the second is the DMA control and management function, the third is the IP calculation module, and the fourth is the Data_Mover (and... Figure 2 The memory data transfer modules in the FPGA board serve the same purpose: a hardware engine module specifically designed for efficient data transfer between different memory levels (e.g., between HBM and DDR) within the FPGA board. Each of the four Masters can potentially access three types of Slaves; therefore, a 4*3 crossbar switch network is initially needed, followed by a 1*n crossbar switch network depending on the number of caches connected to the backend. Specifically... Figure 4 As shown.

[0074] This application embodiment integrates multiple request interfaces, memory controllers, and compute core read / write modules, and achieves unified interconnection via a first crossbar switch, constructing a flexible and efficient data read / write path. This architecture allows multiple master devices, such as hybrid memory address extension, DMA control, data transfer, and compute cores, to access RAM, HBM, DDR, and other slave device memories in parallel, thereby achieving unified scheduling and efficient utilization of heterogeneous memory resources and breaking through the bottleneck of memory access in traditional systems.

[0075] Optionally, in one embodiment of this application, the first cross switch is used to respond to a memory access request from the processing device 100 to transfer the memory data corresponding to the memory access request to the processing device 100.

[0076] In some embodiments, the data path is used to respond to data responses when the CPU acts as a completer. In this case, Figure 2 The "Hybrid Memory Address Extension Module" marked in the text manages the addresses of the three types of memory in a unified manner.

[0077] When the CPU accesses the address space, this port of the hybrid memory address extension module enables direct memory access, essentially acting as an extended memory segment for the CPU. However, this interface masks the interface characteristics of different memory types, providing the CPU with only the first accessible memory space. This module unpacks the PCIe TLP (Transaction Layer Packet) protocol and then transmits data via AXI4 (Advanced eXtensible Interface 4, a high-performance, scalable on-chip system bus standard, such as...) Figure 4 The high-level extensible interfaces (Master 1, Master 2, ..., Master n, extended interfaces (Slave 0, Slave 1, Slave 2, Slave 0-0, Slave 0-1, ..., etc.) are used to transmit data to the backend modules.

[0078] At this time, the first cross switch is used to respond to the CPU's memory access request in order to transfer the memory data corresponding to the memory access request to the processing device 100.

[0079] In this embodiment, the CPU can respond to the memory access request of the processing device 100 through the first cross switch, so that the CPU can access the heterogeneous memory resources (such as HBM and DDR) on the FPGA directly and transparently as if it were accessing local memory. This greatly simplifies the data interaction process between the host and the accelerator, reduces the complexity of software development, and reduces unnecessary data copying, thereby enabling low-latency data sharing.

[0080] Optionally, in one embodiment of this application, the first cross switch is further configured to respond to read / write requests from the programmable logic device 200 to move and transmit memory data of the programmable logic device 200 to the processing device 100 and / or the hard disk corresponding to the processing device 100.

[0081] In other embodiments, another type of data path is a data path in which the FPGA side initiates data read / write requests as a requester. In this case, it is typically used to move data from the FPGA-side memory to the host-side memory or directly to the hard disk.

[0082] Therefore, the FPGA needs to complete this at this time. Figure 2 The "DMA control and management function" in the system initiates a DMA write operation when the result needs to be transferred to the host after the calculation is completed. The data is then encapsulated and transferred to the host-side memory through the PCIe module.

[0083] At this time, the second cross switch is used to respond to read / write requests from the programmable logic device 200 to transfer memory data from the programmable logic device 200 to the processing device 100 and / or the hard disk corresponding to the processing device 100.

[0084] This application embodiment can respond to read / write requests initiated by programmable logic devices through a first cross switch, thereby supporting the efficient transfer of data from FPGA memory to host memory or direct writing to hard disk. This effectively improves the data recycling and persistent storage path in the heterogeneous computing system 10 of this application, and is particularly suitable for application scenarios such as calculation result back-up, intermediate data backup, or direct disk writing after streaming data processing, thereby improving the integrity and flexibility of data processing.

[0085] Optionally, in one embodiment of this application, the multiple memory layers include a random access memory layer, a high bandwidth memory layer, and a dual data rate synchronous dynamic random access memory layer.

[0086] Based on the descriptions of other embodiments, it is understood that HBM can support concurrent access, meaning that multiple parallel computing IP cores can access HBM simultaneously, thereby achieving true parallel computing. However, using HBM can lead to insufficient utilization of the DDR within the accelerator card, resulting in idle DDR, low memory resource utilization, and failure to fully leverage the performance advantages of heterogeneous memory.

[0087] As one possible approach, in order to effectively utilize the characteristics of different types of memory and schedule and use different memory resources, embodiments of this application can allocate the data to be computed to multiple different memory layers (providing memory resources), and the physical characteristics of the multiple memory layers are also different.

[0088] For example, this application may, but is not limited to, classify the cache memory of a heterogeneous computing platform into the following three types based on the physical characteristics of the memory (latency, bandwidth, capacity): On-chip RAM (Random Access Memory layer) is a low-latency layer characterized by low latency but with the smallest capacity (from a few Mb to hundreds of Mb). Different FPGA chips offer different amounts of RAM. The HBM layer (High Bandwidth Memory Layer) is characterized by high bandwidth (300-500GB / s), medium capacity (currently commonly 16GB and 32GB), and medium latency (typically 30-60ns). The DDR layer (Dual Data Rate Synchronous Dynamic Random Memory layer) is characterized by large capacity, but has the highest latency (60-100ns) and relatively low bandwidth (tens of GB / s) compared to HBM and RAM.

[0089] Therefore, in this embodiment of the application, different data packets of data to be computed can be allocated to different memory layers according to the data usage of the data to be computed in the heterogeneous computing task.

[0090] For example, very small amounts of data (generally less than 256M) that require fast access and low latency are allocated to the on-chip RAM layer; small amounts of data (generally less than 16GB) that balance access rate (high bandwidth) and access latency are allocated to the HBM layer; and large amounts of data (generally less than 64GB) that do not require high access rate and access latency are allocated to the DDR layer.

[0091] Therefore, the embodiments of this application can allocate the data to be computed to different memory layers, thereby making full use of the resources on the platform. Through reasonable scheduling and control, the acceleration platform can achieve the maximum computing effect, providing an effective solution for improving the performance of heterogeneous acceleration platforms and effectively improving the overall performance of the memory system.

[0092] Optionally, in one embodiment of this application, the multiple memory layers include a random access memory layer and a high-bandwidth memory layer.

[0093] In some embodiments, when the data to be computed contains only a very small amount of data that requires fast access and low latency, and a small amount of data that balances access rate (high bandwidth) and access latency, the multiple memory layers that need to be allocated to the data to be computed are the corresponding random access memory layer and high bandwidth memory layer.

[0094] That is, data packets to be computed are allocated to the random access memory layer and the high bandwidth memory layer respectively. Data packets that require fast access and low latency can be allocated to the on-chip RAM layer, while low-volume data that requires a balance between access rate (high bandwidth) and access latency can be allocated to the HBM layer.

[0095] Optionally, in one embodiment of this application, the multiple memory layers include a high-bandwidth memory layer and a dual-data-rate synchronous dynamic random access memory layer.

[0096] In some embodiments, when the data to be computed consists of only a small amount of data that requires a balance between access rate (high bandwidth) and access latency, and a large amount of data for which access rate and access latency requirements are not high, the multiple memory layers that need to be allocated to the data to be computed are the corresponding high-bandwidth memory layer and dual-data-rate synchronous dynamic random access memory layer.

[0097] That is, only the data packets to be calculated are allocated to the high-bandwidth memory layer and the dual-data-rate synchronous dynamic random access memory layer respectively. Among them, low-volume data that needs to balance access rate (high bandwidth) and access latency can be allocated to the HBM layer; large-volume data that does not have high requirements for access rate and access latency can be allocated to the DDR layer.

[0098] Optionally, in one embodiment of this application, the multiple memory layers include a random access memory layer and a dual data rate synchronous dynamic random access memory layer.

[0099] In other embodiments, when the data to be computed contains only a very small amount of data that requires fast access with low latency and a large amount of data for which access rate and latency requirements are not high, the multiple memory layers that need to be allocated to the data to be computed are the corresponding random access memory layer and dual data rate synchronous dynamic random access memory layer.

[0100] That is, only the data packets to be calculated are allocated to the random access memory layer and the dual data rate synchronous dynamic random access memory layer respectively. Among them, the very small amount of data that requires fast access and low latency can be allocated to the on-chip RAM layer; the large amount of data that does not have high requirements for access rate and access latency can be allocated to the DDR layer.

[0101] This application defines various memory layer combinations (RAM+HBM+DDR, RAM+HBM, HBM+DDR, RAM+DDR), demonstrating the flexible configuration capabilities of this application. Different combinations can adapt to the performance, capacity, and cost requirements of different computing tasks: a full combination provides a complete performance hierarchy; pairwise combinations can be optimized for resource-constrained or specific scenarios, ensuring that the system can efficiently utilize available memory resources under various hardware configurations.

[0102] The embodiments of this application also provide a heterogeneous computing method for heterogeneous computers, and the method is described in detail in conjunction with the execution flow of heterogeneous computing on computers.

[0103] Specifically, Figure 5 This is a flowchart of a heterogeneous computing process for a computer according to an embodiment of this application.

[0104] like Figure 5 As shown, the heterogeneous computing method of this computer uses a heterogeneous computing system 10, wherein the method includes the following steps: In step S501, the memory resources corresponding to multiple memory layers in the programmable logic device 200 are read, and the memory resources are address encoded to obtain multiple virtual addresses corresponding to the memory resources. The multiple memory layers include a random access memory layer, a high bandwidth memory layer, and a dual data rate synchronous dynamic random access memory layer.

[0105] Understandably, after a user issues a computational task, the CPU typically performs further processing. Therefore, at the software level, after the user issues the computational task, the CPU can first read the programmable logic device 200 (and... Figure 2 The FPGA accelerator identifier serves the same purpose. The memory resource information corresponding to multiple memory layers is stored in the RAM inside the FPGA accelerator and written in advance. The CPU can read the relevant information through the PCIe register read / write channel.

[0106] In some embodiments, the CPU can read memory resource information corresponding to multiple memory layers and establish a three-layer memory hierarchy model.

[0107] In establishing the three-layer memory hierarchy model, this embodiment of the application may, but is not limited to, divide the memory of the heterogeneous computing platform into three layers based on the physical characteristics (latency, bandwidth, capacity) of the multiple memory layers (random access memory layer, high bandwidth memory layer, and dual data rate synchronous dynamic random access memory layer) in the previous embodiments: L1: On-chip RAM (Random Access Memory Layer), a low-latency layer characterized by low latency but with the smallest capacity (a few Mb to hundreds of Mb). Different FPGA chips can provide different amounts of RAM. L2: HBM layer (High Bandwidth Memory Layer), characterized by high bandwidth (300-500GB / s), medium capacity (currently commonly used are 16GB and 32GB), and medium latency (30-60ns). L3: DDR layer (Dual Data Rate Synchronous Dynamic Random Memory layer), characterized by large capacity, but with the highest latency (60-100ns) and relatively low bandwidth (tens of GB / s) compared to HBM and RAM.

[0108] Next, the CPU can, but is not limited to, use memory hot-swapping technology to uniformly address the accessible memory within the hardware FPGA accelerator, thereby mapping all memory resources to a unified virtual address space, obtaining multiple virtual addresses corresponding to the memory resources, and achieving unified virtual address space management. For example... Figure 6 As shown, Figure 6This illustration shows a schematic diagram of the 64-bit virtual address space partitioning of an embodiment of this application: on-chip random access memory mapping area address: 0x0-0xFFFFFFF, high bandwidth mapping area address: 0x10000000-0x3FFFFFFFF, dual data rate synchronous dynamic random access memory mapping area address: 0x400000000-0x1400000000.

[0109] After unifying the addressing, the CPU can select the corresponding memory module based on the virtual address after allocating the address for each computing task according to the memory space required and speed requirements of the computing task. It can also dynamically configure the data source address and destination address for each computing IP core in the FPGA acceleration card.

[0110] This application embodiment can construct a three-level caching model, making full use of all memory resources in heterogeneous resources. By adopting a multi-level caching mode, data is sent to the place where data needs to be calculated as quickly as possible. Data is stored in different memory resources according to its hot or cold characteristics, thus avoiding resource waste.

[0111] Optionally, in one embodiment of this application, before reading the memory resources corresponding to multiple memory layers in the programmable logic device 200 and addressing the memory resources, the method further includes: obtaining the task requirements of the computing task; and determining the number of paths corresponding to the multiple memory layers based on the task requirements.

[0112] In some embodiments, before address encoding the memory resources of multiple memory layers, this application may first determine the number of paths corresponding to multiple memory layers based on the task requirements of the computing task.

[0113] Specifically, depending on the actual application: Typically, the number of paths in the DDR layer is relatively small, usually 2. Although the HBM layer supports 32 required channels, in practical applications it has been found that when each virtual channel is accessed simultaneously, it will compete with the physical channel, which will reduce the throughput on each channel. Therefore, the HBM in this embodiment sets up 16 channels, that is, the externally connectable HBM includes 16 physical channels (each physical channel contains 2 virtual channels).

[0114] It should be noted that when the software allocates access to different Slave channels for the Master, although it can achieve full address access, it tries to select the physical channel that actually corresponds to the port to avoid access delay caused by the cross switch inside the HBM controller. Furthermore, the selection of the number of HBM pathways depends not only on the on-chip RAM capacity supported by the actual chip, but also primarily on its role as a cache for computing units. Therefore, its number should be kept as consistent as possible with the number of computing IP cores. The access size can be determined based on the processing capabilities of each part of the pipeline, including data transmission, computation, and backhaul in the overall data link. Setting an appropriate size ensures that each part of the pipeline can fully utilize its performance, preventing some modules from being saturated while others are in a state of starvation.

[0115] The specific number of DDR channels and HBM channels can be determined by those skilled in the art based on actual conditions and needs. The embodiments in this application are for illustrative purposes only and are not subject to specific limitations.

[0116] The embodiments of this application can dynamically determine the number of paths in each memory layer (especially HBM) according to the needs of specific computing tasks. This on-demand configuration strategy can avoid the waste or excessive contention of hardware resources, ensure that the data path bandwidth matches the computing bandwidth, and thus achieve balanced processing of the performance of different computing units within the computing platform. It can fully utilize the pipeline and parallelism of the FPGA acceleration platform, ensure that each computing module on the pipeline is always in a "working" state, and maximize resource utilization.

[0117] Optionally, in one embodiment of this application, reading memory resources corresponding to multiple memory layers in the programmable logic device 200 includes: reading the capacity and speed corresponding to multiple memory layers in the programmable logic device 200; and determining the memory resources based on the capacity and speed.

[0118] In actual execution, the memory resources corresponding to multiple memory layers in the programmable logic device 200 read by the CPU side include, but are not limited to, the capacity and speed corresponding to multiple memory layers.

[0119] Here, the capacity and speed of the memory layer refer to the available storage space (capacity) and data read / write hardware performance (speed) of each memory layer in the three-level hierarchical storage architecture (on-chip RAM / HBM / DDR) designed by the FPGA to match the memory access requirements of the computing IP cores (compression / decompression / convolution) for high parallel operation.

[0120] In simple terms, capacity determines how much data each memory layer can store, and speed determines how quickly each memory layer can read and write data. By reading these two types of parameters, the CPU can understand the hardware capabilities of each memory layer of the FPGA, realize hierarchical scheduling of data and reasonable allocation of memory access by computing IP cores, and avoid the memory access bottleneck where computing IP cores have fast operation speed but data read and write speed cannot keep up (which is also the core problem of multi-computing IP core parallel architecture).

[0121] Since the speed and capacity of memory layers are strictly inversely proportional—that is, the closer the memory layer is to the FPGA computing IP core, the faster the speed and the smaller the capacity; conversely, the farther away from the computing IP core, the larger the capacity and the slower the speed—this application embodiment employs a hierarchical memory layer design. This design balances the low-latency memory access requirements of the computing IP core's high-speed parallel computing with the storage requirements of large data volumes. As the main device, the CPU must first obtain the capacity and speed parameters of each memory layer to enable efficient data flow between them.

[0122] For example, by obtaining the capacity of the on-chip RAM, the CPU can determine the amount of real-time computation data that a single computing IP core can process at one time. For instance, if the on-chip RAM is only 16MB, the convolution IP core will not be loaded with 20MB of real-time feature data at one time to avoid data overflow. Knowing the speed, the CPU can match the computing IP core's clock speed to ensure that data reading and writing and computation are completely synchronized, achieving zero-wait computation.

[0123] Knowing the capacity of HBM, the CPU can allocate a shared data area for the entire computing cluster. For example, eight compression IP cores can share 1GB of HBM space to store batch compressed data. Knowing its ultra-high bandwidth, the CPU can allow multiple IP cores to read data from HBM in parallel, without multiple computing IP cores competing for bandwidth and causing memory access delays.

[0124] Knowing the capacity of the DDR, the CPU can determine the maximum amount of computational data that the entire FPGA system can handle. For example, if the DDR is 64GB, it can load 64GB of raw video data at once for the decompression IP core to process. Knowing the speed, it can reasonably arrange data preloading, such as loading the data in the DDR into the HBM / on-chip RAM in advance to avoid calculating data for the IP core.

[0125] Taking the batch processing of 10GB of raw data in DDR by 8 compression IP cores as an example, after the CPU reads the capacity and speed of the three-level cache, it can confirm that the 10GB of data can be stored in the DDR capacity (64GB). Based on the DDR speed (64GB / s), it starts data preloading and writes the raw data in DDR to HBM (8GB) in batches. Based on the HBM capacity (8GB), it allocates a shared data area of ​​1GB / core to each of the 8 compression IP cores. Based on the HBM bandwidth (1TB / s), it allows the 8 IP cores to read data from HBM in parallel. Based on the on-chip RAM capacity (16MB / core) and speed (20GB / s), it allows each compression IP core to grab 16MB of real-time data from HBM and write it to the on-chip RAM to achieve zero-wait compression calculation. After the calculation is completed, the IP core first writes the result to the on-chip RAM, then writes it back to HBM in batches, and finally the CPU writes the result in HBM to DDR to complete the entire operation.

[0126] This application embodiment can read the capacity and speed of each memory layer, thereby mastering the storage hardware capabilities of the FPGA, and thus realizing the "on-demand flow and speed matching" of the data to be calculated between multiple memory layers. It supports multiple parallel IPs to read data from RAM at the same time and write the calculation results to multiple HBMs, maximizing the parallel computing performance of multiple computing IP cores, and truly realizing the parallel processing of data transmission and computing. It avoids the memory access bottleneck of waiting for the previous computing IP core to complete the data reading operation before the next data acquisition and calculation.

[0127] Step S502: Detect the task type of the computing task, and when the task type is a heterogeneous computing task, allocate the data to be computed corresponding to the heterogeneous computing task to multiple memory layers based on multiple virtual addresses and programmable logic devices 200, so as to execute the heterogeneous computing task according to the data to be computed in multiple memory layers and generate the computing result of the heterogeneous computing task.

[0128] In some embodiments, the CPU may sometimes simply call resources from the FPGA side without requiring the FPGA side to perform calculations.

[0129] Therefore, in this embodiment of the application, after the CPU uniformly addresses all caches, the CPU can detect the task type of the computing task according to the corresponding computing task situation. So that when the computing task is a heterogeneous computing task, that is, when the computing task can be offloaded to the FPGA accelerator for execution, the register unit and data read / write unit in the FPGA accelerator can be used to allocate the data to be computed in the heterogeneous computing task to multiple memory layers.

[0130] Ultimately, the computing units in the FPGA accelerator can call memory resources previously allocated to multiple memory layers based on multiple virtual addresses, thereby executing the heterogeneous computing task and generating its computation results.

[0131] Optionally, in one embodiment of this application, the method further includes: obtaining the usage frequency of the data to be computed corresponding to the heterogeneous computing task; and storing the data to be computed into the dual data rate synchronous dynamic random access memory layer in the programmable logic device 200 when the usage frequency meets the target conditions.

[0132] As one possible approach, considering that the data of some heterogeneous computing tasks may be reused in subsequent processes in addition to being used for current data transmission and computation, this application embodiment can obtain the usage frequency of the data to be computed corresponding to the heterogeneous computing task, and then store the data to be computed into the DDR layer of the FPGA when the usage frequency of the data to be computed meets the target conditions.

[0133] Here, the target condition can be understood as the condition that triggers the storage of data in the DDR layer. Data that meets certain conditions can also be understood as hot data, that is, data that may be accessed again in a short period of time.

[0134] For example, in the embodiments of this application, while data is being transmitted and computed, hot data that will be accessed later can be written to a large-capacity but relatively slow DDR memory, so that data can be moved between caches during the next access, reducing the movement of data from the CPU-side cache or disk to the accelerator, until all computations are completed and cache resources are released.

[0135] It should be noted that the specific target conditions can be determined by those skilled in the art based on the actual situation. The embodiments in this application are only illustrative and do not impose specific limitations. For example, they can be set based on data access frequency (the number of times the data is accessed exceeds a threshold within a specific time window), temporal locality (data that has been recently accessed may be accessed again in the short term), spatial locality (adjacent data is accessed, and the current data may also be accessed), data block size (consistent with the size of a cache line or prefetch unit), etc.

[0136] This application embodiment can transfer temporarily unused data to a larger capacity DDR cache for scenarios where hot data that needs to be accessed again or calculation results will be reused. The data transfer can be completed directly within the chip when used next, thereby effectively reducing the latency caused by data retrieval from the CPU or disk.

[0137] Optionally, in one embodiment of this application, the method further includes: dividing heterogeneous computing tasks according to the transmission bandwidth and computing bandwidth of the data link to obtain multiple slice tasks; and allocating the data to be computed corresponding to the heterogeneous computing tasks to multiple memory layers based on the multiple slice tasks.

[0138] In actual implementation, before allocating the data to be computed corresponding to the heterogeneous computing task to multiple memory layers in the FPGA, in order to improve the efficiency of data transmission and utilization, this application may, but is not limited to, divide the heterogeneous computing task issued by the user according to the transmission bandwidth and computing bandwidth of the data link to obtain multiple slice tasks, and then allocate the data to be computed corresponding to the heterogeneous computing task to multiple memory layers according to the multiple slice tasks.

[0139] In other words, the embodiments of this application can divide a heterogeneous computing task into multiple slice tasks, and the corresponding data to be computed is also divided into the same number as the slice tasks. That is, each slice task contains a portion of the data to be computed. At this time, the data to be computed in each slice task can be transmitted simultaneously. Therefore, the data to be computed in the entire heterogeneous computing task can be divided into multiple parts and transmitted simultaneously as the slice tasks are divided, which can effectively improve data transmission efficiency.

[0140] For example, after a user initiates a computation request, such as performing a full table scan on 8GB of data, the CPU in the heterogeneous computing system 10 in this embodiment of the application, upon receiving such a heterogeneous computing task request, will not first move the 8GB of data to the FPGA simultaneously before starting the computation. Instead, it will divide the task according to the transmission bandwidth and computing bandwidth of the entire data link. In the example above, if the size of each data move is 1MB, 16 data move channels will be started simultaneously to move the data from the disk to the memory of the FPGA.

[0141] Here, the transmission bandwidth of the data link refers to the actual maximum amount of data transmitted per second along the entire data transmission path from the disk to the multiple memory layers of the FPGA. It is not a single path, but the effective speed of the complete link from disk to host memory to FPGA board to FPGA memory layer (the actual value after bus, interface, and protocol losses). It determines how quickly data can be sent into the FPGA.

[0142] The computing bandwidth here refers to the computing bandwidth of the FPGA, which is the maximum amount of data that all computing IP cores in the FPGA participating in heterogeneous computing tasks can process per second when operating in parallel. It determines how quickly the FPGA can complete the calculation of the data it receives.

[0143] For example, if data is not split and moved from disk to FPGA memory all at once, a serious speed mismatch will occur: Assuming the data link bandwidth is only 1GB / s, it would take 8 seconds to move 8GB. FPGA computing bandwidth may be 16GB / s, and it can complete 8GB of computation in just 0.5 seconds; The final total time = 8 seconds (moving) + 0.5 seconds (computation) = 8.5 seconds. The FPGA spends 8 seconds in an idle state, and the expensive computing resources are completely wasted.

[0144] By splitting heterogeneous computing tasks into two bandwidth segments, the total data transfer speed can be precisely matched with the FPGA's computing speed. This allows the CPU to simultaneously transfer the next batch of small data blocks while the FPGA is processing the previous batch, achieving pipelined transfer and computation with no idle time. The final total time is approximately equal to the maximum value (total transfer time + total computation time), resulting in an efficiency improvement of several times.

[0145] Taking an 8GB full table scan computation task, with 1MB data blocks and 16 data transfer sites as an example, the specific operations can be, but are not limited to, as follows: The CPU first calculates the actual single-path transmission bandwidth of the data link and the FPGA computing bandwidth, and then determines two core splitting parameters based on the ratio between the two: Calculate bandwidth ratio: For example, the CPU calculates the single-channel data transmission bandwidth as 1MB / ms, and the FPGA calculates the bandwidth as 16MB / ms (the FPGA can calculate 16GB per second). Determine the number of parallel data transfer sites: In order to match the total transfer speed with the computing speed, start 16 data transfer channels (parallel). At this time, the total data transfer speed = 16 channels × 1MB / ms = 16MB / ms, which is completely synchronized with the FPGA computing speed. Determine the size of the small data blocks: Divide the entire 8GB data into individual 1MB small data blocks (the block size should not be too large or too small: if it is too large, the relocation time will be long and the FPGA will be idle; if it is too small, frequent switching of data blocks will generate additional hardware overhead). Pipeline execution: 16 transfer sites simultaneously move 16 1M data blocks to the FPGA memory. After the FPGA receives the 16M data, it immediately starts calculation. While the FPGA is calculating the 16M data, the 16 transfer sites are already moving the next batch of 16 1M data blocks. This process is repeated until all 8GB of data has been processed.

[0146] Among them, the data transfer site is an independent parallel processing thread / hardware channel created by the CPU for data transfer. The 16 sites are 16 parallel data transfer channels that simultaneously transfer data from the disk to the FPGA memory without interfering with each other. This can improve the overall speed of data transfer through parallel transportation, thereby matching the ultra-high computing speed of the FPGA.

[0147] In simple terms, the CPU breaks down large tasks into smaller data blocks based on the ratio of how quickly the data can be sent to the FPGA to how quickly the FPGA can process the data. Then, multiple parallel data transfer channels are used to ensure that the data transfer speed keeps up with the FPGA's data processing speed, achieving simultaneous data transfer and processing, and fully utilizing the collaborative capabilities of the CPU-FPGA heterogeneous computing system 10.

[0148] Efficiency comparison before and after segmentation: Taking 8GB of data, 1GB / s single-channel transmission, and 16GB / s FPGA computing as an example: Without splitting (one-time transfer): Total time = 8s (transfer) + 0.5s (calculation) = 8.5s, FPGA idle for 8s; Segmentation (1M block + 16 sites): Total transfer speed 16GB / s, total transfer time 0.5s, total calculation time 0.5s, total time consumption ≈ 0.5s, FPGA has no idle time throughout, efficiency improved by 17 times.

[0149] This application embodiment achieves pipelined parallelism between data transmission and FPGA computation by decomposing the task into multiple small data blocks (slice tasks) that can be transmitted and computed in parallel and by initiating multiple data transfer channels. This effectively masks data transfer latency, ensures that the FPGA computing unit is continuously operating at full capacity, and greatly improves the overall system throughput and hardware utilization.

[0150] Optionally, in one embodiment of this application, based on multiple virtual addresses and programmable logic devices 200, the data to be computed corresponding to the heterogeneous computing task is allocated to multiple memory layers to execute the heterogeneous computing task according to the data to be computed in the multiple memory layers and generate the computing result of the heterogeneous computing task, including: obtaining the computing density characteristics and performance requirements of the heterogeneous computing task; and calling the data to be computed in the multiple memory layers to execute the heterogeneous computing task based on the computing density characteristics, performance requirements and unit access energy consumption of the multiple memory layers.

[0151] In actual execution, when the computing unit of the FPGA accelerator in the heterogeneous computing system 10 calls the data to be computed from multiple memory layers to execute computing tasks, it can, but is not limited to, call the data to be computed from multiple memory layers based on the computing density characteristics, performance requirements and unit access energy consumption of the heterogeneous computing task, thereby executing the heterogeneous computing task.

[0152] Here, computation density can be understood as the ratio between the computational operations (such as multiplication and addition) and memory access operations (reading and writing data) required by a computational task per unit of time or unit of data. For example, computationally intensive tasks have a high computation / memory access ratio, such as matrix multiplication and deep learning convolution operations, which require a large number of repetitive calculations on a small amount of data. Memory-intensive tasks have a low computation / memory access ratio, such as data transposition and stream processing, which require frequent movement of large amounts of data from memory, but each data point only undergoes simple processing.

[0153] Performance requirements can be understood here as quantitative metrics that task execution needs to meet, typically including latency (the total time required from input to output completion, for example, processing one frame of an image must be completed within 33 milliseconds to meet the real-time requirement of 30 frames per second) and throughput (the amount of data or number of tasks processed per unit time, for example, processing 1000 images per second).

[0154] The energy consumption per unit access across multiple memory layers can be understood here as the energy consumed to read or write a unit of data (e.g., 1KB) from different levels and technologies of memory. Generally, the faster and smaller the memory, the higher the energy consumption per unit access. For example: Registers / on-chip cache: extremely fast, smallest capacity, highest energy consumption per unit access; HBM: fast, larger capacity, moderate to high energy consumption per unit access; DDR: slower, larger capacity, relatively low energy consumption per unit access.

[0155] Taking the execution of an image reconstruction task on a heterogeneous computing system 10 as an example (the CPU is responsible for task scheduling, control flow, and preprocessing, while the FPGA accelerator is responsible for the most time-consuming core iterative reconstruction algorithm): Multi-level caching: On-chip RAM: extremely fast speed, very small capacity (MB level); HBM: High speed, medium capacity (GB level); DDR: Slower speed, larger capacity (GB level).

[0156] First, the embodiments of this application can obtain the computational density characteristics and performance requirements of heterogeneous computing tasks: the heterogeneous computing system 10 analyzes the task and determines that the core reconstruction algorithm is computationally intensive with high computational density characteristics (requiring sine / cosine interpolation and integral operations on a large amount of projection data); the performance requirements are high throughput (requiring rapid processing of large amounts of patient data) and acceptable latency (a single reconstruction is completed within a few seconds).

[0157] (1) Due to the high computational density of the task and the stringent bandwidth requirements, the system decided to place the complete original projection dataset in HBM. This is because the bandwidth of HBM is sufficient to meet the computational needs of the FPGA, and its unit access energy consumption is lower than the sum of "transportation energy consumption + computation energy consumption" of frequent data exchange using on-chip RAM. DDR is used as a backup pool to store temporarily unused data blocks or data for the next batch of tasks.

[0158] (2) The data management engine within the FPGA monitors that the computing core is accessing data in the HBM in a specific pattern (such as angular order). It predicts several data blocks needed for the next computing cycle and prefetches them from the HBM into the on-chip RAM in advance. In this way, when the computing core needs it, the data is already in the fastest, zero-latency cache, and the computing unit does not need to wait.

[0159] (3) The energy efficiency control unit detects that the bandwidth requirement has decreased slightly in a certain iteration stage of the current reconstruction algorithm. In order to save energy, it can dynamically reduce the voltage frequency of some channels of HBM (enter a low power state) by configuring registers, while ensuring that the performance requirements of this stage can still be met through the cooperation of the remaining channels and on-chip RAM, thereby achieving optimal energy efficiency.

[0160] The embodiments of this application can make more intelligent data scheduling decisions by comprehensively analyzing the computational density characteristics (computation / memory access ratio), performance requirements (latency, throughput), and unit access energy consumption of different memory layers. For example, high-bandwidth memory can be prioritized for computationally intensive tasks, or data can be temporarily stored in low-power memory if performance allows, thereby optimizing the overall energy efficiency of the system while meeting performance goals.

[0161] The following is a detailed explanation of the heterogeneous computing method of the computer using the heterogeneous computing system 10 in the embodiments of this application, using a specific example.

[0162] Figure 7 This is a schematic diagram of a heterogeneous acceleration system with unified multi-level cache management according to an embodiment of this application. Figure 7 As shown, this heterogeneous acceleration system includes CPU and FPGA acceleration devices, and its workflow can be, but is not limited to, represented as follows: (1) After the system is powered on, after the PCIe device is initialized and the device is enumerated, the CPU first reads the relevant information of the multi-level cache in the accelerator, including capacity and speed, and then establishes a three-level memory hierarchy model after obtaining the relevant information. (2) On the FPGA accelerator side, the design treats all available cache resources as PCIe devices and provides device address information. On the software side, all caches are uniformly addressed, all memory resources are mapped to a unified 64-bit virtual address space, and an address translation table is established. The division of the address space will be described in detail in subsequent chapters. (3) When a user initiates a computing task request, the CPU determines whether the task can be unloaded to the accelerator for execution based on the corresponding task situation. For tasks that can be unloaded, the intelligent data placement decision-driven engine is started, and the management and scheduling process of "data transmission-computation-result collection" is initiated. (4) While transmitting data and performing calculations, “hot data” that will be accessed again in the future is written to the large-capacity but relatively slow DDR. The data can be moved between caches during the next access, reducing the movement of data from the CPU-side cache or disk to the accelerator until all calculations are completed and cache resources are released.

[0163] Furthermore, taking 16 computing IP cores as an example, Figure 8 This is a flowchart of a heterogeneous computing process according to an embodiment of this application, such as... Figure 8 As shown: Since RAM has the fastest read and write speed, the DMA operation initiated by the disk writes data into RAM, and 16 channels simultaneously start data transfer (there will be a slight start delay). At the same time, 16 functional IP operators on the FPGA board start working, and the calculation results are written to the HBM cache that supports 16 user interfaces. After the calculation is completed, the result processing unit feeds back the calculation results to the CPU-side memory through the DMA controller on the FPGA side, or directly writes the data to the disk through the memory expansion module, according to the needs of the CPU.

[0164] There are two usage scenarios for DDR: (1) For the source data before the calculation, other calculation operations may be performed on the data again later; (2) The results of the previous calculation will be used as input for the next round of calculation or saved as historical data, similar to the results of the previous dialogue in a large artificial intelligence model.

[0165] In case (1), the embodiments of this application can synchronously write the source data into DDR when the source data is written into RAM or after the data transmission is completed. Since the crossbar switch is a full network connection, hot data backup can be achieved simply by changing the destination address of the DMA data transfer.

[0166] In case (2), the data calculation results can be temporarily stored in HBM and can be directly obtained from HBM in the next round of calculation. However, when the space of HBM is full or the result data is not used for a long time, it needs to be transferred to DDR for temporary storage.

[0167] Both scenarios involve the need to move data between caches. For RAM, it can be configured as a dual-port RAM. Therefore, data is written to RAM from the DMA path on one side and read from the other side through the IP core via the switch, which is equivalent to completing the data movement between caches.

[0168] For data migration between DDR and HBM, a Data_Mover module (inter-memory data migration module) needs to be designed. This module has two external interfaces: First, there is the AXI_Lite_Slave interface (a slave endpoint of the AXI-Lite bus protocol). This interface receives instructions from the CPU through the requester / requester completion interface in PCIe, thereby initiating read and write operations to the backend memory device. Second is the AXI_Stream interface (Advanced eXtensible Interface-Stream), which allows access to the backend device's memory. A diagram illustrating data migration is shown below. Figure 8 As shown.

[0169] To enable faster data transfer, the Data_Mover's data interface can be set to AXI-Stream. The backend converts the data to an AXI4 interface via a protocol and then accesses the device memory via a switch to move data between memory. Hot data or intermediate results are written to DDR, and can be read directly from DDR during the next calculation, reducing the latency caused by moving data from disk or host memory.

[0170] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0171] Embodiments of this application also provide a heterogeneous computing device 20 for a computer, employing a heterogeneous computing system 10 for a computer, such as... Figure 9 As shown, the heterogeneous computing device 20 of the computer includes an addressing module 300 and a computing module 400.

[0172] The addressing module 300 is used to read memory resources corresponding to multiple memory layers in the programmable logic device, encode the memory resources to obtain multiple virtual addresses corresponding to the memory resources, wherein the multiple memory layers include a random access memory layer, a high bandwidth memory layer and a dual data rate synchronous dynamic random access memory layer. The computing module 400 is used to detect the task type of the computing task, and when the task type is a heterogeneous computing task, it allocates the data to be computed corresponding to the heterogeneous computing task to multiple memory layers based on multiple virtual addresses and programmable logic devices, so as to execute the heterogeneous computing task according to the data to be computed in multiple memory layers and generate the computing result of the heterogeneous computing task.

[0173] Optionally, in one embodiment of this application, it further includes: The first acquisition module is used to acquire the task requirements of the computing task before reading the memory resources corresponding to multiple memory layers in the programmable logic device and addressing the memory resources. The determination module is used to determine the number of paths corresponding to multiple memory layers based on task requirements.

[0174] Optionally, in one embodiment of this application, the addressing module 300 includes: The read unit is used to read the capacity and speed of multiple memory layers in a programmable logic device. The determination unit is used to determine memory resources based on capacity and speed.

[0175] Optionally, in one embodiment of this application, it further includes: The second acquisition module is used to acquire the usage frequency of the data to be computed corresponding to the heterogeneous computing task. The storage module is used to store the data to be calculated into the dual data rate synchronous dynamic random access memory layer in the programmable logic device, provided that the usage frequency meets the target conditions.

[0176] Optionally, in one embodiment of this application, it further includes: The partitioning module is used to divide heterogeneous computing tasks according to the transmission bandwidth and computing bandwidth of the data link, resulting in multiple slice tasks; The allocation module is used to allocate the data to be computed for heterogeneous computing tasks to multiple memory layers based on multiple slice tasks.

[0177] Optionally, in one embodiment of this application, the computing module 400 includes: The acquisition unit is used to acquire the computational density characteristics and performance requirements of heterogeneous computing tasks; The invocation unit is used to invoke data to be computed in multiple memory layers to execute heterogeneous computing tasks based on computing density characteristics, performance requirements, and unit access energy consumption of multiple memory layers.

[0178] For a description of the features in the embodiments corresponding to the heterogeneous computing device of the computer, please refer to the relevant descriptions in the embodiments corresponding to the heterogeneous computing method of the computer, which will not be repeated here.

[0179] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the heterogeneous computing method embodiments of the computer described above.

[0180] Embodiments of this application also provide a non-volatile computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described embodiments of the heterogeneous computing method for computers at runtime.

[0181] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0182] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described embodiments of the heterogeneous computing method for computers.

[0183] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described embodiments of the heterogeneous computing method for computers.

[0184] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0185] The above provides a detailed description of a heterogeneous computing system and method for computers provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A heterogeneous computing system for computers, characterized in that, It includes processing devices and programmable logic devices, wherein the programmable logic devices include register units, data read / write units, and computing units, wherein... The register unit is used to determine the computing core based on the physical address of the data to be computed corresponding to the heterogeneous computing task of the processing device, determine the target configuration register based on the physical address and the computing core, and allocate the data to be computed to the target configuration register. The data read / write unit is used to allocate the data to be computed to the corresponding memory layers among multiple memory layers through a first crossbar switch based on the target configuration register, so as to drive the computing unit to execute the heterogeneous computing task according to the data to be computed corresponding to the multiple memory layers. Each memory layer has different physical characteristics, and each memory layer is communicatively connected to the target configuration register through the first crossbar switch. The register unit includes: a register configuration management module, which parses the data to be calculated to obtain the data type of the data to be calculated; and a cascading unit, which allocates the data to be calculated to the target configuration register according to the data type and the base address of the register. The cascaded unit further includes: an address decoder, used to allocate the data to be computed to at least one slave interface according to the data type and the base address of the register; and at least one second cross switch, used to allocate the data to be computed to the target configuration register based on the at least one slave interface and the number of computing cores.

2. The heterogeneous computing system of a computer according to claim 1, characterized in that, The address decoder is connected to at least one second cross switch, and the at least one second cross switch is connected to at least one of the target configuration registers.

3. The heterogeneous computing system of a computer according to claim 1, characterized in that, The data read / write unit includes: Multiple request interfaces, multiple controllers, and multiple compute core read / write modules; The first cross switch is connected to multiple request interfaces, multiple controllers, and multiple computing core read / write modules, respectively, wherein each controller is connected to the corresponding memory layer, and each computing core is connected to the corresponding target configuration register; The first cross switch connects the random access memory layer, the high bandwidth memory layer, and the dual data rate synchronous dynamic random access memory layer.

4. The heterogeneous computing system of a computer according to claim 1, characterized in that, The first cross switch is used to respond to a memory access request from the processing device to transfer the memory data corresponding to the memory access request to the processing device.

5. The heterogeneous computing system of a computer according to claim 1, characterized in that, The first cross switch is also used to respond to read / write requests from the programmable logic device to move and transfer memory data of the programmable logic device to the processing device and / or the hard disk corresponding to the processing device.

6. The heterogeneous computing system of a computer according to claim 1, characterized in that, The multiple memory layers include a random access memory layer, a high-bandwidth memory layer, and a dual data rate synchronous dynamic random access memory layer.

7. The heterogeneous computing system of a computer according to claim 1, characterized in that, The multiple memory layers include a random access memory layer and a high-bandwidth memory layer.

8. The heterogeneous computing system of a computer according to claim 1, characterized in that, The multiple memory layers include a high-bandwidth memory layer and a dual-data-rate synchronous dynamic random access memory layer.

9. The heterogeneous computing system of a computer according to claim 1, characterized in that, The multiple memory layers include a random access memory layer and a dual data rate synchronous dynamic random access memory layer.

10. A heterogeneous computing method for computers, characterized in that, A heterogeneous computing system employing the computer as described in any one of claims 1-9, wherein the method comprises the following steps: Read the memory resources corresponding to multiple memory layers in the programmable logic device, encode the memory resources by address to obtain multiple virtual addresses corresponding to the memory resources, wherein the multiple memory layers include a random access memory layer, a high bandwidth memory layer and a dual data rate synchronous dynamic random access memory layer; The task type of the computing task is detected, and when the task type is a heterogeneous computing task, the data to be computed corresponding to the heterogeneous computing task is allocated to the multiple memory layers based on the multiple virtual addresses and programmable logic devices, so as to execute the heterogeneous computing task according to the data to be computed in the multiple memory layers and generate the computing result of the heterogeneous computing task.

11. The method according to claim 10, characterized in that, Before reading the memory resources corresponding to multiple memory layers in the programmable logic device and encoding the addresses of the memory resources, the method further includes: Obtain the task requirements for the computation task; The number of paths corresponding to the multiple memory layers is determined based on the task requirements.

12. The method according to claim 10, characterized in that, The reading of memory resources corresponding to multiple memory layers in the programmable logic device includes: Read the capacity and speed of multiple memory layers in a programmable logic device; The memory resources are determined based on the capacity and the speed.

13. The method according to claim 10, characterized in that, Also includes: Obtain the usage frequency of the data to be computed corresponding to the heterogeneous computing task; When the usage frequency meets the target conditions, the data to be calculated is stored in the dual data rate synchronous dynamic random access memory layer in the programmable logic device.

14. The method according to claim 10, characterized in that, Also includes: The heterogeneous computing tasks are divided according to the data link's transmission bandwidth and computing bandwidth to obtain multiple slice tasks; Based on the multiple slice tasks, the data to be computed corresponding to the heterogeneous computing tasks is allocated to the multiple memory layers.

15. The method according to claim 10, characterized in that, The step of allocating the data to be computed corresponding to the heterogeneous computing task to the multiple memory layers based on the multiple virtual addresses and programmable logic devices, and executing the heterogeneous computing task according to the data to be computed in the multiple memory layers to generate the computing result of the heterogeneous computing task, includes: Obtain the computational density characteristics and performance requirements of the heterogeneous computing task; Based on the computational density characteristics, the performance requirements, and the unit access energy consumption of the multiple memory layers, the heterogeneous computing task is executed by calling the data to be computed in the multiple memory layers.

16. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the heterogeneous computing method of the computer as described in any one of claims 10 to 15 when executing the computer program.

17. A non-volatile computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the heterogeneous computing method of the computer as described in any one of claims 10 to 15.

18. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the heterogeneous computing method of the computer as described in any one of claims 10 to 15.

Images