A real-time fault diagnosis method for edge computing platform

Abstract

The application provides a real-time fault diagnosis method for an edge computing platform, comprising collecting sensor signals through a data acquisition card, and transmitting the collected data to a shared buffer of the edge computing platform; performing frequency domain or time-frequency domain transformation on the original time domain signals in the shared buffer to generate a frequency domain or time-frequency domain feature tensor obtained after signal processing, the data scale of the feature tensor being smaller than that of the corresponding original time domain signal; and inputting the feature tensor into a deep learning model deployed on the edge computing platform for real-time fault identification. In addition, the application also proposes a model automatic deployment and rollback mechanism based on a decision logic tree, which effectively solves the reasoning accuracy degradation problem after model deployment through multi-stage decisions such as accuracy detection, problem positioning and operator replacement. Through systematic optimization in aspects such as hardware platform selection, data processing mode and model deployment strategy, the real-time performance, stability and adaptability of the system in an industrial environment are significantly improved.

Description

Technical Field

[0001] This invention belongs to the field of fault diagnosis technology, and in particular relates to a real-time fault diagnosis method for edge computing platforms. Background Technology

[0002] With the development of industrial automation and intelligent manufacturing, equipment operation status monitoring and fault diagnosis technologies are playing an increasingly important role in industrial production. Especially in rotating machinery (such as bearings, gears, and motors), equipment faults are often accompanied by changes in vibration signal characteristics. Therefore, fault diagnosis through vibration signal analysis has become an important technical means.

[0003] In recent years, with the development of deep learning technology, intelligent fault diagnosis methods based on models such as convolutional neural networks and deep neural networks have been gradually applied to the field of industrial equipment monitoring. Compared with traditional signal processing methods, deep learning models can automatically extract complex feature patterns, thereby significantly improving the accuracy and robustness of fault identification.

[0004] However, most deep learning models typically rely on significant computing resources, and their training and inference processes often require high-performance computing devices. In practical industrial applications, many monitoring systems need to be deployed on edge devices or embedded devices, such as industrial gateways or edge computing nodes, to achieve real-time monitoring and rapid response of device status. Therefore, how to achieve efficient deployment and real-time inference of deep learning models on resource-constrained edge devices has become an important direction of current technological research.

[0005] Current technologies primarily attempt to solve this problem through the following methods:

[0006] (1) Model lightweighting method:

[0007] By reducing the model size through methods such as model pruning, parameter quantization, and knowledge distillation, the computational complexity and storage requirements of the model can be reduced, thereby adapting to resource-constrained hardware platforms.

[0008] (2) Optimization of the edge reasoning framework:

[0009] We implement deep learning model inference on embedded platforms using lightweight inference frameworks such as TensorFlow Lite and ncnn.

[0010] (3) Low-power embedded deployment:

[0011] Deploy fault diagnosis models on Raspberry Pi, microcontrollers, or other embedded devices to enable real-time monitoring of field equipment.

[0012] While the aforementioned technologies have driven the development of edge intelligent fault diagnosis to some extent, several challenges remain in real-world industrial environments. For example, low-power embedded devices face significant limitations in computing power, memory capacity, and data processing capabilities, often struggling to simultaneously meet the requirements of real-time performance and diagnostic accuracy when dealing with high-frequency vibration signal acquisition and complex deep learning models. Furthermore, in high-speed data acquisition scenarios, the large volume of data generated by sensors can easily lead to excessive system computational load without an effective data processing mechanism, thus impacting model inference efficiency.

[0013] Therefore, how to achieve coordinated optimization among high-frequency data acquisition, efficient feature processing, and stable model inference on edge computing platforms has become an urgent problem to be solved in current technology.

[0014] While many studies have achieved promising experimental results in laboratory or simulated environments, the adaptability and stability of these technologies still face significant challenges when applied to real-world industrial environments. Industrial sites typically exhibit complex and variable operating conditions, such as changes in equipment operating status, environmental noise interference, differences in operating conditions, and fluctuations in sensor data. These factors all affect the stability and accuracy of model inference. Most existing technologies validate their effectiveness under relatively ideal experimental conditions. However, in real industrial environments, due to variations in data distribution and hardware resource limitations, it is often difficult to guarantee long-term stable operation. Furthermore, many existing solutions rely primarily on general-purpose edge devices and standard inference frameworks. When faced with scenarios involving high-frequency vibration signal acquisition, real-time inference requirements, and complex model deployments, they often lack sufficient flexibility and robustness, making it difficult to effectively cope with the constantly changing operating environments of industrial sites. Summary of the Invention

[0015] In view of this, the present invention aims to overcome the shortcomings of the above-mentioned problems in the prior art and proposes a real-time fault diagnosis method for edge computing platforms. By systematically optimizing hardware platform selection, data processing methods and model deployment strategies, the real-time performance, stability and adaptability of the system in industrial environments can be significantly improved.

[0016] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0017] In a first aspect, the present invention provides a real-time fault diagnosis method for edge computing platforms, comprising the following steps:

[0018] Sensor signals are acquired at a high-speed sampling frequency using a data acquisition card, and the acquired data is transmitted to the shared buffer of the edge computing platform.

[0019] The original time-domain signal in the shared buffer is transformed into a frequency domain or a time-frequency domain to generate a frequency domain or time-frequency domain feature tensor after signal processing. The data size of the feature tensor is smaller than that of the corresponding original time-domain signal.

[0020] The feature tensor is input into a deep learning model deployed on an edge computing platform for real-time fault identification;

[0021] It also includes a model deployment and rollback mechanism, which includes:

[0022] Standard model deployment phase: During the model training phase, the PyTorch deep learning framework is used to train the model, and FP32 precision is used to optimize the model parameters. After training, the model is exported as a computation graph structure in ONNX format, and then an FP16 inference engine is built through TensorRT. The accuracy of the inference results of the TensorRT engine is verified.

[0023] Accuracy Anomaly Detection Phase: When the error between the TensorRT FP16 inference result and the PyTorch FP32 inference result exceeds a preset threshold, the problem investigation and repair process begins.

[0024] Furthermore, performing frequency domain or time-frequency domain transformation on the original time-domain signal in the shared buffer includes: Fast Fourier Transform or Continuous Wavelet Transform.

[0025] Furthermore, the shared buffer is a circular queue or a double-buffered queue structure, and is implemented in any of the following ways:

[0026] User-space shared memory based on mmap;

[0027] Cross-driver shared buffer based on dma-buf;

[0028] CPU / GPU shared buffer based on CUDA page-locked memory or unified memory.

[0029] Furthermore, the edge computing platform is a Jetson series platform that integrates a GPU and a CPU.

[0030] Furthermore, the troubleshooting and repair process includes:

[0031] Link investigation steps: Divide the model deployment process into the PyTorch to ONNX model conversion stage and the ONNX to TensorRT inference engine construction stage. Compare the inference output between PyTorch and ONNX, and ONNX and TensorRT respectively to pinpoint the conversion stage where accuracy loss occurs.

[0032] Module-level localization steps: Decouple the neural network model into multiple functional sub-modules, execute ONNX export and TensorRT inference engine construction for each sub-module, compare the output of each module, and locate the problem sub-module;

[0033] Operator-level diagnostic steps: Identify anomalous operators in problematic submodules using ONNX computation graph parsing tools and TensorRT engine log building tools;

[0034] Operator replacement steps: Replace the original problematic operators by customizing the TensorRT Plugin, constructing equivalent operator combinations, or modifying the ONNX computation graph structure.

[0035] Furthermore, when an abnormal operator cannot be replaced or the replacement cost exceeds a preset threshold, a combined inference rollback mechanism is adopted: submodules that do not exhibit precision anomalies continue to be executed using the TensorRT FP16 engine, while submodules that exhibit precision anomalies roll back to the PyTorch FP32 inference mode.

[0036] Furthermore, for the submodules that fall back to PyTorch FP32 inference, the PyTorch compilation optimization tools are used for further compilation and execution.

[0037] Furthermore, it also includes using the Polygraphy toolchain provided by NVIDIA to compare the output of ONNX Runtime inference results with TensorRT inference results layer by layer, and to identify the specific levels of numerical deviations within the model by performing error analysis on the output tensors of the two inference engines.

[0038] Secondly, the present invention provides a real-time fault diagnosis system for edge computing platforms, comprising:

[0039] The data acquisition module is used to acquire sensor signals at a high-speed sampling frequency through the data acquisition card and transmit the acquired data to the shared buffer of the edge computing platform;

[0040] The signal preprocessing module is used to perform frequency domain or time-frequency domain transformation on the original time domain signal in the shared buffer to generate a frequency domain or time-frequency domain feature tensor obtained after signal processing. The data size of the feature tensor is smaller than that of the corresponding original time domain signal.

[0041] The model inference module is used to input the feature tensor into a deep learning model deployed on an edge computing platform for real-time fault identification.

[0042] The model deployment and rollback module includes:

[0043] Standard model deployment phase: During the model training phase, the PyTorch deep learning framework is used to train the model, and FP32 precision is used to optimize the model parameters. After training, the model is exported as a computation graph structure in ONNX format, and then an FP16 inference engine is built through TensorRT. The accuracy of the inference results of the TensorRT engine is verified.

[0044] Accuracy Anomaly Detection Phase: When the error between the TensorRT FP16 inference result and the PyTorch FP32 inference result exceeds a preset threshold, the problem investigation and repair process begins.

[0045] Compared with existing technologies, the real-time fault diagnosis method for edge computing platforms described in this invention has the following advantages:

[0046] 1. Improved Inference Performance and Stability of Edge Devices: Unlike existing technologies that generally rely on low-power platforms such as Raspberry Pi, this invention is specifically optimized for the more powerful Jetson edge computing platform, enabling it to support more complex deep learning models and achieve an optimal balance between inference accuracy and speed. Especially in industrial scenarios where the requirements for high accuracy and low latency are stringent, this invention can operate more stably and efficiently in these environments.

[0047] 2. Addressing the mismatch between data acquisition and inference: When facing the challenge of high-speed data acquisition (such as millions of data points per second), this invention successfully reduces the amount of data through innovative data acquisition and signal preprocessing technologies, thereby ensuring smooth execution of model inference in a high-speed acquisition environment. This effectively solves the inference latency problem existing in the prior art and improves the efficiency of real-time inference.

[0048] 3. Balance and optimization of accuracy and inference speed: This invention uses a hybrid inference mode, TensorRT's optimization and acceleration technology and PyTorch's fallback scheme to ensure that the balance between inference speed and accuracy can be flexibly adjusted. The most suitable inference accuracy is selected for different sub-modules to maximize inference efficiency and ensure that accuracy is not lost.

[0049] 4. Modular Design and Automatic Rollback Repair Mechanism: This invention solves the problems of operator incompatibility or accuracy collapse in existing technologies by modularizing and decoupling the model, combined with stepwise accuracy verification and operator replacement. Even in the event of accuracy degradation, the system can restore accuracy through an automatic rollback mechanism and compensate for the performance loss caused by rollback through a performance compensation mechanism, thereby ensuring that the model always maintains stability and efficiency on edge devices.

[0050] 5. Strong robustness in industrial environments: Compared to traditional solutions that rely on cloud-based inference, this invention reduces reliance on the cloud and enables local real-time inference on edge devices, making it particularly suitable for fault diagnosis tasks in complex industrial environments. Whether in high-frequency vibration data acquisition or under varying industrial conditions, this invention provides stronger robustness and adaptability.

[0051] 6. Memory Management and Inference Efficiency Optimization: This invention employs advanced memory management technology, significantly reducing I / O operation latency and improving data transmission efficiency by residing data in memory or pre-loading it to GPU memory. The system can efficiently execute complex deep learning tasks on edge computing platforms, further enhancing inference speed. Attached Figure Description

[0052] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings:

[0053] Figure 1 This is a schematic diagram of the test bench structure of the present invention;

[0054] Figure 2 Flowchart for the data access and computing power collaboration phase;

[0055] Figure 3 Ideal deployment flowchart;

[0056] Figure 4 This is a flowchart for the problem investigation phase. Detailed Implementation

[0057] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0058] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0059] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0060] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0061] Example 1

[0062] This invention is specifically optimized for the Jetson edge computing platform, differing from the general-purpose embedded platforms such as the Raspberry Pi commonly used in existing technologies. The Jetson series platform integrates a high-performance GPU and a multi-core CPU, providing stronger parallel computing capabilities and higher inference throughput, making it particularly suitable for real-time inference tasks of deep learning models. By fully leveraging the advantages of the Jetson platform in GPU acceleration, parallel computing, and deep learning inference frameworks, this invention can support more complex neural network models and achieve low-latency inference while maintaining high inference accuracy. Furthermore, through targeted optimization of the Jetson platform's operating environment and inference framework, the overall system computational efficiency can be significantly improved, enabling it to maintain stable and reliable operation even in complex industrial scenarios.

[0063] This invention not only focuses on model inference accuracy but also addresses the real-time inference problem of end-side devices under high-speed sensor data acquisition conditions. In industrial equipment monitoring scenarios, vibration sensors often collect equipment operation data at extremely high sampling frequencies, such as tens of thousands or even hundreds of thousands of sampling points per second. Directly performing model inference on the raw data often leads to excessive computational load, thereby affecting the system's real-time response capability.

[0064] To address the aforementioned issues, this invention introduces a frequency reduction and dimensionality reduction mechanism for high-frequency signals during the data processing stage. By extracting frequency or time-frequency domain features from the original vibration signal, the original time-domain data stream, generated continuously at an extremely high sampling rate, is transformed into a frequency or time-frequency domain feature stream with lower data volume but retaining key fault characteristics, thereby significantly reducing the input data size. Simultaneously, by optimizing the data processing and inference processes, the system can significantly reduce the model's computational burden and improve inference efficiency while ensuring the integrity of feature information.

[0065] Through the above optimization methods, the present invention can achieve low-latency and high-efficiency real-time inference in high-speed data acquisition environments, significantly reducing the inference latency problem of traditional systems in high-frequency data scenarios, enabling the system to operate stably for a long time in industrial environments, and possessing stronger adaptability and robustness.

[0066] The following is a detailed description of the real-time fault diagnosis method for edge computing platforms provided by this invention, including two core parts: the data access and computing power collaboration stage and the model deployment and rollback logic tree.

[0067] I. Data Access and Computing Power Collaboration Phase

[0068] like Figure 2 As shown, before entering model inference, this invention first constructs a data access and cache scheduling mechanism for high-speed sampling scenarios to solve the mismatch between the high-speed sampling rate of sensors and the model inference rate of edge computing platforms, thereby ensuring that the system can still stably perform real-time preprocessing and intelligent inference under high-speed data acquisition conditions.

[0069] In this invention, the sensor does not directly transmit the raw signal to the CPU or GPU. Instead, the data acquisition card first samples, buffers, and encapsulates the sensor's output signal, and then transmits the sampled data to the Jetson edge computing platform via a USB interface. The test bench is as follows... Figure 1 As shown, it includes a vibration sensor 1, a data acquisition card 2, an experimental bearing 3, a Jetson edge computing platform 4, and a drive motor 5.

[0070] The Jetson side uses a C++-based data receiving module to receive data streams uploaded by the acquisition card via the USB driver layer or user-space communication library, and writes the received data into a pre-allocated memory buffer for subsequent preprocessing and inference modules to read.

[0071] To reduce the latency caused by repeated copying of data between the receiving, preprocessing, and inference stages, this invention establishes a shared buffer mechanism on the Jetson side.

[0072] As a further solution, the shared buffer of the present invention adopts a circular queue or double-buffered queue structure. The USB receiving thread is responsible for sequentially writing data blocks, and the preprocessing thread and the model inference thread read from the shared buffer without locks or with low locks according to the read and write pointers, thereby realizing the continuous transfer of data streams between different processing modules.

[0073] On the Jetson platform, the shared buffer can be configured as follows:

[0074] User-space shared memory buffer based on mmap; or

[0075] Cross-driver / cross-module shared buffer based on dma-buf; or

[0076] CPU / GPU shared buffer based on CUDA pinned memory or unified memory.

[0077] Since Jetson uses an architecture where the CPU and integrated GPU share physical memory, the GPU can directly access the data in the corresponding buffer after the CPU completes USB data reception, reducing the overhead of the traditional "main memory → video memory" explicit copy and thus improving the overall processing throughput.

[0078] As a further approach, this invention employs Fast Fourier Transform (FFT) or Continuous Wavelet Transform (CWT) to convert long-time high-frequency signals into frequency domain or time-frequency domain feature tensors. These transformations can effectively extract periodic features, fault features, and energy distribution features from the signal, and significantly compress the amount of original data, enabling the model inference process to proceed smoothly at lower inference frequencies.

[0079] By converting time-domain signals into frequency-domain features, the FFT can highlight periodic components and ignore noise and redundant information, thereby reducing data dimensionality and improving processing efficiency. The formula for FFT is:

[0080]

[0081] Where: X(f) is the frequency domain signal; x(n) is the time domain signal; N is the signal length; f is the frequency; and j is the imaginary unit.

[0082] By performing FFT, the original high-frequency time-domain signal can be converted into frequency-domain features, while retaining the core frequency information of the fault signal and significantly compressing the amount of data.

[0083] CWT, on the other hand, decomposes a signal into components of different frequencies through multi-scale analysis, thus capturing the time-frequency variations in the signal. The formula for CWT is:

[0084]

[0085] Where: ψ(a,b) are wavelet transform coefficients; a is the scaling parameter; b is the translation parameter; is the complex conjugate of the wavelet basis function; x(t) is the time-domain signal.

[0086] Through CWT's multi-scale analysis, the system can extract the time-frequency characteristics of signals, making it suitable for processing non-stationary signals, especially those with instantaneous changes or high-frequency vibrations.

[0087] By dividing a continuously sampled signal into multiple data segments according to a time window and performing FFT or CWT transformation on each data segment, two-dimensional or three-dimensional feature tensors suitable for neural network inputs can be generated. These feature tensors not only preserve the main fault features, periodic features, or energy distribution features of the original signal, but also greatly reduce the dimensionality of the input data, avoiding the computational burden caused by high-frequency signals.

[0088] For example, by performing FFT or CWT transformations on the original time-domain signal within each time window, the generated feature tensors become more compact and information-rich. In this way, the system transforms the original time-domain data stream, which was originally generated continuously at extremely high sampling rates, into a frequency-domain or time-frequency-domain feature stream with lower data volume but retaining key fault characteristics. This allows the input scale of the model inference to match the real-time processing capabilities of the edge computing platform. While ensuring the integrity of fault characteristics, this effectively reduces the computational load of model inference, enabling the system to continuously and stably perform real-time fault identification in industrial settings.

[0089] By employing frequency reduction and dimensionality reduction preprocessing, this invention effectively transforms data from ultra-high-frequency time-domain signals into feature tensors with low data volume but high data feature density. This allows subsequent model inference to meet real-time recognition requirements with only a lower inference frequency. In this way, the system reduces the computational burden of data processing while ensuring real-time performance and efficiency in industrial scenarios.

[0090] To further improve real-time performance, this invention pre-allocates and manages the data buffer, preprocessing result buffer, and model input buffer.

[0091] As a further solution, the shared buffer is initialized upon system startup, and the USB receiving module, preprocessing module and inference module are pipelined around the same batch of buffers through page-locked memory or unified memory method, avoiding frequent memory allocation / release during operation.

[0092] Meanwhile, by using event synchronization, read / write index synchronization, or CUDA synchronization mechanisms, data consistency and timing correctness between CPU writes and GPU reads are ensured, thereby reducing I / O wait time and memory transfer latency, and improving system response speed and real-time inference stability. NVIDIA documentation also notes that while shared buffers can reduce copying, synchronization control is still necessary during concurrent CPU / GPU access.

[0093] II. Model Deployment and Rollback Mechanism Based on Decision Logic Tree

[0094] To address the potential issues of decreased inference accuracy, operator incompatibility, and insufficient model stability during the deployment of deep learning models on edge devices, this invention proposes an automatic model deployment and rollback mechanism based on decision logic trees.

[0095] This mechanism constructs a multi-stage decision structure with capabilities for accuracy detection, problem localization, operator repair, and safe rollback. This enables the model to automatically identify inference accuracy anomalies during deployment and select operator replacement, combined inference, or rollback strategies based on specific circumstances, thereby improving the overall system efficiency and stability while ensuring inference accuracy.

[0096] In this invention, the deployment logic preferably includes the following two stages.

[0097] (I) Standard Model Deployment Phase

[0098] like Figure 3 As shown, under ideal conditions, the present invention first performs the standard model deployment process.

[0099] Specifically, during the model training phase, the PyTorch deep learning framework is used to train the model, and FP32 precision is used to optimize the model parameters. After training, the model is exported as a computation graph structure in ONNX (Open Neural Network Exchange) format.

[0100] Subsequently, the ONNX model is optimized and built using the TensorRT inference engine, transforming it into a TensorRT inference engine suitable for edge device deployment. Preferably, FP16 inference accuracy is used in this process to fully utilize the parallel computing power of the GPU and improve inference speed.

[0101] After the model conversion is completed, the system verifies the accuracy of the TensorRT engine inference results. When the error between the TensorRT FP16 inference results and the PyTorch FP32 inference results meets the preset threshold, it indicates that the model conversion has not affected the model accuracy, and the model can be directly deployed to the target device for online inference.

[0102] When the detected inference result error exceeds a preset threshold, it indicates that the model may experience accuracy degradation during the conversion process. At this point, the system automatically enters the problem-solving phase. Figure 4 As shown.

[0103] (II) Model Conversion Accuracy Check Mechanism

[0104] When an abnormality in model inference accuracy is detected, this invention first uses a model conversion link investigation mechanism to preliminarily locate the source of accuracy loss.

[0105] In this mechanism, the model deployment process is divided into two independent phases:

[0106] PyTorch to ONNX model conversion stage

[0107] ONNX to TensorRT Inference Engine Development Phase

[0108] By comparing and analyzing the inference outputs of the two stages separately, the specific point at which accuracy loss occurs can be determined. For example, when the inference results of PyTorch and ONNX are consistent, but the inference results of TensorRT deviate, it can be determined that the accuracy problem originates from the TensorRT engine optimization or operator implementation process.

[0109] By using the methods described above, the scope of problem identification can be quickly narrowed down, and the efficiency of investigation can be improved.

[0110] (III) Model structure decoupling and module-level localization mechanism

[0111] After completing the macro-level link investigation, this invention further performs fine-grained analysis of the internal computational structure of the model through a model structure decoupling mechanism.

[0112] Specifically, the complete neural network model is decomposed into multiple independent functional sub-modules, such as a feature extraction module, a feature fusion module, and a prediction output module. Subsequently, the decomposed sub-modules are validated through serial forward propagation in the PyTorch environment to ensure that the model decomposition operation does not alter the original computational logic of the model or introduce new accuracy errors.

[0113] After confirming that the decomposition process would not affect the model accuracy, the system further performed ONNX export and TensorRT inference engine construction on each sub-module, and compared the inference output of each sub-module one by one.

[0114] This module-by-module verification method can accurately pinpoint the specific sub-module that causes a decrease in inference accuracy.

[0115] (iv) Operator-level precision diagnosis mechanism

[0116] After locating the problem submodule, this invention further performs operator-level analysis of the internal calculation process of the module.

[0117] First, the model structure is visualized and analyzed using the ONNX computation graph analysis tool to identify the specific operator types contained within the modules. Simultaneously, the TensorRT engine build log tool is used to analyze the TensorRT optimization process, thereby identifying situations such as operator precision degradation, operator rollback, or unsupported operators.

[0118] Furthermore, this invention preferably employs the Polygraphy toolchain provided by NVIDIA to perform a layer-by-layer output comparison between the ONNX Runtime inference results and the TensorRT inference results. By performing error analysis on the output tensors of the two inference engines, the specific levels at which numerical deviations occur within the model can be identified.

[0119] Finally, this invention also constructs a hierarchical forward propagation debugging mechanism in the PyTorch environment. Specifically, by registering forward propagation hook functions on key modules of the model, the feature tensors of each layer's output are recorded during forward propagation. Subsequently, the output results of each layer in PyTorch are compared and analyzed with the corresponding layer outputs during TensorRT inference, thereby tracing the propagation path of numerical errors in the network and achieving more refined hierarchical diagnosis.

[0120] (v) Operator replacement and repair mechanism

[0121] When operator-level analysis identifies a problematic operator, this invention can repair the model structure through an operator replacement mechanism.

[0122] Specifically, the numerical stability of TensorRT FP16 inference can be restored by replacing the original problematic operators through custom TensorRT Plugins, constructing equivalent operator combinations, or modifying the ONNX computation graph structure.

[0123] This approach effectively addresses the issue of operator precision anomalies while maintaining TensorRT's inference acceleration capabilities.

[0124] (vi) Backtracking mechanism for combinatorial reasoning

[0125] In some cases, problematic operators may be difficult to resolve through operator replacement, or the cost of repair may be too high. In such cases, this invention employs a combinatorial reasoning mechanism to construct a hybrid reasoning pipeline.

[0126] Under this mechanism, the model inference process is divided into multiple sub-computation modules. Modules that do not affect accuracy continue to be executed using the TensorRT FP16 engine, while modules that experience accuracy anomalies retain the PyTorch FP32 inference method.

[0127] This hybrid inference structure allows for the acceleration of other modules using TensorRT while ensuring the inference accuracy of critical computation modules, thus achieving a balance between inference efficiency and accuracy.

[0128] (vii) Performance optimization mechanism for rollback module

[0129] When some modules fall back to PyTorch inference, this invention further optimizes their execution efficiency through a model compilation optimization mechanism.

[0130] Specifically, the rollback module is compiled and executed using PyTorch's compiler optimization tools, thereby reducing the performance overhead of the Python interpretation layer and improving computational efficiency. This approach effectively mitigates the performance loss caused by the rollback strategy, thus maintaining the overall inference capability of the system.

[0131] In summary, the method proposed in this invention combines efficient data processing with intelligent inference technology to ensure a balance between accuracy and real-time performance of deep learning models on edge devices.

[0132] First, in the data and computing power preparation phase, this invention addresses the mismatch between data acquisition speed and inference speed through a high-speed data acquisition module. Specifically, the system uses a low-level data acquisition unit built in C++ to ensure that sensor data can be quickly transmitted to the computing platform (e.g., CPU or GPU). Through core preprocessing techniques such as Fourier Transform (FFT) or Continuous Wavelet Transform (CWT), the system converts high-frequency vibration signals into periodic feature tensors, effectively reducing data volume while retaining key information, ensuring the real-time requirements of model inference. Furthermore, the memory management mechanism further optimizes data storage and access efficiency, minimizing I / O operations and improving overall inference speed.

[0133] During the model deployment phase (Phase 1: Ideal Main Process), the system first exports the trained PyTorch model to ONNX format using a standard model training and conversion process. Then, it uses TensorRT to convert the ONNX model into an FP16 format inference engine. This process effectively improves inference speed and ensures that the inference accuracy in FP16 mode meets business requirements through accuracy verification. If the accuracy meets the requirements, the model will be directly deployed and begin real-time inference.

[0134] If a decrease in accuracy occurs during FP16 inference, the system will enter Phase 2: Macro-level investigation and isolation. In this phase, the system uses methods such as segmented accountability mechanisms, model decoupling, and baseline verification to progressively analyze the accuracy changes at each step of the conversion from PyTorch to ONNX, and then to TensorRT. Through module-by-module verification and comparison, the system can accurately pinpoint the specific submodule where the accuracy collapse occurred.

[0135] Once the model accuracy issue is clearly identified, this invention provides Phase 3: a repair and rollback mechanism, offering two repair paths to address the accuracy loss. If the problem lies with a specific operator or submodule, the system first attempts to repair the accuracy issue through operator replacement. If operator replacement fails to fix the problem or is too costly, the system adopts a safe rollback strategy, rolling back the inference of that submodule to PyTorch (FP32) mode to ensure that inference accuracy is not affected. Simultaneously, through a performance compensation mechanism, the system uses PyTorch compilation optimization to improve inference performance after rollback, minimizing the speed loss caused by rollback.

[0136] Through this series of integrated mechanisms, this invention ensures the real-time performance and high accuracy of the model during high-speed data acquisition and inference, thereby enabling reliable and efficient intelligent fault diagnosis on edge computing platforms (such as Jetson). The overall system can flexibly address issues such as accuracy degradation and operator incompatibility, demonstrating strong adaptability and robustness in industrial applications.

[0137] Example 2

[0138] A real-time fault diagnosis system for edge computing platforms includes:

[0139] The data acquisition module is used to acquire sensor signals at a high-speed sampling frequency through the data acquisition card and transmit the acquired data to the shared buffer of the edge computing platform;

[0140] The signal preprocessing module is used to perform frequency domain or time-frequency domain transformation on the original time domain signal in the shared buffer to generate a frequency domain or time-frequency domain feature tensor obtained after signal processing. The data size of the feature tensor is smaller than that of the corresponding original time domain signal.

[0141] The model inference module is used to input the feature tensor into a deep learning model deployed on an edge computing platform for real-time fault identification.

[0142] The model deployment and rollback module includes:

[0143] Standard model deployment phase: During the model training phase, the PyTorch deep learning framework is used to train the model, and FP32 precision is used to optimize the model parameters. After training, the model is exported as a computation graph structure in ONNX format, and then an FP16 inference engine is built through TensorRT. The accuracy of the inference results of the TensorRT engine is verified.

[0144] Accuracy Anomaly Detection Phase: When the error between the TensorRT FP16 inference result and the PyTorch FP32 inference result exceeds a preset threshold, the problem investigation and repair process begins.

[0145] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A real-time fault diagnosis method for edge computing platforms, characterized in that: Includes the following steps: Sensor signals are acquired at a high-speed sampling frequency using a data acquisition card, and the acquired data is transmitted to the shared buffer of the edge computing platform. The original time-domain signal in the shared buffer is transformed into a frequency domain or a time-frequency domain to generate a frequency domain or time-frequency domain feature tensor after signal processing. The data size of the feature tensor is smaller than that of the corresponding original time-domain signal. The feature tensor is input into a deep learning model deployed on an edge computing platform for real-time fault identification; It also includes a model deployment and rollback mechanism, which includes: Standard model deployment phase: During the model training phase, the PyTorch deep learning framework is used to train the model, and FP32 precision is used to optimize the model parameters. After training, the model is exported as a computation graph structure in ONNX format, and then an FP16 inference engine is built through TensorRT. The accuracy of the inference results of the TensorRT engine is verified. Accuracy Anomaly Detection Phase: When the error between the TensorRT FP16 inference result and the PyTorch FP32 inference result exceeds a preset threshold, the problem investigation and repair process begins. The troubleshooting and repair process includes: Link investigation steps: Divide the model deployment process into the PyTorch to ONNX model conversion stage and the ONNX to TensorRT inference engine construction stage. Compare the inference output between PyTorch and ONNX, and ONNX and TensorRT respectively to pinpoint the conversion stage where accuracy loss occurs. Module-level localization steps: Decouple the neural network model into multiple functional sub-modules, execute ONNX export and TensorRT inference engine construction for each sub-module, compare the output of each module, and locate the problem sub-module; Operator-level diagnostic steps: Identify anomalous operators in problematic submodules using ONNX computation graph parsing tools and TensorRT engine log building tools; Operator replacement steps: Replace the original problematic operators by customizing the TensorRT Plugin, constructing equivalent operator combinations, or modifying the ONNX computation graph structure.

2. The real-time fault diagnosis method for edge computing platforms according to claim 1, characterized in that: Performing frequency domain or time-frequency domain transformation on the original time-domain signal in the shared buffer includes: Fast Fourier Transform or Continuous Wavelet Transform.

3. The real-time fault diagnosis method for edge computing platforms according to claim 1, characterized in that: The shared buffer is a circular queue or a double-buffered queue structure, and is implemented in any of the following ways: User-space shared memory based on mmap; Cross-driver shared buffer based on dma-buf; CPU / GPU shared buffer based on CUDA page-locked memory or unified memory.

4. The real-time fault diagnosis method for edge computing platforms according to claim 1, characterized in that: The edge computing platform is a Jetson series platform that integrates a GPU and a CPU.

5. The real-time fault diagnosis method for edge computing platforms according to claim 1, characterized in that: When an abnormal operator cannot be replaced or the replacement cost exceeds a preset threshold, a combined inference rollback mechanism is adopted: submodules that do not exhibit precision anomalies continue to be executed using the TensorRT FP16 engine, while submodules that exhibit precision anomalies roll back to the PyTorchFP32 inference mode.

6. The real-time fault diagnosis method for edge computing platforms according to claim 5, characterized in that: For submodules that fall back to PyTorch FP32 inference, further compilation and execution are performed using PyTorch compilation optimization tools.

7. The real-time fault diagnosis method for edge computing platforms according to claim 1, characterized in that: It also includes using the Polygraphy toolchain provided by NVIDIA to compare the output of ONNX Runtime inference results with TensorRT inference results layer by layer, and to identify the specific levels of numerical deviations within the model by performing error analysis on the output tensors of the two inference engines.

8. A real-time fault diagnosis system for edge computing platforms, characterized in that: include: The data acquisition module is used to acquire sensor signals at a high-speed sampling frequency through the data acquisition card and transmit the acquired data to the shared buffer of the edge computing platform; The signal preprocessing module is used to perform frequency domain or time-frequency domain transformation on the original time domain signal in the shared buffer to generate a frequency domain or time-frequency domain feature tensor obtained after signal processing. The data size of the feature tensor is smaller than that of the corresponding original time domain signal. The model inference module is used to input the feature tensor into a deep learning model deployed on an edge computing platform for real-time fault identification. The model deployment and rollback module includes: Standard model deployment phase: During the model training phase, the PyTorch deep learning framework is used to train the model, and FP32 precision is used to optimize the model parameters. After training, the model is exported as a computation graph structure in ONNX format, and then an FP16 inference engine is built using TensorRT. The accuracy of the TensorRT engine inference results is verified. Accuracy anomaly detection phase: When the error between the TensorRT FP16 inference result and the PyTorch FP32 inference result exceeds a preset threshold, the problem investigation and repair process is initiated. The troubleshooting and repair process includes: Link investigation steps: Divide the model deployment process into the PyTorch to ONNX model conversion stage and the ONNX to TensorRT inference engine construction stage. Compare the inference output between PyTorch and ONNX, and ONNX and TensorRT respectively to pinpoint the conversion stage where accuracy loss occurs. Module-level localization steps: Decouple the neural network model into multiple functional sub-modules, execute ONNX export and TensorRT inference engine construction for each sub-module, compare the output of each module, and locate the problem sub-module; Operator-level diagnostic steps: Identify anomalous operators in problematic submodules using ONNX computation graph parsing tools and TensorRT engine log building tools; Operator replacement steps: Replace the original problematic operators by customizing the TensorRT Plugin, constructing equivalent operator combinations, or modifying the ONNX computation graph structure.

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