A method and apparatus for processing operating system memory data under strong electromagnetic interference

Abstract

This application relates to the field of data processing technology, specifically providing a method and apparatus for processing operating system memory data under strong electromagnetic interference. It periodically polls the ripple voltage of the power management chip, the bus width of the memory controller bus, and the memory temperature of the DRAM. Within each polling cycle, the ripple voltage, bus width, and memory temperature are compared with a preset threshold set. If any parameter exceeds the threshold, a bit error repair operation and a temporary memory frequency reduction operation are triggered simultaneously. Through parameter polling and hierarchical error repair, proactive protection of memory data under strong electromagnetic interference is achieved. An adaptive polling cycle is adopted to collect power ripple, bus width, and DRAM temperature in real time, simultaneously initiating error repair and memory frequency reduction, blocking interference propagation, improving the success rate of atomic page replacement repair, enhancing system stability in strong electromagnetic environments, and effectively solving the problem of ensuring memory data integrity under extreme interference.

Description

Technical Field

[0001] This application relates to the field of data processing technology, specifically to a method and apparatus for processing operating system memory data under strong electromagnetic interference. Background Technology

[0002] In the presence of strong electromagnetic pulses, the core storage components of a computer system can be affected, leading to system crashes or data corruption. For example, Dynamic Random Access Memory (DRAM) uses capacitors to store charge to represent binary "0" and "1". Strong electromagnetic pulses can directly interfere with the charge retention capacity of capacitors, causing abnormal charge loss or accumulation and triggering random bit flips. Static Random Access Memory (SRAM) relies on bistable flip-flops to store data in a stable state. Strong electromagnetic pulses can disrupt the equilibrium state of the flip-flops, causing irreversible changes to the stored bit values.

[0003] Traditional ECC (Error-Correcting Code) memory verification has the ability to automatically detect and correct memory data errors. Its error correction mechanism involves ECC memory generating and storing an additional set of parity bits when storing data, typically adding 8 parity bits for every 64 bits of data. Then, various complex algorithms are used to establish the association between data and parity bits, including Hamming code, BCH code, etc. When data is read, the memory controller recalculates the parity value and compares it with the stored parity bits. If it is a single-bit error, the ECC memory algorithm can automatically locate the erroneous bit and flip it to correct it. The whole process is completed at the hardware level, and the system is unaware of it. If it is a multi-bit error, the ECC memory algorithm can only detect the existence of the error, but cannot correct it. At this time, it will trigger system warnings, such as hardware indicator lights and server log records.

[0004] The limitations of existing ECC memory verification are that passive verification is lagging. Traditional ECC memory verification only passively detects single-bit errors after an error occurs, and cannot proactively trigger protection against high-frequency, sudden strong interference such as power supply ripple. This results in a high rate of missed detection of multi-bit errors and untimely data recovery. Moreover, the ECC memory algorithm is relatively complex, and the repair execution consumes a lot of CPU resources. Especially when the system is in a strong electromagnetic interference environment, the system performance is limited. When combined with the ECC memory verification algorithm, it is easy to conflict with the system's computing resources and cannot meet the real-time business requirements.

[0005] Therefore, the existing ECC memory error detection and correction mechanism has limitations in its single-bit error correction capability when facing extreme scenarios such as strong electromagnetic interference, and cannot yet meet the data protection barrier requirements of high-reliability systems. It urgently needs further improvement and perfection. Summary of the Invention

[0006] Based on this, in order to solve the problems of high multi-bit error detection rate and untimely data recovery mentioned in the prior art, this application proposes a method and apparatus for processing operating system memory data under strong electromagnetic interference.

[0007] In a first aspect, this application discloses a method for processing operating system memory data under strong electromagnetic interference, comprising the following steps: Periodically poll to obtain the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM; In each polling cycle, the ripple voltage, bus eye width, and memory temperature are compared with a preset set of thresholds. If any parameter exceeds the threshold, a bit error repair operation and a temporary memory frequency reduction operation are triggered simultaneously. The steps involved in bit error correction include: Perform full-page CRC-64 redundancy check on the currently active memory pages; If the first full-page CRC-64 redundancy check fails to match, the hardware single-bit error automatic flip-to-repair is triggered, and a second full-page CRC-64 redundancy check is performed immediately after the repair is completed. If the secondary full-page CRC-64 redundancy check does not match, multi-bit error repair is triggered, and CRC-64 check is performed on the backup page of the corresponding active memory page of the currently running process in the DRAM hardware reserve area. If the backup page data is valid, an atomic page replacement is triggered, which atomically writes the backup page data to a new free memory page, updates the page table mapping, and marks the active memory page of the currently running process as unavailable. If the backup page data is invalid, a memory snapshot process is triggered to write the active memory pages of the currently running process to the disk temporary storage area and mark them as read-only.

[0008] Furthermore, the periodic polling step includes: The initial polling period is set to 50ms; During each polling cycle, environmental change parameters are calculated synchronously: the instantaneous rate of change of ripple voltage, the fluctuation amplitude of bus eye width, and the rate of rise of memory temperature. The new polling cycle is calculated based on the environmental change parameters: New polling cycle = Initial polling cycle × (1 - a × Instantaneous change rate of ripple voltage - b × Fluctuation amplitude of bus eye width - c × Rise rate of memory temperature), where a is the weight of ripple change rate, b is the weight of eye width fluctuation, c is the weight of temperature rise, and a, b, and c are the normalized values ​​of the corresponding environmental change parameters exceeding the threshold. When the corresponding environmental change parameters do not exceed the threshold, the weight is 0. The polling period can be adjusted within the range of 1ms to 100ms, and the adjustment of the polling period is performed by the hardware timer of the memory controller.

[0009] Furthermore, the steps for obtaining the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM include: The PMIC generates a read command through the I2C communication protocol, specifies the address of the ripple voltage sampling register, and converts the analog ripple voltage signal into a digital signal through the internal 12-bit ADC. The signal is then returned to the hardware monitoring module via the I2C bus. After eliminating sampling noise through moving average filtering, the ripple voltage is output. The ripple voltage is the AC fluctuation component in the DC output voltage of the power management chip, measured in mV, and reflects the stability of the power output. The memory-mapped I / O instruction accesses the built-in bus eye width measurement register of the memory. The memory uses the bus eye width measurement circuit to collect the rising and / or falling edge jitter of the data signal in real time, outputs an 8-bit digital value and converts it into the bus eye width. The conversion steps are: after the digital value is multiplied by 2 / 255, it is normalized and compared with the standard eye width of the corresponding memory specification to obtain the bus eye width. Among them, the bus eye width is the effective reception window of the data transmission signal between the memory and DRAM in the time and voltage dimensions. The time is the unit interval UI, 1UI=1 / memory data rate. The smaller the bus eye width, the worse the signal integrity. The read command is generated through the SMBus communication protocol, specifying the device address of the DRAM temperature sensor and the temperature data register address. The thermistor built into the DRAM converts the junction temperature into a 16-bit digital signal, which is returned through the SMBus bus. The memory temperature is the junction temperature inside the DRAM chip, measured in °C. The higher the temperature, the faster the charge leakage rate of the DRAM memory cell and the higher the bit error rate. The acquisition and processing of ripple voltage, bus width, and memory temperature are performed in parallel by the hardware monitoring module.

[0010] Furthermore, the threshold set includes a ripple voltage trigger threshold, a bus eye width trigger threshold, and a memory temperature trigger threshold; the threshold set is stored in the BIOS's SPI Flash non-volatile memory and can be customized through the hardware configuration interface of the operating system kernel. After modification, it is automatically synchronized to the dedicated register of the memory controller.

[0011] Furthermore, the step of comparing the ripple voltage, bus eye width, and memory temperature with a preset threshold set includes: When the sampled value of the ripple voltage is greater than or equal to the ripple voltage trigger threshold, the judgment parameter exceeds the threshold. When the sampled value of the bus eye width is less than or equal to the bus eye width trigger threshold, the judgment parameter exceeds the threshold. If the collected memory temperature value is greater than or equal to the memory temperature trigger threshold, the parameter is determined to exceed the threshold. The determination result is notified to the processor in real time via an interrupt request.

[0012] Furthermore, the steps for automatic flip-flop repair of hardware single-bit errors include: The memory controller locates the physical address of the erroneous bit using ECC error correction code. The physical address includes the DRAM chip number, row address, column address, and bit position. The value of the erroneous bit is atomically flipped using a hardware flip circuit; After the repair is completed, a second full-page CRC-64 redundancy check is triggered to verify the repair result; If the second full-page CRC-64 redundancy check matches, a single-bit error repair log is recorded, and the normal operation of the user process is restored. If the second full-page CRC-64 redundancy check does not match, the next step is triggered.

[0013] Furthermore, the step of performing CRC-64 verification on the backup page of the corresponding active memory page of the currently running process in the DRAM hardware reserve area includes: When the secondary full-page CRC-64 redundancy check fails to match, the memory controller detects that the number of error bits is ≥2 through the ECC error correction code and judges it as a multi-bit error. The backup page address in the corresponding DRAM hardware reserve area is located based on the active memory page of the currently running process. The hardware reserve area is a separately allocated area in physical memory, which is protected by ECC and is used only to store backup data of active memory pages. The CRC-64 redundancy check of the backup page uses the same standard as the original active memory page; If the CRC-64 redundancy check of the backup page matches, the backup page data is considered valid; if the CRC-64 redundancy check of the backup page does not match, the backup page data is considered invalid.

[0014] Furthermore, the steps that trigger atomic page replacement include: The memory management module allocates one new free memory page from the free memory page list; The backup page data is atomically written to a new free memory page via a DMA channel. The writing process uses a hardware locking mechanism to ensure the atomicity of data transfer. After the write operation is complete, the page table mapping of the currently running process is immediately updated to map the virtual address of the original active memory page to the physical address of the new memory page. Page table updates use atomic operations and prohibit other processes from accessing them during the update process; After the update is complete, the original active memory pages are marked as unavailable and added to the memory reclamation chain to await subsequent garbage collection; After the update is complete, a signal is sent to the currently running process to notify it to resume normal operation; Once the currently running process resumes, all accesses to the original virtual address will be automatically mapped to new free memory pages without requiring modification of the process code.

[0015] Furthermore, the steps of triggering a memory snapshot process to write the active memory pages of the currently running process to a temporary disk storage area and mark them as read-only include: The memory management module triggers a memory snapshot process, freezing all threads of the currently running process. Allocate a temporary memory buffer to store compressed data of active memory pages; The LZ4 compression algorithm is used to compress active memory page data, with a compression ratio of ≥2:1; The compressed data is written to the temporary disk storage area via the DMA channel; After writing is complete, the CRC-64 checksum of the snapshot data is calculated and stored for subsequent integrity verification; Mark the original active memory page as read-only, and prohibit processes from writing to it; Unfreeze the threads of the currently running process and notify them to resume running; Record the time, size, and disk path of the memory snapshot for subsequent data recovery; Once the system returns to normal, the memory page data can be restored using disk snapshot files. After the recovery is complete, the original memory pages are marked as writable, and the normal operation of the recovery process is restored.

[0016] Furthermore, the steps to trigger a temporary memory frequency downclocking operation include: Read the current memory frequency register of the power management chip and parse the current operating frequency of the DDR memory; Reduce the current operating frequency of the DDR memory while ensuring it does not fall below the minimum operating frequency of the memory. Construct SMBus protocol control instructions. The instruction frame contains a 16-bit binary code of the frequency reduction target value and a synchronous memory voltage adjustment coefficient. Write the SMBus protocol control command into the frequency control register of the power management chip and wait for the device's ACK response; If the write operation is successful, the memory frequency node in the system clock tree is updated, and the memory frequency statistics are updated synchronously. If the write operation fails, the kernel-mode error log is triggered, and the current frequency is maintained.

[0017] Secondly, this application provides an operating system memory data processing apparatus under strong electromagnetic interference, used for applying the operating system memory data processing method under strong electromagnetic interference as described in any one of the first aspects, the apparatus comprising: The parameter acquisition module is used to periodically poll and acquire the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM. The parameter comparison module is used to compare the ripple voltage, bus eye width and memory temperature with the preset threshold set in each polling cycle. If any parameter exceeds the threshold, a bit error repair operation and a temporary memory frequency reduction operation are triggered simultaneously. The error repair module, which performs bit error repair operations, includes the following steps: Perform full-page CRC-64 redundancy check on the active memory pages of the currently running process; If the first full-page CRC-64 redundancy check fails to match, the hardware single-bit error automatic flip-to-repair is triggered, and a second full-page CRC-64 redundancy check is performed immediately after the repair is completed. If the secondary full-page CRC-64 redundancy check does not match, multi-bit error repair is triggered, and CRC-64 check is performed on the backup page of the corresponding active memory page of the currently running process in the DRAM hardware reserve area. If the backup page data is valid, an atomic page replacement is triggered, which atomically writes the backup page data to a new free memory page, updates the page table mapping, and marks the active memory page of the currently running process as unavailable. If the backup page data is invalid, a memory snapshot process is triggered to write the active memory pages of the currently running process to the disk temporary storage area and mark them as read-only.

[0018] The operating system memory data processing method and apparatus under strong electromagnetic interference provided in this application have the following advantages: In this embodiment, the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM are obtained by periodic polling. In each polling cycle, the ripple voltage, bus eye width, and memory temperature are compared with a preset threshold set. If any parameter exceeds the threshold, a bit error repair operation and a temporary memory frequency reduction operation are triggered simultaneously. This solves the problems of limitations of single-bit error correction and passive detection lag in the prior art. Through parameter polling and hierarchical error repair, active protection of memory data under strong electromagnetic interference is achieved. An adaptive polling cycle is adopted to collect power ripple, bus eye width, and DRAM temperature in real time, triggering threshold response at the microsecond level, and simultaneously starting error repair and memory frequency reduction to block the spread of interference. Single-bit errors are repaired through hardware atomic flipping; multi-bit errors are repaired through DRAM hardware reserved area backup pages, improving the success rate of atomic page replacement repair. In addition, when the backup page fails, a memory snapshot is triggered as a fallback to avoid system crash. System stability is improved in strong electromagnetic environments, effectively solving the problem of ensuring memory data integrity under extreme interference. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is one of the flowcharts illustrating an operating system memory data processing method under strong electromagnetic interference in one embodiment; Figure 2 This is a second flowchart illustrating an operating system memory data processing method under strong electromagnetic interference in one embodiment. Figure 3 This is the third flowchart illustrating an operating system memory data processing method under strong electromagnetic interference in one embodiment; Figure 4 This is the fourth flowchart illustrating an operating system memory data processing method under strong electromagnetic interference in one embodiment. Figure 5 This is the fifth flowchart illustrating an operating system memory data processing method under strong electromagnetic interference in one embodiment. Figure 6 This is a flowchart of a method for processing operating system memory data under strong electromagnetic interference in one embodiment; Figure 7 This is the seventh flowchart illustrating an operating system memory data processing method under strong electromagnetic interference in one embodiment. Figure 8 This is a structural block diagram of an operating system memory data processing device under strong electromagnetic interference in one embodiment. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] Example 1

[0023] In existing technologies, the limitation of ECC memory verification is that passive verification has a lag. Traditional ECC memory verification only passively detects single-bit errors after an error occurs, and cannot proactively trigger protection against high-frequency, sudden strong interference such as power supply ripple. This results in a high rate of missed detection of multi-bit errors and untimely data recovery. Moreover, the ECC memory algorithm is relatively complex, and the repair execution will occupy a lot of CPU resources. Especially when the system is in a strong electromagnetic interference environment, the system performance is limited. The addition of the ECC memory verification algorithm can easily conflict with the system's computing resources and cannot meet the real-time business requirements.

[0024] See Figure 1 As shown, this embodiment provides a method for processing operating system memory data under strong electromagnetic interference, including the following steps: S101: Periodically poll to obtain the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM. In step S101, the power management chip register is read using the I2C protocol, converted into a digital signal by the ADC, and noise is eliminated by moving average filtering; the built-in register of the memory controller is accessed through memory-mapped I / O to collect the rising edge jitter and falling edge jitter of the data signal in real time and convert it into the eye width value per unit interval; the data of the built-in thermistor of the DRAM is read through the SMBus protocol and converted into the chip junction temperature ℃.

[0025] S102. In each polling cycle, the ripple voltage, bus eye width and memory temperature are compared with the preset threshold set. If any parameter exceeds the threshold, the bit error repair operation and the memory frequency temporary frequency reduction operation are triggered at the same time. In step S102, the threshold set includes warning thresholds and trigger thresholds, stored in the BIOS non-volatile memory, and supports custom modification. Parameter comparison is performed in parallel by the memory controller's built-in hardware logic unit, and abnormal results are notified to the kernel via the highest priority interrupt. When a parameter exceeds the threshold, error repair and temporary memory frequency reduction are triggered simultaneously. By using tiered thresholds to achieve gradient responses for warnings and triggers, the false trigger rate and missed trigger rate are reduced. Memory frequency reduction reduces bus signal jitter, and combined with error repair, the multi-bit error rate is reduced.

[0026] S103, The steps of the bit error repair operation include: In step S103, bit errors are corrected.

[0027] S1031. Perform full-page CRC-64 redundancy check on the currently active memory pages; In step S1031, the CRC-64 / ISO standard is adopted, and the memory controller’s built-in hardware CRC unit performs full-page verification. When a memory page is allocated for the first time, the hardware automatically calculates the CRC-64 checksum and stores it in the page table extension field. During verification, it is compared with the real-time calculated value. The detection range covers all data in the memory page, avoiding the problem of missed detection in partial verification.

[0028] S1032. If the first full-page CRC-64 redundancy check fails to match, the hardware single-bit error automatic flip-over repair is triggered. After the repair is completed, the second full-page CRC-64 redundancy check is performed immediately. In step S1032, the memory controller locates the physical address of the error bit through the ECC error correction code, triggers the built-in flip circuit through hardware instructions, and atomically flips the error bit value, such as 0→1 or 1→0. The repair process is uninterrupted. After the repair is completed, CRC-64 redundancy check is performed to verify the repair result.

[0029] S1033. If the secondary full-page CRC-64 redundancy check does not match, multi-bit error repair is triggered, and CRC-64 check is performed on the backup page of the corresponding active memory page of the currently running process in the DRAM hardware reserved area. In step S1033, if the secondary CRC check fails, and the memory controller detects an error bit count ≥ 2 via ECC, it is determined to be a multi-bit error. The DRAM hardware reserved area is a separately allocated ECC protection area in the physical memory. A backup is automatically generated when an active memory page is allocated for the first time and synchronized in real time through a hardware mirroring circuit. The backup page is checked using the same CRC-64 standard as the original page to ensure that the backup data is not interfered with or damaged.

[0030] S1034. If the backup page data is valid, then an atomic page replacement is triggered, the backup page data is atomically written to a new free memory page, the page table mapping relationship is updated, and the active memory page of the currently running process is marked as unavailable. In step S1034, the backup page data is atomically written to a new free memory page through the DMA channel. The transfer process uses a hardware lock mechanism to ensure uninterrupted transmission. The memory controller automatically updates the page table mapping relationship through instructions, pointing the process virtual address to the new memory page. The original erroneous page is marked as unavailable and added to the memory reclamation list to prevent subsequent access and avoid reuse of erroneous data.

[0031] S1035. If the backup page data is invalid, trigger the memory snapshot process to write the active memory pages of the currently running process to the disk temporary storage area and mark them as read-only.

[0032] In step S1035, compressed data is written to the disk temporary storage area via the DMA channel to avoid CPU intervention; read-only marking and process recovery: the original error page is marked as read-only, the process thread is unfrozen, and the error context is preserved. System crashes are prevented when the backup page is invalid, improving system availability.

[0033] It should be noted that in this embodiment, the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM are obtained through periodic polling. Within each polling cycle, the ripple voltage, bus eye width, and memory temperature are compared with a preset threshold set. If any parameter exceeds the threshold, a bit error repair operation and a temporary memory frequency reduction operation are triggered simultaneously. This addresses the limitations of single-bit error correction in ECC memory and the lag in passive detection in existing technologies. Through parameter polling and hierarchical error repair, proactive protection of memory data under strong electromagnetic interference is achieved. An adaptive polling cycle is adopted to collect power ripple, bus eye width, and DRAM temperature in real time, triggering threshold responses at the microsecond level and simultaneously initiating error repair and memory frequency reduction to block interference propagation. Single-bit errors are repaired through hardware atomic flips; multi-bit errors are repaired through DRAM hardware reserved area backup pages, improving the success rate of atomic page replacement repair. Furthermore, when backup pages fail, a memory snapshot is triggered as a fallback to prevent system crashes. This improves system stability under strong electromagnetic environments and effectively solves the problem of ensuring memory data integrity under extreme interference.

[0034] Example 2

[0035] This embodiment provides a further technical solution based on Embodiment 1.

[0036] See Figure 2 As shown, in this embodiment, the periodic polling step includes: S111, the initial polling period is set to 50ms; In step S111, the initial polling period is set to 50ms to balance the real-time performance of detection with the power consumption of the system.

[0037] S112. In each polling cycle, synchronously calculate environmental change parameters: instantaneous change rate of ripple voltage, fluctuation amplitude of bus eye width, and rise rate of memory temperature. In step S112, the degree of interference is predicted by the changing trend of parameters. Among them, the instantaneous change rate of ripple voltage reflects the deterioration speed of power supply stability, the bus eye width fluctuation amplitude reflects the degree of fluctuation of signal transmission quality, and the memory temperature rise rate reflects the thermal aging and interference accumulation effect of DRAM memory cells.

[0038] S113. Calculate the new polling cycle based on environmental change parameters: New polling cycle = Initial polling cycle × (1 - a × instantaneous rate of change of ripple voltage - b × fluctuation amplitude of bus eye width - c × rate of increase of memory temperature), where a is the weight of ripple change rate, b is the weight of eye width fluctuation, c is the weight of temperature increase, and a, b, and c are the normalized values ​​of the corresponding environmental change parameters exceeding the threshold. When the corresponding environmental change parameters do not exceed the threshold, the weight is 0. In step S113, for example, ripple voltage has the greatest impact on power supply stability, with the highest weight 'a' (e.g., 0.4); bus eye width directly affects data transmission, with the next highest weight 'b' (e.g., 0.3); memory temperature is a slow variable, with the lowest weight 'c' (e.g., 0.3); the weights are normalized values ​​(0-1) for parameters exceeding the threshold, and are 0 when the threshold is not exceeded, ensuring that the cycle is shortened only when interference increases. This achieves smooth adaptive adjustment of the polling cycle, linearly shortening the cycle when interference increases to improve detection sensitivity, and linearly extending the cycle when interference decreases to reduce system power consumption.

[0039] S114. The polling period can be adjusted within the range of 1ms to 100ms. The adjustment of the polling period is performed by the hardware timer of the memory controller.

[0040] It should be noted that 1ms is the minimum response limit of the hardware timer, and 100ms is the optimal power consumption value in low interference scenarios, to avoid resource exhaustion due to too short a period or missed detection due to too long a period.

[0041] See Figure 3 As shown, in this embodiment, the steps of obtaining the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM include: S121. A read instruction is generated through the I2C communication protocol, specifying the address of the ripple voltage sampling register. The 12-bit ADC inside the PMIC converts the analog ripple voltage signal into a digital signal and returns it to the hardware monitoring module through the I2C bus. After eliminating sampling noise through moving average filtering, the ripple voltage is output. The ripple voltage is the AC fluctuation component in the DC output voltage of the power management chip, measured in mV, and reflects the stability of the power output. In step S121, the ripple voltage sampling register of the power management chip is read via the I2C communication protocol. The analog ripple signal is converted into a digital signal using the PMIC's internal 12-bit ADC, and then high-frequency noise is eliminated through moving average filtering. Finally, the ripple voltage value reflecting the power supply stability is output. Ripple voltage is the AC fluctuation component in DC power supply, which directly affects the charge retention capability of DRAM capacitors. This method achieves high-precision, low-noise ripple voltage acquisition, reducing the multi-bit error rate caused by power supply problems.

[0042] S122. Access the built-in bus eye width measurement register of the memory through the memory-mapped I / O instruction. The memory collects the rising edge and / or falling edge jitter of the data signal in real time through the bus eye width measurement circuit, outputs an 8-bit digital value and converts it into the bus eye width. The conversion steps are: after the digital value is multiplied by 2 / 255, it is normalized and compared with the standard eye width of the corresponding memory specification to obtain the bus eye width. Among them, the bus eye width is the effective reception window of the data transmission signal between the memory and DRAM in the time and voltage dimensions. The time is the unit interval UI, 1UI=1 / memory data rate. The smaller the bus eye width, the worse the signal integrity. In step S122, the bus eye width measurement register built into the memory controller is directly accessed via memory-mapped I / O. Hardware circuitry is used to collect the rising / falling edge jitter of the data signal in real time, outputting an 8-bit digital value. This value is then normalized to obtain the bus eye width in unit intervals. A smaller eye width results in a narrower effective signal reception window and a higher data transmission error rate. Real-time, accurate measurement of the bus eye width improves the sensitivity of eye width change detection, triggering protection before signal integrity deteriorates to a critical value, thus reducing the data transmission error rate.

[0043] S123. Generate a read instruction through the SMBus communication protocol, specifying the device address of the DRAM temperature sensor and the temperature data register address. The thermistor built into the DRAM converts the junction temperature into a 16-bit digital signal and returns it through the SMBus bus. The memory temperature is the junction temperature inside the DRAM chip, measured in °C. The higher the temperature, the faster the charge leakage rate of the DRAM memory cell and the higher the bit error rate. The acquisition and processing of S124, ripple voltage, bus eye width, and memory temperature are performed in parallel by the hardware monitoring module.

[0044] It should be noted that the data from the DRAM's built-in thermistor is read via the SMBus communication protocol, converting the chip junction temperature into a 16-bit digital signal, which is then converted into the actual junction temperature (°C) using a formula. This enables accurate real-time acquisition of the DRAM core junction temperature, triggering frequency reduction protection before the temperature reaches a critical value, thus reducing the incidence of thermally induced bit errors.

[0045] In this embodiment, the threshold set includes a ripple voltage trigger threshold, a bus eye width trigger threshold, and a memory temperature trigger threshold. The threshold set is stored in the BIOS's SPI Flash non-volatile memory and can be customized through the hardware configuration interface of the operating system kernel. After modification, it is automatically synchronized to the dedicated register of the memory controller.

[0046] It should be noted that custom thresholds are supported for different application scenarios. For example, in industrial environments, the ripple threshold can be increased to 200mV to adapt to complex power supply environments. The threshold is stored in a dedicated register of the memory controller and compared in real time by the hardware logic to ensure that protection actions are triggered immediately under strong electromagnetic interference. The non-volatile storage of SPI Flash ensures that the threshold is not lost when power is off and is automatically loaded upon startup without the need for repeated configuration. The kernel interface supports online modification without restarting the system and can be configured in batches through automated scripts, greatly improving operation and maintenance efficiency.

[0047] In this embodiment, the step of comparing the ripple voltage, bus eye width, and memory temperature with a preset threshold set includes: When the sampled value of the ripple voltage is greater than or equal to the ripple voltage trigger threshold, the judgment parameter exceeds the threshold. When the sampled value of the bus eye width is less than or equal to the bus eye width trigger threshold, the judgment parameter exceeds the threshold. If the collected memory temperature value is greater than or equal to the memory temperature trigger threshold, the parameter is determined to exceed the threshold. The determination result is notified to the processor in real time via an interrupt request.

[0048] It should be noted that higher ripple voltage leads to poorer power supply output stability and lower charge retention capability of DRAM capacitors; smaller bus eye width results in a narrower effective reception window for data transmission, poorer signal integrity, and a higher bit error rate; higher temperature leads to faster charge leakage rate in DRAM memory cells, causing the bit error rate to increase exponentially. Any abnormality in any of these three parameters immediately triggers a response, enabling monitoring of power supply stability, signal integrity, and thermal reliability, thereby improving the system's fault-free operation time under strong electromagnetic environments.

[0049] See Figure 4 As shown, in this embodiment, the steps for automatic flip-flop repair of hardware single-bit errors include: S10321. The memory controller locates the physical address of the erroneous bit using ECC error correction code. The physical address includes the DRAM chip number, row address, column address, and bit position. S10322, The value of the error bit is atomically flipped using a hardware flip circuit; S10323. After the repair is completed, trigger a second full-page CRC-64 redundancy check to verify the repair result; S10324. If the secondary full-page CRC-64 redundancy check matches, record the single-bit error repair log and restore the normal operation of the user process. If the secondary full-page CRC-64 redundancy check does not match, trigger the next step.

[0050] It should be noted that the memory controller generates and stores an ECC checksum during data writing. During reading, it uses an XOR operation between the checksum and the data to pinpoint the precise physical address of the erroneous bit, including the DRAM chip number, row address, column address, and bit position. This positioning is performed by the memory controller's hardware logic without CPU intervention, achieving bit-level accuracy for a single memory cell. Then, utilizing the memory controller's built-in hardware bit-flipping circuit, a bit-flipping instruction is sent directly to the target DRAM memory cell, achieving atomic operation on the erroneous bit. This operation bypasses the conventional read / write process between the CPU and the memory bus, modifying only a single bit instead of rewriting the entire memory row or page. The CRC-64-generated checksum has extremely strong error detection capabilities, detecting single-bit, multi-bit, and burst errors, ensuring that the repaired data is completely consistent with the original written data. Verification is performed in parallel by the hardware monitoring module, without consuming CPU resources. During verification matching, the memory controller's error log register records information such as the physical address of the single-bit error, repair time, and DRAM chip number. The log can be exported through the operating system kernel interface for fault analysis; simultaneously, an interrupt signal is sent to the CPU to notify the business process to resume normal operation. If the verification fails, it is determined to be a multi-bit error or a DRAM hardware failure, triggering the next level of protection process.

[0051] See Figure 5 As shown, in this embodiment, the step of performing CRC-64 verification on the backup page of the corresponding active memory page of the currently running process in the DRAM hardware reserve area includes: S10331. When the secondary full-page CRC-64 redundancy check does not match, the memory controller detects that the number of error bits is ≥2 through the ECC error correction code and judges it as a multi-bit error. In step S10331, when the secondary full-page CRC-64 checksum does not match, single-bit error repair fails. At this time, the memory controller calculates the Syndrome of the ECC checksum to detect the number of error bits. If the number of error bits is ≥2, the ECC can only detect errors but cannot correct them, and it is determined to be a multi-bit error, triggering the advanced fault handling process. This detection is completed by the memory controller hardware logic without CPU intervention.

[0052] S10332. Locate the backup page address in the corresponding DRAM hardware reserved area based on the active memory page of the currently running process. The hardware reserved area is a separately allocated area in physical memory, protected by ECC and used only to store backup data of active memory pages. In step S10332, a dedicated area is allocated in the physical memory and isolated from the business memory area through the ECC full protection mechanism. It is used only to store real-time backup data of active memory pages to avoid interference from business data writes. The memory controller maintains a hardware mapping table between the original active pages and backup pages, recording the correspondence between the physical addresses of the original pages and the physical addresses of the backup pages. When a multi-bit error is detected, the backup page is quickly located directly through the mapping table without the need for software traversal.

[0053] S10333, The CRC-64 redundancy check of the backup page adopts the same standard as the original active memory page; In step S10333, the backup page verification result is comparable to the original page verification result.

[0054] S10334. If the CRC-64 redundancy check of the backup page matches, the backup page data is determined to be valid; if the CRC-64 redundancy check of the backup page does not match, the backup page data is determined to be invalid.

[0055] In step S10334, if the checksum of the backup page matches the checksum stored in the original page exactly, it indicates that the backup page has not been damaged by electromagnetic interference and the data is valid; if they do not match, it indicates that the backup page has also malfunctioned due to strong electromagnetic interference, the data is invalid, and the offline isolation of the memory page or the system warning process is triggered. The determination result is directly output to the memory controller by the hardware logic to drive subsequent processing actions.

[0056] It should be noted that this embodiment achieves accurate and rapid determination of multi-bit errors, avoiding confusion between single-bit repair processes and multi-bit error handling processes; hardware-level detection ensures microsecond-level response, buying time for subsequent backup page verification and reducing the risk of error propagation.

[0057] See Figure 6 As shown, in this embodiment, the step of triggering atomic page replacement includes: S10341, The memory management module allocates one new free memory page from the free memory page list; S10342. The backup page data is atomically written to a new free memory page through the DMA channel. The writing process uses a hardware lock mechanism to ensure the atomicity of data transmission. S10343. After writing is complete, immediately update the page table mapping relationship of the currently running process, mapping the virtual address of the original active memory page to the physical address of the new memory page; S10344: Page table updates use atomic operations and prohibit other processes from accessing them during the update process; S10345. After the update is complete, the original active memory pages are marked as unavailable and added to the memory reclamation chain to await subsequent garbage collection. S10346. After the update is completed, a signal is sent to the currently running process to notify it to resume normal operation; S10347. After the currently running process resumes, all accesses to the original virtual address are automatically mapped to new free memory pages without modifying the process code.

[0058] It should be noted that in this embodiment, an atomic page replacement scheme is used to recover multi-bit errors under strong electromagnetic interference scenarios, ensuring high reliability. Backup page data is atomically written via a DMA channel, coupled with a hardware locking mechanism to ensure uninterrupted and uninterrupted transmission, avoiding secondary errors that may be introduced by traditional software copying, thus improving data transmission reliability. Page table updates employ atomic operations and temporarily prohibit access by other processes, eliminating the risk of page table inconsistency caused by multi-process concurrency and reducing mapping switching latency. Previously active pages are marked as unavailable and added to the recycling list, isolating faulty memory regions at the hardware level and cutting off the propagation path of multi-bit errors.

[0059] See Figure 7 As shown, in this embodiment, the step of triggering a memory snapshot process to write the active memory pages of the currently running process to the disk temporary storage area and mark them as read-only includes: S10351, The memory management module triggers a memory snapshot process, freezing all threads of the currently running process; S10352. Allocate a temporary memory buffer to store compressed data of active memory pages; S10353. Use the LZ4 compression algorithm to compress active memory page data, with a compression ratio ≥ 2:1; S10354. Write the compressed data to the disk temporary storage area through the DMA channel; S10355. After writing is complete, calculate and store the CRC-64 checksum of the snapshot data for subsequent integrity verification. S10356. Mark the original active memory page as read-only and prohibit the process from writing to it; S10357. Unfreeze the threads of the currently running process and notify them to resume running; S10358. Record the time, size, and disk path of the memory snapshot for subsequent data recovery. S10359. After the system returns to normal, restore the memory page data using the disk snapshot file; S103510. After the recovery is complete, the original memory pages are marked as writable, and the recovery process runs normally.

[0060] It should be noted that in this embodiment, a memory snapshot process is used to protect memory data in scenarios with strong electromagnetic interference, achieving highly reliable data retention and low-interruption operation of services. By freezing all threads of the current process, data write conflicts during the snapshot process are avoided, ensuring that the snapshot data is completely consistent with the real-time memory state. The LZ4 compression algorithm achieves a high compression ratio of ≥2:1, and combined with DMA channels for direct writing to disk, both halving the disk space occupied and avoiding CPU involvement in data transfer. CRC-64 checksums provide integrity verification for subsequent recovery, preventing snapshot data from being corrupted due to disk fluctuations or interference. The original active pages are marked as read-only, isolating the faulty memory area at the permission level and preventing secondary data corruption caused by accidental process writes. After the threads are unfrozen, services recover quickly, with no noticeable impact on the user. The overall solution balances the reliability of data protection with the continuity of business operations. In this embodiment, the steps to trigger a temporary memory frequency downclocking operation include: Read the current memory frequency register of the power management chip and parse the current operating frequency of the DDR memory; Reduce the current operating frequency of the DDR memory while ensuring it does not fall below the minimum operating frequency of the memory. Construct SMBus protocol control instructions. The instruction frame contains a 16-bit binary code of the frequency reduction target value and a synchronous memory voltage adjustment coefficient. Write the SMBus protocol control command into the frequency control register of the power management chip and wait for the device's ACK response; If the write operation is successful, the memory frequency node in the system clock tree is updated, and the memory frequency statistics are updated synchronously. If the write operation fails, the kernel-mode error log is triggered, and the current frequency is maintained.

[0061] It should be noted that the frequency status register of the power management chip is accessed via the system SMBus bus to parse the current memory operating frequency. Based on the JEDEC specifications of the memory chips, the frequency is reduced by one standard level from the current frequency to ensure that the result is not lower than the minimum operating frequency of the memory, thus avoiding memory initialization failure. After the instruction is written, it waits for an ACK response from the power management chip, employing a hardware handshake mechanism to ensure successful instruction transmission and avoid instruction loss due to electromagnetic interference. The memory clock division ratio in the system clock tree is updated to ensure synchronization of the CPU, memory, and peripheral clocks. Simultaneously, the kernel memory frequency statistics node is updated for system monitoring and upper-layer application reading. Voltage and frequency are adjusted synchronously to ensure that the memory operates at optimal timings after frequency reduction, without additional hardware loss. If frequency reduction fails, the kernel error log is triggered, recording information such as time and register values ​​for subsequent fault analysis and localization. Updating the clock tree ensures CPU and memory clock matching, minimizing performance loss after frequency reduction and balancing stability and performance requirements.

[0062] Example 3

[0063] See Figure 8 As shown, this embodiment provides an operating system memory data processing device under strong electromagnetic interference, used to apply the operating system memory data processing method under strong electromagnetic interference described in any of the above embodiments. The device includes: The parameter acquisition module 100 is used to periodically poll and acquire the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM. The parameter comparison module 200 is used to compare the ripple voltage, bus eye width and memory temperature with a preset threshold set in each polling cycle. If any parameter exceeds the threshold, a bit error repair operation and a temporary memory frequency reduction operation are triggered simultaneously. The error repair module 300 performs bit error repair operations using the following steps: Perform full-page CRC-64 redundancy check on the active memory pages of the currently running process; If the first full-page CRC-64 redundancy check fails to match, the hardware single-bit error automatic flip-to-repair is triggered, and a second full-page CRC-64 redundancy check is performed immediately after the repair is completed. If the secondary full-page CRC-64 redundancy check does not match, multi-bit error repair is triggered, and CRC-64 check is performed on the backup page of the corresponding active memory page of the currently running process in the DRAM hardware reserve area. If the backup page data is valid, an atomic page replacement is triggered, which atomically writes the backup page data to a new free memory page, updates the page table mapping, and marks the active memory page of the currently running process as unavailable. If the backup page data is invalid, a memory snapshot process is triggered to write the active memory pages of the currently running process to the disk temporary storage area and mark them as read-only.

[0064] It should be noted that the beneficial effects of the operating system memory data processing device under strong electromagnetic interference provided in this embodiment are as follows: In this embodiment, the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM are obtained by periodic polling. In each polling cycle, the ripple voltage, bus eye width, and memory temperature are compared with a preset threshold set. If any parameter exceeds the threshold, a bit error repair operation and a temporary memory frequency reduction operation are triggered simultaneously. This solves the problems of single-bit error correction limitations and passive detection lag in the prior art of ECC memory. Through parameter polling and hierarchical error repair, active protection of memory data under strong electromagnetic interference is achieved. An adaptive polling cycle is adopted to collect power ripple, bus eye width, and DRAM temperature in real time, triggering threshold response at the microsecond level, and simultaneously starting error repair and memory frequency reduction to block the spread of interference. Single-bit errors are repaired through hardware atomic flipping; multi-bit errors are repaired through DRAM hardware reserved area backup pages, improving the success rate of atomic page replacement repair. In addition, when the backup page fails, a memory snapshot is triggered as a fallback to avoid system crash. System stability is improved in strong electromagnetic environments, effectively solving the problem of ensuring memory data integrity under extreme interference.

[0065] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0066] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for processing operating system memory data under strong electromagnetic interference, characterized in that, Including the following steps: Periodically poll to obtain the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM; In each polling cycle, the ripple voltage, bus eye width, and memory temperature are compared with a preset set of thresholds. If any parameter exceeds the threshold, a bit error repair operation and a temporary memory frequency reduction operation are triggered simultaneously. The steps of bit error repair include: Perform full-page CRC-64 redundancy check on the currently active memory pages; If the first full-page CRC-64 redundancy check fails to match, the hardware single-bit error automatic flip-to-repair is triggered, and a second full-page CRC-64 redundancy check is performed immediately after the repair is completed. If the secondary full-page CRC-64 redundancy check does not match, multi-bit error repair is triggered, and CRC-64 check is performed on the backup page of the corresponding active memory page of the currently running process in the DRAM hardware reserve area. If the backup page data is valid, an atomic page replacement is triggered, which atomically writes the backup page data to a new free memory page, updates the page table mapping, and marks the active memory page of the currently running process as unavailable. If the backup page data is invalid, the memory snapshot process is triggered to write the active memory pages of the currently running process to the disk temporary storage area and mark them as read-only; The threshold set includes ripple voltage trigger threshold, bus eye width trigger threshold, and memory temperature trigger threshold; the threshold set is stored in the BIOS's SPI Flash non-volatile memory and can be customized through the hardware configuration interface of the operating system kernel. After modification, it is automatically synchronized to the dedicated register of the memory controller.

2. The method for processing operating system memory data under strong electromagnetic interference according to claim 1, characterized in that, The steps of the periodic polling include: The initial polling period is set to 50ms; During each polling cycle, environmental change parameters are calculated synchronously: the instantaneous rate of change of ripple voltage, the fluctuation amplitude of bus eye width, and the rate of rise of memory temperature. The new polling cycle is calculated based on the environmental change parameters: New polling cycle = Initial polling cycle × (1 - a × Instantaneous change rate of ripple voltage - b × Fluctuation amplitude of bus eye width - c × Rise rate of memory temperature), where a is the weight of ripple change rate, b is the weight of eye width fluctuation, c is the weight of temperature rise, and a, b, and c are the normalized values ​​of the corresponding environmental change parameters exceeding the threshold. When the corresponding environmental change parameters do not exceed the threshold, the weight is 0. The polling period can be adjusted within the range of 1ms to 100ms, and the adjustment of the polling period is performed by the hardware timer of the memory controller.

3. The method for processing operating system memory data under strong electromagnetic interference according to claim 1, characterized in that, The steps to obtain the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM include: The PMIC generates a read command through the I2C communication protocol, specifies the address of the ripple voltage sampling register, and converts the analog ripple voltage signal into a digital signal through the internal 12-bit ADC. The signal is then returned to the hardware monitoring module via the I2C bus. After eliminating sampling noise through moving average filtering, the ripple voltage is output. The ripple voltage is the AC fluctuation component in the DC output voltage of the power management chip, measured in mV, and reflects the stability of the power output. The memory-mapped I / O instruction accesses the built-in bus eye width measurement register of the memory. The memory uses the bus eye width measurement circuit to collect the rising and / or falling edge jitter of the data signal in real time, outputs an 8-bit digital value and converts it into the bus eye width. The conversion steps are: after the digital value is multiplied by 2 / 255, it is normalized and compared with the standard eye width of the corresponding memory specification to obtain the bus eye width. Among them, the bus eye width is the effective reception window of the data transmission signal between the memory and DRAM in the time and voltage dimensions. The time is the unit interval UI, 1UI=1 / memory data rate. The smaller the bus eye width, the worse the signal integrity. The read command is generated through the SMBus communication protocol, specifying the device address of the DRAM temperature sensor and the temperature data register address. The thermistor built into the DRAM converts the junction temperature into a 16-bit digital signal, which is returned through the SMBus bus. The memory temperature is the junction temperature inside the DRAM chip, measured in °C. The higher the temperature, the faster the charge leakage rate of the DRAM memory cell and the higher the bit error rate. The acquisition and processing of ripple voltage, bus width, and memory temperature are performed in parallel by the hardware monitoring module.

4. The method for processing operating system memory data under strong electromagnetic interference according to claim 1, characterized in that: The steps for comparing ripple voltage, bus eye width, and memory temperature with a preset threshold set include: When the sampled value of the ripple voltage is greater than or equal to the ripple voltage trigger threshold, the judgment parameter exceeds the threshold. When the sampled value of the bus eye width is less than or equal to the bus eye width trigger threshold, the judgment parameter exceeds the threshold. If the collected memory temperature value is greater than or equal to the memory temperature trigger threshold, the parameter is determined to exceed the threshold. The determination result is notified to the processor in real time via an interrupt request.

5. The method for processing operating system memory data under strong electromagnetic interference according to claim 1, characterized in that, The steps for automatic toggle repair of hardware single-bit errors include: The memory controller locates the physical address of the erroneous bit using ECC error correction code. The physical address includes the DRAM chip number, row address, column address, and bit position. The value of the erroneous bit is atomically flipped using a hardware flip circuit; After the repair is completed, a second full-page CRC-64 redundancy check is triggered to verify the repair result; If the second full-page CRC-64 redundancy check matches, a single-bit error repair log is recorded, and the normal operation of the user process is restored. If the second full-page CRC-64 redundancy check does not match, the next step is triggered.

6. The method for processing operating system memory data under strong electromagnetic interference according to claim 1, characterized in that, The steps for performing a CRC-64 check on the backup page of the corresponding active memory page of the currently running process in the DRAM hardware reserve area include: When the secondary full-page CRC-64 redundancy check fails to match, the memory controller detects that the number of error bits is ≥2 through the ECC error correction code and judges it as a multi-bit error. The backup page address in the corresponding DRAM hardware reserve area is located based on the active memory page of the currently running process. The hardware reserve area is a separately allocated area in physical memory, which is protected by ECC and is used only to store backup data of active memory pages. The CRC-64 redundancy check of the backup page uses the same standard as the original active memory page; If the CRC-64 redundancy check of the backup page matches, the backup page data is considered valid; if the CRC-64 redundancy check of the backup page does not match, the backup page data is considered invalid.

7. The method for processing operating system memory data under strong electromagnetic interference according to claim 1, characterized in that, The steps that trigger an atomic page replacement include: The memory management module allocates one new free memory page from the free memory page list; The backup page data is atomically written to a new free memory page via a DMA channel. The writing process uses a hardware locking mechanism to ensure the atomicity of data transfer. After the write operation is complete, the page table mapping of the currently running process is immediately updated to map the virtual address of the original active memory page to the physical address of the new memory page. Page table updates use atomic operations and prohibit other processes from accessing them during the update process; After the update is complete, the original active memory pages are marked as unavailable and added to the memory reclamation chain to await subsequent garbage collection; After the update is complete, a signal is sent to the currently running process to notify it to resume normal operation; Once the currently running process resumes, all accesses to the original virtual address will be automatically mapped to new free memory pages without requiring modification of the process code.

8. The method for processing operating system memory data under strong electromagnetic interference according to claim 1, characterized in that, The steps to trigger a memory snapshot process to write the active memory pages of the currently running process to a temporary disk storage area and mark them as read-only include: The memory management module triggers a memory snapshot process, freezing all threads of the currently running process. Allocate a temporary memory buffer to store compressed data of active memory pages; The LZ4 compression algorithm is used to compress active memory page data, with a compression ratio of ≥2:1; The compressed data is written to the temporary disk storage area via the DMA channel; After writing is complete, the CRC-64 checksum of the snapshot data is calculated and stored for subsequent integrity verification; Mark the original active memory page as read-only, and prohibit processes from writing to it; Unfreeze the threads of the currently running process and notify them to resume running; Record the time, size, and disk path of the memory snapshot for subsequent data recovery; Once the system returns to normal, the memory page data can be restored using disk snapshot files. After the recovery is complete, the original memory pages are marked as writable, and the normal operation of the recovery process is restored.

9. The method for processing operating system memory data under strong electromagnetic interference according to claim 1, characterized in that, The steps to trigger a temporary memory frequency downclocking operation include: Read the current memory frequency register of the power management chip and parse the current operating frequency of the DDR memory; Reduce the current operating frequency of the DDR memory while ensuring it does not fall below the minimum operating frequency of the memory. Construct SMBus protocol control instructions. The instruction frame contains a 16-bit binary code of the frequency reduction target value and a synchronous memory voltage adjustment coefficient. Write the SMBus protocol control command into the frequency control register of the power management chip and wait for the device's ACK response; If the write operation is successful, the memory frequency node in the system clock tree is updated, and the memory frequency statistics are updated synchronously. If the write operation fails, the kernel-mode error log is triggered, and the current frequency is maintained.

10. An operating system memory data processing device under strong electromagnetic interference, characterized in that, A method for processing operating system memory data under strong electromagnetic interference as described in any one of claims 1 to 9, the apparatus comprising: The parameter acquisition module is used to periodically poll and acquire the ripple voltage of the power management chip, the bus eye width of the memory controller bus, and the memory temperature of the DRAM. The parameter comparison module is used to compare the ripple voltage, bus eye width and memory temperature with the preset threshold set in each polling cycle. If any parameter exceeds the threshold, a bit error repair operation and a temporary memory frequency reduction operation are triggered simultaneously. The error repair module, which performs bit error repair operations, includes the following steps: Perform full-page CRC-64 redundancy check on the active memory pages of the currently running process; If the first full-page CRC-64 redundancy check fails to match, the hardware single-bit error automatic flip-to-repair is triggered, and a second full-page CRC-64 redundancy check is performed immediately after the repair is completed. If the secondary full-page CRC-64 redundancy check does not match, multi-bit error repair is triggered, and CRC-64 check is performed on the backup page of the corresponding active memory page of the currently running process in the DRAM hardware reserve area. If the backup page data is valid, an atomic page replacement is triggered, which atomically writes the backup page data to a new free memory page, updates the page table mapping, and marks the active memory page of the currently running process as unavailable. If the backup page data is invalid, a memory snapshot process is triggered to write the active memory pages of the currently running process to the disk temporary storage area and mark them as read-only.

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