A joint dynamic memory allocation method for a CXL heterogeneous memory system

Abstract

The application discloses a kind of CXL heterogeneous memory system's joint dynamic memory allocation method, belong to heterogeneous memory management technical field.The method obtains the running state information of heterogeneous memory system, the running state information includes DRAM available memory information, CXL available memory information, system throughput information, current memory allocation proportion information and CPU performance index information;According to target CXL allocation proportion, execute memory allocation control, and guide subsequent page allocation to CXL node by adjusting the available DRAM capacity visible to system;The performance index collected is processed, the combined performance score is constructed, and according to the performance score difference, simulated annealing acceptance, adaptive step updating, damping control and local refinement search are executed, and the optimal allocation proportion is updated and the optimal CXL allocation proportion is output.The application is used to solve the problem that fixed proportion method is difficult to determine optimal allocation proportion and dynamic allocation algorithm converges slowly and is easy to oscillate.

Description

Technical Field

[0001] This invention relates to the field of heterogeneous memory management technology, and in particular to a joint dynamic memory allocation method for CXL heterogeneous memory systems. Background Technology

[0002] With the continuous development of scientific computing and complex deep learning tasks, memory-intensive applications exhibit high memory consumption, frequent allocation and release, and high memory bandwidth requirements. Single-channel DRAM is gradually becoming insufficient to meet the needs of these applications in terms of capacity, bandwidth, and cost. The continuous growth in the size of deep learning models and the expansion of multimodal data processing further amplify this contradiction. The paper points out that in computing clusters dominated by multi-channel DRAM, memory costs account for approximately 50% of the total server cost, and the memory wall problem caused by the uneven development of CPU and memory performance has become a bottleneck in system deployment.

[0003] Compute-X Link (CXL) is an open interconnect standard built on top of the PCIe physical layer. It provides high-bandwidth, low-latency, and cache-coherent access capabilities to CPUs, memory expansion devices, and accelerators through three protocols: CXL.io, CXL.cache, and CXL.mem. In particular, CXL Type 3 devices are designed for memory expansion scenarios, enabling hosts to access extended memory resources in a manner close to memory, thereby forming a unified and manageable heterogeneous memory pool.

[0004] Existing research on memory allocation for CXL heterogeneous memory systems mainly includes three paths: static allocation, dynamic allocation, and page management. Previous works have used static allocation methods to reveal the bandwidth expansion potential of CXL memory; other works have proposed a transparent page placement mechanism to distribute hot and cold pages across hierarchical memory; and still others have proposed a Caption dynamic allocation algorithm that uses linear regression and a greedy strategy to adjust memory allocation ratios to improve throughput.

[0005] Existing dynamic allocation methods still suffer from slow convergence speed, lag in dynamic response, and issues such as non-convergence or reduced throughput under specific workloads. These problems limit the full realization of the performance advantages of CXL heterogeneous memory systems. On the other hand, while fixed DRAM:CXL ratio testing can observe performance changes under different ratios, it cannot directly obtain the optimal ratio and its corresponding maximum throughput. Therefore, a joint dynamic memory allocation method is needed that can identify the optimal DRAM:CXL ratio and improve system throughput with fewer tuning rounds. Summary of the Invention

[0006] (a) Technical problems to be solved

[0007] The purpose of this invention is to provide a joint dynamic memory allocation method in a CXL heterogeneous memory system, so as to solve the problems of slow convergence, obvious oscillation, and difficulty in determining the optimal ratio in existing dynamic memory allocation algorithms.

[0008] (II) Technical Solution

[0009] This invention includes the following steps:

[0010] Step 1: Obtain running status information.

[0011] Obtain the operating status information of the heterogeneous memory system, including DRAM available memory information, CXL available memory information, system throughput information, current memory allocation ratio information, and CPU performance index information.

[0012] Step 2: Memory allocation control.

[0013] Memory allocation control is performed according to the target CXL allocation ratio. By setting a fixed DRAM allocation weight, combined with the application memory requirement, the current available memory capacity and the reserved memory capacity, the target memory amount and the additional DRAM usage of the local node are determined. When the additional DRAM usage is greater than zero, a memory usage process is started to occupy DRAM memory, and the operating system's default NUMA allocation strategy is used to guide subsequent pages to be allocated to the CXL node.

[0014] Step 3: Construct the combined performance score.

[0015] Within each tuning round, IPC, L1 mismatch latency, DDR read latency, and average throughput are collected. The collected performance metrics are accumulated and averaged to obtain a combined performance score. A performance score difference is then generated based on the combined performance score between the current tuning round and the previous tuning round. S.

[0016] Step 4: Simulate annealing acceptance strategy.

[0017] When the performance score difference When S is less than or equal to zero, the acceptance probability of the suboptimal direction is calculated based on the current annealing temperature, and the current suboptimal allocation ratio adjustment direction is adjusted based on the acceptance probability.

[0018] Step 5: Adaptive step size update and damping control.

[0019] When the performance score difference When S is greater than zero, an adaptive step size update strategy based on momentum factor, learning rate and modulation factor is executed to determine the proportional adjustment step size of the current round; when multiple consecutive tuning rounds meet the requirements of continuous performance improvement and consistent proportional adjustment direction, a damping constraint is applied to the proportional adjustment step size of the current round.

[0020] Step 6: Optimal ratio update and local refinement search.

[0021] The optimal allocation ratio R is updated based on the average throughput of each optimization round. best When the optimization rounds exceed the initial exploration phase, the allocation ratio for the next round is limited to the neighborhood of the current optimal allocation ratio to perform a local refinement search and output the optimal CXL allocation ratio.

[0022] (III) Beneficial Effects

[0023] The advantages of this invention are as follows:

[0024] Compared with existing technologies, this invention has at least the following advantages: First, by combining memory allocation with ratio optimization, the target DRAM:CXL ratio is implemented as the actual page allocation state, and the ratio is dynamically updated based on performance feedback, improving the executability of ratio control. Second, by combining simulated annealing, adaptive step size, damped control, and local refinement search, the global search capability and later convergence stability of ratio tuning are improved. Third, FA-PAMO achieves 33% faster convergence compared to the dynamic allocation algorithm, reaches stability on average 3 to 4 rounds earlier, and increases throughput by approximately 29.14%. Approximately 80% of memory-intensive applications exhibit higher throughput and limited additional latency overhead in heterogeneous memory systems with CXL enabled. Attached Figure Description

[0025] Figure 1 This is a flowchart of the joint dynamic memory allocation method for the CXL heterogeneous memory system proposed in this invention.

[0026] Figure 2 This is a schematic diagram of the joint dynamic memory allocation method for the CXL heterogeneous memory system proposed in this invention.

[0027] Figure 3 is a schematic diagram of the changes in real-time available memory of DRAM and CXL under different loads in the heterogeneous memory system of the present invention. Figure 3(a) shows the changes in available memory of DRAM and CXL under deep learning load, and Figure 3(b) shows the changes in available memory of DRAM and CXL under SPEC2017 benchmark load.

[0028] Figure 4 is a schematic diagram of the dynamic adjustment process of DRAM:CXL memory allocation ratio under different loads according to the present invention. Figure 4(a) shows the adjustment process under SPEC2017 load, which corresponds to mcf, cactuBSSN and roms from top to bottom. Figure 4(b) shows the adjustment process under deep learning load, which corresponds to Convolution, RNN Inference, CNNInference and RNN Training from top to bottom.

[0029] Figure 5 is a schematic diagram of the system throughput of the present invention under different loads and the change of adjustment rounds. Figure 5(a) shows the throughput evolution trend under SPEC2017 load, corresponding to mcf, cactusBSSN and roms from top to bottom. Figure 5(b) shows the throughput evolution trend under deep learning load, corresponding to Convolution, RNN Inference, CNNInference and RNN Training from top to bottom. Detailed Implementation

[0030] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings:

[0031] Reference Figure 1 The specific implementation steps of the present invention are as follows:

[0032] Step 1: Obtain running status information.

[0033] Within each tuning round, the operational status information of the heterogeneous memory system is acquired. This operational status information includes DRAM available memory information, CXL available memory information, system throughput information, CPU performance metrics, and current memory allocation ratio information. The CPU performance metrics include at least instruction-per-cycle (IPC), L1 mismatch latency, and DDR read latency. This operational status information serves as dynamic tuning input for subsequent memory allocation control, combined performance score construction, and allocation ratio updates.

[0034] Step 2: Memory allocation control.

[0035] Figure 2 This demonstrates the process of dynamically allocating memory.

[0036] Memory allocation control is performed based on the target CXL allocation ratio. First, a fixed DRAM allocation weight, denoted as W, is preset; then, the currently available memory capacity is obtained, denoted as M. a The application memory requirement is obtained and denoted as M. Based on the application memory requirement M, the fixed DRAM allocation weight W, and the current CXL allocation ratio, the target memory amount M0 of the local node is determined, and its calculation formula is:

[0037]

[0038] Where r represents the current CXL allocation ratio. Based on the current available memory capacity M a Reserved memory capacity M r And the target memory amount M0 of the local node, determine the DRAM usage control amount M. eThe formula for its calculation is:

[0039]

[0040] M e This represents the additional DRAM capacity required to achieve the target CXL allocation ratio. When the DRAM occupancy control value M... e When the target CXL allocation ratio is greater than 0, a memory-occupying process is initiated to occupy DRAM memory, thereby reducing the system's visible available DRAM capacity. The operating system's default NUMA allocation strategy is then used to guide subsequent pages to be allocated to CXL nodes, thus establishing an actual memory usage state corresponding to the target CXL allocation ratio. To reduce sudden performance fluctuations caused by ratio switching, a resource reservation buffer mechanism is used to gradually adjust the reserved memory capacity Mr. When the target CXL allocation ratio increases, the reserved memory capacity Mr is increased; when the target CXL allocation ratio decreases, the reserved memory capacity Mr is gradually released, achieving a smooth transition between different allocation ratios.

[0041] Step 3: Construct the combined performance score.

[0042] During the tuning rounds, continuously collect IPC per instruction cycle, L1 mismatch latency, DDR read latency, and average throughput TP. avg The collected performance metrics are accumulated and averaged according to predefined weights to obtain a combined performance score that represents the overall performance trend of the current memory allocation configuration. This combined performance score reflects the overall performance change trend under a given memory allocation configuration, rather than a single instantaneous fluctuation.

[0043] When the CPU of NUMA node 1 is turned off and the pcm-latency tool is unavailable, the number of L1 cache mismatch pause cycles C is collected. L1 N times of L1 cache mismatch L1 Calculate L1 mismatch delay L L1 The formula for its calculation is:

[0044]

[0045] Among them, f CPU Indicates CPU frequency. The L... L1 The combined performance score construction process is incorporated to ensure the continuous availability of the performance evaluation process under different operating conditions.

[0046] After obtaining the combined performance score for the current tuning round, calculate the performance score difference based on the combined performance score between the current tuning round and the previous tuning round. S, and the performance score difference S serves as the optimization signal for updating the current allocation ratio. Simultaneously, the total system throughput is continuously monitored throughout each tuning round, and the average throughput TP is calculated at the end of each round. avg To achieve the average throughput TP avg This serves as a basis for characterizing the actual system performance status in the current round.

[0047] Step 4: Simulate annealing acceptance strategy.

[0048] When the performance score difference When S ≤ 0, the simulated annealing acceptance strategy is executed. First, the current annealing temperature Tt, initial annealing temperature T0, cooling rate λ, and minimum temperature threshold Tmin are set. After each tuning round, the current annealing temperature is updated using the following formula:

[0049]

[0050] Based on the current performance score difference S and current annealing temperature T t Calculate the probability P of accepting the suboptimal direction. a Determine whether to accept the current suboptimal allocation ratio adjustment direction. This method preserves the ability to explore non-optimal directions even when system performance degrades or stagnates, preventing the proportional search process from prematurely falling into local optima and allowing the proportional search to gradually transition from large-scale exploration in the early stages to stable convergence in the later stages. When the performance score difference... When S is less than or equal to 0, the probability of acceptance P in the suboptimal direction is calculated using the exponential descent method. a And based on the suboptimal direction acceptance probability P a Determine whether to accept the current suboptimal allocation ratio adjustment direction; wherein, the simulated annealing acceptance strategy is used to retain the ability to explore non-optimal adjustment directions when the system performance declines or stagnates, so as to avoid the allocation ratio update process from falling into a local optimum state too early, and to gradually transition the ratio search process from a large-scale exploration in the early stage to stable convergence in the later stage through temperature decay in rounds.

[0051] Step 5: Adaptive step size update and damping control.

[0052] When the performance score difference When S > 0, an adaptive step size update strategy based on momentum factor, learning rate, and modulation factor is implemented. The step size is adjusted according to the proportion of the previous round and the difference in the current performance score. S and the modulation factor are used to determine the proportional adjustment step size for the current round, and the calculation formula is as follows:

[0053]

[0054] in, Represents the momentum factor. This indicates that the modulation factor has been learned. This represents the combined performance score for the current tuning round. This represents the combined performance score from the previous tuning round. This represents the cutoff factor. The modulation factor γ is used to amplify or suppress the step size variation based on the degree of performance improvement, balancing update speed and adjustment stability. γ is determined based on the combined performance score of the current tuning round and the previous tuning round, and its calculation formula is:

[0055]

[0056] When multiple consecutive optimization rounds meet the performance score difference When S > 0 and the proportional adjustment direction is consistent, a damping constraint is applied to the proportional adjustment step size of the current round. The damping factor D is calculated as follows:

[0057]

[0058] in, denoted by the damping attenuation coefficient, and n representing the number of consecutive unidirectional improvement rounds. The damping factor D is used to constrain the proportional adjustment step size of the current round, thereby limiting step size growth and reducing the risk of proportional oscillation.

[0059] Step 6: Optimal ratio update and local refinement search.

[0060] At the start of optimization, the current allocation ratio is used as the initial value, and after each optimization round, the average throughput (TP) of the current round is used as the initial value. avg With the current optimal throughput TP best Update the comparison results; when the average throughput TP of the current round... avg Greater than the current optimal throughput TP best When the optimal allocation ratio R is reached, the allocation ratio corresponding to the current round is updated to the optimal allocation ratio R. best And simultaneously update the current optimal throughput TP. best ;

[0061] After the optimization rounds exceed the initial exploration phase, the next round of allocation ratio is limited to a local range near the current optimal allocation ratio for exploration. The adaptive step size update is used to determine the ratio update range by combining the historical adjustment direction and the current performance change magnitude. The modulation factor is used to amplify or suppress the step size according to the degree of performance improvement. The damping control is used to limit the step size growth to reduce the risk of oscillation when continuously improving in the same direction. The local refinement search is used to shrink the search range to the neighborhood of the current optimal allocation ratio after the initial exploration phase ends, thereby improving the convergence accuracy and stability of the subsequent optimization process.

[0062] Example

[0063] The effects of the present invention will be further illustrated by the following data:

[0064] In this embodiment, the proposed joint dynamic memory allocation method is used to dynamically optimize the DRAM and CXL allocation ratio in a heterogeneous memory system. First, system operating status information is acquired, including available DRAM memory, available CXL memory, system throughput, current memory allocation ratio, and CPU performance metrics. Then, forced memory allocation control is executed according to the target CXL allocation ratio. By setting a fixed DRAM allocation weight and combining it with application memory requirements, current available memory capacity, and reserved memory capacity, the target memory amount and DRAM occupancy control amount for the local node are determined. When the DRAM occupancy control amount is greater than zero, a memory occupancy process is initiated to reduce the system's visible available DRAM capacity. A NUMA allocation strategy is used to guide subsequent pages to be allocated to the CXL node, thereby forming the actual memory usage state corresponding to the target CXL allocation ratio. Within each optimization round, instruction cycle count (IPC), L1 mismatch latency, DDR read latency, and average throughput are continuously collected. The collected performance metrics are accumulated and averaged to obtain a combined performance score. A performance score difference is generated based on the combined performance score between the current and previous optimization rounds. S; when the performance score difference When S is less than or equal to zero, a simulated annealing acceptance strategy is executed. The acceptance probability of the suboptimal direction is calculated based on the current annealing temperature, and a decision is made based on this probability to determine whether to accept the current suboptimal allocation ratio and adjust the direction. When the performance score difference... When S is greater than zero, an adaptive step size update strategy based on momentum factor, learning rate, and modulation factor is executed to determine the proportional adjustment step size for the current round. If performance continues to improve and the proportional adjustment direction is consistent across multiple consecutive tuning rounds, a damping constraint is applied to the proportional adjustment step size for the current round to limit step size growth and reduce the risk of proportional oscillation. After the tuning rounds exceed the initial exploration phase, the allocation ratio for the next round is limited to the current optimal allocation ratio R. best Within its vicinity, perform a local refinement search and update the optimal allocation ratio R based on the average throughput of each tuning round. bestFigure 3 shows that during the fixed-ratio control process, as the CXL allocation ratio increases, the available memory on the DRAM side and the CXL side changes synchronously, indicating that the present invention can effectively realize the target DRAM:CXL ratio as the actual memory usage state. Figure 4 shows that the present invention has a faster convergence speed and requires fewer rounds during the optimization process. Figure 5 shows that the present invention can achieve higher throughput during the optimization process and maintain a small fluctuation range in subsequent rounds. As can be seen from the above, the present invention can not only effectively realize the target DRAM:CXL allocation ratio as the actual memory usage state, but also achieve rapid search, stable convergence, and continuous optimization of the allocation ratio based on system performance feedback, enabling the system to reach a better memory configuration in fewer optimization rounds. The experimental results in the paper further show that the present invention achieves 33% faster convergence compared to the dynamic allocation algorithm, reaches stability on average 3 to 4 rounds earlier, and increases the system throughput by about 29.14%, thus demonstrating higher allocation ratio optimization efficiency, operational stability, and performance optimization effect.

[0065] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

[0066] The innovation of this invention is reflected in the following aspects:

[0067] This invention addresses the problems of existing fixed-ratio methods in CXL heterogeneous memory systems, which struggle to determine the optimal DRAM:CXL allocation ratio, and the slow convergence and oscillation issues of existing dynamic allocation algorithms. It proposes a joint dynamic memory allocation method that combines memory allocation control with ratio optimization updates. At the allocation control level, this invention adjusts the system's visible available DRAM capacity and combines a reserved memory buffer mechanism with the operating system's default NUMA allocation strategy to transform the target DRAM:CXL ratio into the actual page allocation state, thereby achieving controllable adjustment of the heterogeneous memory allocation ratio. At the ratio optimization level, this invention constructs a combined performance score using IPC, L1 mismatch latency, DDR read latency, and average throughput, and uses the performance score difference... S serves as the optimization signal for proportional updates. When performance degrades, a simulated annealing acceptance strategy is employed to enhance global search capabilities. When performance improves, an adaptive step-size update strategy based on momentum factor, learning rate, and modulation factor is used to increase convergence speed. Simultaneously, damping control is combined to suppress proportional oscillations, and local refinement search is performed using the optimal allocation ratio Rbest. This ensures search capabilities while improving later convergence accuracy and stability. Thus, this invention forms a closed-loop dynamic allocation mechanism of "target ratio implementation—performance feedback evaluation—proportional adaptive update—optimal ratio refinement," enabling the DRAM and CXL allocation ratio in heterogeneous memory systems to be continuously optimized according to the operating status, exhibiting strong engineering practicality and dynamic optimization capabilities.

Claims

1. A joint dynamic memory allocation method for a CXL heterogeneous memory system, characterized in that, include: (1) Obtain the operating status information of the heterogeneous memory system, including DRAM available memory information, CXL available memory information, system throughput information, CPU performance index information and current memory allocation ratio information, so as to form input information for dynamic optimization; (2) Forced memory allocation control is performed according to the target CXL allocation ratio. By adjusting the available DRAM capacity of the system and maintaining the reserved memory buffer, the DRAM resource status visible to the operating system is changed. The default NUMA allocation strategy of the operating system is used to guide subsequent pages to be allocated to CXL nodes, so as to form the actual memory usage status corresponding to the target CXL allocation ratio. (3) Collect instruction cycle per cycle (IPC), L1 mismatch latency, DDR read latency, and average throughput during each tuning round. Accumulate and average the collected performance metrics to obtain a combined performance score that represents the overall performance trend of the current memory allocation configuration. Calculate the performance difference based on the combined performance score of the current tuning round and the previous tuning round. S; (4) Based on the aforementioned performance difference S updates the current allocation ratio, where, in When S is less than or equal to 0, a simulated annealing acceptance strategy is executed to determine whether to accept the suboptimal allocation ratio adjustment direction. When S is greater than 0, an adaptive step size update strategy based on momentum factor, learning rate, and modulation factor is implemented, and damping control and local refinement search are applied to the updated allocation ratio. The optimal allocation ratio R is updated based on the average throughput. best Output the optimal CXL allocation ratio for subsequent rounds of memory allocation.

2. The joint dynamic memory allocation method for CXL heterogeneous memory systems according to claim 1, characterized in that, The adjustment of the system's available DRAM capacity according to the target CXL allocation ratio includes: A fixed DRAM allocation weight is pre-set, and the current available memory capacity is obtained. Based on the application memory requirement, the fixed DRAM allocation weight, and the current CXL allocation ratio, the target memory amount M0 of the local node is determined according to the proportion of the fixed DRAM allocation weight in the sum of the fixed DRAM allocation weight and the current CXL allocation ratio. Then, based on the current available memory capacity, the reserved memory capacity, and the target memory amount M0 of the local node, the reserved memory capacity and the target memory amount M0 of the local node are subtracted from the current available memory capacity to obtain the DRAM occupancy control amount M. e When the DRAM occupancy control value M e When the value is greater than 0, a memory-consuming process is started to occupy DRAM memory, thereby reducing the available DRAM capacity visible to the system and guiding subsequent pages to be allocated to CXL nodes.

3. The joint dynamic memory allocation method for the CXL heterogeneous memory system according to claim 1, characterized in that, The system adjusts the available DRAM capacity according to the target CXL allocation ratio. A proportional control model is used to establish a mapping relationship between the target CXL allocation ratio and the actual memory usage status. A resource reservation buffer mechanism is used to gradually adjust the reserved memory capacity. Specifically, the reserved memory capacity is increased when the target CXL allocation ratio increases and gradually released when the target CXL allocation ratio decreases. This achieves a smooth transition during the memory allocation ratio switching process and reduces allocation oscillations and performance mutations caused by workload fluctuations.

4. The joint dynamic memory allocation method for CXL heterogeneous memory systems according to claim 1, characterized in that, The combined performance score is obtained by accumulating and averaging instruction per cycle (IPC), L1 mismatch latency, and DDR read latency according to predefined weights. When the CPU on NUMA node 1 is disabled and the pcm-latency tool is unavailable, the score is calculated by collecting the number of L1 cache mismatch pause cycles (C). L1 N times of L1 cache mismatch L1 Calculate L1 mismatch delay L L1 The formula for its calculation is: ， Where f CPU This indicates the CPU frequency.

5. The joint dynamic memory allocation method for CXL heterogeneous memory systems according to claim 1, characterized in that, After the combined performance score is constructed, the performance score difference is calculated based on the combined performance score of the current tuning round and the combined performance score of the previous tuning round. S, and the performance score difference S serves as the optimization signal for updating the current allocation ratio. Simultaneously, the total system throughput is continuously monitored within each tuning round, and the average throughput is calculated at the end of the round. The average throughput is used as the basis for characterizing the actual system performance status in the current round and is used for subsequent updates to the optimal allocation ratio.

6. The joint dynamic memory allocation method for CXL heterogeneous memory systems according to claim 1, characterized in that, The simulated annealing acceptance strategy includes: Set the current annealing temperature to T. t The initial annealing temperature is T0; the annealing temperature is updated according to the following rules: ， in T represents the cooling rate. min Indicates the minimum temperature threshold; when the performance score difference... When S is less than or equal to 0, the probability of acceptance P in the suboptimal direction is calculated using the exponential descent method. a And based on the suboptimal direction acceptance probability P a Determine whether to accept the current suboptimal allocation ratio adjustment direction; wherein, the simulated annealing acceptance strategy is used to retain the ability to explore non-optimal adjustment directions when the system performance declines or stagnates, so as to avoid the allocation ratio update process from falling into a local optimum state too early, and to gradually transition the ratio search process from a large-scale exploration in the early stage to stable convergence in the later stage through temperature decay in rounds.

7. The joint dynamic memory allocation method for CXL heterogeneous memory systems according to claim 1, characterized in that, The adaptive step size update, damping control, and local refinement search include: Adjust the step size according to the proportion of the previous round. Current performance score difference and modulation factor Calculate the adjustment step size for the current round. The formula for its calculation is: ， in Represents the momentum factor. Represents the learning rate; the combined performance score based on the current tuning round. Combined performance score with the previous tuning round Calculate the modulation factor The formula for its calculation is: ， in This represents the cutoff factor; when the performance score difference is satisfied in multiple consecutive tuning rounds. When the damping factor D is greater than 0 and the proportional adjustment direction is consistent, the formula for calculating the damping factor D is: ， in The damping factor D represents the damping attenuation coefficient, and n represents the number of consecutive unidirectional improvement cycles. The damping factor D is used to adjust the step size of the current cycle ratio. Apply constraints.

8. The joint dynamic memory allocation method for CXL heterogeneous memory systems according to claim 1, characterized in that, The optimal allocation ratio R best At the start of optimization, the current allocation ratio is used as the initial value, and after each optimization round, the average throughput (TP) of the current round is used as the initial value. avg With the current optimal throughput TP best Update the comparison results; average throughput (TP) for the current round. avg Greater than the current optimal throughput TP best When the optimal allocation ratio R is reached, the allocation ratio corresponding to the current round is updated to the optimal allocation ratio R. best And simultaneously update the current optimal throughput TP. best When the number of optimization rounds exceeds the initial exploration phase, the next round of memory allocation ratio is limited to a local range near the current optimal allocation ratio for searching. The adaptive step size update is used to determine the ratio update range by combining the historical adjustment direction and the current performance change magnitude. The modulation factor is used to amplify or suppress the step size according to the degree of performance improvement. The damping control is used to limit the step size growth to reduce the risk of oscillation when continuously improving in the same direction. The local refinement search is used to shrink the search range to the neighborhood of the current optimal allocation ratio after the initial exploration phase ends, thereby improving the convergence accuracy and stability of the subsequent optimization process.

Images