A method for bidirectional communication based on SPI bus and related device

Abstract

The application discloses a kind of based on SPI bus's two-way communication method and related equipment, method includes: when host detects the state of SST signal line changes, length synchronization frame is sent to slave;If slave determines length synchronization frame is valid, slave changes the level state of SST signal line;When host detects the state of SST signal line changes, instruction data is sent to slave;After slave executes instruction data and generates response data, slave changes the level state of SST signal line;When host detects the state of SST signal line changes, based on the length of valid response data and SST signal line change, start data back reading procedure and obtain response data.The two-way communication method based on SPI bus of the application can solve the frame length negotiation problem existing in traditional SPI communication, while ensuring that the state of host and slave is kept synchronous before and after data transmission, and can be widely applied in data communication technical field.

Description

Technical Field

[0001] This invention relates to the field of data communication technology, and in particular to a bidirectional communication method and related equipment based on the SPI bus. Background Technology

[0002] Among related technologies, SPI (Serial Peripheral Interface) communication is currently widely used in embedded systems due to its high speed and reliability. However, traditional SPI communication typically only supports fixed-length data transmissions, making it inflexible in responding to varying data volume requirements. Furthermore, in traditional SPI communication, the master cannot know the real-time status of the slave device, easily leading to data loss or conflicts, and causing communication delays and errors. Therefore, while current SPI communication offers high speed and reliability, its fixed data frame length limits the diversity of application scenarios. Additionally, synchronization between the master and slave devices usually relies on fixed timing, lacking flexible dynamic adjustment capabilities.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] This invention aims to solve at least one of the technical problems existing in related technologies. To this end, this invention proposes a bidirectional communication method based on the SPI bus, which can solve the frame length negotiation problem existing in traditional SPI communication, while ensuring that the master and slave devices remain synchronized before and after data transmission, reducing the waiting time during data transmission, and also reducing the communication error rate.

[0005] The present invention also proposes a bidirectional communication device based on an SPI bus that has the above-mentioned bidirectional communication method based on an SPI bus.

[0006] The present invention also proposes an electronic device having the above-mentioned bidirectional communication method based on the SPI bus.

[0007] The present invention also proposes a computer-readable storage medium having the above-mentioned bidirectional communication method based on the SPI bus.

[0008] The present invention also proposes a computer program product having the above-mentioned bidirectional communication method based on the SPI bus.

[0009] According to a first aspect of the present invention, a bidirectional communication method based on an SPI bus is applied to a communication system, the communication system including a master and a slave, the SPI bus including an SS signal line and an SST signal line, the method comprising the following steps: When the slave device detects a change in the current pin state of the SS signal line, it changes the current level state of the SST signal line via the slave device. When the host detects a change in the current level state of the SST signal line, it sends a synchronization frame of the first length to the slave. The slave device verifies whether the first length synchronization frame is valid. If the slave device determines that the first length synchronization frame is valid, the slave device changes the current level state of the SST signal line. When the host detects a change in the current level of the SST signal line, it sends instruction data to the slave. After the slave device executes the instruction data and generates response data, the current level state of the SST signal line is changed by the slave device. When the host detects a change in the current level of the SST signal line, it initiates a response data readback process based on the valid response data length and the change in the SST signal line to receive the response data sent by the slave device.

[0010] According to an embodiment of the present invention, a bidirectional communication method based on an SPI bus has at least the following advantages: This scheme is applied to a communication system, which includes a master and a slave. The SPI bus includes an SS signal line and an SST signal line. When the slave detects a change in the current pin state of the SS signal line, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it sends a first-length synchronization frame to the slave. The slave verifies the validity of the first-length synchronization frame. If the slave determines that the first-length synchronization frame is valid, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it sends instruction data to the slave. After the slave executes the instruction data and generates response data, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it initiates a response data readback process based on the valid response data length and the change in the SST signal line to receive the response data sent by the slave. This invention introduces a data length synchronization frame, allowing the communication data frame length to be dynamically adjusted according to actual needs, no longer limited to a fixed length, thus solving the frame length negotiation problem in traditional SPI communication. At the same time, based on the SPI standard interface, the introduction of the auxiliary signal SST ensures that the master and slave remain synchronized before and after data transmission, significantly improving the synchronization reliability between the master and slave, reducing the waiting time during data transmission, and also reducing the communication error rate.

[0011] According to some embodiments of the present invention, when the host detects a change in the current level state of the SST signal line, the host initiates a response data readback process based on the valid response data length and the change in the SST signal line to receive the response data sent by the slave device, including: After the slave device generates the response data, if the master device detects a change in the current level state of the SST signal line, it sends a second-length synchronization frame to the slave device and obtains the length information of the response data sent by the slave device based on the second-length synchronization frame. After the host obtains the response data length information, the host verifies whether the response data length in the response data length information is valid. If the host determines that the response data length is valid and the host detects a change in the current level state of the SST signal line, then the host receives the response data according to the response data frame length.

[0012] According to some embodiments of the present invention, the response data length information includes response data length and response data verification information. The step of verifying the validity of the response data length in the response data length information by the host after the host obtains the response data length information includes: The host extracts the response data length and the response data verification information from the response data length information. The host verifies the validity of the response data length based on the response data verification information.

[0013] According to some embodiments of the present invention, the step of receiving the response data according to the response data frame length if the host determines that the response data length is valid and the host detects a change in the current level state of the SST signal line includes: If the host determines that the response data length is valid and the host detects that the current level state of the SST signal line has changed, then the host receives the response data frame sent by the slave according to the response data length. The host performs data parsing on the response data frame to obtain the response data.

[0014] According to some embodiments of the present invention, the first length synchronization frame includes instruction data length information and instruction data verification information. The step of verifying the validity of the first length synchronization frame by the slave device, and if the slave device determines that the first length synchronization frame is valid, then changing the current level state of the SST signal line by the slave device includes: The slave device extracts the instruction data length information and the instruction data verification information from the first length synchronization frame. The slave device performs a validity check on the instruction data length information based on the instruction data verification information. If the instruction data length information passes the validity check, then the first length synchronization frame is determined to be valid; If the slave device determines that the first length synchronization frame is valid, then the slave device changes the current level state of the SST signal line.

[0015] According to some embodiments of the present invention, before the slave device changes the current level state of the SST signal line when it detects a change in the current pin state of the SS signal line, the method further includes: The host computer can change the current pin state of the SS signal line.

[0016] According to a second aspect of the present invention, a bidirectional communication device based on an SPI bus is applied to a communication system, the communication system including a master and a slave, the SPI bus including an SS signal line and an SST signal line, and the device including the following modules: The slave communication preparation module is used to change the current level state of the SST signal line when the slave detects a change in the current pin state of the SS signal line. The length synchronization frame sending module is used to send a first length synchronization frame to the slave when the host detects a change in the current level state of the SST signal line; The length synchronization frame verification module is used to verify whether the first length synchronization frame is valid through the slave device. If the slave device determines that the first length synchronization frame is valid, the current level state of the SST signal line is changed through the slave device. The instruction data transmission module is used to send instruction data to the slave device when the host detects a change in the current level state of the SST signal line; The response data generation module is used to change the current level state of the SST signal line through the slave device after the slave device executes the instruction data and generates response data; The response data readback module is used to receive the response data sent by the slave device when the host detects a change in the current level state of the SST signal line. This is achieved by the host initiating a response data readback process based on the valid response data length and the change in the SST signal line.

[0017] An electronic device according to a third aspect of the present invention includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method described above.

[0018] According to a fourth aspect of the present invention, a computer-readable storage medium stores a computer program that, when executed by a processor, implements the method described above.

[0019] A computer program product according to a fifth aspect of the present invention includes a computer program that, when executed by a processor, implements the method described above.

[0020] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein: Figure 1 A flowchart illustrating the steps of a bidirectional communication method based on an SPI bus provided in an embodiment of the present invention; Figure 2 A schematic diagram of a host workflow provided in an embodiment of the present invention; Figure 3 A schematic diagram of a slave device's workflow is provided as an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a bidirectional communication device based on the SPI bus provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the hardware structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0022] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0023] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0024] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0025] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0026] In the description of this invention, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0027] Currently, SPI communication is widely used in embedded systems, characterized by high speed and reliability. However, traditional SPI communication typically only supports fixed-length data transmission, which cannot flexibly meet the needs of varying communication data volume. In addition, traditional SPI communication lacks an effective synchronization mechanism, and the master cannot know the real-time status of the slave, which can easily lead to data transmission loss or conflicts. To address the above problems, the relevant technologies have the following shortcomings: (1) Fixed data length limitation: The standard SPI data frame length is generally fixed, which is difficult to adapt to the needs of dynamic changes in the amount of data transmitted and received; (2) One-way communication dominance: The slave cannot actively initiate communication, and relies on the master polling, which causes communication delay; (3) Inability to achieve state synchronization: The master can easily cause communication errors when initiating communication when the slave's status is unknown. Therefore, although the current SPI communication has the characteristics of high speed and reliability, its fixed data frame length limits the diversity of application scenarios. In addition, the synchronization between the master and slave usually depends on a fixed timing sequence and lacks flexible dynamic adjustment capabilities.

[0028] In view of this, this embodiment of the invention provides a bidirectional communication method and related device based on an SPI bus. This scheme is applied to a communication system, which includes a master and a slave. The SPI bus includes an SS signal line and an SST signal line. When the slave detects a change in the current pin state of the SS signal line, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it sends a first-length synchronization frame to the slave. The slave verifies whether the first-length synchronization frame is valid. If the slave determines that the first-length synchronization frame is valid, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it sends instruction data to the slave. After the slave executes the instruction data and generates response data, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it initiates a response data readback process to receive the response data sent by the slave. This invention introduces a data length synchronization frame, allowing the communication data frame length to be dynamically adjusted according to actual needs, no longer limited to a fixed length, thus solving the frame length negotiation problem in traditional SPI communication. At the same time, based on the SPI standard interface, the introduction of the auxiliary signal SST ensures that the master and slave remain synchronized before and after data transmission, significantly improving the synchronization reliability between the master and slave, reducing the waiting time during data transmission, and also reducing the communication error rate.

[0029] This invention provides a bidirectional communication method based on an SPI bus, relating to the field of data communication technology. This bidirectional communication method based on an SPI bus can be applied to a terminal, a server, or software running on either a terminal or a server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, smart speaker, smartwatch, or in-vehicle terminal, but is not limited thereto. The server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network. The software can be an application implementing a bidirectional communication method based on an SPI bus, but is not limited to the above forms.

[0030] This invention can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This invention can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This invention can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0031] Please see Figure 1 , Figure 1 This is an optional flowchart of a bidirectional communication method based on an SPI bus provided in an embodiment of the present invention. Figure 1 The method described above is applied to a communication system, which includes a master and a slave, and the SPI bus includes SS signal lines and SST signal lines. Figure 1 The method may include, but is not limited to, steps S101 to S106.

[0032] Step S101: When the slave device detects a change in the current pin state of the SS signal line, the slave device changes the current level state of the SST signal line. In this embodiment of the invention, the communication system refers to a hardware communication architecture consisting of three core components: a host, a slave, and a five-wire SPI bus. It is specifically designed to enable bidirectional, synchronous data transmission between the host and the slave with adaptive data frame length.

[0033] In the SPI communication architecture, the master is the initiator and controller of communication, responsible for leading the timing and command issuance of the entire communication process. It is the core control node of the communication link. Furthermore, the master's core control role is also reflected in providing a synchronization clock (SCK) signal. The timing rhythm (such as transmission rate, clock polarity / phase) is determined by the master, and the slave must strictly synchronize with this clock to complete data sampling and transmission. Simultaneously, the master can also issue data frame length configuration commands to achieve state synchronization with the slave. The slave is the responder and executor of communication, needing to complete data transmission and reception under the control of the master. It does not actively initiate communication itself, but only provides feedback to the master's commands, such as sending back acknowledgment data.

[0034] In practical applications, the SPI standard interface mainly includes four basic signal lines: SCK (Serial Clock), MOSI (Master Out Slave In), MISO (Master In Slave Out), and SS (Slave Select). However, the communication system in this embodiment of the invention uses a five-wire SPI communication method, which introduces an auxiliary signal line SST (Sync Signal for Transmission) on the basis of the SPI standard interface.

[0035] Among them, the SCK signal line is used to transmit clock signals; the MOSI signal line is used for the master to send data to the slave; the MISO signal line is used for the master to receive data returned by the slave; the SS signal line is used to select the target slave; and the SST signal line is used to synchronize the status of the master and slave.

[0036] State synchronization refers to the synchronization between the master and slave devices during the communication process, waiting for changes in the other's control pin signals to initiate communication. For example, if the master pulls the SS pin low, the slave is polling the state of that pin, waiting for the master to initiate a transmission; if the slave controls the level of the SST signal line, the master is also continuously polling the state of the SST signal line, waiting for the slave to be idle before sending data.

[0037] In some embodiments, prior to step S101, the method may further include: changing the current pin state of the SS signal line via the host.

[0038] In step S101, firstly, the master device pulls the pin of the SS signal line low to indicate that communication can begin; then, when the slave device detects a change in the current pin state of the SS signal line, the slave device notifies the master device that it is ready to receive data length information by controlling the level state change of the SST signal line (e.g., from high level to low level).

[0039] Step S102: When the host detects a change in the current level state of the SST signal line, it sends a synchronization frame of the first length to the slave. Optionally, the first length synchronization frame includes instruction data length information and instruction data verification information. The first length synchronization frame is a data frame used by the master to send data length information to the slave.

[0040] In step S102, when the host detects a change in the current level of the SST signal line (i.e., a change in the level of the SST signal line controlled by the slave in step S101, such as from high level to low level), the host sends a fixed-length synchronization frame to the slave through the MOSI signal line. This frame contains instruction data length information and instruction data verification information. For ease of distinction, the length synchronization frame in this step is called the first length synchronization frame.

[0041] It should be noted that the length of the data frame sent by the master to the slave, and the length of the data frame sent by the slave back by the master, can be synchronized to the other party according to the actual data length to be transmitted. The master will send the corresponding number of SCK clocks according to the amount of data sent or received. The data length value in the synchronization frame can be changed during the communication process.

[0042] Step S103: The slave device verifies whether the first length synchronization frame is valid. If the slave device determines that the first length synchronization frame is valid, the slave device changes the current level state of the SST signal line. In some embodiments, step S103 may include: extracting instruction data length information and instruction data verification information from the first length synchronization frame by the slave device; performing validity verification on the instruction data length information by the slave device based on the instruction data verification information; determining that the first length synchronization frame is valid if the instruction data length information passes the validity verification; and changing the current level state of the SST signal line by the slave device if the slave device determines that the first length synchronization frame is valid.

[0043] In step S103, after the slave device receives the first length synchronization frame sent by the master device, it first verifies the validity of the first length synchronization frame. If the first length synchronization frame is valid, the slave device notifies the master device that it is ready to receive data by controlling the state change of the SST signal line (such as changing from low level to high level).

[0044] Step S104: When the host detects a change in the current level state of the SST signal line, it sends instruction data to the slave. Instruction data refers to control information sent by the master to the slave to instruct the slave to perform specific operations.

[0045] In step S104, after the host detects a change in the state of the SST signal line, it initiates the data transmission process, that is, it sends the negotiated (host synchronization) number of SCK clocks and transmits instruction data to the slave.

[0046] Step S105: After the slave device executes the instruction data and generates response data, the current level state of the SST signal line is changed by the slave device. The response data is status / result information fed back to the host by the slave device after receiving and executing the instruction data issued by the host.

[0047] In step S105, after the slave device receives the instruction data sent by the master device, it stores the instruction data in the buffer. Then, the slave device executes the instruction data and generates response data. After the slave device executes the instruction data and generates response data, it notifies the master device to read back the length information of the response data by controlling the state change of the SST signal line (such as changing from high level to low level).

[0048] Step S106: When the host detects a change in the current level of the SST signal line, the host initiates a response data readback process based on the valid response data length and the change in the SST signal line to receive the response data sent by the slave device.

[0049] In some embodiments, step S106 may include: after the slave device generates response data, if the master device detects a change in the current level state of the SST signal line, the master device sends a second-length synchronization frame to the slave device and obtains the response data length information sent by the slave device based on the second-length synchronization frame; after the master device obtains the response data length information, the master device verifies whether the response data length in the response data length information is valid; if the master device determines that the response data length is valid and the master device detects a change in the current level state of the SST signal line, the master device receives the response data according to the response data frame length.

[0050] The second-length synchronization frame is a data frame used by the master to obtain the data length information from the slave. It should be noted that SPI is a full-duplex communication system; simultaneously, the master sends the second-length synchronization frame to the slave and can receive the response data length information sent by the slave via the MISO signal line.

[0051] Optionally, the response data length information includes the response data length and response data verification information.

[0052] In some specific embodiments, after the host obtains the response data length information, the step of verifying whether the response data length in the response data length information is valid may include: extracting the response data length and response data verification information from the response data length information by the host; and verifying the validity of the response data length by the host based on the response data verification information.

[0053] In some specific embodiments, if the host determines that the response data length is valid and the host detects a change in the current level state of the SST signal line, the step of receiving response data according to the response data frame length may include: if the host determines that the response data length is valid and the host detects a change in the current level state of the SST signal line, then receiving the response data frame sent by the slave according to the response data length; and obtaining the response data by parsing the response data frame through the host.

[0054] In step S106, after the slave device generates response data and controls the state change of the SST signal line (e.g., from high level to low level), when the master device detects the state change of the SST signal line, it pulls the SS signal line pin low and sends a fixed-length synchronization frame (i.e., a second-length synchronization frame) to the slave device. The second-length synchronization frame is used to read back the response data length and response data verification information provided by the slave device. After receiving the second-length synchronization frame, the slave device completes the response data preparation and notifies the master device to read back the response data and waits for the master device to read back by controlling the state change of the SST signal line (e.g., from low level to high level). At the same time as the master device sends the second-length synchronization frame to the slave device, it receives the response data length information sent by the slave device through the MISO signal line. After the master receives the response data length information sent by the slave, it first verifies the validity of the response data length in the information. If the master verifies that the response data length is valid, it acquires the valid response data length. Furthermore, when the master detects a change in the state of the SST signal line again, it initiates the response data readback process through SPI communication, sending the negotiated (slave synchronization) number of SCK clocks to the slave, so that the slave sends a response data frame of length N (N = response data length) to the master through the MISO signal line according to the negotiated (slave synchronization) number of SCK clocks. Then, the master receives the response data frame sent by the slave to extract the corresponding response data. Finally, the master stores the received response data in its local buffer.

[0055] In steps S101 to S106 of this embodiment of the invention, when the slave device detects a change in the current pin state of the SS signal line, it changes the current level state of the SST signal line; when the master device detects a change in the current level state of the SST signal line, it sends a first-length synchronization frame to the slave device; the slave device verifies whether the first-length synchronization frame is valid, and if the slave device determines that the first-length synchronization frame is valid, it changes the current level state of the SST signal line; when the master device detects a change in the current level state of the SST signal line, it sends instruction data to the slave device; after the slave device executes the instruction data and generates response data, it changes the current level state of the SST signal line; when the master device detects a change in the current level state of the SST signal line, it initiates a response data readback process based on the valid response data length and the change in the SST signal line to receive the response data sent by the slave device. This invention introduces a data length synchronization frame, allowing the communication data frame length to be dynamically adjusted according to actual needs, no longer limited to a fixed length, thus solving the frame length negotiation problem in traditional SPI communication. At the same time, based on the SPI standard interface, the introduction of the auxiliary signal SST ensures that the master and slave remain synchronized before and after data transmission, significantly improving the synchronization reliability between the master and slave, reducing the waiting time during data transmission, and also reducing the communication error rate.

[0056] To explain in detail the principle of the technical solution of the present invention, the overall process of the present invention will be described below with reference to some specific embodiments. It is easy to understand that the following is an explanation of the technical principle of the present invention and should not be regarded as a limitation of the present invention.

[0057] Please see Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of a host workflow provided in an embodiment of the present invention. Figure 3 A schematic diagram of a slave device's workflow is provided for an embodiment of the present invention, such as... Figure 2 and Figure 3 As shown in the figure, the specific implementation process of a bidirectional communication method based on the SPI bus provided by this embodiment of the invention is as follows: (1) Host sending instruction process: 1) Initialization phase: The master indicates the start of communication by pulling the pin of the SS signal line low; when the slave detects a change in the current pin state of the SS signal line, the slave notifies the master that it is ready to receive data length information by controlling the state change of the SST signal line (such as changing from high level to low level).

[0058] 2) Synchronization data length stage: The master sends a fixed-length synchronization frame (i.e., the first-length synchronization frame) to the slave via the MOSI signal line. This frame contains instruction data length information and instruction data verification information. After receiving the first-length synchronization frame, the slave first verifies and confirms the validity of the first-length synchronization frame. If the first-length synchronization frame is valid, the slave notifies the master that it is ready to receive data by controlling the state change of the SST signal line (e.g., from low level to high level).

[0059] It should be noted that during the data length synchronization phase, the host and slave devices perform a handshake interaction before data transmission using a fixed-length synchronization frame. This handshake process is a length negotiation process. This fixed-length synchronization frame is of the agreed length between the host and slave devices, and they can determine the data length for the next stage of transmission and reception through this synchronization frame. For example, the host can inform the slave device of how much data it needs to send through the first-length synchronization frame; or, the slave device can inform the host device of how much data it is waiting for the host to read back through the second-length synchronization frame.

[0060] 3) Data transmission phase: After the host detects the change in the state of the SST signal line, it starts the data transmission process, that is, it sends the negotiated (host synchronization) number of SCK clocks and transmits instruction data; the slave receives the instruction data and stores it in the buffer area, and then the slave executes the instruction and generates response data.

[0061] (2) The process of the master reading back (slave) response data: 1) Initialization phase: The readback process is initiated by the slave device. After the slave device executes the instruction, it generates response data and notifies the master device of the length information of the response data by controlling the state change of the SST signal line (such as changing from high level to low level).

[0062] 2) Synchronization Data Length Stage: After the master detects a change in the state of the SST signal line, it pulls the SS signal line pin low and sends a fixed-length synchronization frame (i.e., the second-length synchronization frame) to the slave. This second-length synchronization frame is used to read back the response data length information and response data verification information provided by the slave. After receiving the second-length synchronization frame, the slave prepares the response data and notifies the master to read back the response data by controlling the state change of the SST signal line (e.g., from low to high), and then waits for the master to read back.

[0063] It should be noted that the synchronization data length stage is a negotiation process between the slave and the master to synchronize the length information. In this process, the master sends a second-length synchronization frame to the slave and provides the SCK clock for the second-length synchronization frame. The slave does not need to perform verification of the second-length synchronization frame in this process. The slave only needs to prepare the response data after receiving the second-length synchronization frame and control the state change of the SST signal line, and wait for the master to read back.

[0064] 3) Data readback stage: While the master sends a second-length synchronization frame to the slave, it receives the response data length information sent by the slave via the MISO signal line. After receiving the response data length information from the slave, the master first verifies the validity of the response data length. If the master verifies that the response data length is valid, when the master detects a change in the state of the SST signal line again, it initiates the response data readback process, sending an SCK clock of the negotiated (slave synchronization) number to the slave, so that the slave sends a response data frame of length N to the master via the MISO signal line. Then, the master receives the response data frame sent by the slave to extract the corresponding response data. Finally, the master stores the received response data in its local buffer.

[0065] For example, suppose the master sends a command (0xA001, 0x0001) to the slave to obtain the slave's software version information (0x0000, 0x07E9, 0x0009, 0x0002, 0x12D4, 0x1B62, 0x2000, 0x0000). In this scenario, the workflows of the master and slave are as follows: (1) Host workflow: 1) Initialization: The host pulls the chip select signal line SS high; 2) The host pulls the chip select signal line SS low to initiate a communication process; 3) When the slave device is detected to be pulling low on the synchronization SST signal line, the master device sends a length synchronization frame (e.g., 6 bytes, containing parameter checksum prmChecksum1, instruction length dataLen1, and data checksum dataChecksum1, where data checksum1 = 0xA001 + 0x0001 + dataLen1, and parameter checksum prmChecksum1 = ~(dataChecksum1 + dataLen1), i.e., 0x5FF9, 0x0002, 0xA004) to the slave device via the MOSI signal line. 4) When the slave device pulls the SST signal line high, a command data frame (0xA001, 0x0001) is sent to the slave device through the MOSI signal line. 5) When the slave device pulls the SST signal line low, the master device receives the response data length information (e.g., 6 bytes, including parameter checksum prmChecksum2, data length dataLen2, and data checksum2) sent by the slave device through the MISO signal line. After the master device receives the response data length information sent by the slave device, the master device first verifies the validity of the response data length dataLen2 in the response data length information. If the verification confirms that the response data length dataLen2 is valid, the master device obtains the response data length dataLen2 = 0x0008 for this time. 6) When the slave device pulls the SST signal line high, the master device receives the response data frame sent by the slave device through the MISO signal line according to the data length value dataLen2 sent by the slave device, and obtains the software version data (0x0000,0x07E9,0x0009,0x0002, 0x12D4,0x1B62,0x2000,0x0000) sent by the slave device from the response data frame.

[0066] 7) The communication process ends.

[0067] (2) Slave machine workflow: 1) Initialization: The slave device pulls the SST signal line high to synchronize the signal level; 2) Wait for the host to pull the chip select signal line SS low; 3) When the master pulls the chip select signal line SS low, the slave pulls the state synchronization SST signal line low to notify the master that it is ready to receive data length information. Then, it receives the length synchronization frame sent by the master through the MOSI signal line (e.g., 6 bytes, including the receive parameter checksum prmChecksum1, the instruction length dataLen1, and the data checksum dataChecksum1). After the synchronization frame is verified, the instruction length dataLen1 = 0x0002 transmitted by the master is obtained. 4) After verifying the validity of the synchronization frame, the slave device pulls the level of the state synchronization SST signal line high to notify the master device that it is ready to receive data. It receives the instruction data frame (0xA001, 0x0001) sent by the master device through the MOSI signal line and executes the instruction. At the same time, it prepares the software version data (0x0000, 0x07E9, 0x0009, 0x0002, 0x12D4, 0x1B62, 0x2000, 0x0000). 5) The slave device actively pulls down the SST status synchronization signal line to notify the master device to read back the length information of the response data. It then sends the response data length information (6 bytes, including parameter checksum prmChecksum2, data length dataLen2, and data checksum2) via the MISO signal line. Here, dataChecksum2 = 0x0000+0x07E9+0x0009 + 0x0002 + 0x12D4 + 0x1B62 + 0x2000 + 0x0000 + dataLen2, prmChecksum2 = ~(dataChecksum2 + dataLen2), i.e., 0xA9C5, 0x0008. 0x5632) to the host; it should be noted that after the host obtains the response data length information sent by the slave, the host first verifies the validity of the response data length dataLen2 in the response data length information. If the verification confirms that the response data length dataLen2 is valid, the host will start the response data readback process when it detects a change in the state of the SST signal line again. 6) The slave device pulls the SST signal line high to notify the master device that it can read the response data (i.e., software version data). It sends a response data frame of length dataLen2 to the master device through the MISO signal line. The response data frame contains the software version data (0x0000, 0x07E9, 0x0009, 0x0002, 0x12D4, 0x1B62, 0x2000, 0x0000). 7) The communication process ends.

[0068] It should be noted that this embodiment is only a brief illustrative description of the overall process of a bidirectional communication method based on the SPI bus. Detailed descriptions of each step can be found in the relevant content of the foregoing embodiments, and will not be repeated here. It is understood that the present invention does not limit this.

[0069] This invention is applied to a communication system, which includes a master and a slave. The SPI bus includes an SS signal line and an SST signal line. When the slave detects a change in the current pin state of the SS signal line, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it sends a first-length synchronization frame to the slave. The slave verifies the validity of the first-length synchronization frame. If the slave determines that the first-length synchronization frame is valid, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it sends instruction data to the slave. After the slave executes the instruction data and generates response data, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it initiates a response data readback process based on the valid response data length and the change in the SST signal line to receive the response data sent by the slave. This invention introduces a data length synchronization frame, allowing the communication data frame length to be dynamically adjusted according to actual needs, no longer limited to a fixed length, thus solving the frame length negotiation problem in traditional SPI communication. At the same time, based on the SPI standard interface, the introduction of the auxiliary signal SST ensures that the master and slave remain synchronized before and after data transmission, significantly improving the synchronization reliability between the master and slave, reducing the waiting time during data transmission, and also reducing the communication error rate.

[0070] The key point of the bidirectional communication method based on the SPI bus provided in this embodiment of the invention is as follows: (1) Dynamically adjust the length of the data frame: By introducing a data length synchronization frame, the length of the communication data frame can be dynamically adjusted according to actual needs, and is no longer limited to a fixed length.

[0071] Its core technical points are: 1) using synchronization frames to transmit data length information and check information; 2) allowing the host and slave to negotiate and determine the specific length of the data frame during the communication process.

[0072] (2) The function of auxiliary signal SST: Based on the SPI standard interface (SCK, MOSI, MISO, SS), auxiliary signal SST is introduced to ensure that the master and slave remain synchronized before and after data transmission.

[0073] Its core technical points are: 1) defining the state changes of the SST signal (such as high and low level switching) as an indication signal of the communication state; 2) clarifying the specific uses of the SST signal in each stage of communication, such as initialization, synchronization of data length, data transmission / readback, etc.

[0074] (3) Two-way communication mechanism: realizes the two-way communication function of sending command data from the master to the slave and reading data back from the slave to the master.

[0075] Its core technical points are: 1) The master transmission process includes three stages: initialization, data length synchronization, and data transmission; 2) The master readback (slave transmission) process includes three stages: initialization, data length synchronization, and data readback; 3) In each stage, the interaction process and signal control rules between the master and slave are clearly defined.

[0076] In summary, the bidirectional communication method based on the SPI bus provided by this invention can be widely applied in the field of data communication technology, especially in the field of embedded communication. This invention relates to an improvement on bidirectional communication based on the SPI (Serial Peripheral Interface) bus and its synchronization mechanism. Specifically, this invention introduces a data length synchronization frame into the SPI communication process, achieving a variable data frame length. An auxiliary signal SST is introduced in hardware to ensure that the master and slave devices remain synchronized before and after data transmission. This scheme can adapt to different data length requirements and improve synchronization efficiency. It is suitable for scenarios where the master and slave devices need to dynamically adjust the length of transmitted and received data and achieve efficient synchronization.

[0077] This invention solves the frame length negotiation problem in traditional SPI communication and significantly improves the synchronization reliability between the master and slave devices by introducing an auxiliary signal SST. Compared with existing related technologies, this invention has the following advantages: (1) Dynamically negotiate data frame length to adapt to various application scenarios; (2) No additional protocol layer is required, simplifying system design; (3) The efficient synchronization mechanism reduces the waiting time in data transmission and lowers the communication error rate.

[0078] Please see Figure 4 This invention also provides a bidirectional communication device 400 based on an SPI bus, applied to a communication system. The communication system includes a master and a slave device. The SPI bus includes SS signal lines and SST signal lines, which can implement the above-described method. The device includes the following modules: Slave communication preparation module 401 is used to change the current level state of the SST signal line when the slave detects a change in the current pin state of the SS signal line. The length synchronization frame sending module 402 is used to send a first length synchronization frame to the slave when the host detects a change in the current level state of the SST signal line; The length synchronization frame verification module 403 is used to verify whether the first length synchronization frame is valid through the slave device. If the slave device determines that the first length synchronization frame is valid, the slave device changes the current level state of the SST signal line. The instruction data transmission module 404 is used to send instruction data to the slave device when the host detects a change in the current level state of the SST signal line; The response data generation module 405 is used to change the current level state of the SST signal line through the slave device after the slave device executes the instruction data and generates response data; The response data readback module 406 is used to initiate the response data readback process when the host detects a change in the current level state of the SST signal line, so as to receive the response data sent by the slave device.

[0079] It is understood that the content of the above method embodiments is applicable to the present device embodiments. The specific functions implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0080] This invention also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method described above. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0081] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0082] Please see Figure 5 , Figure 5 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 501 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present invention. The memory 502 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 502 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 502 and is called and executed by the processor 501 to execute the methods described above in the embodiments of this invention. The input / output interface 503 is used to implement information input and output; The communication interface 504 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 505 transmits information between various components of the device (e.g., processor 501, memory 502, input / output interface 503, and communication interface 504); The processor 501, memory 502, input / output interface 503, and communication interface 504 are connected to each other within the device via bus 505.

[0083] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0084] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0085] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0086] It is understood that the content of the above method embodiments is applicable to the embodiments of this program product. The specific functions implemented by the embodiments of this program product are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0087] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0088] This invention provides a bidirectional communication method and related device based on an SPI bus, applied to a communication system. The communication system includes a master and a slave. The SPI bus includes an SS signal line and an SST signal line. When the slave detects a change in the current pin state of the SS signal line, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it sends a first-length synchronization frame to the slave. The slave verifies the validity of the first-length synchronization frame. If the slave determines that the first-length synchronization frame is valid, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it sends instruction data to the slave. After the slave executes the instruction data and generates response data, it changes the current level state of the SST signal line. When the master detects a change in the current level state of the SST signal line, it initiates a response data readback process based on the valid response data length and the change in the SST signal line to receive the response data sent by the slave. This invention introduces a data length synchronization frame, allowing the communication data frame length to be dynamically adjusted according to actual needs, no longer limited to a fixed length, thus solving the frame length negotiation problem in traditional SPI communication. At the same time, based on the SPI standard interface, the introduction of the auxiliary signal SST ensures that the master and slave remain synchronized before and after data transmission, significantly improving the synchronization reliability between the master and slave, reducing the waiting time during data transmission, and also reducing the communication error rate.

[0089] The embodiments described in this invention are for the purpose of more clearly illustrating the technical solutions of the embodiments of this invention, and do not constitute a limitation on the technical solutions provided by the embodiments of this invention. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this invention are also applicable to similar technical problems.

[0090] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present invention, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0091] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0092] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0093] The terms "first," "second," "third," "fourth," etc. (if present) in the specification and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0094] It should be understood that in this invention, "at least one (item)" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0095] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0096] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0097] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0098] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0099] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments, and various changes can be made within the scope of knowledge possessed by those skilled in the art without departing from the spirit of the present invention. Furthermore, the embodiments of the present invention and the features thereof can be combined with each other unless otherwise specified.

Claims

1. A bidirectional communication method based on an SPI bus, characterized in that, The method is applied to a communication system, which includes a master and a slave, and the SPI bus includes SS signal lines and SST signal lines. The method includes the following steps: When the slave device detects a change in the current pin state of the SS signal line, it changes the current level state of the SST signal line via the slave device. When the host detects a change in the current level state of the SST signal line, it sends a synchronization frame of the first length to the slave. The slave device verifies whether the first length synchronization frame is valid. If the slave device determines that the first length synchronization frame is valid, the slave device changes the current level state of the SST signal line. When the host detects a change in the current level of the SST signal line, it sends instruction data to the slave. After the slave device executes the instruction data and generates response data, the current level state of the SST signal line is changed by the slave device. When the host detects a change in the current level of the SST signal line, it initiates a response data readback process based on the valid response data length and the change in the SST signal line to receive the response data sent by the slave device.

2. The bidirectional communication method based on SPI bus according to claim 1, characterized in that, When the host detects a change in the current level of the SST signal line, it initiates a response data readback process based on the valid response data length and the change in the SST signal line to receive the response data sent by the slave device, including: After the slave device generates the response data, if the master device detects a change in the current level state of the SST signal line, it sends a second-length synchronization frame to the slave device and obtains the length information of the response data sent by the slave device based on the second-length synchronization frame. After the host obtains the response data length information, the host verifies whether the response data length in the response data length information is valid. If the host determines that the response data length is valid and the host detects a change in the current level state of the SST signal line, then the host receives the response data according to the response data frame length.

3. The bidirectional communication method based on SPI bus according to claim 2, characterized in that, The response data length information includes the response data length and response data verification information. The step of verifying the validity of the response data length in the response data length information after the host obtains the response data length information includes: The host extracts the response data length and the response data verification information from the response data length information. The host verifies the validity of the response data length based on the response data verification information.

4. The bidirectional communication method based on SPI bus according to claim 2, characterized in that, If the host determines that the response data length is valid and the host detects a change in the current level state of the SST signal line, then receiving the response data according to the response data frame length includes: If the host determines that the response data length is valid and the host detects that the current level state of the SST signal line has changed, then the host receives the response data frame sent by the slave according to the response data length. The host performs data parsing on the response data frame to obtain the response data.

5. The bidirectional communication method based on SPI bus according to claim 1, characterized in that, The first length synchronization frame includes instruction data length information and instruction data verification information. The step of verifying the validity of the first length synchronization frame by the slave device, and if the slave device determines that the first length synchronization frame is valid, then changing the current level state of the SST signal line by the slave device includes: The slave device extracts the instruction data length information and the instruction data verification information from the first length synchronization frame. The slave device performs a validity check on the instruction data length information based on the instruction data verification information. If the instruction data length information passes the validity check, then the first length synchronization frame is determined to be valid; If the slave device determines that the first length synchronization frame is valid, then the slave device changes the current level state of the SST signal line.

6. The bidirectional communication method based on SPI bus according to claim 1, characterized in that, Before the slave device changes the current level state of the SST signal line when it detects a change in the current pin state of the SS signal line, the method further includes: The host computer can change the current pin state of the SS signal line.

7. A bidirectional communication device based on an SPI bus, characterized in that, Applied to a communication system, the communication system including a master and a slave, the SPI bus including SS signal lines and SST signal lines, the device includes the following modules: The slave communication preparation module is used to change the current level state of the SST signal line when the slave detects a change in the current pin state of the SS signal line. The length synchronization frame sending module is used to send a first length synchronization frame to the slave when the host detects a change in the current level state of the SST signal line; The length synchronization frame verification module is used to verify whether the first length synchronization frame is valid through the slave device. If the slave device determines that the first length synchronization frame is valid, the current level state of the SST signal line is changed through the slave device. The instruction data transmission module is used to send instruction data to the slave device when the host detects a change in the current level state of the SST signal line; The response data generation module is used to change the current level state of the SST signal line through the slave device after the slave device executes the instruction data and generates response data; The response data readback module is used to receive the response data sent by the slave device when the host detects a change in the current level state of the SST signal line. This is achieved by the host initiating a response data readback process based on the valid response data length and the change in the SST signal line.

8. An electronic device, characterized in that, The electronic device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements a bidirectional communication method based on an SPI bus as described in any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements a bidirectional communication method based on the SPI bus according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements a bidirectional communication method based on the SPI bus according to any one of claims 1 to 6.

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