Artificial intelligence chip and operating method thereof

Abstract

The application relates to an artificial intelligence chip and an operation method thereof. Based on the application, a multi-channel transmitter of the artificial intelligence chip can only be provided with a loading signal generator for generating a loading signal based on a clock signal in a transmitter common circuit, and a serializer of each transmitter channel circuit can output serialized parallel input channel data for being sent through a corresponding physical channel of a multi-channel bus based on the clock signal and the loading signal received from the transmitter common circuit. Therefore, the serializers of the plurality of transmitter channel circuits do not need to be provided with the loading signal generator, and the serialized output of the parallel input channel data can be completed by using the loading signal. Compared with the related art in which the serializers of each transmitter channel circuit are all provided with the loading signal generator, the circuit area and the circuit power consumption of the multi-channel transmitter can be reduced by reducing the loading signal generator.

Description

Technical Field

[0001] This application relates to the field of AI (Artificial Intelligence) chips, and in particular to an AI chip and a method of operating the AI ​​chip. Background Technology

[0002] AI chips can achieve data transmission based on a multi-channel bus, and the multiple physical channels (lanes) of the multi-channel bus can transmit channel data independently of each other. Accordingly, the AI ​​chip may include a multi-channel transmitter, and the multi-channel transmitter of the AI ​​chip may include multiple transmitter channel circuits, each corresponding to one of the multiple physical channels of the multi-channel bus. Therefore, the circuit area and power consumption of the multi-channel transmitter of the AI ​​chip are directly proportional to the number of physical channels of the multi-channel bus, resulting in a relatively high overall circuit area and overall power consumption of the AI ​​chip.

[0003] Therefore, how to reduce the circuit area and power consumption of multi-channel transmitters for AI chips has become a technical problem that needs to be solved in related technologies.

[0004] It is understood that the content of the "Background Art" section is intended to aid in understanding this disclosure. Some (or all) of the content disclosed in the "Background Art" section may not be known to those skilled in the art. The content disclosed in the "Background Art" section does not imply that such content was known to those skilled in the art prior to this disclosure. Summary of the Invention

[0005] Embodiments of this application provide an AI chip and an operating method for the AI ​​chip, which helps to reduce the circuit area and power consumption of a multi-channel transmitter.

[0006] In one embodiment of this application, an AI chip includes a multi-channel transmitter for transmitting data via a multi-channel bus. The multi-channel transmitter includes a transmitter common (tx common) circuit and multiple transmitter lane (tx lane) circuits corresponding to multiple physical channels of the multi-channel bus.

[0007] The transmitter common circuit includes a clock source and a load generator, the clock source being configured to generate a clock signal, and the load generator being configured to generate a load signal based on the clock signal.

[0008] Each of the transmitter channel circuits includes a serializer, and the serializer of each of the transmitter channel circuits is configured to serialize and output channel data that is input in parallel and is intended to be transmitted through the corresponding physical channel based on the clock signal and the load signal received from the transmitter common circuit.

[0009] In some examples, optionally, each of the transmitter channel circuits further includes a channel clock path, and the clock signal reaches the serializer via the channel clock path in each of the transmitter channel circuits; the transmitter common circuit further includes a delay compensation path; wherein the delay compensation path is configured to give the load signal a delay compensation that matches the channel transmission delay of the clock signal in each of the transmitter channel circuits due to the channel clock path.

[0010] In some examples, optionally, the delay compensation path is located between the clock source and the load signal generator, and the delay compensation path is specifically configured to generate the delay compensation for the clock signal transmitted from the clock source to the load signal generator in the transmitter common circuit, so that the load signal generated by the load signal generator has the delay compensation; the clock signal of each transmitter channel circuit reaching the serializer via the channel clock path bypasses the delay compensation path in the transmitter common circuit.

[0011] In some examples, the serializer optionally includes a shift register that includes a plurality of flip-flops; the load signal is used to control the cascading state among the plurality of flip-flops to trigger the parallel input channel data to be loaded in parallel to the plurality of flip-flops and then serialized and output by shifting in the cascading direction of the plurality of flip-flops.

[0012] In some examples, optionally, when the cascading state between the plurality of said triggers is set to disconnect by the load signal, the channel data input in parallel is loaded in parallel to the plurality of said triggers; when the cascading state between the plurality of said triggers is set to connect by the load signal, the channel data that has been loaded is serialized and output from the serializer by shifting in the cascading direction of the plurality of said triggers.

[0013] In some examples, optionally, the channel data is shifted in the loading of the plurality of flip-flops and in the cascading direction of the plurality of flip-flops by the flip-flops based on the toggling of the clock signal, the delay compensation being configured to match the timing relationship between the loading signal and the clock signal to the toggling association parameter of the flip-flops, and the toggling association parameter including the setup time (T) of the flip-flops. su Threshold and Hold Time (T) hd Threshold.

[0014] In some examples, optionally, the serializer of each of the transmitter channel circuits further includes a clock shaping buffer and a signal shaping buffer, wherein: the clock shaping buffer is configured such that the clock signal transmitted to the serializer is subjected to the single-path load level of beamforming correction before reaching the shift serializer, and the load signal is subjected to the single-path load level of beamforming correction before reaching the shift register.

[0015] In some examples, the delay compensation is optionally configured to ensure that the timing relationship between the load signal and the clock signal satisfies the following: the actual setup time of the trigger for the channel data is greater than the setup time threshold; and the actual hold time of the trigger for the channel data is greater than the hold time threshold.

[0016] In some examples, the actual setup time and the actual hold time may optionally be associated with the channel transmission delay of the clock signal, the delay compensation of the load signal, and the load delay generated by the parallel loading process of the channel data to multiple triggers.

[0017] In some examples, optionally, the actual setup time SU_margin = 2UI + Delay_clk - Delay_load - Delay_trans; the actual hold time HD_margin = Delay_load + Delay_trans - Delay_clk; where 2UI represents one signal period of the clock signal, Delay_clk represents the channel transmission delay of the clock signal, Delay_load represents the delay compensation of the load signal, and Delay_trans represents the loading delay generated by the parallel loading process of the channel data to multiple triggers.

[0018] In some examples, the transmitter common circuit may optionally include a drive buffer; wherein the drive buffer is configured to enable the signal load of the clock signal and the signal load of the load signal (e.g., the load signal with the delay compensation) to be boosted to a multi-path load level matching the multiple transmitter channel circuits, and then split into single-path load levels for transmission to the multiple transmitter channel circuits.

[0019] In some examples, the drive buffer may optionally include a clock drive buffer and a signal drive buffer, wherein: the clock drive buffer is configured to make the signal load of the clock signal reach the multiplexing load level matching the multiple transmitter channel circuits; and the signal drive buffer is configured to make the signal load of the loaded signal reach the multiplexing load level matching the multiple transmitter channel circuits.

[0020] In some examples, optionally, the load signal of the clock signal generated by the clock source has a signal load at the single-channel load level, and the clock drive buffer is configured to increase the signal load of the clock signal generated by the clock source from the single-channel load level to the multi-channel load level matching the plurality of transmitter channel circuits; the load signal generated by the load signal generator has a signal load at the single-channel load level, and the signal drive buffer is specifically configured to increase the signal load of the load signal generated by the load signal generator from the single-channel load level to the multi-channel load level matching the plurality of transmitter channel circuits.

[0021] In some examples, optionally, at least one of the clock-driven buffer and the signal-driven buffer includes a multi-stage inverter with progressively increasing size.

[0022] In some examples, the size of the multi-stage inverter may optionally increase by an equal multiple at each stage.

[0023] In some examples, optionally, the serializer of each of the transmitter channel circuits serializes the parallel-input channel data by serializing the odd-numbered bits and even-numbered bits of the channel data, respectively.

[0024] In some examples, the serializer optionally includes a shift register comprising two sets of flip-flops corresponding to odd and even bits, respectively; the load signal is used to control the intra-group cascading state between the two sets of flip-flops, so that the odd and even bits of the channel data are loaded in parallel to the two sets of flip-flops and then serialized and output by shifting in the cascading direction of the flip-flops in the corresponding groups.

[0025] In some examples, optionally, when the intra-group cascading state of both sets of the flip-flops is set to disconnect by the load signal, the odd and even bits of the parallel-input channel data are loaded in parallel to the two sets of the flip-flops respectively; when the intra-group cascading state of the two sets of the flip-flops is set to connect by the load signal, the odd and even bits of the loaded channel data are serialized and output from the serializer by shifting in the cascading direction of the flip-flops in the corresponding sets respectively.

[0026] In some examples, optionally, the odd and even bits of the channel data are shifted in the loading of the corresponding group of flip-flops and in the cascading direction of the corresponding group of flip-flops, respectively, by the flip-flops based on the toggling of the clock signal. The delay compensation is configured to match the timing relationship between the loading signal and the clock signal with the toggling association parameter of the flip-flops, and the toggling association parameter includes the setup time threshold and the hold time threshold of the flip-flops.

[0027] In some examples, each of the transmitter channel circuits may optionally include a pre-driver circuit and a final driver circuit, wherein: the pre-driver circuit is configured to alternately generate control codes using odd and even bits of the separately serialized output of the channel data; and the final driver circuit is configured to serially transmit the level signal corresponding to the channel data in the physical channel corresponding to the control code in the multi-channel bus.

[0028] In another embodiment of this application, an operating method for an AI chip is provided. The AI ​​chip includes a multi-channel transmitter for transmitting data via a multi-channel bus. The multi-channel transmitter includes a transmitter common circuit and multiple transmitter channel circuits corresponding to multiple physical channels of the multi-channel bus. The operating method includes:

[0029] A clock signal is generated by the clock source of the transmitter common circuit, and a load signal is generated by the load signal generator of the transmitter common circuit based on the clock signal;

[0030] The serializer of each of the transmitter channel circuits serializes the parallel-input channel data for transmission through the corresponding physical channel based on the clock signal and the load signal received from the transmitter common circuit.

[0031] In some examples, optionally, each of the transmitter channel circuits further includes a channel clock path, and the clock signal reaches the serializer via the channel clock path in each of the transmitter channel circuits; the transmitter common circuit further includes a delay compensation path, and the method of operation further includes: using the delay compensation path to give the load signal a delay compensation that matches the channel transmission delay of the clock signal in each of the transmitter channel circuits due to the channel clock path.

[0032] Optionally, in some examples, utilizing the delay compensation path to give the load signal a delay compensation that matches the channel transmission delay of the clock signal in each of the transmitter channel circuits due to the channel clock path includes: using the delay compensation path to generate the delay compensation for the clock signal transmitted from the clock source to the load signal generator in the transmitter common circuit, so that the load signal generated by the load signal generator has the delay compensation; wherein the clock signal arriving at the serializer via the channel clock path in each of the transmitter channel circuits bypasses the delay compensation path in the transmitter common circuit.

[0033] In some examples, optionally, the serializer includes a shift register comprising a plurality of flip-flops; the load signal is used to control the cascading state among the plurality of flip-flops to trigger the parallel input channel data to be loaded in parallel to the plurality of flip-flops and then serialized and output by shifting in the cascading direction of the plurality of flip-flops; wherein the loading of the channel data in the plurality of flip-flops and the shifting in the cascading direction of the plurality of flip-flops are achieved by the flip-flops based on the toggling of the clock signal, the delay compensation is configured to match the timing relationship between the load signal and the clock signal to the toggling association parameters of the flip-flops, and the toggling association parameters include the setup time threshold and the hold time threshold of the flip-flops.

[0034] In some examples, optionally, the serializer of each of the transmitter channel circuits further includes a clock shaping buffer and a signal shaping buffer, and the operation method further includes: using the clock shaping buffer to cause the clock signal transmitted to the serializer to be beam-shaped at the single-channel load level before reaching the shift register; and using the signal shaping buffer to cause the load signal transmitted to the serializer to be beam-shaped at the single-channel load level before reaching the shift register.

[0035] In some examples, the transmitter common circuit may optionally include a drive buffer, and the operation method may further include: using the drive buffer to boost the signal load of the clock signal and the signal load of the load signal (e.g., the load signal with the delay compensation) to a multi-channel load level matching the multiple transmitter channel circuits, and then transmitting the signal loads split into single-channel load levels to the multiple transmitter channel circuits.

[0036] In some examples, optionally, the drive buffer includes a clock drive buffer and a signal drive buffer, and the step of using the drive buffer to boost the signal load of the clock signal and the signal load of the load signal with the delay compensation to a multi-path load level matching the multiple transmitter channel circuits, and then transmitting the signal loads split into single-path load levels to the multiple transmitter channel circuits, includes: using the clock drive buffer to make the signal load of the clock signal reach the multi-path load level matching the multiple transmitter channel circuits; and using the signal drive buffer to make the signal load of the load signal reach the multi-path load level matching the multiple transmitter channel circuits.

[0037] In some examples, optionally, the loading signal of the clock signal generated by the clock source has the signal load of the single-channel load level, and the step of using the clock drive buffer to make the signal load of the clock signal reach the multi-channel load level matching the multiple transmitter channel circuits includes: using the clock drive buffer to increase the signal load of the clock signal generated by the clock source from the single-channel load level to the multi-channel load level matching the multiple transmitter channel circuits.

[0038] In some examples, optionally, the load signal generated by the load signal generator has a signal load at the single-channel load level, and the step of using the signal drive buffer to bring the signal load of the load signal to the multi-channel load level matching the multiple transmitter channel circuits includes: using the signal drive buffer to increase the signal load of the load signal generated by the load signal generator from the single-channel load level to the multi-channel load level matching the multiple transmitter channel circuits.

[0039] Based on the embodiments of this application, the multi-channel transmitter of the AI ​​chip can be equipped with a load signal generator only in the transmitter common circuit, and the serializers of multiple transmitter channel circuits do not need to be equipped with load signal generators. The serialization output of parallel input channel data can be completed using the load signal. Therefore, compared with related technologies that require a load signal generator in the serializer of each transmitter channel circuit, the circuit area and power consumption of the multi-channel transmitter can be reduced by reducing the number of load signal generators.

[0040] Furthermore, as an optional optimization, the multi-channel transmitter of the AI ​​chip can also additionally set up a redundant or dummy clock path in the transmitter common circuit as a delay compensation path. This allows the load signal generated by the load signal generator in the transmitter common circuit to have delay compensation, which matches the channel transmission delay of the clock signal in each transmitter channel circuit due to the channel clock path, thus avoiding timing errors when using load signals in multiple transmitter channel circuits. And / or, the transmitter common circuit of the multi-channel transmitter of the AI ​​chip can also include a drive buffer. The load signal generated by the load signal generator in the transmitter common circuit can be driven and buffered to a multi-channel load level matching multiple transmitter channel circuits, just like the clock signal, before being split into single-channel load levels and transmitted to multiple transmitter channel circuits. This avoids waveform abnormalities in the load signals used in multiple transmitter channel circuits due to insufficient signal load. Furthermore, by delay compensation and / or load boosting of the load signal, abnormalities in the serialized output quality of multiple transmitter channel circuits due to the reduction of load signal generators can be avoided. Attached Figure Description

[0041] The following figures are for illustrative purposes only and do not limit the scope of this application:

[0042] Figure 1 This is an exemplary structural diagram of a multi-channel transmitter for an AI chip according to an embodiment of this application;

[0043] Figure 2 This is a comparative example schematic diagram of a serializer for a multi-channel transmitter of an AI chip according to an embodiment of this application.

[0044] Figure 3 This is a schematic diagram of an example structure of the shift register in the serializer of the multi-channel transmitter of the AI ​​chip according to an embodiment of this application;

[0045] Figure 4 This is a schematic diagram of the optimized structure of the multi-channel transmitter of the AI ​​chip in the embodiments of this application;

[0046] Figure 5 This is a timing diagram of the multi-channel transmitter of the AI ​​chip in the embodiments of this application;

[0047] Figure 6 This is a schematic diagram of an improved structure of the serializer for the multi-channel transmitter of the AI ​​chip in an embodiment of this application;

[0048] Figure 7 This is a schematic diagram of an improved example structure of the shift register in the serializer of the multi-channel transmitter of the AI ​​chip according to an embodiment of this application.

[0049] Figure 8 This is an exemplary structural diagram of the pre-drive circuit and the final drive circuit of the multi-channel transmitter of the AI ​​chip in the embodiments of this application;

[0050] Figure 9 This is an exemplary flowchart illustrating the operation method of the AI ​​chip in the embodiments of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.

[0052] Figure 1 This is an exemplary structural diagram of a multi-channel transmitter for an AI chip according to an embodiment of this application. Please refer to... Figure 1 In the embodiments of this application, the multi-channel transmitter of the AI ​​chip can be used to transmit data through a multi-channel bus. The multi-channel transmitter used to transmit data through the multi-channel bus may include a transmitter common circuit 10 and multiple transmitter channel circuits 20 corresponding to multiple physical channels of the multi-channel bus.

[0053] Exemplary examples, in embodiments of this application, include, as Figure 1 The AI ​​chip in the multi-channel transmitter shown can be any integrated circuit chip suitable for AI, such as GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Units).

[0054] Exemplary examples, in embodiments of this application, such as Figure 1The multi-channel transmitter shown can utilize buses such as PCIE (Peripheral Component Interconnect Express), UCIE (Universal Chiplet Interconnect Express), and HBM (High Bandwidth Memory), which include multiple physical channels. Furthermore, data transmission via this multi-channel bus can involve either off-chip or on-chip data transfer. For example, the PCIE bus in the multi-channel bus can be used to implement off-chip data transfer between the AI ​​chip and other integrated circuit chips. As another example, for an AI chip packaged with at least two dies using Chiplet technology, the UCIE bus in the multi-channel bus can be used to implement on-chip data transfer between different dies, i.e., on-chip D2D (Die to Die) data transfer. Yet another example is the HBM bus in the multi-channel bus, which can be used to implement on-chip data transfer (or intra-die data transfer) between the SoC (System on Chip) within the AI ​​chip (or die) and other on-chip structures.

[0055] As an example, in embodiments of this application, the transmitter common circuit 10 can be used to provide a clock signal. For instance, the transmitter common circuit 10 may include a clock source for generating the clock signal.

[0056] For example, in an embodiment of this application, each transmitter channel circuit 20 may include a channel clock path 200, a serializer 210, a pre-driver circuit 220, and a final-stage driver circuit 230.

[0057] For example, in an embodiment of this application, the clock signal provided by the transmitter common circuit 10, after being transmitted to any transmitter channel circuit 20, can reach the serializer 210 of the transmitter channel circuit 20 via the channel clock path 200 of that transmitter channel circuit 20. The channel clock path 200 can be a local transmission network of the transmitter channel circuit 20. The clock signal may experience channel transmission delay in each transmitter channel circuit 20 due to transmission via the channel clock path 200. Furthermore, the embodiments of this application do not impose unnecessary limitations on the channel clock path 200.

[0058] For example, in an embodiment of this application, the serializer 210 of each transmitter channel circuit 20 is configured to serialize the channel data input in parallel for transmission through the physical channel corresponding to the transmitter channel circuit 20, and the clock signal transmitted to the serializer 210 is used to control the frequency of the serialized output channel data.

[0059] For example, in an embodiment of this application, the pre-drive circuit 220 of each transmitter channel circuit 20 can be configured to generate a control code based on the channel data serialized and output by the serializer 210 of the transmitter channel circuit 20, and control the final-stage drive circuit 230 of the transmitter channel circuit 20 to serially transmit the level signal corresponding to the channel data on the corresponding physical channel in the multi-channel bus based on the generated control code. That is, the final-stage drive circuit 230 of each transmitter channel circuit 20 can be configured to serially transmit the level signal corresponding to the channel data on the corresponding physical channel in the multi-channel bus based on the control code generated by the pre-drive circuit 220 of the transmitter channel circuit 20.

[0060] For example, in embodiments of this application, the control codes generated by the pre-drive circuit 220 of each transmitter channel circuit 20 may optionally implement at least one of the rcal (impedance calibration) function and the eq (equalization) function. The rcal function is used to maintain the output impedance of the final-stage drive circuit 230 at a target impedance (e.g., 25Ω), and the eq function is used to ensure that the transition edge of the level signal generated by the final-stage drive circuit 230 in the corresponding physical channel has a peak. The peak of the transition edge is used to pre-compensate for the high-frequency component loss of the level signal in the physical channel.

[0061] Figure 2 This is a comparative example schematic diagram of the serializer of the multi-channel transmitter of the AI ​​chip in an embodiment of this application. Please refer to... Figure 2 In the embodiments of this application, the serializer 210 of each transmitter channel circuit 20 may include a shift register 215. The channel data of the physical channel corresponding to the transmitter channel circuit 20 may be loaded into the shift register 215 of the serializer 210 of the transmitter channel circuit 20. The loaded channel data may be serialized and output from the serializer 210 of the transmitter channel circuit 20 by shifting the shift register 215 of the serializer 210 of the transmitter channel circuit 20.

[0062] For example, in embodiments of this application, the loading of channel data into shift register 215 and the shifting of channel data after loading into shift register 215 can be controlled by a loading signal. That is, the serializer 210 of each transmitter channel circuit 20 can be configured to serialize the channel data input in parallel for transmission through the physical channel corresponding to the transmitter channel circuit 20 based on the received clock signal and loading signal.

[0063] Figure 3 This is a schematic diagram illustrating an example structure of the shift register in the serializer of the multi-channel transmitter of the AI ​​chip according to an embodiment of this application. Please refer to... Figure 3 In embodiments of this application, the shift register 215 of the serializer 210 of each transmitter channel circuit 20 may include multiple flip-flops ( Figure 3 (The following is a diagram illustrating the D flip-flop as an example).

[0064] For example, in an embodiment of this application, multiple flip-flops of the shift register 215 can be cascaded. Specifically, the multiple flip-flops of the shift register 215 can be cascaded by connecting the Q pin of the preceding flip-flop to the D pin of the following flip-flop via a multiplexer switch. In this case, each bit of the parallel input channel data can be connected to the D pin of the first-stage flip-flop and each multiplexer switch, and the clock signal can be connected to the CLK (clock) pin of each flip-flop of the shift register 215. Thus, the load signal can control the cascade state between the multiple flip-flops of the shift register 215 by controlling each multiplexer switch, so that the parallel input channel data is loaded in parallel to the multiple flip-flops and then serialized and output by shifting in the cascade direction of the multiple flip-flops.

[0065] For example, in an embodiment of this application, when the cascading state between multiple flip-flops of the shift register 215 is set to open by a load signal, that is, when the D pins of the flip-flops other than the first flip-flop receive the corresponding bits of the channel data, the parallel input channel data can be loaded into multiple flip-flops in parallel (i.e., the parallel loading of channel data into the shift register 215 is realized).

[0066] For example, in an embodiment of this application, when the cascaded state between multiple flip-flops in the shift register 215 is set to connected by the load signal, that is, when the D pins of the flip-flops other than the first flip-flop are turned on with the Q pins of the preceding flip-flops, the channel data that has been loaded can be serialized and output from the serializer by shifting in the cascaded direction of the multiple flip-flops (that is, shifting the loaded channel data in the shift register 215). Furthermore, the loading of the channel data in the multiple flip-flops and the shifting in the cascaded direction of the multiple flip-flops are achieved by the flipping of the multiple flip-flops based on the clock signal.

[0067] Exemplarily, in embodiments of this application, if as Figure 2 As shown, each transmitter channel circuit 20's serializer 210 includes a load signal generator 300 that generates a load signal based on a clock signal. Therefore, each transmitter channel circuit 20 will have its circuit area ΔS increased accordingly due to the load signal generator 300. load and circuit power consumption ΔP load Accordingly, for a multi-channel transmitter including M transmitter channel circuits 20, the increased overall circuit area and power consumption due to the addition of the signal generator 300 will reach M×ΔS respectively. load and M×ΔP load Therefore, embodiments of this application aim to reduce the corresponding increase in circuit area ΔS for each transmitter channel circuit 20 due to the inclusion of a load signal generator 300 in the serializer 210. load and circuit power consumption ΔP load This reduces the overall circuit area and power consumption of a multi-channel transmitter, which includes multiple transmitter channel circuits 20, due to the addition of the signal generator 300.

[0068] Figure 4 This is a schematic diagram of the optimized structure of the multi-channel transmitter of the AI ​​chip in this embodiment. Please refer to... Figure 4 In embodiments of this application, the transmitter common circuit 10 of the multi-channel transmitter may include, in addition to a clock source 100 configured to generate a clock signal, a load signal generator 300 configured to generate a load signal based on the clock signal. Furthermore, the serializer 210 of each transmitter channel circuit 20 may not include the load signal generator 300. In this case, embodiments of this application can reduce the circuit area and power consumption of the multi-channel transmitter by reducing the load signal generator 300. For example, for a multi-channel transmitter including M transmitter channel circuits 20, since the load signal generator 300 is only provided in the transmitter common circuit 10, the overall circuit area and power consumption of the multi-channel transmitter increased by the load signal generator 300 can be reduced to approximately ΔS. load and ΔP load That is, based on the embodiments of this application, the overall circuit area and circuit power consumption of the multi-channel transmitter are compared to... Figure 2 The reduction can reach approximately (M-1)×ΔS. load and (M-1)×ΔP load .

[0069] For example, in embodiments of this application, the improvement to the multi-channel transmitter is not simply a reduction in the number and a change in the position of the load signal generators 300 (i.e., replacing the multiple load signal generators 300 located in the serializers 210 of the multiple transmitter channel circuits 20 with a single load signal generator 300 located in the transmitter common circuit 10), but also includes additional improvements made as the number and position of the load signal generators 300 are reduced, which ensure that the normal operation of the multi-channel transmitter is not affected by the reduction in the number and the change in the position of the load signal generators 300.

[0070] For example, in an embodiment of this application, the transmitter common circuit 10 may further include a delay compensation path 350 and a drive buffer 400.

[0071] For example, in an embodiment of this application, the delay compensation path 350 of the transmitter common circuit 10 can be configured to give the loading signal a delay compensation that matches the channel transmission delay of the clock signal in each transmitter channel circuit 20 caused by the channel clock path 200. Similar to the channel clock path 200, the delay compensation path 350 can be a local transmission network of the transmitter common circuit 10, where the clock signal may experience transmission delay due to transmission via the delay compensation path 350. Furthermore, embodiments of this application do not impose unnecessary limitations on the channel clock path 200.

[0072] For example, in an embodiment of this application, the delay compensation path 350 of the transmitter common circuit 10 is not a network necessary for signal transmission in the transmitter common circuit 10. Therefore, the delay compensation path 350 can be regarded as a redundant or dummy clock path set up to create delay. Furthermore, the transmission delay of the clock signal in the transmitter common circuit 10 due to transmission through the delay compensation path 350 can trigger delay compensation of the load signal generated based on the clock signal. Since this delay compensation matches the channel transmission delay of the clock signal in each transmitter channel circuit 20 caused by the channel clock path 200, timing errors (such as timing errors affecting the flip-flop toggling of the shift register 215 of the serializer 210) can be avoided when the load signal is used in multiple transmitter channel circuits 20.

[0073] Exemplarily, in an embodiment of this application, the delay compensation path 350 of the transmitter common circuit 10 may be located between the clock source 100 and the load signal generator 300. Specifically, the delay compensation path 350 may be configured to provide delay compensation for the clock signal transmitted from the clock source 100 to the load signal generator 300 in the transmitter common circuit 10, so that the load signal generated by the load signal generator 300 based on the clock signal has the same delay compensation. In this case, the clock signal arriving at the serializer 210 via the channel clock path 200 in each transmitter channel circuit 20 is bypassed by the delay compensation path 350 in the transmitter common circuit 10.

[0074] For example, in an embodiment of this application, the delay compensation for the loading signal generated by the delay compensation path 350 can be configured to match the timing relationship between the loading signal and the clock signal transmitted to each transmitter channel circuit with the flip-flop's toggle association parameter (the toggle association parameter is a hardware parameter of the flip-flop), and the toggle association parameter includes the flip-flop's setup time threshold and hold time threshold. The configuration of the delay compensation can be achieved by setting the topology of the delay compensation path 350.

[0075] For example, in an embodiment of this application, the delay compensation generated by the loading signal using the delay compensation path 350 can be specifically configured such that: the actual setup time of the trigger for the channel data is greater than the setup time threshold of the trigger, and the actual hold time of the trigger for the channel data is greater than the hold time threshold of the trigger.

[0076] Figure 5 This is a timing diagram illustrating the operation of the multi-channel transmitter of the AI ​​chip in this embodiment. Please refer to... Figure 5 In the embodiments of this application, the actual setup time SU_margin and actual hold time HD_margin of the flip-flops for channel data can be associated with the channel transmission delay Delay_clk of the clock signal in any transmitter channel circuit 20, the delay compensation Delay_load of the load signal in the transmitter common circuit 10, and the loading delay Delay_trans generated by the parallel loading process of the channel data to multiple flip-flops in the shift register 215 of the serializer 210. The loading delay Delay_trans can be caused by a multiplexer cascaded between multiple flip-flops, and the loading delay Delay_trans can also be used to switch the delay on and off.

[0077] For example, in an embodiment of this application, the actual setup time SU_margin for the channel data of the trigger can be expressed as: SU_margin = 2UI + Delay_clk - Delay_load - Delay_trans. Wherein, 2UI represents one signal cycle of the clock signal.

[0078] For example, in an embodiment of this application, the actual hold time HD_margin of the trigger for channel data can be expressed as: HD_margin = Delay_load + Delay_trans - Delay_clk.

[0079] For example, in an embodiment of this application, the drive buffer 400 of the transmitter common circuit 10 can be configured to boost the signal load of the clock signal and the signal load of the load signal with delay compensation to a multi-channel load level matching the multiple transmitter channel circuits 20, and then split them into single-channel load level signal loads for transmission to the multiple transmitter channel circuits 20. Thus, the load signal generated by the load signal generator 300 in the transmitter common circuit 10 can be driven and buffered to a multi-channel load level matching the multiple transmitter channel circuits 20, just like the clock signal, and then split into single-channel load level signal loads for transmission to the multiple transmitter channel circuits 20, thereby preventing waveform abnormalities in the load signals used in the multiple transmitter channel circuits 20 due to excessively low signal load.

[0080] For example, in an embodiment of this application, the drive buffer 400 of the transmitter common circuit 10 may include a clock drive buffer 410 and a signal drive buffer 430. The clock drive buffer 410 may be configured to enable the signal load of the clock signal to reach a multiple load level matching the multiple transmitter channel circuits 20; the signal drive buffer 430 may be configured to enable the signal load of the loaded signal to reach a multiple load level matching the multiple transmitter channel circuits.

[0081] For example, in an embodiment of this application, the clock signal load signal generated by the clock source 100 has a single-channel load level signal load, and the clock drive buffer 410 can be configured to increase the signal load of the clock signal generated by the clock source 100 from a single-channel load level to a multi-channel load level matching multiple transmitter channel circuits 20.

[0082] For example, in an embodiment of this application, the load signal generator 300 generates a load signal based on a signal load with a single-channel load level and a clock signal with delay compensation, and also has a signal load with a single-channel load level and delay compensation for the clock signal. Furthermore, the signal drive buffer 430 can be specifically configured to increase the signal load of the load signal generated by the load signal generator 300 from a single-channel load level to a multi-channel load level that matches multiple transmitter channel circuits 20.

[0083] For example, in embodiments of this application, at least one of the clock drive buffer 410 and the signal drive buffer 430 may include a multi-stage inverter with progressively increasing dimensions. For instance, the dimensions of the multi-stage inverter increase by an equal multiple at each stage.

[0084] As can be seen above, the embodiments of this application can avoid the abnormality of the serialized output quality of multiple transmitter channel circuits 20 due to the reduction of the load signal generator 300 by using the delay compensation path 350 in the transmitter common circuit 10 to compensate for the delay of the load signal and / or using the drive buffer 400 (e.g., signal drive buffer 430) in the transmitter common circuit 10 to boost the load of the load signal.

[0085] For example, in an embodiment of this application, the serializer 210 of each transmitter channel circuit 20 may further include a clock shaping buffer 211 and a signal shaping buffer 213. The clock shaping buffer 211 may be configured to allow the clock signal transmitted to the serializer 210 to be subjected to single-path load level beamforming correction before reaching the shift register 215. The signal shaping buffer 213 may be configured to allow the load signal transmitted to the serializer 210 to be subjected to single-path load level beamforming correction before reaching the shift register 215.

[0086] Figure 6 This is a schematic diagram of an improved structure of the serializer for the multi-channel transmitter of the AI ​​chip in an embodiment of this application. Please refer to [link / reference]. Figure 6In the embodiments of this application, the serializer 210 of each transmitter channel circuit 20 can serialize the parallel input channel data into two paths, namely, serializing the odd-numbered bits D_e and even-numbered bits D_e of the channel data respectively. In this case, the pre-drive circuit 220 of each transmitter channel circuit 20 can be configured to alternately generate control codes using the odd-numbered bits D_e and even-numbered bits D_e of the separately serialized channel data outputs. Furthermore, the final-stage drive circuit 230 can be configured to serially transmit the level signal corresponding to the channel data in the corresponding physical channel of the multi-channel bus based on the control codes generated by the pre-drive circuit 220 using the odd-numbered bits D_e and even-numbered bits D_e alternately. The serializer 210 serializes the odd-numbered bits D_e and even-numbered bits D_e of the channel data respectively, and the pre-drive circuit 220 alternately uses the odd-numbered bits D_e and even-numbered bits D_e to control the final-stage drive circuit 230 to serially transmit the level signal corresponding to the channel data in the corresponding physical channel, which helps to improve the bit width consistency of the level signal in the physical channel.

[0087] Figure 7 This is a schematic diagram illustrating an improved example structure of the shift register in the serializer of the multi-channel transmitter of the AI ​​chip according to an embodiment of this application. Please refer to... Figure 7 If the serializer 210 of each transmitter channel circuit 20 is configured to serialize the odd-numbered bits D_e and even-numbered bits D_e of the output channel data respectively, then the shift register 215 of the serializer 210 may include two sets of flip-flops corresponding to the odd-numbered bits D_e and even-numbered bits D_e respectively, and the load signal can synchronously control the cascaded state of the two sets of flip-flops corresponding to the odd-numbered bits D_e and even-numbered bits D_e respectively.

[0088] Exemplarily, in embodiments of this application, multiple flip-flops in each group of shift register 215 can be cascaded. Specifically, multiple flip-flops in each group of shift register 215 can be cascaded by connecting the Q pins of the preceding flip-flops to the D pins of the following flip-flops in the same group via multiplexers. In this case, each odd-numbered bit of the parallel input channel data can be connected to the D pin of the first-stage flip-flop of one group and each multiplexer of that group; each even-numbered bit of the parallel input channel data can be connected to the D pin of the first-stage flip-flop of another group and each multiplexer of that group; and the clock signal can be connected to the CLK pin of each flip-flop in both groups of shift register 215. Thus, the load signal can control the intra-group cascade state of the two groups of flip-flops in shift register 215 by controlling the multiplexers of both groups, so that the odd-numbered bits D_e and even-numbered bits D_e of the channel data are loaded in parallel to the two groups of flip-flops respectively, and then serialized and output by shifting in the cascade direction of the corresponding groups of flip-flops.

[0089] For example, in the embodiments of this application, when the cascaded state of the two sets of flip-flops in the shift register 215 is set to open by the load signal, that is, when the D pins of the other flip-flops in each set of flip-flops (excluding the first flip-flop) receive the corresponding odd or even bits of the channel data, the odd and even bits of the parallel input channel data can be loaded into the two sets of flip-flops in parallel (that is, the parallel loading of channel data into the shift register 215 is realized).

[0090] For example, in an embodiment of this application, when the cascaded state of the two sets of flip-flops in the shift register 215 is set to connected by a load signal, that is, when the D pins of the flip-flops other than the first flip-flop in each set are turned on with the Q pins of the preceding flip-flops in the same set, the odd and even bits of the channel data that have been loaded can be serialized and output from the serializer by shifting in the cascaded direction of the multiple flip-flops in the corresponding set (that is, shifting the loaded channel data in the shift register 215). Furthermore, the odd and even bits of the channel data are shifted in the loading of the two sets of flip-flops and in the cascaded direction of the two sets of flip-flops by the toggling of the two sets of flip-flops based on the clock signal.

[0091] Figure 8 This is an exemplary structural diagram of the pre-amplifier and final-stage amplifier of the multi-channel transmitter in the AI ​​chip of this application embodiment. Please refer to... Figure 8 In the embodiments of the application, the pre-drive circuit 220 of each transmitter channel circuit 20 may include a first logic circuit 221, a second logic circuit 222, a first transistor group drive array 223a and a second transistor group drive array 223b, and the final drive circuit 230 of each transmitter channel circuit 20 may include a first transistor group 230a controlled by the first transistor group drive array 223a and a second transistor group 230b controlled by the second transistor group drive array 223b.

[0092] Exemplarily, in an embodiment of this application, the first transistor group 230a of the final stage drive circuit 230 of each transmitter channel circuit 20 may be located between the power supply VSS and the output terminal of the corresponding physical channel. Specifically, the first transistor group 230a of the final stage drive circuit 230 of each transmitter channel circuit 20 may include multiple first switching transistors connected in parallel between the power supply VSS and the output terminal of the corresponding physical channel. That is, the first transistor group 230a may include multiple parallel branches (legs), and when at least one first switching transistor in the first transistor group 230a is turned on, the final stage drive circuit 230 can generate a high-level signal of "1" in the corresponding ventilation channel data in the corresponding physical channel. For example, the first switching transistor may be a PMOS (P-channel Metal-Oxide-Semiconductor).

[0093] For example, in an embodiment of this application, the second transistor group 230b of the final stage drive circuit 230 of each transmitter channel circuit 20 may be located between ground GND and the output terminal connected to the corresponding physical channel. Specifically, the second transistor group 230b of the final stage drive circuit 230 of each transmitter channel circuit 20 may include multiple second switching transistors connected in parallel between ground GND and the output terminal connected to the corresponding physical channel. That is, the second transistor group 230b may also include multiple parallel branches, and when at least one of the second switching transistors in the second transistor group 230b is turned on, the final stage drive circuit 230 may generate a low-level signal of "0" in the corresponding ventilation channel data in the corresponding physical channel. For example, the second switching transistor may be an NMOS (N-channel Metal-Oxide-Semiconductor).

[0094] For example, in an embodiment of this application, the rcal function implemented by the pre-drive circuit 220 can maintain the output impedance of the final drive circuit 230 at a target impedance (e.g., 25Ω) by adjusting the number of first switching transistors turned on in the first transistor group 230a or the number of second switching transistors turned on in the second transistor group 230b.

[0095] For example, in an embodiment of this application, the eq function implemented by the pre-drive circuit 220 can enable the first switch in the first transistor group 230a and the second switch in the second transistor group 230b to be turned on simultaneously, and adjust the ratio of the number of the first switch and the second switch to be turned on, so that the transition edge of the level signal generated by the final stage drive circuit 230 in the corresponding physical channel has a peak for pre-compensating the high-frequency component loss peak of the level signal in the physical channel.

[0096] For example, in an embodiment of this application, the first logic circuit 221 of the pre-drive circuit 220 of each transmitter channel circuit 20 may be configured to drive the second logic circuit 222 to generate (e.g., concurrently generate) multiple sets of control codes for adapting multiple states in which each of the rcal and eq functions is selectively activated or deactivated, based on the odd-numbered bits D_e and even-numbered bits D_e of the channel data serialized from the serializer 210.

[0097] For example, in an embodiment of this application, the first logic circuit 221 of the pre-drive circuit 220 can be configured to output odd-numbered bits D_e and even-numbered bits D_e of channel data to the second logic circuit 222, as well as odd-numbered bit balanced data D_e_eq of odd-numbered bits D_e and even-numbered bit balanced data D_o_eq of even-numbered bits D_e for supporting the eq function.

[0098] For example, in the embodiments of this application, the odd-bit equalized data D_e_eq can be obtained by delaying the odd-bit D_e by one clock cycle and then inverting it, and the even-bit equalized data D_o_eq can be obtained by delaying the even-bit D_e by one clock cycle and then inverting it. The embodiments of this application are not intended to impose unnecessary restrictions on the generation methods of the odd-bit equalized data D_e_eq and the even-bit equalized data D_o_eq.

[0099] For example, in an embodiment of this application, the second logic circuit 222 of the pre-drive circuit 220 can be configured to generate multiple sets of control codes based on odd-numbered bits D_e and even-numbered bits D_e, as well as odd-numbered bit equalization data D_e_eq and even-numbered bit equalization data D_o_eq, for adapting multiple states in which each of the rcal function and eq function is selectively activated or deactivated.

[0100] Exemplarily, in an embodiment of this application, the second logic circuit 222 of the pre-driver circuit 220 can be configured to generate four sets of control codes based on odd-numbered bits D_e and even-numbered bits D_e, as well as odd-numbered bit equalization data D_e_eq and even-numbered bit equalization data D_o_eq. The first set of control codes adapts to a state where both the rcal function and eq function are off; the second set of control codes adapts to a state where the rcal function is off and the eq function is active; the third set of control codes adapts to a state where the rcal function is active and the eq function is off; and the fourth set of control codes adapts to a state where both the rcal function and eq function are active. The algorithms for the four sets of control codes can refer to related technologies, and the embodiments of this application do not limit this.

[0101] For example, in the embodiments of this application, each set of control codes generated by the second logic circuit 222 of the pre-drive circuit 220 can include a first transistor group control code provided to the first transistor group drive array 223a and a second transistor group control code provided to the second transistor group drive array 223b. That is, the first transistor group control code in the four sets of control codes can be provided to the first transistor group drive array 223a in parallel, and the second transistor group control code in the four sets of control codes can be provided to the second transistor group drive array 223b in parallel. Furthermore, the first transistor group drive array 223a and the second transistor group drive array 223b can selectively enable one set of the first transistor group control code and the second transistor group control code in the four sets of control codes according to the input mode selection signal, so as to control the first transistor group 230a and the second transistor group 230b according to the activation and deactivation states of the rcal function and eq function represented by the mode selection signal.

[0102] Embodiments of this application also provide an operation method for an AI chip, applicable to AI chips including the multi-channel transmitter described above.

[0103] Figure 9This is an exemplary flowchart illustrating the operation method of the AI ​​chip in this application embodiment. Please refer to... Figure 9 In embodiments of this application, the operation method of the AI ​​chip may include:

[0104] S910: A clock signal is generated by the clock source of the transmitter common circuit, and a load signal is generated by the load signal generator of the transmitter common circuit based on the clock signal;

[0105] S930: The serializer of each transmitter channel circuit serializes the parallel input channel data to be transmitted through the corresponding physical channel based on the clock signal and load signal received from the transmitter common circuit.

[0106] Based on the above process, the multi-channel transmitter of the AI ​​chip can only set a load signal generator in the common transmitter circuit. Furthermore, multiple transmitter channel circuits do not need to set load signal generators; the load signal can be used to complete the serialization output of parallel input channel data. Therefore, compared with related technologies that set a load signal generator in each transmitter channel circuit, the circuit area and power consumption of the multi-channel transmitter can be reduced by reducing the number of load signal generators.

[0107] For example, in an embodiment of this application, the operation method may further include an additional step for delay compensation (e.g., the additional step may be performed during S910): using the delay compensation path of the transmitter common circuit, the load signal generated by the load signal generator of the transmitter common circuit has delay compensation, which matches the channel transmission delay caused by the channel clock path in each transmitter channel circuit by the clock signal generated by the clock source of the transmitter common circuit.

[0108] Based on the additional steps for delay compensation described in the embodiments of this application, the multi-channel transmitter of the AI ​​chip can also set up a redundant or dummy clock path in the transmitter common circuit as a delay compensation path, so that the load signal generated by the load signal generator in the transmitter common circuit can have delay compensation. This delay compensation matches the channel transmission delay caused by the channel clock path in each transmitter channel circuit, so as to avoid timing errors when using load signals in multiple transmitter channel circuits.

[0109] For example, in an embodiment of this application, the additional steps for delay compensation may specifically include: using the delay compensation path of the transmitter common circuit to generate delay compensation for the clock signal transmitted from the clock source to the load signal generator in the transmitter common circuit, so that the load signal generated by the load signal generator based on the clock signal has delay compensation; wherein, the clock signal that arrives at the serializer via the channel clock path in each transmitter channel circuit bypasses the delay compensation path in the transmitter common circuit.

[0110] For example, in an embodiment of this application, the operation method may further include an additional step for boosting the signal load (for example, the additional step may be performed before S930): using the drive buffer of the transmitter common circuit, the signal load of the clock signal generated by the clock source of the transmitter common circuit and the signal load of the load signal with delay compensation generated by the load signal generator of the transmitter common circuit are both boosted to the multi-channel load level matching multiple transmitter channel circuits, and then the signal loads are split into single-channel load levels and transmitted to multiple transmitter channel circuits.

[0111] Based on the additional steps for increasing signal load described in the embodiments of this application, the transmitter common circuit of the multi-channel transmitter of the AI ​​chip may further include a drive buffer. The load signal generated by the load signal generator in the transmitter common circuit can be driven and buffered to a multi-channel load level matching multiple transmitter channel circuits, just like a clock signal, and then split into single-channel load levels and transmitted to multiple transmitter channel circuits. This avoids waveform abnormalities in the load signals used in multiple transmitter channel circuits due to insufficient signal load. Furthermore, by compensating for the delay of the load signal and increasing the load, the serialized output quality of multiple transmitter channel circuits can be prevented from becoming abnormal due to the reduction of the load signal generator.

[0112] For example, in the embodiments of this application, the additional steps for increasing the signal load may specifically include: using the clock drive buffer in the drive buffer of the transmitter common circuit to make the signal load of the clock signal generated by the clock source of the transmitter common circuit reach the multi-channel load level matching multiple transmitter channel circuits, and then the signal load is split into a single-channel load level and transmitted to multiple transmitter channel circuits; and using the signal drive buffer in the drive buffer of the transmitter common circuit to make the signal load of the load signal with delay compensation generated by the load signal generator of the transmitter common circuit increase to the multi-channel load level matching multiple transmitter channel circuits, and then the signal load is split into a single-channel load level and transmitted to multiple transmitter channel circuits.

[0113] For example, in the embodiments of this application, the additional steps for increasing the signal load may specifically include: using a clock drive buffer to increase the signal load of the clock signal generated by the clock source from a single-channel load level to a multi-channel load level that matches multiple transmitter channel circuits; and using a signal drive buffer to increase the signal load of the load signal generated by the load signal generator from a single-channel load level to a multi-channel load level that matches multiple transmitter channel circuits.

[0114] For example, in an embodiment of this application, the operation method of the AI ​​chip may further include an additional step for signal beamforming (e.g., this additional step may be performed during S930): utilizing the clock shaping buffer of each transmitter channel circuit, the clock signal transmitted to the serializer of the transmitter channel circuit is subjected to beamforming correction at a single-path load level before reaching the shift register of the serializer.

[0115] It is understood that, in the embodiments of this application, the various parts described by example may be related by an "and / or" relationship. In this document, "and / or" means that the contexts connected by it may be a common "and" relationship or an alternative "or" relationship. Therefore, the various parts having an "and / or" relationship can be understood to include different combinations of situations where the "and / or" between each pair of parts represents a common "and" relationship or an alternative "or" relationship, and such combinations of different situations can be considered substantially equivalent to the scope of "at least one of the parts".

[0116] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An artificial intelligence chip, characterized in that, The device includes a multi-channel transmitter for transmitting data via a multi-channel bus, the multi-channel transmitter including a transmitter common circuit and multiple transmitter channel circuits corresponding to multiple physical channels of the multi-channel bus; The transmitter common circuit includes a clock source and a load signal generator, the clock source being configured to generate a clock signal, and the load signal generator being configured to generate a load signal based on the clock signal; Each of the transmitter channel circuits includes a serializer, and the serializer of each of the transmitter channel circuits is configured to serialize and output channel data that is input in parallel and is intended to be transmitted through the corresponding physical channel based on the clock signal and the load signal received from the transmitter common circuit.

2. The artificial intelligence chip according to claim 1, characterized in that, Each of the transmitter channel circuits further includes a channel clock path, and the clock signal reaches the serializer via the channel clock path in each of the transmitter channel circuits; The transmitter common circuit further includes a delay compensation path; wherein the delay compensation path is configured to give the load signal a delay compensation that matches the channel transmission delay of the clock signal in each of the transmitter channel circuits caused by the channel clock path.

3. The artificial intelligence chip according to claim 2, characterized in that, The delay compensation path is located between the clock source and the load signal generator, and the delay compensation path is specifically configured to generate the delay compensation for the clock signal transmitted from the clock source to the load signal generator in the transmitter common circuit, so that the load signal generated by the load signal generator has the delay compensation; The clock signal that arrives at the serializer via the channel clock path in each of the transmitter channel circuits is bypassed in the transmitter common circuit via the delay compensation path.

4. The artificial intelligence chip according to claim 2, characterized in that, The serializer includes a shift register, and the shift register includes multiple flip-flops; The loading signal is used to control the cascading state between the multiple flip-flops, so that the channel data input in parallel is loaded into the multiple flip-flops in parallel and then serialized and output by shifting in the cascading direction of the multiple flip-flops; The channel data is loaded into multiple triggers and shifted in the cascading direction of multiple triggers, all by the flipping of the triggers based on the clock signal; the delay compensation is configured to match the timing relationship between the loading signal and the clock signal with the flipping association parameter of the trigger, and the flipping association parameter includes the setup time threshold and the hold time threshold of the trigger.

5. The artificial intelligence chip according to claim 4, characterized in that, The delay compensation is specifically configured to ensure that the timing relationship between the loading signal and the clock signal satisfies: The actual setup time for the channel data by the trigger is greater than the setup time threshold. The actual holding time of the channel data by the trigger is greater than the holding time threshold.

6. The artificial intelligence chip according to claim 5, characterized in that, The actual setup time and the actual hold time are related to the channel transmission delay of the clock signal, the delay compensation of the load signal, and the loading delay generated by the parallel loading process of the channel data to multiple triggers.

7. The artificial intelligence chip according to claim 6, characterized in that, The actual setup time SU_margin = 2UI + Delay_clk - Delay_load - Delay_trans; The actual hold time HD_margin = Delay_load + Delay_trans - Delay_clk; Wherein, 2UI represents one signal period of the clock signal, Delay_clk represents the channel transmission delay of the clock signal, Delay_load represents the delay compensation of the load signal, and Delay_trans represents the loading delay generated by the parallel loading process of the channel data to multiple triggers.

8. The artificial intelligence chip according to any one of claims 1 to 7, characterized in that, The transmitter common circuit also includes a drive buffer; wherein the drive buffer is configured to boost the signal load of the clock signal and the signal load of the loading signal to a multi-channel load level matching the multiple transmitter channel circuits, and then split the signal loads into single-channel load levels and transmit them to the multiple transmitter channel circuits.

9. The artificial intelligence chip according to claim 4, characterized in that, The transmitter common circuit also includes a drive buffer; wherein the drive buffer is configured to boost the signal load of the clock signal and the signal load of the loading signal to a multi-channel load level matching the multiple transmitter channel circuits, and then split the signal loads into single-channel load levels and transmit them to the multiple transmitter channel circuits. The serializer of each of the transmitter channel circuits further includes a clock shaping buffer and a signal shaping buffer, wherein: The clock shaping buffer is configured to cause the clock signal transmitted to the serializer to be beam-shaped after being subjected to the single-path load level before reaching the shift register; The signal shaping buffer is configured such that the load signal transmitted to the serializer is subjected to the single-path load level beamforming correction before reaching the shift register.

10. The artificial intelligence chip according to claim 8, characterized in that, The drive buffer includes a clock drive buffer and a signal drive buffer, wherein: The clock drive buffer is configured to make the signal load of the clock signal reach the multiple load level that matches the multiple transmitter channel circuits; The signal drive buffer is configured to make the signal load of the loaded signal reach the multiple load level that matches the multiple transmitter channel circuits.

11. The artificial intelligence chip according to claim 10, characterized in that, The clock signal generated by the clock source has a load signal at the single-channel load level, and the clock drive buffer is configured to increase the load signal of the clock signal generated by the clock source from the single-channel load level to the multi-channel load level matching the multiple transmitter channel circuits. The load signal generated by the load signal generator has a signal load at the single-channel load level, and the signal drive buffer is configured to increase the signal load of the load signal generated by the load signal generator from the single-channel load level to the multi-channel load level matching the multiple transmitter channel circuits.

12. The artificial intelligence chip according to claim 2, characterized in that, The serializer of each of the transmitter channel circuits serializes the parallel-input channel data by serializing the odd-numbered bits and even-numbered bits of the channel data, respectively. The serializer includes a shift register, which includes two sets of flip-flops corresponding to odd-numbered bits and even-numbered bits, respectively. The loading signal is used to control the intra-group cascading state between the two sets of triggers, so that the odd and even bits of the channel data are loaded in parallel to the two sets of triggers respectively, and then serialized and output by shifting in the cascading direction of the corresponding sets of triggers. The odd and even bits of the channel data are shifted in the loading of the corresponding group of the flip-flops and in the cascading direction of the corresponding group of the flip-flops, respectively, by the flip-flops based on the toggling of the clock signal. The delay compensation is configured to match the timing relationship between the loading signal and the clock signal with the toggling association parameter of the flip-flops. The toggling association parameter includes the setup time threshold and the hold time threshold of the flip-flops.

13. A method for operating an artificial intelligence chip, characterized in that, The artificial intelligence chip includes a multi-channel transmitter for transmitting data via a multi-channel bus. The multi-channel transmitter includes a transmitter common circuit and multiple transmitter channel circuits corresponding to multiple physical channels of the multi-channel bus. The operation method includes: A clock signal is generated by the clock source of the transmitter common circuit, and a load signal is generated by the load signal generator of the transmitter common circuit based on the clock signal; The serializer of each of the transmitter channel circuits serializes the parallel-input channel data for transmission through the corresponding physical channel based on the clock signal and the load signal received from the transmitter common circuit.

14. The operating method according to claim 13, characterized in that, Each of the transmitter channel circuits further includes a channel clock path, and the clock signal reaches the serializer via the channel clock path in each of the transmitter channel circuits; The transmitter common circuit also includes a delay compensation path, and the operation method further includes: The delay compensation path is used to make the loading signal have delay compensation that matches the channel transmission delay of the clock signal in each of the transmitter channel circuits caused by the channel clock path.

15. The operating method according to claim 13 or 14, characterized in that, The transmitter common circuit also includes a drive buffer, and the operation method further includes: After the signal load of the clock signal and the signal load of the loading signal are both boosted to the multi-channel load level matching the multiple transmitter channel circuits by the drive buffer, the signal loads are split into single-channel load levels and transmitted to the multiple transmitter channel circuits.

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