Io chip design supporting communication-aware routing

By introducing communication-aware routing IO core design into the core interconnect system, integrating virtual channel router, in-situ data processing engine and non-blocking Crossbar switching structure, the problems of low communication efficiency and waste of computing resources in existing technologies are solved, and high-efficiency and stable multi-core system performance is achieved.

CN122111936APending Publication Date: 2026-05-29SHAOXIN LABORATORY
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHAOXIN LABORATORY
Filing Date
2026-01-20
Publication Date
2026-05-29

AI Technical Summary

Technical Problem

Existing communication technologies are inefficient when dealing with complex collective communication patterns, resulting in significant waste of computing resources and a lack of hardware support, making it difficult to stably expand system performance.

Method used

Introducing a communication-aware routing IO core design into the core-core interconnect system, integrating a virtual channel router, an in-situ data processing engine, a central controller, and a non-blocking Crossbar switching structure to achieve hardware-level aggregated communication support.

Benefits of technology

It improves the efficiency of aggregated communication, reduces latency and energy consumption, enhances system stability and scalability, and optimizes data transmission and protocol stack efficiency.

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Abstract

The application relates to an IO chip design supporting communication-aware routing, which serves as a centralized inter-chip communication node, integrates a virtual channel router, an in-situ data processing engine, a central controller and a non-blocking Crossbar switch structure, introduces communication semantic information in a data packet, realizes hardware-level identification and unified scheduling of point-to-point communication and collective communication, and directly completes collective communication operations such as addition, accumulation, reduction and normalization on a data transmission path through the in-situ data processing engine, and combines a hardware-level broadcast mechanism to one-time distribute processing results to multiple computing chips, thereby reducing repeated data transmission and scheduling overhead. Meanwhile, a priority-aware virtual channel management and deadlock detection and recovery mechanism is introduced to improve system reliability and scalability. The application has the effect of reducing communication delay and energy consumption of a multi-chip system without increasing the burden of computing chips.
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