A ghost attack defense method based on instruction pollution marking and related equipment

By adding pollution markers and physical register tables to the instruction microcode and implementing latency control, the problem of insufficient defense against Spectre attacks on the RISC-V architecture is solved, achieving efficient and transparent hardware defense and reducing performance overhead.

CN122113114APending Publication Date: 2026-05-29SOUTH CHINA UNIV OF TECH
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SOUTH CHINA UNIV OF TECH
Filing Date
2026-01-26
Publication Date
2026-05-29

AI Technical Summary

Technical Problem

Existing technologies lack efficient and systematic hardware defense mechanisms for Spectre attacks targeting open instruction set architectures such as RISC-V, resulting in high performance overhead and limited protection scope.

Method used

Add a first pollution flag and a second pollution flag to the microcode of the instruction, maintain a physical register pollution table, and implement delay control or access restrictions by updating the pollution flags and register states of the instruction, thereby finely managing the predicted execution risks.

Benefits of technology

It implements a hardware-transparent defense solution that is easy to deploy, requires no modification to the operating system or compiler, has minimal performance impact, is suitable for RISC-V architecture, and provides comprehensive protection.

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Abstract

The embodiment of the application provides a ghost attack defense method based on instruction pollution marks and related equipment, and belongs to the technical field of processor security. The method comprises the following steps: setting a first pollution mark and a second pollution mark in an instruction microcode; maintaining a physical register pollution table to track the register pollution state; in the instruction renaming stage, updating the above-mentioned marks and the pollution table according to the speculation execution state and the source register pollution condition; in the instruction emission and access stage, if the second pollution mark of the instruction is valid and a specific risk condition (such as being in the speculation execution period, a cache miss occurring) is met, then fine control measures such as delayed emission, delayed memory request or cache write prohibition are taken. The application accurately blocks the potential leakage path through the hardware mechanism, does not need to modify the upper software, effectively defends the side channel attack, significantly reduces the influence on the processor performance, and is especially suitable for RISC-V and other processor architectures.
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