Circuit network layout optimization methods, electronic devices, circuit boards and dielectrics

Abstract

This invention discloses a layout optimization method for circuit networks, an electronic device, a circuit board, and a dielectric, relating to the field of circuit technology. On one hand, it determines a first force based on the density gradient between the target area and the surrounding areas; on the other hand, it determines a second force based on the current power status of the logic units. Finally, the layout of the logic units is adjusted based on the combined force of the first and second forces. The first force can adjust the logic units in the target area to positions with lower density, and the second force can adjust them to positions closer to power lines when the power status of the logic units is abnormal. This solves the problem of IR Drop failing to meet preset standards due to excessively high logic unit density in circuit networks. It achieves dual-objective collaborative layout optimization from both unit density and power status perspectives, effectively reducing or even eliminating IR Drop in circuit networks.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a method for optimizing the layout of circuit networks, electronic devices, circuit boards, and dielectrics. Background Technology

[0002] IR Drop (Current-Resistance Voltage Drop) refers to the phenomenon of voltage drop and rise between the power and ground networks in integrated circuits. IR Drop can cause problems such as insufficient power supply to logic units and processing delays. With the continuous evolution of semiconductor technology, the width of metal interconnects used in circuit networks is becoming narrower, their resistance is increasing, and the supply voltage in some applications is decreasing. Therefore, the impact of IR Drop is becoming increasingly significant, and circuit network design and chip design are gradually incorporating IR Drop analysis as a necessary step in chip signoff.

[0003] It is evident that effectively avoiding IR drop in circuit networks and chip design is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a method for optimizing the layout of circuit networks, electronic devices, circuit boards, and media, which can solve the IR drop problem existing in circuit networks and chips.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a method for optimizing the layout of circuit networks, comprising:

[0006] Determine the target region in the circuit network;

[0007] The first force is determined based on the density gradient between the target region and the surrounding region; the direction of the first force is from the region with high density to the region with low density.

[0008] The second force is determined based on the power status of the logic units in the target area;

[0009] The layout of the logic units corresponding to the target area is adjusted according to the resultant force of the first and second forces.

[0010] In some embodiments, determining a target region in a circuit network includes:

[0011] Identify areas in the circuit network where the violation rate exceeds a preset value;

[0012] The area with a violation level greater than the preset value is divided into several grids;

[0013] Define one or more grids obtained from the division as the target region.

[0014] In some embodiments, determining the first force based on the density gradient between the target region and the surrounding region includes:

[0015] Determine the area density of the area surrounding the target area; the area surrounding the target area includes a first adjacent area adjacent to the target area in the x direction and a second adjacent area adjacent to the target area in the y direction; the area density is the ratio between the area occupied by logical units in the area and the total available area of ​​the area;

[0016] Calculate the density gradient of the target region in the x-direction based on the regional density of the first neighboring region;

[0017] Calculate the density gradient of the target region in the y-direction based on the regional density of the second adjacent region;

[0018] The vector formed by the density gradient of the target region in the x-direction and the density gradient of the target region in the y-direction is converted into a force vector to obtain the first force.

[0019] In some embodiments, the first neighboring region includes a left neighboring region and a right neighboring region; calculating the density gradient of the target region in the x-direction based on the region density of the first neighboring region includes:

[0020] Determine the density difference between the region density of the left adjacent region and the region density of the right adjacent region;

[0021] Determine the distance difference in the x-direction between the reference point of the left adjacent region and the reference point of the right adjacent region;

[0022] The ratio between density difference and distance difference is determined as the density gradient of the target region in the x-direction.

[0023] In some embodiments, converting the vector formed by the density gradient of the target region in the x-direction and the density gradient of the target region in the y-direction into a force vector includes:

[0024] The product of the density gradient of the target region in the x-direction and the step size coefficient is determined as the first component of the force vector in the x-direction;

[0025] The product of the density gradient of the target region in the y-direction and the step size coefficient is determined as the second component of the force vector in the y-direction.

[0026] In some embodiments, determining the second force based on the power status of the logic cells in the target region includes:

[0027] Determine the voltage drop along the power supply path corresponding to the logic unit in the target area and the unit power consumption of the logic unit;

[0028] The magnitude of the second force is determined based on the relationship between the supply voltage drop and the preset voltage drop threshold, and the unit power consumption.

[0029] The direction of the second force is determined based on the distribution of power lines around the logic unit.

[0030] In some embodiments, determining the magnitude of the second force based on the relationship between the supply voltage drop and a preset voltage drop threshold and the unit power consumption includes:

[0031] If the voltage drop is less than or equal to the preset voltage drop threshold, the second force is set to zero;

[0032] If the supply voltage drop is greater than the preset voltage drop threshold, determine the absolute value of the difference between the supply voltage drop and the preset voltage drop threshold;

[0033] The maximum value among the absolute value and the minimum value excluding zero is determined as the denominator term;

[0034] The ratio between the unit power consumption and the denominator term is determined as the magnitude of the second force.

[0035] In some embodiments, determining the direction of the second force based on the power line distribution around the logic cell includes:

[0036] Determine the cell coordinates of the logic unit and the power line coordinates of several power lines surrounding the logic unit;

[0037] The Euclidean distance between each power line and the logic unit is determined based on the cell coordinates and the power line coordinates, respectively.

[0038] The power line coordinates corresponding to the minimum Euclidean distance are determined as the target direction of the second force.

[0039] In some embodiments, after adjusting the layout of the logic units corresponding to the target region according to the resultant force of the first force and the second force, the method further includes:

[0040] Perform voltage drop analysis on the circuit network after the layout adjustment;

[0041] If the voltage drop analysis result of the circuit network does not meet the preset standard, the process will jump back to the step of determining the target region in the circuit network until the voltage drop analysis result of the circuit network meets the preset standard.

[0042] In some embodiments, adjusting the layout of the logic units corresponding to the target region according to the resultant force of the first force and the second force includes:

[0043] Assign a first weight to the first force and a second weight to the second force;

[0044] The resultant force of the first and second forces is determined based on the first and second weights.

[0045] In some embodiments, the process of determining the first weight specifically includes:

[0046] Determine the first ratio between the regional density and the permissible density of the target area;

[0047] The product of the cube of the first ratio and the preset density penalty base is determined as the first weight corresponding to the first force.

[0048] In some embodiments, the process of determining the second weight specifically includes:

[0049] Determine the difference between the supply voltage drop on the power supply path corresponding to the logic unit in the target area and the preset voltage drop threshold, and the second ratio between the preset voltage drop threshold and the target area;

[0050] Perform a function transformation on the second ratio;

[0051] The product of the result of the function transformation of the second ratio and the preset sensitivity coefficient is determined as the second weight corresponding to the second force.

[0052] To address the aforementioned technical problems, embodiments of the present invention also provide an electronic device, comprising:

[0053] Memory, used to store computer programs;

[0054] A processor is used to execute computer programs to implement the layout optimization method for circuit networks as described above.

[0055] To address the aforementioned technical problems, embodiments of the present invention also provide a circuit board, wherein the circuit network design on the circuit board is generated after adjustment based on the aforementioned circuit network layout optimization method.

[0056] To address the aforementioned technical problems, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned circuit network layout optimization method.

[0057] As can be seen from the above technical solution, the entire optimization method determines the first force based on the density gradient between the target area and the surrounding areas; and determines the second force based on the current power status of the logic units. Finally, the layout of the logic units is adjusted based on the combined force of the first and second forces. The beneficial effect of this invention is that the first force can adjust the logic units in the target area to a position with lower area density, and the second force can adjust them to a position closer to the power lines when the power status of the logic units is abnormal. This solves the problem that the IR Drop in the circuit network cannot meet the preset standard due to excessively high logic unit density. It achieves dual-objective collaborative layout optimization from the perspectives of unit density and power status, effectively reducing or even eliminating the IR Drop of the circuit network. Attached Figure Description

[0058] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 A schematic flowchart illustrating a circuit network layout optimization method provided in an embodiment of the present invention;

[0060] Figure 2 This is a schematic diagram of the layout inspection results of a circuit board provided in an embodiment of the present invention;

[0061] Figure 3 A schematic diagram of a violation area determined based on the layout inspection results of a circuit board, provided for an embodiment of the present invention;

[0062] Figure 4 A schematic flowchart illustrating a circuit board layout optimization process provided in an embodiment of the present invention;

[0063] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0064] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0065] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0066] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0067] Next, a method for optimizing the layout of a circuit network provided by an embodiment of the present invention will be described in detail. See also... Figure 1 As shown, Figure 1 This is a flowchart illustrating a circuit network layout optimization method provided in an embodiment of the present invention; the circuit network layout optimization method includes:

[0068] S11: Determine the target region in the circuit network;

[0069] It is easy to understand that after the initial layout design of a circuit network is completed, some areas may have serious IR drop problems, affecting the performance and normal operation of logic units. This can cause logic units to fail to obtain the minimum operating voltage required for operation or cause delays in logic units. For these areas, the layout optimization method provided by this invention can be used to further adjust the layout of the circuit network based on the initial layout design, thereby avoiding or even eliminating the impact of IR drop in the initial layout design on the operation of the circuit network. Therefore, the target area refers to the specific local area in the circuit network that needs to be adjusted in layout. It is usually a specific area where IR drop problems need to be addressed, or it can be a specific area where IR drop needs to be mitigated according to application requirements. This application does not make any special limitations here. A circuit network refers to an overall circuit structure with specific electrical functions formed by interconnecting circuit elements through nodes and traces. Specifically, it can be a specific circuit structure on a circuit board composed of discrete components and PCB (Printed Circuit Board) traces, or it can be an on-chip circuit structure composed of standard cells and metal interconnect layers inside a chip. This application does not make any special limitations on the specific implementation form of the circuit network.

[0070] It should be noted that this application does not impose any special restrictions on the specific method of determining the target area. The user can directly define a specific area as the target area based on the user's instructions, or the target area can be determined by the layout inspection results obtained after checking and analyzing the initial layout design of the circuit network using simulation analysis software. The simulation analysis software can calculate and display the IR Drop of each point in the initial layout design. At this time, the local area with severe IR Drop in the circuit network can be determined based on the display results and identified as the target area.

[0071] Furthermore, IR Drop refers to the voltage drop that occurs when current flows through the metal conductors that carry power in a circuit network. The criteria for judging the severity of IR Drop can be predetermined based on actual application requirements and the operational requirements that logic units need to meet. This application does not impose any special limitations here; it can be achieved directly by setting thresholds. For example, for the on-chip circuit network corresponding to a chip, the severity of IR Drop at a certain point on the circuit network can be determined based on the chip's corresponding Signoff standard. The Signoff standard includes IR Drop analysis of the on-chip circuit network. Different process nodes and different application scenarios have different Signoff standards, which can be selected and determined according to the actual application scenario. See also... Figure 2 As shown, Figure 2 This is a schematic diagram of the layout inspection results of a circuit board provided in an embodiment of the present invention. After the initial layout design of a certain circuit network is completed, an IR Drop check is performed on the initial layout design using an EDA (Electronic Design Automation) tool. The EDA tool will display the IR Drop analysis results with colors, such as marking severely affected areas in red. Figure 2 The image shows the results of an IR Drop test on a circuit network, with black dots indicating locations that do not meet the Signoff criteria.

[0072] S12: Determine the first force based on the density gradient between the target region and the surrounding region; the direction of the first force is from the region with high density to the region with low density.

[0073] Understandably, considering that the severity of dynamic IR drop mainly depends on the density of logic cells, the higher the density of logic cells in a local area, the more transistors will be performing switching actions, and the more obvious the dynamic IR drop will be. Therefore, in order to effectively solve the IR drop problem, especially to effectively avoid the impact of dynamic IR drop on the operation of the circuit network, this application will adjust the layout of the circuit network based on the cell density. According to the density gradient between the target area and the surrounding areas, it will determine which direction the logic cells can be adjusted according to the cell density. The adjustment is based on the principle of adjusting from the area with high density to the area with low density, thereby mitigating or avoiding the situation where excessive density leads to aggravated IR drop.

[0074] It should be noted that the surrounding area refers to the local area located around the target area in the circuit network. Taking the target area as a rectangle as an example, the surrounding area can be four local areas around the rectangular area. This application does not make any special limitations on the specific implementation method of the surrounding area. A preferred embodiment is to implement it in the same way as the target area, specifically including the same shape and area as the target area. Density gradient refers to the trend of regional density change in spatial location, that is, the direction and magnitude of the change in regional density of the target area and the regional density of the surrounding area in space. The regional density of a certain area refers to the cell density of the logic cells in that area, that is, the ratio between the area occupied by the logic cells in that area and the total available area of ​​the area (i.e., the unoccupied free area).

[0075] S13: Determine the second force based on the power status of the logic units in the target area;

[0076] It is easy to understand that, considering the severity of IR drop is directly reflected in the power supply status of the corresponding logic unit, this invention also directly adjusts the layout of the circuit network based on the power supply status of the logic unit. The power supply status specifically refers to the state exhibited by the logic unit and the power lines supplying it, including the actual supply voltage received by the logic unit's power supply terminal (usually the magnitude of the supply voltage), the unit power consumption generated by the logic unit operating based on the received supply voltage, and the voltage drop generated by the power lines supplying power to the logic unit. This application does not impose any particular limitations on these aspects. A logic unit (Cell) refers to a hardware circuit module in the circuit network that can implement basic functions, such as a standard cell (Stdcell) or macro cell (Macro) in a standard cell library.

[0077] It should be noted that the first force and the second force in this application are not applied directly to the logic unit, but are force vectors. The force vector is used to represent the adjustment direction and adjustment distance. This application does not make any special restrictions on the specific implementation of the first force and the second force, and they can be directly represented by a vector.

[0078] S14: Adjust the layout of the logic units corresponding to the target area according to the resultant force of the first and second forces.

[0079] It is understandable that the final adjustment of the logic cell layout will be achieved by utilizing the resultant force of the first and second forces acting simultaneously. This resultant force is the vector sum of the first and second forces. The vector superposition of the first force (density negative gradient force) and the second force (voltage drop directional force) is calculated through the resultant force, determining the direction and distance of the final adjustment. This application primarily focuses on the layout adjustment of logic cells, adjusting the layout on a per-unit basis within the circuit network. In practical applications, it is not limited to adjusting logic cells; it can also be combined with the layout of traces within the circuit network. This application does not impose any particular limitations on this. The entire layout optimization method can be performed during the circuit network layout design phase, or it can be used to inspect and generate layout optimization schemes for finished products that have already been manufactured or even applied. Its application scenarios are wide-ranging, and this application does not impose any particular limitations on this.

[0080] It should be noted that the layout optimization method provided by this invention can be directly integrated into circuit network simulation analysis software. After performing IR Drop checks on the circuit network, the corresponding layout optimization adjustment scheme can be generated directly based on the check results, for example, directly integrated into software for chip Signoff standard checks. Alternatively, a separate hardware electronic device can be set up to generate the corresponding layout optimization adjustment scheme based on the initial layout design of the input circuit network and the corresponding IR Drop check results. There are multiple implementation options, and this application does not impose any particular limitation here.

[0081] This invention provides a circuit network layout optimization method that can optimize and adjust the layout of the circuit network to address IRD (Inverter-Reduced Drop). The first force employs a negative gradient-driven diffusion behavior, effectively balancing resource distribution within the circuit network and avoiding resource waste (e.g., wiring resources). Simultaneously, a second force is balanced to form a directional pull force coupling power consumption and voltage drop, reducing IR drop by guiding high-power logic cells closer to power lines. This invention simultaneously optimizes the location of local logic cells based on both cell density and power conditions, achieving a one-time joint optimization of cell density and voltage drop. The dual-physical field coupling of the first and second forces achieves a joint mechanical balance between cell density and voltage drop, effectively reducing or eliminating the impact of IR Drop. In particular, it effectively solves the IR Drop problem caused by excessively high logic cell density in localized high-frequency switching areas.

[0082] See Figure 3 As shown, Figure 3 This invention provides a schematic diagram of a violation area determined based on the layout inspection results of a circuit board; in some embodiments, determining the target area in the circuit network includes:

[0083] Identify areas in the circuit network where the violation rate exceeds a preset value;

[0084] The area with a violation level greater than the preset value is divided into several grids;

[0085] Define one or more grids obtained from the division as the target region.

[0086] It is understood that the specific area in the circuit network with a violation degree greater than a preset value can be used as the adjustment target. The violation degree refers to the severity level of the violation of electrical constraints (mainly the size of IR Drop in this application), that is, the deviation of a certain parameter (mainly IR Drop in this application) from the preset standard (e.g., the chip's Signoff standard) in the circuit network inspection and analysis results. The area with a violation degree greater than the preset value is also the area with severe violations. Violations include voltage drop and / or area density violations. In this application, it can be a local area where the IR Drop does not meet the preset standard, or the deviation between the IR Drop and the preset standard is too large, or it can be a local area where the area density does not meet the preset standard, or the deviation between the area density and the preset standard is too large. This application does not make special restrictions on the specific implementation method of the preset value, etc., and can directly adopt the preset standard or the IR Drop threshold specified by the preset standard. Figure 3 As shown, in Figure 2Based on the inspection results shown, you can use a rectangle to select the areas with serious violations (a) and (b), and then make layout adjustments for these two areas respectively.

[0087] It should be noted that, considering the inability to accurately determine the size of severely violating areas in actual circuit networks, after identifying these areas, they need to be further divided into several grids, and then the layout is adjusted on a grid-by-grid basis. Gridding clearly defines the shape and size of the target area, facilitating standardized layout adjustments. The size and shape of the grids can be defined and adjusted according to the actual application, for example, a 5µm × 5µm grid. The determination of severely violating areas is not limited to using a schematic diagram of the inspection results; it can also be achieved by calculating the IR drop at various points in the circuit network. This application does not impose any particular limitation on this method.

[0088] Furthermore, this application adjusts the layout on a unit basis, meaning that during layout adjustment, there is typically a one-to-one correspondence between a target region and a logical unit. There are multiple ways to establish this one-to-one correspondence. For example, when determining the target region, the grid size can be configured to be small during mesh generation, ensuring that only one logical unit exists per grid, thus establishing a one-to-one correspondence between the target region and the logical unit. If multiple logical units exist within a target region, the layout adjustment scheme can be determined based on one of these logical units. For instance, the logical unit corresponding to the base point used in calculating the region density of the target region can be used as the logical unit corresponding one-to-one with that target region, and the second force can be determined based on this logical unit. If a logical unit spans multiple grids (across target regions), its affiliation to the grids (target regions) can be defined according to specific criteria. These criteria include the area occupied by the logical unit in each grid and / or the cell density of each grid. The logical unit is assigned to the grid with the largest area; if the areas are the same, it is assigned to the grid with the highest cell density. Subsequently, the one-to-one correspondence between the target region and the logical units is determined based on the affiliation between the logical units and the grids (target regions). Logic units present in the target region are those belonging to that target region. After determining the layout adjustment scheme, the layout of a single logical unit can be adjusted based on the one-to-one correspondence between the target region and the logical units. If multiple logical units actually exist in the target region, their layouts can also be adjusted uniformly according to the determined layout adjustment scheme.

[0089] Specifically, the area requiring layout adjustment is effectively determined by judging the degree of violation, and the layout adjustment process of the entire area with serious violations is further divided into several grid-based layout adjustments, so that the final layout adjustment can be more refined and the accuracy and reliability of the layout adjustment plan can be improved.

[0090] In some embodiments, determining the first force based on the density gradient between the target region and the surrounding region includes:

[0091] Determine the area density of the area surrounding the target area; the area surrounding the target area includes a first adjacent area adjacent to the target area in the x direction and a second adjacent area adjacent to the target area in the y direction; the area density is the ratio between the area occupied by logical units in the area and the total available area of ​​the area;

[0092] Calculate the density gradient of the target region in the x-direction based on the regional density of the first neighboring region;

[0093] Calculate the density gradient of the target region in the y-direction based on the regional density of the second adjacent region;

[0094] The vector formed by the density gradient of the target region in the x-direction and the density gradient of the target region in the y-direction is converted into a force vector to obtain the first force.

[0095] In some embodiments, the first neighboring region includes a left neighboring region and a right neighboring region; calculating the density gradient of the target region in the x-direction based on the region density of the first neighboring region includes:

[0096] Determine the density difference between the region density of the left adjacent region and the region density of the right adjacent region;

[0097] Determine the distance difference in the x-direction between the reference point of the left adjacent region and the reference point of the right adjacent region;

[0098] The ratio between density difference and distance difference is determined as the density gradient of the target region in the x-direction.

[0099] It is easy to understand that this embodiment uses two-dimensional layout adjustment as an example to explain in detail the process of determining the first force. In order to push logic units from high-density areas to low-density areas and balance the layout density so that the wiring resources of the circuit network can meet the design rules of the process plant, the first force can be determined by determining the density gradient in vector form. Specifically, the first force... The expression is:

[0100] ;

[0101] in, Representing coordinates The ratio of the logical unit area to the available area. The sign indicates the density gradient, pointing in the direction of the fastest density increase. The negative sign indicates a negative gradient, which is used to specify that logic cells should move in the direction of decreasing density.

[0102] In the actual calculation of the first force, it needs to be determined based on the density of the target area and the surrounding area. After meshing the severely violated area, the density of each mesh can be directly calculated, that is, the ratio of the total area of ​​the cells in each mesh to the usable area. Then, the density gradient is calculated. For ease of calculation and representation, a base point is selected as the region coordinates for a target area. For region coordinates... For the target area, determine its first adjacent area, and the area coordinates corresponding to the two first adjacent areas are respectively and . This can be determined based on the grid size; determine its second adjacent region, and the region coordinates corresponding to the two second adjacent regions are respectively... and . and This can be determined based on the grid size; at this point, the density gradient of the target region in the x-direction is:

[0103] ;

[0104] The density gradient of the target region in the y-direction is calculated similarly to that in the x-direction, and will not be repeated here. The density gradient of the target region in the y-direction is:

[0105] ;

[0106] And ultimately, the direction of the first force is from the center of the high-density grid to the surrounding low-density area.

[0107] Specifically, the first force can be generated by the density vector corresponding to the unit density, so that the layout adjustment can effectively avoid local wiring congestion and wiring resource exhaustion in the circuit network, and effectively balance the layout density of the circuit network.

[0108] In some embodiments, converting the vector formed by the density gradient of the target region in the x-direction and the density gradient of the target region in the y-direction into a force vector includes:

[0109] The product of the density gradient of the target region in the x-direction and the step size coefficient is determined as the first component of the force vector in the x-direction;

[0110] The product of the density gradient of the target region in the y-direction and the step size coefficient is determined as the second component of the force vector in the y-direction.

[0111] Understandably, considering that the regional density is a dimensionless quantity and is usually expressed as a percentage, the calculated density gradient and the vector formed by the density gradient need to be further converted into a spatial distance value (i.e., a displacement) to obtain the final first force. Therefore, a step size factor can be pre-set, and based on the step size factor, the vector formed by the percentage density gradient can be converted into an actual physical displacement (e.g., from 1% / um → 0.01um). -1 (conversion), thus obtaining the first force. This application does not impose specific limitations on the specific value and implementation method of the step size coefficient, which can be set and adjusted according to the grid size, etc. If the grid size is relatively large, the step size coefficient will also be relatively large.

[0112] As a specific implementation, a square with a mesh size of 5um × 5um is used as an example. A certain region with coordinates (i,j) is taken as the target region. The first adjacent meshes are the meshes with coordinates (i-1,j) and (i+1,j), and the second adjacent meshes are the meshes with coordinates (i,j-1) and (i,j+1). One unit in the coordinate system represents 5um on the circuit network layout. The pre-calculated region density is 70% for mesh (i-1,j), 90% for mesh (i,j) (beyond the limit), 60% for mesh (i+1,j), 75% for mesh (i,j-1), and 80% for mesh (i,j+1). Based on this, the density gradient of the target region in the x-direction is calculated:

[0113] ;

[0114] Calculate the density gradient of the target region in the y-direction:

[0115] ;

[0116] Finally, the gradient vector The density gradient between the target region and its surrounding region is represented in this way. Then multiply by the step size factor. This is used to convert the gradient vector into a first force. Assume a step size coefficient. ,but:

[0117] .

[0118] Since the density of the adjacent area on the left is greater than that of the adjacent area on the right, the +x direction indicates moving to the right. Since the density of the adjacent area above is greater than that of the adjacent area below, the -y direction indicates moving downwards.

[0119] Specifically, by using a preset step size coefficient, the gradient vector is converted into the actual displacement, thereby obtaining a force vector that can effectively represent the direction and distance of movement during adjustment, which serves as the first force. This is closer to actual application scenarios, simple, effective, and easy to implement.

[0120] In some embodiments, determining the second force based on the power status of the logic cells in the target region includes:

[0121] Determine the voltage drop along the power supply path corresponding to the logic unit in the target area and the unit power consumption of the logic unit;

[0122] The magnitude of the second force is determined based on the relationship between the supply voltage drop and the preset voltage drop threshold, and the unit power consumption.

[0123] The direction of the second force is determined based on the distribution of power lines around the logic unit.

[0124] In some embodiments, determining the magnitude of the second force based on the relationship between the supply voltage drop and a preset voltage drop threshold and the unit power consumption includes:

[0125] If the voltage drop is less than or equal to the preset voltage drop threshold, the second force is set to zero;

[0126] If the supply voltage drop is greater than the preset voltage drop threshold, determine the absolute value of the difference between the supply voltage drop and the preset voltage drop threshold;

[0127] The maximum value among the absolute value and the minimum value excluding zero is determined as the denominator term;

[0128] The ratio between the unit power consumption and the denominator term is determined as the magnitude of the second force.

[0129] It is easy to understand that this embodiment uses two-dimensional layout adjustment as an example to explain in detail the process of determining the second force. In order to effectively reduce the voltage drop generated when supplying power to logic units in the target area, driving logic units, especially high-power logic units, closer to the power rail can effectively reduce the voltage drop. This can be achieved by determining the supply voltage drop on the power supply path corresponding to the logic unit in the current target area, the unit power consumption of the logic unit, and the distribution of power lines around the logic unit. Specifically, the second force... The expression is:

[0130] ;

[0131] in, The power consumption of the logic cells in the target region can be determined using Liberty files or power analysis tools, etc. This is the direction vector from the logic cell to the power line closest to the logic cell, used to characterize the direction of the second force. This refers to the voltage drop corresponding to the logic unit, that is, the voltage drop when the supply voltage reaches the current logic unit position (e.g., 5%). This information can be obtained using power integrity analysis tools, etc. Preset voltage drop threshold (e.g., 3%) (The unit power consumption is...) ; The switch activity factor (0~1) can be provided through switch activity analysis tools, etc. The load capacitor (including downstream logic units and interconnects during power supply). The supply voltage output by the power supply. This is the clock frequency.

[0132] In the actual calculation of the second force, the power supply network in the circuit network is first analyzed to obtain the voltage drop distribution diagram of the power supply network; at the same time, the power consumption of each logic unit is calculated, and the power consumption of each unit is mapped and marked on the corresponding region coordinates. In order to minimize the voltage drop when supplying power to the logic unit, the power supply line closest to the logic unit is used to supply power to the logic unit, and if If the voltage drop across the logic unit meets the standard, then the second force can be set to zero, meaning it will not move. If the voltage drop of the logic unit does not meet the standard, it means that the direction of the second force needs to be directed towards the nearest power line. In other words, the direction of the second force is determined by determining the direction vector. The magnitude of the second force is proportional to the unit's power consumption and the degree to which the voltage drop exceeds the standard. It is inversely proportional. This application does not impose any special restrictions on the specific value of the preset voltage drop threshold or its implementation method.

[0133] Specifically, The formula for calculating the denominator term that characterizes voltage drop sensitivity is as follows:

[0134] ;

[0135] in, This indicates the prevention of zero minimum quantity, with a typical value of 1×10. -6 This is used to avoid mathematical calculation crashes (if ΔV ≥ 0.000001, then the denominator = ΔV (normal calculation); if ΔV < 0.000001, then the denominator = 0.000001 (avoiding division by zero error).

[0136] As a specific embodiment, assume that a=0.1 for a logic unit in a certain target region. , If f = 1 GHz, then the unit power consumption is: Assume that the logical units in a certain target region... , ,but denominator =1%, voltage drop sensitivity = 1 / 1% = 100, which means the voltage drop sensitivity is 100.

[0137] Specifically, by combining the unit power consumption and the actual power supply voltage drop to form a directional pull force that couples power consumption and voltage drop as a second force, and by guiding high-power logic units closer to the power lines, IR drop is reduced, thereby ensuring the power integrity of the circuit network and avoiding problems such as timing failure or functional error of logic units due to insufficient voltage, thus minimizing the direct impact of voltage drop on logic units.

[0138] In some embodiments, determining the direction of the second force based on the power line distribution around the logic cell includes:

[0139] Determine the cell coordinates of the logic unit and the power line coordinates of several power lines surrounding the logic unit;

[0140] The Euclidean distance between each power line and the logic unit is determined based on the cell coordinates and the power line coordinates, respectively.

[0141] The power line coordinates corresponding to the minimum Euclidean distance are determined as the target direction of the second force.

[0142] It is understandable that the direction vector from a logic cell to the nearest power line can be obtained by finding the nearest power line to the logic cell and then using the direction vector (specifically, a unit direction vector) pointing from the logic cell to the corresponding nearest power line. This effectively guides the movement of the logic cell and reduces voltage drop. This application does not impose any special limitations on the method for determining the power lines of each logic cell. They can be determined directly based on the initial layout design. The power line coordinates are not limited to obtaining the coordinates of several power lines around the logic cell; they can also be obtained directly from the coordinates of all power lines in the circuit network, or several specific power lines can be selected according to the actual situation. This application does not impose any special limitations on this method.

[0143] As a specific implementation, taking the determination of the target direction of the second force using a unit direction vector as an example, firstly, the cell coordinates of the logic unit and the power line coordinates of several power lines are obtained by using placement and routing tools and executing specific commands. The cell coordinates of the logic unit are similar to the region coordinates of the target area; a base point on the logic unit is selected as the cell coordinates. Similarly, the power line coordinates are selected by choosing a base point on the power line. A preferred embodiment is to select the point on the power line closest to the logic unit as the base point of the power line. Then, the Euclidean distance from the logic unit to each power line is calculated, and the minimum value is taken. The specific calculation formula is as follows:

[0144] ;

[0145] Where i can be any positive integer from 1 to n (n is a positive integer), and the coordinates of the n power lines are respectively , … , These are the cell coordinates of the logic unit.

[0146] The power line corresponding to the minimum Euclidean distance is taken as the power line closest to the logic unit. Then, based on the coordinates of this power line closest to the logic unit and the unit coordinates of the logic unit, the vector difference of the direction vector is calculated. The difference in the x-direction between the coordinates of the power line closest to the logic unit and the unit coordinates of the logic unit is... And the difference in the y-direction between the power line coordinates of the power line closest to the logic cell and the cell coordinates of the logic cell. After determining the difference, normalization is performed to convert the vector size to unit length, and the vector direction points from the unit coordinates to the nearest power line.

[0147] Taking a 5um × 5um square grid as an example, assuming the cell coordinates of a certain logic cell are (10, 20)um and the coordinates of the power line closest to that logic cell are (15, 25)um, calculate the vector difference between them. Then, normalization is performed:

[0148] ;

[0149] Thus, the direction vector is finally obtained: the vector direction is from (10,20) to (15,25); the components of the vector in the x and y directions are (7.07,7.07).

[0150] Specifically, the voltage drop during logic cell power supply can be optimized by identifying the nearest power line, minimizing IR drop caused by excessively long power lines, and thus minimizing the impact of voltage drop on the logic cells.

[0151] See Figure 4 As shown, Figure 4 A schematic flowchart illustrating a circuit board layout optimization process provided by an embodiment of the present invention; in some embodiments, after adjusting the layout of the logic units corresponding to the target area according to the resultant force of the first force and the second force, the process further includes:

[0152] Perform voltage drop analysis on the circuit network after the layout adjustment;

[0153] If the voltage drop analysis result of the circuit network does not meet the preset standard, the process will jump back to the step of determining the target region in the circuit network until the voltage drop analysis result of the circuit network meets the preset standard.

[0154] It's easy to understand that in practical applications, the circuit network may have multiple target areas requiring layout optimization. For example, after identifying violation areas and dividing the network into meshes, each mesh within those meshes needs layout optimization. Therefore, the entire layout optimization process needs to be iteratively implemented until the voltage drop analysis results of the entire circuit network converge to a preset standard. The above embodiments describe the specific implementation process of a single layout optimization. Therefore, after a single layout optimization and adjustment, the voltage drop analysis of the adjusted circuit network needs to be performed again. Then, it is determined whether the voltage drop analysis results of the circuit network converge to the preset standard. If they do not converge to the preset standard, the target areas that do not meet the preset standard are re-optimized and adjusted until the voltage drop of the entire circuit network converges to the preset standard.

[0155] It should be noted that, considering the first force directly moves the physical distance, in this iteration process, in addition to setting a preset step size coefficient, it is also necessary to set an iteration step size for the first force to control the magnitude of the logic unit movement during each iteration optimization, preventing excessive movement distance from causing oscillations. This application does not impose specific limitations on the specific value and implementation method of the iteration step size; the specific value range can be 0.1~1.0µm.

[0156] Specifically, through continuous iterative layout optimization, it is possible to effectively ensure that the entire circuit network eventually reaches the preset standard, which is closer to the actual application scenario. At the same time, the single layout optimization process optimizes density and voltage drop at one time, which can effectively reduce the number of iterations and shorten the design cycle.

[0157] In some embodiments, adjusting the layout of the logic units corresponding to the target region according to the resultant force of the first force and the second force includes:

[0158] Assign a first weight to the first force and a second weight to the second force;

[0159] The resultant force of the first and second forces is determined based on the first and second weights.

[0160] Understandably, to achieve more flexible and controllable synergistic optimization of the first and second forces, weights can be configured for the first and / or second forces respectively. The combined force of the two forces is then obtained through the configured weights, and a trade-off between the dual objectives of density reduction and voltage drop reduction can be achieved through dynamic weight adjustments. For example, for chips using a 3nm process, the weight of the second force can be increased (e.g., increased to 0.6) during layout optimization to adapt to the advanced process requirements of the chip. This application does not impose specific limitations on the specific values ​​and implementation methods of the first and second weights.

[0161] Specifically, weights are configured and dynamically adjusted for the first and second forces respectively. The weight design achieves a dual-objective trade-off during layout optimization. The combined force of the two forces after weight configuration is used to move the logic unit. Thus, the synergistic optimization of density and voltage drop is used to effectively reduce or eliminate IR Drop.

[0162] In some embodiments, the process of determining the first weight specifically includes:

[0163] Determine the first ratio between the regional density and the permissible density of the target area;

[0164] The product of the cube of the first ratio and the preset density penalty base is determined as the first weight corresponding to the first force.

[0165] It's easy to understand that, for the first action force, a cubic penalty can be used to apply a nonlinear penalty to the over-density region, thereby avoiding local congestion (i.e., excessively high local logic unit density). The first action force corresponds to the first weight. The formula for calculation is:

[0166] ;

[0167] in, The density penalty base can be any value between 0 and 1, with a preferred embodiment having a value between 0.3 and 0.7. Increasing the size can enhance the density balance of the circuit network after layout optimization, therefore The value of can be dynamically updated and adjusted based on feedback during actual iterative optimization. In other words, the density penalty base can be adaptively adjusted according to the degree of density violations in the current circuit network layout, and dynamically increased when the degree of density violations in the circuit network is relatively large. ; This represents the region density of the current target region, which is also the percentage of logical unit area within the current target region. The target density, which is allowed by the current process, is generally 70% to 85%, and can be determined according to the DRC (Design Rule Check) rules of the process plant. The first weight is proportional to the cube of the degree to which the density of the target area exceeds the limit.

[0168] As a specific example, suppose a target area 90%, which is permissible by the process. 80%, If we take 0.5, then:

[0169] ;

[0170] It is evident that the density of the target area exceeds the limit by 12.5%, which is quite serious. With the first weight pre-configured as 0.5, the weight of the first force can be further increased to 0.71 to avoid the density from exceeding the limit.

[0171] Taking the 5um × 5um square grid from the above embodiment as an example, the grid with region coordinates (i,j) is taken as the target region, and the step size coefficient is... The gradient vector calculated based on the density gradient is multiplied by the first weight, the step size coefficient, and the iteration step size to finally obtain the movement vector under the first force in this layout optimization. Assuming the iteration step size... Then the movement vector for:

[0172] ;

[0173] Substituting the gradient vector obtained from the above embodiment... ,but:

[0174] ;

[0175] Therefore, under the action of the first force, the logic unit needs to move 0.71nm to the right (+) and 0.355nm down (-).

[0176] Specifically, by setting and dynamically adjusting the first weight, the optimization effect on the density balance objective can be effectively controlled during each layout optimization, and the dual objective trade-off can be achieved in conjunction with the second weight.

[0177] In some embodiments, the process of determining the second weight specifically includes:

[0178] Determine the difference between the supply voltage drop on the power supply path corresponding to the logic unit in the target area and the preset voltage drop threshold, and the second ratio between the preset voltage drop threshold and the target area;

[0179] Perform a function transformation on the second ratio;

[0180] The product of the result of the function transformation of the second ratio and the preset sensitivity coefficient is determined as the second weight corresponding to the second force.

[0181] Understandably, for the second force, soft threshold gating can be implemented using the Sigmoid function to achieve adaptive allocation of the second weight. The Sigmoid function smoothly activates the second weight, causing the voltage drop to gradually change around a preset voltage drop threshold. The second weight corresponds to the second force. The formula for calculation is:

[0182] ;

[0183] in, The preset sensitivity coefficient represents the sensitivity during voltage drop layout optimization. It can be any value between 0 and 1, with a preferred embodiment having a value between 0.2 and 0.5. Increasing the voltage drop can enhance the convergence of the optimized circuit network to a preset standard, therefore The value of can be dynamically updated and adjusted based on feedback during actual iterative optimization. In other words, the preset sensitivity coefficient can be adaptively adjusted according to the degree of voltage drop violation in the current circuit network layout, and dynamically increased when the voltage drop violation in the circuit network is relatively large. To improve the impact of the current layout optimization process on voltage drop control; The voltage drop supplied to the current logic unit. This is a preset voltage drop threshold. .

[0184] As a specific embodiment, suppose the current supply voltage drop of a logic cell in a certain target region is... The preset voltage drop threshold is 6%. 5%, If the value is 0.3, then:

[0185] ;

[0186] As can be seen, the voltage drop of the logic cell in the target area exceeds the standard by 20%, and the second weight is activated to 0.165 accordingly.

[0187] Specifically, by setting and dynamically adjusting the second weight, the optimization effect on the goal of converging the voltage drop to the preset standard can be effectively controlled each time the layout is optimized, and the dual-objective trade-off can be achieved in conjunction with the first weight.

[0188] As a specific embodiment, such as Figure 4 As shown, after performing parallel density and voltage drop analyses on the initial layout design, the first and second forces are obtained. Based on feedback results from local wiring congestion and voltage drop distribution, the corresponding first and second weights are dynamically calculated. Finally, the resultant force of the first and second forces is determined based on the first and second weights, and the final logic unit movement is achieved according to the calculated resultant force. Therefore, the actual movement vector for the final single layout optimization is... for:

[0189] ;

[0190] Assuming iteration step size Based on the above embodiment, taking a square with a mesh size of 5um × 5um as an example, the gradient vector and direction vector are determined as follows:

[0191] ;

[0192] That is, under the combined effect, the logic unit will move 8.18nm to the right in the x direction and 7.115nm upward in the y direction.

[0193] Furthermore, during actual layout optimization and adjustment, it is possible to... and Dynamic and coordinated adjustments can also be made separately. and Set boundary protection to prevent a single force from completely dominating the layout, for example, by setting... , Ultimately, dynamic adjustments are made to both based on this boundary protection. This application does not specifically limit the value or implementation method of the boundary protection. According to the above calculation process, after a single layout optimization, the positions of logic units in the corresponding target area can be moved, and an IR Drop check is performed again after the movement is complete. If the circuit network meets the IR Drop convergence to the preset standard, it is determined that the optimization adjustment of all violation areas on the circuit network has been completed, and the entire layout optimization process ends. If the circuit network does not meet the IR Drop convergence to the preset standard, the above process is repeated to recalculate the new positions of logic units in the same target area or another target area, and repeated layout optimization adjustments are performed until the circuit network meets the IR Drop convergence to the preset standard.

[0194] See Figure 5 As shown,Figure 5 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. To solve the above-mentioned technical problems, an embodiment of the present invention also provides an electronic device, comprising:

[0195] Memory 60 is used to store computer program 601;

[0196] Processor 61 is configured to execute a computer program to implement the steps of the circuit network layout optimization method as described above.

[0197] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 61 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0198] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 60 is used to store at least the following computer program 601, which, after being loaded and executed by the processor 61, is capable of implementing the relevant steps of the circuit network layout optimization method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. The operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, data in the circuit network layout optimization method.

[0199] In some embodiments, the electronic device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.

[0200] Those skilled in the art will understand that Figure 5 The structures shown do not constitute a limitation on electronic devices and may include more or fewer components than those shown.

[0201] For a description of the features in the electronic device provided in the embodiments of the present invention, please refer to the relevant description of the embodiments of the circuit network layout optimization method, which will not be repeated here.

[0202] To address the aforementioned technical problems, this invention also provides a circuit board, the circuit network on which is designed and generated based on the aforementioned circuit network layout optimization method. The circuit network layout optimization method can be applied in the design and manufacturing process of circuit boards to optimize and adjust the circuit layout on the board.

[0203] For a description of the features in the circuit board provided in the embodiments of the present invention, please refer to the relevant description of the embodiments of the circuit network layout optimization method, which will not be repeated here.

[0204] It is understood that if the circuit network layout optimization method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk, and other media capable of storing program code.

[0205] To address the aforementioned technical problems, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned circuit network layout optimization method.

[0206] For a description of the features in the computer-readable storage medium provided in the embodiments of the present invention, please refer to the relevant description of the embodiments of the circuit network layout optimization method, which will not be repeated here.

[0207] To address the aforementioned technical problems, embodiments of the present invention also provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the aforementioned circuit network layout optimization method.

[0208] For a description of the features in the computer program product provided in the embodiments of the present invention, please refer to the relevant description of the embodiments of the circuit network layout optimization method, which will not be repeated here.

[0209] The foregoing has provided a detailed description of a circuit network layout optimization method, electronic device, circuit board, and medium provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0210] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0211] The layout optimization method for circuit networks, electronic devices, circuit boards, and media provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A method for optimizing the layout of a circuit network, characterized in that, include: Determine the target region in the circuit network; The first force is determined based on the density gradient between the target region and the surrounding region. The direction of the first force is from the location with high regional density to the location with low regional density; The second force is determined based on the power status of the logic units in the target area; The layout of the logic units corresponding to the target region is adjusted according to the resultant force of the first force and the second force; Determining the first force based on the density gradient between the target region and the surrounding region includes: Determine the region density of the area surrounding the target region; the area surrounding the target region includes a first adjacent region adjacent to the target region in the x-direction and a second adjacent region adjacent to the target region in the y-direction; the region density is the ratio between the area occupied by logical units in the region and the total available area of ​​the region; Calculate the density gradient of the target region in the x-direction based on the regional density of the first adjacent region; The density gradient of the target region in the y-direction is calculated based on the regional density of the second adjacent region; The vector formed by the density gradient of the target region in the x-direction and the density gradient of the target region in the y-direction is converted into a force vector to obtain the first force. Determining the second force based on the power status of the logic units in the target region includes: Determine the voltage drop on the power supply path corresponding to the logic unit in the target area and the unit power consumption of the logic unit; The magnitude of the second force is determined based on the relationship between the supply voltage drop and the preset voltage drop threshold and the unit power consumption. The direction of the second force is determined based on the power line distribution around the logic unit; Adjusting the layout of the logic units corresponding to the target region based on the resultant force of the first force and the second force includes: Assign a first weight to the first force and a second weight to the second force; The resultant force of the first force and the second force is determined based on the first weight and the second weight.

2. The circuit network layout optimization method according to claim 1, characterized in that, Determining the target region in the circuit network includes: Identify regions in the circuit network where the violation level exceeds a preset value; The area with a violation level greater than the preset value is divided into several grids; Define one or more grids obtained from the division as the target region.

3. The circuit network layout optimization method according to claim 1, characterized in that, The first adjacent region includes a left adjacent region and a right adjacent region; calculating the density gradient of the target region in the x-direction based on the region density of the first adjacent region includes: Determine the density difference between the region density of the left adjacent region and the region density of the right adjacent region; Determine the distance difference in the x-direction between the reference point of the left adjacent region and the reference point of the right adjacent region; The ratio between the density difference and the distance difference is determined as the density gradient of the target region in the x-direction.

4. The circuit network layout optimization method according to claim 1, characterized in that, Converting the vector formed by the density gradient of the target region in the x-direction and the density gradient of the target region in the y-direction into a force vector includes: The product of the density gradient of the target region in the x-direction and the step size coefficient is determined as the first component of the force vector in the x-direction; The product of the density gradient of the target region in the y-direction and the step size coefficient is determined as the second component of the force vector in the y-direction.

5. The circuit network layout optimization method according to claim 1, characterized in that, The magnitude of the second force is determined based on the relationship between the supply voltage drop and the preset voltage drop threshold and the unit power consumption, including: If the voltage drop is less than or equal to a preset voltage drop threshold, the second force is determined to be zero; If the supply voltage drop is greater than the preset voltage drop threshold, determine the absolute value of the difference between the supply voltage drop and the preset voltage drop threshold; The maximum value among the absolute value and the minimum value excluding zero is determined as the denominator term; The ratio between the unit power consumption and the denominator term is determined as the magnitude of the second force.

6. The circuit network layout optimization method according to claim 1, characterized in that, Determining the direction of the second force based on the power line distribution around the logic unit includes: Determine the cell coordinates of the logic unit and the power line coordinates of several power lines surrounding the logic unit; The Euclidean distance between each power line and the logic unit is determined based on the unit coordinates and the power line coordinates, respectively. The power line coordinates corresponding to the minimum Euclidean distance are determined as the target direction of the second force.

7. The circuit network layout optimization method according to claim 1, characterized in that, After adjusting the layout of the logic units corresponding to the target region based on the resultant force of the first force and the second force, the method further includes: A voltage drop analysis was performed on the circuit network after the layout was adjusted. If the voltage drop analysis result of the circuit network does not meet the preset standard, the process jumps back to the step of determining the target region in the circuit network until the voltage drop analysis result of the circuit network meets the preset standard.

8. The circuit network layout optimization method according to claim 1, characterized in that, The process of determining the first weight specifically includes: Determine a first ratio between the regional density and the permissible density of the target region; The product of the cube of the first ratio and the preset density penalty base is determined as the first weight corresponding to the first force.

9. The circuit network layout optimization method according to claim 1, characterized in that, The process of determining the second weight specifically includes: Determine the difference between the supply voltage drop on the power supply path corresponding to the logic unit in the target area and a preset voltage drop threshold, and a second ratio between the preset voltage drop threshold; Perform a function transformation on the second ratio; The product of the result of the function transformation of the second ratio and the preset sensitivity coefficient is determined as the second weight corresponding to the second force.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the layout optimization method for circuit networks as described in any one of claims 1 to 9.

11. A circuit board, characterized in that, The circuit network on the circuit board is designed and generated by adjusting the layout optimization method of the circuit network according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the layout optimization method for circuit networks as described in any one of claims 1 to 9.

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