一种基于深度强化学习的抗辐照版图优化方法
By using a layout and routing optimization agent based on deep reinforcement learning to collaboratively optimize integrated circuit layouts, the problems of long cycle time and low efficiency in traditional methods are solved, and efficient and reliable radiation-resistant layout generation is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NORTHWESTERN POLYTECHNICAL UNIV
- Filing Date
- 2026-04-28
- Publication Date
- 2026-07-17
AI Technical Summary
Traditional EDA tools have long optimization cycles and numerous redundant iterations in FinFET process integrated circuit layout optimization. The separation of layout and routing leads to low optimization efficiency, making it difficult to meet the requirements of high reliability and radiation resistance.
A deep reinforcement learning-based approach is adopted to deploy a layout and routing optimization agent. Through global state awareness and hierarchical reward function, collaborative optimization of layout and routing is achieved. A circuit breaker mechanism is used to ensure process compliance and generate a layout that meets radiation resistance requirements.
Significantly shortens the optimization cycle, improves layout quality, meets radiation resistance indicators, increases optimization efficiency by more than 50%, achieves zero DRC violations, and has a 100% LVS verification pass rate.
Smart Images
Figure CN122113810B_ABST