Inquiry end circuit in vehicle ethernet network system

Abstract

The invention provides an interrogator circuit in an automotive Ethernet network system, comprising a hybrid circuit configured to communicate data with a responder circuit through a medium-dependent interface circuit; a transmit circuit coupled to the hybrid circuit and configured to generate and provide a transmit signal to the hybrid circuit; a receive circuit coupled to the hybrid circuit and configured to receive and parse a receive signal from the hybrid circuit to generate a data signal; a processing circuit coupled to the receive circuit and configured to process the data signal; a physical coding sublayer circuit coupled to the processing circuit and configured to perform a physical coding operation according to an instruction from the processing circuit to control operation of the transmit circuit; and an echo cancellation circuit coupled between the transmit circuit and the receive circuit and configured to generate an echo cancellation signal.

Description

Technical Field

[0001] This invention relates to automotive Ethernet communication technologies, and particularly to an interrogation circuit in an automotive Ethernet system. Background Technology

[0002] With technological advancements, the application of automotive Ethernet communication technology is becoming increasingly widespread, and the number of Ethernet communication devices installed in vehicles (such as various Ethernet communication chips) is also growing. According to the specifications of the automotive Ethernet communication protocol, two devices using the automotive Ethernet communication protocol must employ a full-duplex transmission mechanism for various data communications.

[0003] It is well known that full-duplex transmission mechanisms consume a significant amount of power. However, for many vehicles (especially electric vehicles), the power efficiency of automotive devices is a crucial performance indicator. Therefore, failure to effectively reduce the power consumption of automotive Ethernet communication devices will inevitably hinder the development of automotive Ethernet communication technology. Summary of the Invention

[0004] Therefore, how to reduce the power consumption of automotive Ethernet communication devices is a problem that needs to be solved.

[0005] This specification provides an embodiment of an interrogation circuit, comprising: a hybrid circuit configured to communicate data with an interrogated circuit via a media-dependent interface circuit; a transmission circuit coupled to the hybrid circuit, configured to generate and transmit a transmission signal to the hybrid circuit; a receiving circuit coupled to the hybrid circuit, configured to receive and parse a received signal transmitted from the hybrid circuit to generate a data signal; a processing circuit coupled to the receiving circuit, configured to process the data signal; a physical coding sublayer circuit coupled to the processing circuit, configured to perform physical coding operation according to the instructions of the processing circuit to control the operation of the transmission circuit; and an echo cancellation circuit coupled between the transmission circuit and the receiving circuit, configured to generate an echo cancellation signal.

[0006] One of the advantages of the above embodiments is that it can determine whether the queried circuit can support an asymmetric data mode.

[0007] Other advantages of the present invention will be explained in more detail with reference to the following description and drawings. Attached Figure Description

[0008] Figure 1 This is a simplified functional block diagram of an automotive Ethernet network system according to an embodiment of the present invention.

[0009] Figures 2 to 3 This is a simplified flowchart of an embodiment of the data communication method used in the vehicle Ethernet network system of the present invention.

[0010] Figure 4 The following is a simplified timing diagram of different embodiments of the asymmetric data mode of the present invention.

[0011] Symbol Explanation

[0012] 100...Automotive Ethernet system

[0013] 102, 104... twisted pair

[0014] 110...Inquirer-side circuit

[0015] 111... Medium dependent interface circuit (MDI circuit)

[0016] 112... Hybrid circuit

[0017] 113...Transmitting circuit

[0018] 114... Receiving circuit

[0019] 115...processing circuit

[0020] 116...Physical coding sublayer circuit

[0021] 117...Echo cancellation circuit

[0022] 120... Respondent-side circuit

[0023] 121...Media Dependent Interface Circuit (MDI circuit)

[0024] 122... Hybrid circuit

[0025] 123...transmitting circuit

[0026] 124... Receiving circuit

[0027] 125...processing circuit

[0028] 126...Physical coding sublayer circuit

[0029] 127...Echo cancellation circuit

[0030] Operation flow for lines 202-212, 302-314...

[0031] 410...First asymmetry data mode

[0032] 411, 421... Data transmission cycle

[0033] 413, 415, 423, 425... Data transmission period

[0034] 415...Data transmission period

[0035] 420...Second asymmetric data mode

[0036] Sd1, Sd2... data signals

[0037] Sr1, Sr2... received signals

[0038] St1, St2... transmission signals Detailed Implementation

[0039] The embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference numerals denote the same or similar elements or method flows.

[0040] Figure 1This is a simplified functional block diagram of an automotive Ethernet network system 100 according to an embodiment of the present invention. The automotive Ethernet network system 100 includes an interrogator circuit 110 and a queryee circuit 120. Various data communications can be performed between the interrogator circuit 110 and the queryee circuit 120.

[0041] like Figure 1 As shown, the interrogating circuit 110 includes a media-dependent interface circuit 111, a mixing circuit 112, a transmitting circuit 113, a receiving circuit 114, a processing circuit 115, a physical coding sublayer circuit 116, and an echo cancellation circuit 117. The interrogated circuit 120 includes a media-dependent interface circuit 121, a mixing circuit 122, a transmitting circuit 123, a receiving circuit 124, a processing circuit 125, a physical coding sublayer circuit 126, and an echo cancellation circuit 127.

[0042] In the interrogation circuit 110, the media-dependent interface circuit 111 is configured to be coupled to a twisted pair 102, and can transmit signals to the interrogated circuit 120 or receive signals from the interrogated circuit 120 through the twisted pair 102. The hybrid circuit 112 is configured to be coupled to the media-dependent interface circuit 111 to perform various data communications with the interrogated circuit 120 through the media-dependent interface circuit 111.

[0043] Transmitting circuit 113 is coupled to mixing circuit 112 and configured to generate and transmit a transmission signal St1 to mixing circuit 112. Receiving circuit 114 is coupled to mixing circuit 112 and configured to receive and parse a receive signal Sr1 from mixing circuit 112 to generate a data signal Sd1.

[0044] Processing circuit 115 is coupled to receiving circuit 114 and configured to process data signal Sd1 and control the operation of interrogation circuit 110. Physical encoding sublayer circuit 116 is coupled to processing circuit 115 and configured to perform physical encoding operation according to the instructions of processing circuit 115 to control the operation of transmission circuit 113.

[0045] Echo cancellation circuit 117 is coupled between the output of transmitting circuit 113 and the input of receiving circuit 114, and is configured to generate an echo cancellation signal based on the transmitted signal St1 to eliminate or reduce the echo component in the received signal Sr1. As is well known, when interrogation circuit 110 operates in full-duplex mode, transmitting circuit 113 and receiving circuit 114 operate simultaneously. In this case, the received signal Sr1 transmitted to receiving circuit 114 by mixing circuit 112 may contain an echo component corresponding to the transmitted signal St1 generated by transmitting circuit 113. Therefore, when transmitting circuit 113 and receiving circuit 114 operate simultaneously, echo cancellation circuit 117 is needed to generate an echo cancellation signal to eliminate or reduce the echo component in received signal Sr1, thereby improving the accuracy of the signal received by receiving circuit 114.

[0046] In the interrogated circuit 120, the media-dependent interface circuit 121 is configured to be coupled to a twisted pair 104 and can transmit signals to the interrogated circuit 110 via the twisted pair 104, or receive signals from the interrogated circuit 110 via the twisted pair 104. In one embodiment, the aforementioned twisted pair 102 and twisted pair 104 are the same twisted pair. In another embodiment, the aforementioned twisted pair 104 is indirectly connected to the twisted pair 102 via an intermediary circuit (e.g., an adapter, hub, or switch). The hybrid circuit 122 is configured to be coupled to the media-dependent interface circuit 121 to perform various data communications with the interrogated circuit 110 via the media-dependent interface circuit 121.

[0047] The transmitting circuit 123 is coupled to the mixing circuit 122 and is configured to generate and transmit a transmitting signal St2 to the mixing circuit 122. The receiving circuit 124 is coupled to the mixing circuit 122 and is configured to receive and parse a receiving signal Sr2 from the mixing circuit 122 to generate a data signal Sd2.

[0048] Processing circuit 125 is coupled to receiving circuit 124 and configured to process data signal Sd2 and control the operation of query end circuit 120. Physical encoding sublayer circuit 126 is coupled to processing circuit 125 and configured to perform physical encoding operation according to the instructions of processing circuit 125 to control the operation of transmission circuit 123.

[0049] Echo cancellation circuit 127 is coupled between the output of transmitting circuit 123 and the input of receiving circuit 124, and is configured to generate an echo cancellation signal based on the transmitted signal St2 to eliminate or reduce the echo component in the received signal Sr2. Similarly, when the queryed circuit 120 operates in full-duplex mode, transmitting circuit 123 and receiving circuit 124 operate simultaneously. In this case, the received signal Sr2 transmitted to receiving circuit 124 by mixing circuit 122 may contain an echo component corresponding to the transmitted signal St2 generated by transmitting circuit 123. Therefore, when transmitting circuit 123 and receiving circuit 124 operate simultaneously, echo cancellation circuit 127 is needed to generate an echo cancellation signal to eliminate or reduce the echo component in received signal Sr2, thereby improving the accuracy of the signal received by receiving circuit 124.

[0050] The different functional blocks in the aforementioned interrogation circuit 110 can be implemented using different circuits, or integrated into a single circuit or a single device. Similarly, the different functional blocks in the aforementioned query circuit 120 can be implemented using different circuits, or integrated into a single circuit or a single device. For the sake of brevity, Figure 1 Other circuits, components, and connections are omitted.

[0051] In practical applications, the roles played by the interrogating circuit 110 and the querying circuit 120 can be combined in various ways. For example, one of the interrogating circuit 110 and the querying circuit 120 can be an automotive central controller or a local circuit of the aforementioned automotive central controller; while the other can be an actuator of an automotive sensing device (e.g., tire pressure sensor, dashcam, reversing radar, voice detector, physiological feature sensor, air quality sensor, temperature sensor, etc.), an actuator of an automotive device (e.g., accelerator, brake, door, wiper, rearview mirror, sunroof, etc.), a local circuit of the aforementioned automotive sensing device, or a local circuit of the aforementioned actuator.

[0052] In the automotive Ethernet network system 100, the interrogating circuit 110 is configured to operate in an asymmetric data mode as described later in this specification. If the queried circuit 120 also supports the asymmetric data mode proposed in this specification, then the interrogating circuit 110 and the queried circuit 120 can use the asymmetric data mode proposed in this specification when communicating data, thereby obtaining many technical advantages.

[0053] However, whether the query circuit 120 supports the asymmetric data mode proposed in this specification is not determined by the manufacturer of the query circuit 110. For example, in some application scenarios, the query circuit 120 in the automotive Ethernet network system 100 is configured to support the asymmetric data mode proposed in this specification, but subsequently, due to various reasons such as circuit failure, maintenance, parts replacement, or parts update, the query circuit 120 may become unable to support the asymmetric data mode proposed in this specification. As another example, in other application scenarios, the query circuit 120 in the automotive Ethernet network system 100 may not support the asymmetric data mode proposed in this specification, but subsequently, due to various reasons such as parts replacement or parts update, the query circuit 120 may become able to support the asymmetric data mode proposed in this specification.

[0054] The interrogating circuit 110 can adjust the data communication method with the queried circuit 120 according to different conditions of the queried circuit 120. To achieve this, the interrogating circuit 110 can dynamically check whether the queried circuit 120 supports the asymmetric data mode proposed in this specification.

[0055] The following will be paired Figures 2 to 4 To further explain the operation of the vehicle Ethernet network system 100. Figures 2 to 3 This is a simplified flowchart of an embodiment of the data communication method used in the vehicle Ethernet network system 100 of the present invention. Figure 4 The following is a simplified timing diagram of different embodiments of the asymmetric data mode of the present invention.

[0056] exist Figures 2 to 3 In the flowchart, the process located in the field belonging to a specific device represents the process performed by that specific device. For example, the part marked in the "Interrogator Circuit" field is the process performed by the interrogator circuit 110; the part marked in the "Respondent Circuit" field is the process performed by the respondent circuit 120.

[0057] In order to establish an Ethernet link between the interrogating circuit 110 and the queried circuit 120, the interrogating circuit 110 and the queried circuit 120 will first perform a handshake procedure to exchange the information and / or parameters required to establish the link.

[0058] In this case, the interrogating circuit 110 and the querying circuit 120 will perform... Figure 2In process 202, either link synchronization (LinkSync) or auto-negotiation (NWay) is performed. Generally, the interrogating circuit 110 and the queried circuit 120 only need to perform one of these two operations in process 202: link synchronization or auto-negotiation. The manufacturer of the automotive Ethernet system 100 can pre-set whether the interrogating circuit 110 and the queried circuit 120 will perform link synchronization or auto-negotiation.

[0059] During synchronous operation or automatic negotiation, the transmitting circuit 113 of the interrogating circuit 110 transmits a handshake signal conforming to the automotive Ethernet communication protocol to the queried circuit 120, while the transmitting circuit 123 of the queried circuit 120 transmits a handshake signal conforming to the automotive Ethernet communication protocol to the interrogating circuit 110. On the other hand, the receiving circuit 114 of the interrogating circuit 110 receives the handshake signal from the queried circuit 120, and the receiving circuit 124 of the queried circuit 120 receives the handshake signal from the interrogating circuit 110.

[0060] After the interrogating circuit 110 and the queried circuit 120 complete the aforementioned connection synchronization operation or automatic negotiation operation, process 204 will be performed.

[0061] In process 204, the interrogating circuit 110 and the querying circuit 120 begin operating in a training mode to initiate a signal training operation. During operation, one of the interrogating circuit 110 and the querying circuit 120 can act as a master device, while the other can act as a slave device. In process 204, the master device can transmit training data signals to the slave device, and the slave device can perform timing recovery based on the training data signals transmitted from the master device to correct the frequency and / or phase of the slave device's internal operating clock, ensuring that the operating clocks of the master device and the slave device remain synchronized.

[0062] At this time, the processing circuit 115 in the interrogating circuit 110 controls the relevant circuits (e.g., mixing circuit 112, transmission circuit 113, receiving circuit 114, physical coding sublayer circuit 116, etc.) to perform signal training with the interrogated circuit 120. Similarly, the processing circuit 125 in the interrogated circuit 120 also controls the relevant circuits (e.g., mixing circuit 122, transmission circuit 123, receiving circuit 124, physical coding sublayer circuit 126, etc.) to perform signal training with the interrogating circuit 110.

[0063] In other words, the signal training operation performed by the interrogating circuit 110 and the queried circuit 120 can keep the working clocks of the interrogating circuit 110 and the queried circuit 120 synchronized.

[0064] As mentioned above, the interrogating circuit 110 can adjust the data communication method with the interrogated circuit 120 according to the different conditions of the interrogated circuit 120.

[0065] In this embodiment, in order to confirm whether the query circuit 120 supports the asymmetric data mode proposed in this specification, the query circuit 110 will also perform process 206 at an appropriate time point during the signal training operation.

[0066] In process 206, the entity encoding sublayer circuit 116 controls the transmission circuit 113 to generate an asymmetry mode identification signal, indicating that the interrogating circuit 110 supports an asymmetric data mode as described in this specification. In process 206, the transmission circuit 113 also transmits the asymmetry mode identification signal to the interrogated circuit 120 via the mixing circuit 112 and the media-dependent interface circuit 111.

[0067] The aforementioned asymmetric pattern recognition signal can be implemented using a signal containing a predetermined pattern or a signal having a predetermined format. Alternatively, the aforementioned asymmetric pattern recognition signal can also be implemented using a signal containing a predetermined value, a predetermined random code, a predetermined flag, and / or predetermined recognition data.

[0068] Next, the queried circuit 120 will proceed to process 208, while the querying circuit 110 will proceed to process 210.

[0069] In process 208, the receiving circuit 124 of the interrogated circuit 120 receives the asymmetric pattern recognition signal from the interrogating circuit 110 through the media-dependent interface circuit 121 and the hybrid circuit 122.

[0070] If the query-received circuit 120 supports the asymmetric data mode described in this specification, then the receiving circuit 124 should be able to correctly interpret the asymmetric mode recognition signal transmitted from the query-received circuit 110. In this case, the processing circuit 125 of the query-received circuit 120 can perform... Figure 3 In process 306. In other words, if the interrogated circuit 120 can interpret the asymmetric pattern recognition signal transmitted from the interrogating circuit 110 and can support the asymmetric data pattern proposed in this specification, then the processing circuit 125 will perform... Figure 3 In process 306, the entity encoding sublayer circuit 126 controls the transmission circuit 123 to generate a predetermined response signal, indicating that the queried circuit 120 can support an asymmetric data mode as described in this specification.

[0071] The aforementioned predetermined response signal can be implemented using a signal that includes a predetermined implementation method or a signal having a predetermined format. Alternatively, the aforementioned predetermined response signal can also be implemented using a signal that includes a predetermined target value, a predetermined target flag, and / or predetermined target data.

[0072] Additionally, in process 306, the transmission circuit 123 can also transmit the predetermined response signal to the interrogation circuit 110 via the hybrid circuit 122 and the media-related interface circuit 121.

[0073] Conversely, if the receiving circuit 124 cannot interpret the asymmetric pattern recognition signal transmitted from the interrogating circuit 110, or if the interrogated circuit 120 does not support the asymmetric data mode proposed in this specification, the processing circuit 125 of the interrogated circuit 120 will perform... Figure 3 Process 302 in the middle.

[0074] On the other hand, such as Figure 2 As shown, after transmitting the asymmetric pattern recognition signal to the query circuit 120, the query circuit 110 will proceed to process 210.

[0075] In process 210, the receiving circuit 114 of the interrogating circuit 110 continues to receive training data signals from the queried circuit 120 to continue signal training. Furthermore, the interrogating circuit 110 also determines, based on subsequent signals from the queried circuit 120, whether the queried circuit 120 can support the asymmetric data mode proposed in this specification.

[0076] If the receiving circuit 114 receives the aforementioned predetermined response signal from the query circuit 120 during the signal training operation between the interrogating circuit 110 and the query circuit 120, the processing circuit 115 can determine that the query circuit 120 can support the asymmetric data mode proposed in this specification.

[0077] For example, in this embodiment, if the query circuit 120 transmits the aforementioned predetermined response signal to the interrogating circuit 110 within a predetermined time period after the interrogating circuit 110 sends the aforementioned asymmetric pattern recognition signal, then the processing circuit 115 of the interrogating circuit 110 can determine that the query circuit 120 can support the asymmetric data mode proposed in this specification. The aforementioned predetermined time period may be the time period required to receive a predetermined number of signals.

[0078] Conversely, if the query circuit 120 does not transmit a predetermined response signal to the query circuit 110 within the aforementioned predetermined time period, the processing circuit 115 of the query circuit 110 will determine that the query circuit 120 cannot support the asymmetric data mode proposed in this specification.

[0079] For example, after the transmission circuit 113 transmits an asymmetric pattern recognition signal to the query circuit 120, the processing circuit 115 can begin calculating the number of signals transmitted by the query circuit 120. If the receiving circuit 114 receives a predetermined response signal from the query circuit 120 before receiving a predetermined number of signals, the processing circuit 115 will perform... Figure 3 In process 310, it is determined that the queried circuit 120 can support the asymmetric data mode proposed in this specification.

[0080] Conversely, if the receiving circuit 114 receives a predetermined number of signals but still does not receive the predetermined response signal from the query circuit 120, the processing circuit 115 will perform... Figure 2 In process 212, it is determined that the queried circuit 120 cannot support the asymmetric data mode proposed in this specification, and then proceeds to... Figure 3 Process 302 in the middle.

[0081] In practice, the aforementioned predetermined time length can also be changed to a fixed time length, such as 0.5 seconds, 1 second, 1.5 seconds, 2.0 seconds, 2.5 seconds, 3.0 seconds, etc.

[0082] In process 302, the interrogating circuit 110 and the queryed circuit 120 continue the signal training operation that is not yet completed. At this time, the processing circuit 115 controls the interrogating circuit 110 to continue the signal training operation with the queryed circuit 120, and the processing circuit 125 also controls the queryed circuit 120 to continue the signal training operation with the interrogating circuit 110. In other words, the action of the interrogating circuit 110 transmitting the asymmetric pattern recognition signal to the queryed circuit 120 is performed during the signal training operation between the interrogating circuit 110 and the queryed circuit 120.

[0083] After the interrogating circuit 110 and the queried circuit 120 complete the signal training operation in process 302, the interrogating circuit 110 and the queried circuit 120 will proceed to process 304 to operate in a conventional symmetry data mode. According to the specifications of conventional automotive Ethernet communication protocols, the aforementioned symmetry data mode is a full-duplex mode.

[0084] In other words, in process 304, the interrogating circuit 110 can simultaneously perform data transmission and data reception. Similarly, the querying circuit 120 can also simultaneously perform data transmission and data reception. Therefore, the interrogating circuit 110 and the querying circuit 120 can simultaneously transmit data to each other and simultaneously receive data transmitted from each other.

[0085] As mentioned above, if the query-received circuit 120 can interpret the asymmetric pattern recognition signal transmitted by the interrogating circuit 110 and can support the asymmetric data mode proposed in this specification, then the query-received circuit 120 will perform... Figure 3 In process 306, a predetermined response signal representing that the queried circuit 120 can support an asymmetric data mode is transmitted to the interrogating circuit 110.

[0086] In this case, the receiving circuit 114 of the interrogating circuit 110 will perform process 308 to receive the predetermined response signal from the interrogated circuit 120 through the media-related interface circuit 111 and the hybrid circuit 112.

[0087] As can be seen from the foregoing description, if the receiving circuit 114 receives a predetermined response signal from the query circuit 120 within a predetermined time period after the interrogating circuit 110 sends the asymmetric pattern recognition signal, the processing circuit 115 of the interrogating circuit 110 will proceed to process 310 to determine that the query circuit 120 can support the asymmetric data mode proposed in this specification, and then proceed to process 312.

[0088] In process 312, the interrogating circuit 110 and the queryed circuit 120 continue the signal training operation that is not yet completed. At this time, the processing circuit 115 controls the interrogating circuit 110 to continue the signal training operation with the queryed circuit 120, and the processing circuit 125 also controls the queryed circuit 120 to continue the signal training operation with the interrogating circuit 110. In other words, the action of the queryed circuit 120 sending a predetermined response signal to the interrogating circuit 110 is performed during the signal training operation between the interrogating circuit 110 and the queryed circuit 120.

[0089] After the interrogating circuit 110 and the queried circuit 120 complete the signal training operation in process 312, the interrogating circuit 110 and the queried circuit 120 can proceed to process 314.

[0090] In process 314, the interrogating circuit 110 and the interrogated circuit 120 can operate in an asymmetric data mode as described in this specification to perform various data communications between them.

[0091] Please note that the asymmetric data mode proposed in this specification is not the data mode specified by the traditional automotive Ethernet communication protocol, and therefore is not a full-duplex mode.

[0092] For example, Figure 4 Simplified timing diagrams of two different embodiments of the asymmetric data modes of the present invention are shown, including a timing diagram of a first asymmetric data mode 410 and a timing diagram of a second asymmetric data mode 420.

[0093] In the first asymmetric data mode 410, each data transmission cycle 411 includes a first data transmission period 413, a second data transmission period 415, and several other period segments. The first data transmission period 413 and the second data transmission period 415 do not overlap, and the duration of the first data transmission period 413 is greater than the duration of the second data transmission period 415. The duration of the first data transmission period 413 can be 2 times, 2.5 times, 3 times, or more than 3 times the duration of the second data transmission period 415.

[0094] In the second asymmetric data mode 420, each data transmission cycle 421 includes a first data transmission period 423, a second data transmission period 425, and several other period segments. The first data transmission period 423 and the second data transmission period 425 do not overlap, and the duration of the first data transmission period 423 is less than the duration of the second data transmission period 425. The duration of the second data transmission period 425 can be 2 times, 2.5 times, 3 times, or more than 3 times the duration of the first data transmission period 423.

[0095] In one embodiment, the interrogating circuit 110 and the querying circuit 120 are operable in a first asymmetric data mode 410. In this case, the transmission circuit 113 of the interrogating circuit 110 transmits data to the querying circuit 120 during the first data transmission period 413, but not during the second data transmission period 415. On the other hand, the transmission circuit 123 of the querying circuit 120 transmits data to the interrogating circuit 110 during the second data transmission period 415, but not during the first data transmission period 413.

[0096] In the first asymmetric data mode 410, to match the data transmission timing of the query circuit 120, the receiving circuit 114 of the query circuit 110 receives data from the query circuit 120 during the second data transmission period 415, but does not receive data from the query circuit 120 during the first data transmission period 413. Conversely, to match the data transmission timing of the query circuit 110, the receiving circuit 114 of the query circuit 120 receives data from the query circuit 110 during the first data transmission period 413, but does not receive data from the query circuit 110 during the second data transmission period 415.

[0097] In other words, the data transmission and data reception periods of the querying circuit 110 are staggered and do not overlap. Similarly, the data transmission and data reception periods of the queryed circuit 120 are also staggered and do not overlap.

[0098] In another embodiment, the interrogating circuit 110 and the querying circuit 120 are operable in a second asymmetric data mode 420. In this case, the transmission circuit 113 of the interrogating circuit 110 transmits data to the querying circuit 120 during the second data transmission period 425, but not during the first data transmission period 423. On the other hand, the transmission circuit 123 of the querying circuit 120 transmits data to the interrogating circuit 110 during the first data transmission period 423, but not during the second data transmission period 425.

[0099] In the second asymmetric data mode 420, to match the data transmission timing of the query circuit 120, the receiving circuit 114 of the query circuit 110 receives data from the query circuit 120 during the first data transmission period 423, but does not receive data from the query circuit 120 during the second data transmission period 425. Conversely, to match the data transmission timing of the query circuit 110, the receiving circuit 114 of the query circuit 120 receives data from the query circuit 110 during the second data transmission period 425, but does not receive data from the query circuit 110 during the first data transmission period 423.

[0100] As can be seen from the foregoing description, neither the first asymmetric data mode 410 nor the second asymmetric data mode 420 is a full-duplex mode as specified by the traditional automotive Ethernet communication protocol.

[0101] In applications where the amount of data to be transmitted by the interrogating circuit 110 is greater than that of the queried circuit 120, the interrogating circuit 110 and the queried circuit 120 can operate in the first asymmetric data mode 410 in process 314 to improve data transmission efficiency.

[0102] Conversely, in applications where the amount of data to be transmitted by the query circuit 120 is greater than that of the query circuit 110, the query circuit 110 and the query circuit 120 can operate in the second asymmetric data mode 420 in process 314 to improve data transmission efficiency.

[0103] During operation, the interrogating circuit 110 and the interrogated circuit 120 can also dynamically switch between the aforementioned first asymmetric data mode 410 and second asymmetric data mode 420 when the amount of data transmitted between them changes significantly.

[0104] In practical applications, the amount of data that needs to be transmitted between the interrogating circuit 110 and the queried circuit 120 in the automotive Ethernet network system 100 is often unequal, and may even differ significantly. Therefore, if the interrogating circuit 110 adopts the aforementioned process... Figure 2 and Figure 3 The confirmation mechanism determines that the queried circuit 120 can support the asymmetric data mode proposed in this specification, and the asymmetric data mode proposed in this specification can be used to replace the traditional symmetric data mode.

[0105] In this way, not only can the data transmission efficiency between the interrogator circuit 110 and the query circuit 120 be greatly improved, but the bandwidth utilization between the interrogator circuit 110 and the query circuit 120 can also be effectively improved.

[0106] Furthermore, as mentioned earlier, when the transmitting circuit 113 and the receiving circuit 114 in the interrogating circuit 110 operate simultaneously, the echo cancellation circuit 117 is needed to generate an echo cancellation signal to improve the accuracy of the signal received by the receiving circuit 114. Similarly, when the transmitting circuit 123 and the receiving circuit 124 in the interrogated circuit 120 operate simultaneously, the echo cancellation circuit 127 is needed to generate an echo cancellation signal to improve the accuracy of the signal received by the receiving circuit 124.

[0107] However, as can be seen from the foregoing description, when the interrogating circuit 110 and the querying circuit 120 operate in the asymmetric data mode proposed in this specification (e.g., the aforementioned first asymmetric data mode 410 or second asymmetric data mode 420), the transmitting circuit 113 and the receiving circuit 114 in the interrogating circuit 110 will not operate simultaneously, and the transmitting circuit 123 and the receiving circuit 124 in the querying circuit 120 will not operate simultaneously either.

[0108] Therefore, when the interrogator circuit 110 operates in asymmetric data mode, the echo cancellation circuit 117 in the interrogator circuit 110 can be temporarily shut down, causing the echo cancellation circuit 117 to stop operating. Similarly, when the queryee circuit 120 operates in asymmetric data mode, the echo cancellation circuit 127 in the queryee circuit 120 can be temporarily shut down, causing the echo cancellation circuit 127 to stop operating. In this way, the power consumption of both the interrogator circuit 110 and the queryee circuit 120 can be effectively saved.

[0109] Clearly, the aforementioned interrogating circuit 110 dynamically checks whether the queried circuit 120 supports the asymmetric data mode proposed in this specification, and can adjust the data communication method with the queried circuit 120 according to different conditions of the queried circuit 120. This mechanism allows the interrogating circuit 110 to have greater application flexibility in operating with different queried circuits.

[0110] Furthermore, during the signal training operation between the interrogating circuit 110 and the querying circuit 120, the signals (e.g., training data signals and asymmetric pattern recognition signals) that the interrogating circuit 110 needs to transmit to the querying circuit 120 can be encrypted by the transmission circuit 113, processing circuit 115, or physical encoding sublayer circuit 116 before being transmitted to the querying circuit 120. Similarly, the signals (e.g., training data signals and predetermined response signals) that the querying circuit 120 needs to transmit to the interrogating circuit 110 can also be encrypted by the transmission circuit 123, processing circuit 125, or physical encoding sublayer circuit 126 before being transmitted to the interrogating circuit 110.

[0111] In this way, it becomes difficult for other devices or malicious individuals to intercept or identify the asymmetric pattern recognition signal transmitted from the interrogating circuit 110 to the querying circuit 120, nor is it easy to intercept or identify the predetermined response signal transmitted from the querying circuit 120 to the interrogating circuit 110. Therefore, the aforementioned approach ensures data security when the asymmetric pattern recognition signal and the predetermined response signal are transmitted between the interrogating circuit 110 and the querying circuit 120.

[0112] Certain terms are used in the specification and claims to refer to specific elements, and those skilled in the art may use different terms to refer to the same element. This specification and claims do not distinguish elements by differences in name, but rather by differences in function. The term "comprising" in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". Furthermore, the term "coupled" herein includes any direct and indirect connection means. Therefore, if the text describes a first circuit coupled to a second circuit, it means that the first circuit can be directly connected to the second circuit via electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly electrically or signal-connected to the second circuit via other devices or connection means.

[0113] The use of "and / or" in this specification includes any combination of one or more of the listed items. Furthermore, unless otherwise specified in this specification, any singular term also includes the meaning of the plural form.

[0114] The above are merely preferred embodiments of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims

1. An interrogation circuit (110), comprising: A hybrid circuit (112) is configured to communicate data with a query terminal circuit (120) via a media-dependent interface circuit (111); A transmission circuit (113) is coupled to the hybrid circuit (112) and configured to generate and transmit a transmission signal (St1) to the hybrid circuit (112); A receiving circuit (114) is coupled to the mixing circuit (112) and configured to receive and parse a received signal (Sr1) transmitted from the mixing circuit (112) to generate a data signal (Sd1). A processing circuit (115) is coupled to the receiving circuit (114) and configured to process the data signal (Sd1); A physical encoding sublayer circuit (116), coupled to the processing circuit (115), is configured to perform a physical encoding operation according to the instructions of the processing circuit (115) to control the operation of the transmission circuit (113); and An echo cancellation circuit (117) is coupled between the transmitting circuit (113) and the receiving circuit (114) and is configured to generate an echo cancellation signal.

2. The interrogation terminal circuit (110) as described in claim 1, wherein, During a signal training operation between the interrogating circuit (110) and the queried circuit (120), if the receiving circuit (114) receives a predetermined response signal from the queried circuit (120), the processing circuit (115) will determine that the queried circuit (120) can support an asymmetric data mode.

3. The interrogation terminal circuit (110) as described in claim 2, wherein, After the processing circuit (115) determines that the query circuit (120) can support the asymmetric data mode, the processing circuit (115) will control the query circuit (110) to continue to perform the signal training operation with the query circuit (120).

4. The interrogation terminal circuit (110) as described in claim 3, wherein, After the interrogating circuit (110) and the interrogated circuit (120) complete the signal training operation, the processing circuit (115) controls the interrogating circuit (110) to operate in the asymmetric data mode.

5. The interrogation circuit (110) as described in claim 4, wherein, When the interrogation circuit (110) operates in the asymmetric data mode, the echo cancellation circuit (117) will stop operating.

6. The interrogation circuit (110) as described in claim 4, wherein, When the interrogating circuit (110) operates in the asymmetric data mode, the transmitting circuit (113) transmits data to the interrogated circuit (120) during a first data transmission period (413), and the receiving circuit (114) receives data from the interrogated circuit (120) during a second data transmission period (415). The first data transmission period (413) and the second data transmission period (415) do not overlap. The transmitting circuit (113) will not transmit data to the query circuit (120) during the second data transmission period (415), and the receiving circuit (114) will not receive data from the query circuit (120) during the first data transmission period (413).

7. The interrogation terminal circuit (110) as described in claim 6, wherein, The first data transmission period (413) and the second data transmission period (415) have different durations.

8. The interrogation terminal circuit (110) as described in claim 2, wherein, During the signal training operation between the interrogating circuit (110) and the queried circuit (120), the entity coding sublayer circuit (116) controls the transmission circuit (113) to generate an asymmetric pattern recognition signal representing that the interrogating circuit (110) can support the asymmetric data mode, and transmits the asymmetric pattern recognition signal to the queried circuit (120) through the hybrid circuit (112) and the media related interface circuit (111).

9. The interrogation terminal circuit (110) as described in claim 8, wherein, After the interrogating circuit (110) transmits the asymmetric pattern recognition signal to the queried circuit (120), if the receiving circuit (114) receives a predetermined number of signals from the queried circuit (120) but still does not receive a predetermined response signal from the queried circuit (120), the processing circuit (115) will determine that the queried circuit (120) cannot support the asymmetric data mode.

10. The interrogation terminal circuit (110) as described in claim 9, wherein, After the processing circuit (115) determines that the query circuit (120) cannot support the asymmetric data mode, the processing circuit (115) will control the query circuit (110) to continue the signal training operation with the query circuit (120). After the query circuit (110) and the query circuit (120) complete the signal training operation, the processing circuit (115) will control the query circuit (110) to operate in a symmetric data mode.

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