A method for manufacturing a semiconductor structure, a semiconductor structure, and an electronic device
By introducing a metal-oxide-semiconductor transition layer into the DRAM structure and performing thermal annealing, the problem of capacitor interface defects was solved, and the stability and durability of the structure were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2026-04-20
- Publication Date
- 2026-07-31
AI Technical Summary
The current DRAM structure suffers from numerous interface defects in the capacitor fabrication process, leading to structural performance degradation.
Before and/or after the formation of the dielectric layer, a transition layer of metal oxide semiconductor material is introduced, and its conductivity is improved by thermal annealing process. The transition layer is formed to reduce interface defect states and acts as a buffer layer to bear interface stress.
It improves the diffusion between the electrode layer and the dielectric layer, reduces interface defects, and enhances the lifespan, durability, and stability of the semiconductor structure.
Smart Images
Figure CN122121156B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, and an electronic device. Background Technology
[0002] With the development and advancement of technology, the size of semiconductor devices is becoming smaller and smaller, and semiconductor devices are constantly developing towards miniaturization and high integration. Dynamic random access memory (DRAM), as a semiconductor device that allows for high-speed, random writing and reading of data, is widely used in data storage devices or apparatuses.
[0003] DRAM structures typically use capacitors to store information. Although the manufacturing process is relatively mature, there are still many problems with capacitor structures in actual operation that need to be improved. Summary of the Invention
[0004] This disclosure provides a method for fabricating a semiconductor structure, including: Form the first electrode layer; A dielectric layer is formed, the dielectric layer covering at least a portion of the surface of the first electrode layer; A second electrode layer is formed, which covers the surface of the dielectric layer; The preparation method further includes: forming a transition layer before and / or after forming the dielectric layer, the transition layer being located between at least one of the first electrode layer and the second electrode layer and the dielectric layer; Forming the transition layer includes: A transition material layer is formed, wherein the material of the transition material layer includes a metal oxide semiconductor material; A thermal annealing process is performed on the transition material layer to form the transition layer, wherein the electrical conductivity of the material in the transition material layer increases after the thermal annealing process.
[0005] In some embodiments, after the thermal annealing process, the oxygen vacancy concentration of the transition material layer increases.
[0006] In some embodiments, forming the transition layer includes: A first transition material layer is formed, wherein the first transition material layer is located between at least one of the first electrode layer and the second electrode layer and the dielectric layer; The first transition material layer is etched to remove a portion of the first transition material layer to form a groove structure along a first horizontal direction and on the side of the first transition material layer adjacent to the second electrode layer. The groove structure is spaced apart from the remaining first transition material layer. A second transition material layer is formed, and the second transition material layer fills the groove structure; Perform a thermal annealing process to form the transition layer; The material of the first transition material layer includes a metal oxide semiconductor material, and the electrical conductivity of the material of the first transition material layer increases after the thermal annealing process.
[0007] In some embodiments, the temperature range for performing the thermal annealing process is between 350°C and 450°C. And / or, The time range for performing the hot annealing process is between 30 seconds and 3 minutes. And / or, The atmosphere for performing the thermal annealing process is at least one of nitrogen or hydrogen.
[0008] In some embodiments, the metal oxide semiconductor material includes at least one of In-Zn oxides, In-Ga-Zn oxides, In-Sn-Zn oxides, Zn-In-Sn oxides, Si-In-Zn oxides, Al-Zn oxides, Ga-Zn oxides, In-Ga oxides, Zn-Sn-Al oxides, Sn-Zn oxides, In-Al-Zn oxides, Sn-Ga-Zn oxides, and Al-Ga-Zn oxides.
[0009] This disclosure also provides a semiconductor structure, the semiconductor structure comprising: First electrode layer; A dielectric layer is located on the first electrode layer and covers at least a portion of the surface of the first electrode layer; The second electrode layer covers the surface of the dielectric layer and is located on the side of the dielectric layer away from the first electrode; A transition layer is located between at least one of the first electrode layer and the second electrode layer and the dielectric layer; wherein the material of the transition layer includes at least a thermally annealed metal oxide semiconductor material.
[0010] In some embodiments, the electrical conductivity of the transition layer material is in the range of 10. 2 S / cm~10 5 Between S / cm.
[0011] In some embodiments, the transition layer includes a first transition layer and a second transition layer, which are located along a first horizontal direction and on the side of the transition layer adjacent to the second electrode layer, and the first transition layer and the second transition layer are spaced apart. The material of the first transition layer includes a metal oxide semiconductor material that has undergone thermal annealing.
[0012] In some embodiments, the first electrode layer is columnar, the dielectric layer covers the top and side surfaces of the first electrode layer, and the second electrode layer covers the surface of the dielectric layer.
[0013] In some embodiments, the first electrode layer is cylindrical, the dielectric layer covers the top surface, inner surface and outer surface of the first electrode layer, and the second electrode layer covers the surface of the dielectric layer.
[0014] In some embodiments, the first electrode layer extends along a first direction, the dielectric layer covers the surface of the first electrode layer, and the second electrode layer covers the surface of the dielectric layer; Wherein, the first direction is parallel to either the first horizontal direction or the first vertical direction.
[0015] In some embodiments, the semiconductor structure further includes a transistor structure, wherein, in a top view, the structure formed by the first electrode layer, the dielectric layer, the second electrode layer, and the transition layer is disposed adjacent to at least a portion of the transistor structure along a first horizontal direction or a vertical direction; The transistor structure includes one of a planar transistor, a vertical transistor, a buried transistor, or a three-dimensional stacked transistor.
[0016] In some embodiments, the metal oxide semiconductor material includes at least one of In-Zn oxides, In-Ga-Zn oxides, In-Sn-Zn oxides, Zn-In-Sn oxides, Si-In-Zn oxides, Al-Zn oxides, Ga-Zn oxides, In-Ga oxides, Zn-Sn-Al oxides, Sn-Zn oxides, In-Al-Zn oxides, Sn-Ga-Zn oxides, and Al-Ga-Zn oxides.
[0017] This disclosure also provides an electronic device, which includes a semiconductor structure formed by the preparation method described in any of the above embodiments, or the electronic device includes a semiconductor structure as described in any of the above embodiments.
[0018] This disclosure provides a method for fabricating a semiconductor structure, a semiconductor structure, and an electronic device. In this disclosure, a transition material layer comprising a metal oxide semiconductor material is formed before and / or after the formation of a dielectric layer. After annealing, the transition material layer forms a transition layer with increased conductivity. This transition layer is located between at least one of the first electrode layer and the second electrode layer and the dielectric layer. By specifically designing the material, location, and formation process of the transition layer, it is beneficial to improve the diffusion between the material contained in the electrode layer (at least one of the first electrode layer or the second electrode layer) and the material contained in the dielectric layer, reducing interface defect states. Furthermore, the presence of the transition layer can also act as a buffer layer to absorb interface stress. Simultaneously, since the interface defect states are significantly reduced after the thermal annealing process, it is beneficial to form a less defective and more stable bonding surface between the transition layer and the dielectric layer. Compared to the direct contact between the dielectric layer and the electrode layer, which can lead to mutual diffusion, numerous defects, and reactions that easily cause structural functional degradation, the technical solution provided by this disclosure improves the lifespan, durability, and stability of the semiconductor structure.
[0019] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description
[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 2 This is one of the structural schematic diagrams of the capacitor structure provided in an embodiment of the present disclosure during the fabrication process; wherein, Figure 2 Figures (1) and (2) are schematic diagrams of the structure during the formation of the first electrode layer and the transition material layer provided in different embodiments; Figure 3 This is a second schematic diagram of the capacitor structure provided in an embodiment of the present disclosure during the fabrication process. Figure 4 This is the third schematic diagram of the capacitor structure provided in one embodiment of the present disclosure during the fabrication process; Figure 5 One of the schematic diagrams of the capacitor structure provided in different embodiments of this disclosure during the fabrication process; Figure 6 A second schematic diagram of the capacitor structure provided in different embodiments of this disclosure during the fabrication process; Figure 7 The third schematic diagram of the capacitor structure provided in different embodiments of this disclosure during the fabrication process; Figure 8 This is one of the structural schematic diagrams of the capacitor structure provided in another embodiment of the present disclosure during the fabrication process; Figure 9 This is a second schematic diagram of the capacitor structure during the fabrication process, provided in another embodiment of this disclosure. Figure 10 This is the third schematic diagram of the capacitor structure during the fabrication process, provided in another embodiment of this disclosure. Figure 11 This is one of the structural schematic diagrams of the capacitor structure provided in another embodiment of the present disclosure during the fabrication process; Figure 12 A second schematic diagram of the capacitor structure during the fabrication process, provided in yet another embodiment of this disclosure; Figure 13 This is a schematic diagram of the capacitor structure during the fabrication process provided in another embodiment of the present disclosure; Figure 14 One of the schematic diagrams of the capacitor structure during the fabrication process provided in yet another embodiment of this disclosure; Figure 15 A second schematic diagram of the capacitor structure during the fabrication process, which is another embodiment of this disclosure. Figure 16 One of the schematic diagrams of the capacitor structure provided in different embodiments of this disclosure during the fabrication process; Figure 17 A second schematic diagram of the capacitor structure provided in different embodiments of this disclosure during the fabrication process; Figure 18 The third schematic diagram of the capacitor structure provided in different embodiments of this disclosure during the fabrication process; Figure 19 This is one of the structural schematic diagrams of the capacitor structure provided in another embodiment of the present disclosure during the fabrication process; Figure 20 A second schematic diagram of the capacitor structure during the fabrication process, provided in yet another embodiment of this disclosure; Figure 21 One of the schematic diagrams of the capacitor structure provided in different embodiments of this disclosure during the fabrication process; Figure 22 A second schematic diagram of the capacitor structure provided in different embodiments of this disclosure during the fabrication process; Figure 23The third schematic diagram of the capacitor structure provided in different embodiments of this disclosure during the fabrication process; Figure 24 This is one of the structural schematic diagrams of the capacitor structure provided in another embodiment of the present disclosure during the fabrication process; Figure 25 This is a second schematic diagram of the capacitor structure during the fabrication process, provided in another embodiment of this disclosure. Figure 26 One of the schematic diagrams of the capacitor structure provided in different embodiments of this disclosure during the fabrication process; Figure 27 A second schematic diagram of the capacitor structure provided in different embodiments of this disclosure during the fabrication process; Figure 28 One of the schematic diagrams of a transistor structure provided in different embodiments of this disclosure; Figure 29 A second schematic diagram of a transistor structure provided in different embodiments of this disclosure; Figure 30 A third schematic diagram of the transistor structure provided in different embodiments of this disclosure; Figure 31 Fourth schematic diagram of the transistor structure provided in different embodiments of this disclosure; Figure 32 One of the schematic diagrams of the semiconductor structure provided in different embodiments of this disclosure; Figure 33 This is a second schematic diagram of the semiconductor structure provided in different embodiments of this disclosure. Detailed Implementation
[0022] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0023] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0024] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0025] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0026] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0028] In semiconductor devices, such as dynamic random access memory (DRAM), capacitor structures are crucial components. A capacitor structure and a transistor can form a memory cell. A capacitor structure typically consists of two electrodes and a dielectric material layer between them. However, capacitor structures also suffer from performance degradation due to defects or other adverse conditions between adjacent material layers.
[0029] Therefore, there are still many problems that need to be improved in the manufacturing and use of semiconductor structures.
[0030] Based on this, the following technical solutions are proposed for embodiments of this disclosure: This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the preparation method includes the following steps: Step S101: Form the first electrode layer; Step S102: Form a dielectric layer that covers at least a portion of the surface of the first electrode layer; Step S103: Form a second electrode layer, the second electrode layer covering the surface of the dielectric layer; The preparation method further includes: forming a transition layer before and / or after forming the dielectric layer, wherein the transition layer is located between at least one of the first electrode layer and the second electrode layer and the dielectric layer; Step S104: Forming a transition layer includes: A transition material layer is formed, and the material of the transition material layer includes metal oxide semiconductor materials; A thermal annealing process is performed on the transition material layer to form a transition layer, wherein the electrical conductivity of the transition material layer increases after the thermal annealing process.
[0031] In this embodiment, a transition material layer comprising a metal oxide semiconductor material is formed before and / or after the formation of the dielectric layer. After annealing, the transition material layer forms a transition layer with increased conductivity. This transition layer is located between at least one of the first electrode layer and the second electrode layer and the dielectric layer. By specifically designing the material, location, and formation process of the transition layer, it is beneficial to reduce the diffusion between the material contained in the electrode layer (at least one of the first electrode layer or the second electrode layer) and the material contained in the dielectric layer, thereby reducing interface defect states. Furthermore, the presence of the transition layer can also act as a buffer layer to absorb interface stress. Simultaneously, since the interface defect states are significantly reduced after the thermal annealing process, it is beneficial to form a less defective and more stable bonding surface (contact interface) between the transition layer and the dielectric layer. Compared to the direct contact between the dielectric layer and the electrode layer, which can lead to mutual diffusion, numerous defects, and reactions that easily cause structural functional degradation, the technical solution provided in this embodiment is beneficial to improving the lifespan, durability, and stability of the semiconductor structure.
[0032] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.
[0033] Figures 2 to 7 This is a schematic diagram of the capacitor structure provided in one embodiment of the present disclosure during the fabrication process; wherein, Figure 2 Figures (1) and (2) are schematic diagrams of the structure during the formation of the first electrode layer and the transition material layer in different embodiments. Figures 2 to 4 as well as Figures 5 to 7 Schematic diagrams of the capacitor structures provided in different embodiments of this disclosure during the fabrication process; Figures 8 to 18 This is a schematic diagram of the capacitor structure during the fabrication process according to another embodiment of the present disclosure; wherein, Figures 8 to 10 , Figures 11 to 12 , Figure 13 , Figures 14 to 15 , Figure 16 , Figure 17 as well as Figure 18 Schematic diagrams of the capacitor structures provided in different embodiments of this disclosure during the fabrication process; Figures 19 to 23 This is a schematic diagram illustrating the fabrication process of a capacitor structure according to another embodiment of the present disclosure; wherein, Figures 19 to 20 , Figure 21 , Figure 22 as well as Figure 23Schematic diagrams of the capacitor structures provided in different embodiments of this disclosure during the fabrication process; Figures 24 to 27 This is a schematic diagram illustrating the fabrication process of a capacitor structure according to another embodiment of the present disclosure; wherein, Figures 24 to 25 , Figure 26 as well as Figure 27 Schematic diagrams of the capacitor structures provided in different embodiments of this disclosure during the fabrication process; Figures 28 to 31 Schematic diagrams of transistor structures provided in different embodiments of this disclosure; Figure 32 and Figure 33 The diagram shows the structure of the semiconductor structure provided in different embodiments of this disclosure.
[0034] The method for preparing the semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.
[0035] First, execute step S101, as follows: Figure 2 Figures (1) and (2) in the middle Figure 8 , Figure 14 , Figure 19 as well as Figure 24 As shown; the first electrode layer E1 is formed.
[0036] In some embodiments, before forming the first electrode layer E1, the fabrication method may further include the steps of providing a substrate (not shown) and forming a capacitor contact structure 12 on the substrate (not shown), wherein the capacitor contact structure 12 is connected to the first electrode layer E1.
[0037] Here, the substrate (not shown in the figure) can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, the substrate (not shown in the figure) is a silicon substrate.
[0038] In embodiments of this disclosure, the first horizontal direction mentioned later may be a direction parallel to the plane of the substrate (not shown).
[0039] In some embodiments, the material of the first electrode layer E1 includes, but is not limited to, conductive metals, transition metal nitrides, conductive metal oxides, conductive oxides, vanadates, etc., such as titanium nitride (TiN), copper (Cu), ruthenium (Ru), ruthenium dioxide (RuO2), platinum (Pt), molybdenum dioxide (MoO2), tin-doped molybdenum oxide, nickel (Ni), and titanium silicide (TiSi). xMaterials including at least one of strontium vanadate (SrVO3) and vanadates thereof, or combinations thereof.
[0040] Continue to refer to Figure 2 Figures (1) and (2) in the middle Figure 8 , Figure 14 , Figure 19 as well as Figure 24 As can be seen, the first electrode layer E1 can have different shapes, and different capacitor structures C can be obtained based on the different shapes of the first electrode layer E1. Specifically, the capacitor structure C can include the first electrode layer E1, the subsequently formed dielectric layer L1, the second electrode layer E2, and the transition layer 11. The capacitor structures C obtained based on the different shapes of the first electrode layer E1 are as follows: like Figure 2 As shown in Figures (1) and (2), the first electrode layer E1 extends along a direction parallel to the first horizontal direction D1. Based on this first electrode layer E1, the following can be obtained: Figure 4 To be continued Figure 7 Metal-Insulator-Metal (MIM) capacitor structure.
[0041] like Figure 8 as well as Figure 14 As shown, the first electrode layer E1 extends in a vertical direction, which can be a direction perpendicular to the plane of the substrate (not shown in the figure). Based on this first electrode layer E1, the following can be obtained. Figure 10 Appendix Figure 12 Appendix Figure 13 and appendix Figure 15 To be continued Figure 18 The columnar capacitor (Pillar.CAP) shown, and the subsequent formation of the second electrode layer E2 (see appendix for details) Figure 10 Appendix Figure 12 Appendix Figure 13 and appendix Figure 15 To be continued Figure 18 And dielectric layer L1 (see appendix for details) Figure 10 Appendix Figure 12 Appendix Figure 13 and appendix Figure 15 To be continued Figure 18 The capacitor structure C is wrapped in concentric circles on the column formed by the first electrode layer E1. Compared with the MIM capacitor, this capacitor structure C is advantageous in obtaining a capacitor structure with a larger capacitance value by increasing the height of the first electrode layer E1 within a limited substrate area (not shown in the figure).
[0042] like Figure 19As shown, the first electrode layer E1 is a cylindrical structure extending in a vertical direction, which can be a direction perpendicular to the plane of the substrate (not shown in the figure). Based on this first electrode layer E1, the following can be obtained. Figure 20 To be continued Figure 23 The cylindrical capacitor shown (Cylinder.CAP) and the subsequent formation of the second electrode layer E2 (see appendix for details) Figure 20 To be continued Figure 23 It will adhere to the inner and outer walls of the first electrode layer E1, and the dielectric layer L1 (see subsequent appendices for details). Figure 20 To be continued Figure 23 The electrode is sandwiched between the first electrode layer E1 and the second electrode layer E2, which effectively increases the surface area. This capacitor structure C is beneficial for forming a structure with a larger capacitance value.
[0043] like Figure 24 As shown, the first electrode layer E1 extends along the first horizontal direction D1. Based on this first electrode layer E1, the following structure can be obtained: Figures 25 to 27 The horizontal capacitor structure is shown. It should be noted that, although in Figures 25 to 27 The first electrode layer E1 shown is a cylindrical structure extending along the first horizontal direction D1 (corresponding to the formation of a horizontal cylindrical capacitor structure), but it is not limited to this. (See attached diagram.) Figure 24 The first electrode layer E1 shown can also be configured as a columnar structure extending along the first horizontal direction D1 (corresponding to the formation of a horizontal columnar capacitor structure). In actual operation, it can be flexibly configured according to the actual situation, and no specific limitation is made here. The capacitor structure C in this embodiment can be applied to a three-dimensional (3D) stacked semiconductor structure, which is beneficial to improving the integration density.
[0044] It can be seen that the fabrication method provided in this disclosure is applicable to various types of capacitor structures C, and has a wide range of adaptability. The capacitor structure C provided in this disclosure can be adapted to the case where the semiconductor structure is a dynamic random access memory structure, but it is not limited thereto. It can also be adapted to the case where the semiconductor structure includes the capacitor structure C but is another type of semiconductor device, and no specific limitation is made here.
[0045] Next, proceed to step S102, as follows: Figure 3 , Figure 9 , Figures 20 to 23 as well as Figure 24 As shown, a dielectric layer L1 is formed, which covers at least a portion of the surface of the first electrode layer E1.
[0046] In some embodiments, the material of the dielectric layer L1 includes at least a high dielectric constant material, which may include at least one or a combination of hafnium zirconium oxide (HZO) based high dielectric constant material or perovskite based high dielectric constant material (HK).
[0047] In some specific embodiments, the material of the dielectric layer L1 may include hafnium oxide, zirconium oxide, hafnium zirconium oxide (HZO), doped hafnium zirconium oxide (doped HZO), strontium titanate (STO), barium strontium titanate (BST), lead zirconate titanate (PZT), barium titanate (BTO), etc.
[0048] In some embodiments, the thickness of the dielectric layer L1 ranges from 3nm to 10nm (including the endpoint values), such as 3.5nm, 4nm, 4.5nm, 5nm, 6nm, 7nm, 8nm, 9nm, etc.
[0049] Understandably, using a high dielectric constant material as the dielectric layer L1 can help improve the capacitance value of the capacitor structure C obtained based on the first electrode layer E1 and the dielectric layer L1.
[0050] Then, proceed to step S103, as follows: Figure 4 , Figures 5 to 7 , Figure 10 , Figure 12 , Figure 13 , Figures 15 to 18 , Figures 20 to 23 , Figures 25 to 27 As shown, a second electrode layer E2 is formed, which covers the surface of the dielectric layer L1.
[0051] Here, the material of the second electrode layer E2 can be selected from the same range as the material of the first electrode layer E1.
[0052] In some embodiments, the second electrode layer E2 may be made of the same or different material as the first electrode layer E1. No specific limitation is made here, and the material can be flexibly selected according to the requirements.
[0053] In some embodiments, the fabrication method further includes, before and / or after the formation of the dielectric layer L1: A transition layer 11 is formed, which is located between at least one of the first electrode layer E1 and the second electrode layer E2 and the dielectric layer L1.
[0054] In order to form the transition layer 11, the preparation method provided in this embodiment of the present disclosure further includes performing step S104, the specific content of which is as follows: First, such as Figure 2 Figures (1) and (2) in the middle Figure 8 , Figure 11 , Figure 14 , Figure 19 As shown, a transition material layer 11a is formed, and the material of the transition material layer 11a includes a metal oxide semiconductor material; Next, as Figures 3 to 7 , Figure 9, Figure 12 and Figure 13 , Figures 15 to 18 , Figures 20 to 27 As shown, a thermal annealing process is performed on the transition material layer 11a to form the transition layer 11, wherein the electrical conductivity of the material of the transition material layer 11a increases after the thermal annealing process.
[0055] In some embodiments, the metal oxide semiconductor material includes at least one of In-Zn oxides, In-Ga-Zn oxides, In-Sn-Zn oxides, Zn-In-Sn oxides, Si-In-Zn oxides, Al-Zn oxides, Ga-Zn oxides, In-Ga oxides, Zn-Sn-Al oxides (e.g., XEZO), Sn-Zn oxides, In-Al-Zn oxides, Sn-Ga-Zn oxides, and Al-Ga-Zn oxides.
[0056] In some embodiments, the metal oxide semiconductor material may be a multi-component oxide semiconductor material such as indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO).
[0057] In some embodiments, the thickness of the transition layer 11 ranges from 0.1 nm to 2.5 nm (including endpoint values), such as 0.5 nm, 0.8 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, 2.3 nm, etc.
[0058] In some embodiments, the temperature range for performing the thermal annealing process is between 350°C and 450°C (inclusive), such as 380°C, 400°C, 430°C, etc.
[0059] In some embodiments, the time range for performing the thermal annealing process is between 30s and 3min (including the endpoint value), such as 50s, 60s, 1.2min, 1.5min, 1.8min, 2min, 2.2min, 2.5min, 2.8min, etc. In some embodiments, the atmosphere for performing the thermal annealing process is at least one of nitrogen or hydrogen. Using a reducing atmosphere with low oxygen partial pressure for the thermal annealing process promotes oxygen escape and the formation of more oxygen vacancies.
[0060] In some embodiments, after a thermal annealing process, the oxygen vacancy concentration of the transition material layer 11a increases.
[0061] Understandably, when the above annealing conditions are used to perform the annealing process on the transition material layer 11a, it is beneficial to accelerate the escape of oxygen elements in the transition material layer 11a, promote the formation of more oxygen vacancies, and increase the concentration of oxygen vacancies. The increase in oxygen vacancies is beneficial to increase the conductivity of the transition layer 11, thereby enabling the transition layer obtained after the annealing process to have improved electrical conductivity.
[0062] In some embodiments, the electrical conductivity of the transition layer 11 material is in the range of 10. 2 S / cm~10 5 Between S / cm.
[0063] Before the annealing process, due to the high oxygen content and low oxygen vacancy content in the transition material layer 11a, the electrical conductivity of the transition material layer 11a is approximately 10. -4 The conductivity of the transition layer 11 is between S / cm and 10S / cm, and after the hot annealing process, the conductivity can be increased to approximately 10S / cm. 2 ~10 5 Within the range of S / cm.
[0064] In this embodiment, the introduction of a transition layer 11 in the capacitor structure C helps prevent the materials contained in the electrode layers (first electrode layer E1 and / or second electrode layer) and dielectric layer located on both sides of and adjacent to the transition layer 11 from diffusing into each other, thus reducing interface defect states. Simultaneously, the transition layer 11 also functions as a buffer layer to absorb interface stress.
[0065] In addition, since the oxygen vacancies in the transition layer 11 can change accordingly with the process conditions, their proper setting can also help to further adjust the oxygen vacancies in the dielectric layer L1. By adjusting the oxygen vacancies in the dielectric layer L1, the defects in the material can be improved and adjusted, which is beneficial to improving the electrical performance and reliability of the final semiconductor structure.
[0066] Furthermore, the high conductivity of the transition layer 11 facilitates the integration of the aforementioned functions with the functionality of the electrode material, achieving a high degree of synergy between interface optimization and electrode application. Moreover, compared to the situation without the transition layer 11, where direct contact between the dielectric layer L1 and the electrode layers (first electrode layer E1 and / or second electrode layer) leads to a chain reaction of structural performance degradation, including material diffusion, interface layer formation, decreased dielectric constant, decreased capacitance, redox reactions, and leakage, the presence of the transition layer 11 in this embodiment significantly reduces or even avoids these issues. This effectively improves the electrical performance and lifespan of the capacitor structure C, as well as its stability and durability.
[0067] In actual operation, the execution of step S104 can include various cases, and the resulting capacitor structure C can also include various cases. The following will be explained in more detail with reference to the accompanying drawings. For ease of description, in the following content, the part of the transition layer 11 located between the first electrode layer E1 and the dielectric layer L1 is defined as the first sub-layer 111, and the part of the transition layer 11 located between the second electrode layer E2 and the dielectric layer L1 is defined as the second sub-layer 112.
[0068] In some embodiments, such as Figure 4 , Figure 10 , Figure 15 , Figure 20 as well as Figure 25 As shown, a transition layer 11 is formed after the first electrode layer E1 and before the dielectric layer L1 is formed, that is, a first sub-layer 111 is formed. This operation can result in a structure in which the transition layer 11 is located between the first electrode layer E1 and the dielectric layer L1.
[0069] In this embodiment, the transition layer 11, also known as the first sub-layer 111, is located between the first electrode layer E1 and the dielectric layer L1. In addition to achieving the aforementioned effects of the transition layer 11 (such as reducing material diffusion, interface defect states, achieving high synergy between interface optimization and electrode application, and reducing chain reactions), the formation of the transition layer 11, i.e. the first sub-layer 111, before the formation of the dielectric layer L1, is beneficial to provide a highly compatible epitaxial template for the formation of the dielectric layer L1. This is beneficial to ensure that the material contained in the subsequently obtained dielectric layer L1 has the desired crystal phase, thereby improving the electrical performance and stability of the structure.
[0070] In other embodiments, such as Figure 5 , Figure 12 , Figure 21 as well as Figure 26 As shown, a transition layer 11 is formed after the dielectric layer L1 is formed and before the second electrode layer E2 is formed, that is, a second sub-layer 112 is formed. This operation results in a structure in which the transition layer 11 is located between the second electrode layer E2 and the dielectric layer L1.
[0071] In this embodiment, the transition layer 11, i.e., the second sub-layer 112, is located between the second electrode layer E2 and the dielectric layer L1. Besides achieving the aforementioned effects of the transition layer 11 (such as, but not limited to, reducing material diffusion, interface defect states, achieving a high degree of synergy between interface optimization and electrode application, and reducing chain reactions), it also... Figure 12 The formed columnar capacitor, Figure 21 The formed cylindrical capacitor and Figure 26In the formed horizontal capacitor, since the length of the second electrode layer E2 in the extension direction is greater than that of the first electrode layer E1 in the extension direction, although this embodiment only provides a transition layer 11 (i.e., the second sub-layer 112) between an electrode layer (the second electrode layer E2) and a dielectric layer L1, it can significantly improve many properties of the obtained capacitor structure C compared to the case where the second sub-layer 112 is not provided.
[0072] In some other embodiments, such as Figure 6 , Figure 7 , Figure 13 , Figures 16 to 18 , Figure 22 , Figure 23 as well as Figure 27 As shown, the transition layer 11 includes both the first sub-layer 111 and the second sub-layer 112. This configuration can be further understood as follows: in addition to being located between the first electrode layer E1 and the dielectric layer L1, the transition layer 11 is also located between the second electrode layer E2 and the dielectric layer L1.
[0073] In this embodiment, in addition to achieving the aforementioned effects of the transition layer 11 (such as reducing material diffusion, interface defect states, achieving high synergy between interface optimization and electrode application, and reducing chain reactions), the provision of the transition layer 11 can also be understood as increasing the placement location and size of the transition layer 11, since the transition layer 11 is provided between the first electrode layer E1 and the dielectric layer L1, and between the second electrode layer E2 and the dielectric layer L1. Compared with the case where the transition layer 11 is not provided, or the case where the transition layer 11 is only provided between a single electrode layer and the dielectric layer L1, the solution provided by this embodiment is advantageous in obtaining the benefits of the transition layer 11 at multiple locations, thus achieving an enhanced effect. At the same time, since the transition layer 11 is provided between each electrode layer and the dielectric layer L1 in the capacitor structure in this embodiment, it is beneficial to obtain a structure with significantly improved service life, durability, and stability.
[0074] In addition to the foregoing embodiments, this disclosure also provides embodiments in which the transition layer 11 may include multiple structural components, as detailed below: In some embodiments, forming the transition layer 11 includes: A first transition material layer Lc is formed, which is located between at least one of the first electrode layer E1 and the second electrode layer E2 and the dielectric layer L1 (see details). Figure 2 Figure (2) in the middle and Figure 14 ); The first transition material layer Lc is etched to remove a portion of it, forming a groove structure T along the first horizontal direction D1 and on the side of the first transition material layer Lc adjacent to the second electrode layer E2. The groove structure T is spaced apart from the remaining first transition material layer Lc (see details). Figure 2 Figure (2) in the middle and Figure 14 ); A second transition material layer Ld is formed, and the second transition material layer Ld fills the groove structure T (see details). Figure 2 Figure (2) in the middle and Figure 14 ); Perform a hot annealing process to form transition layer 11 (see details). Figure 7 , Figures 15 to 18 as well as Figure 23 ); The first transition material layer Lc is made of metal oxide semiconductor material. After thermal annealing, the conductivity of the first transition material layer Lc increases.
[0075] In some embodiments, the groove structure T may penetrate through the first transition material layer Lc.
[0076] However, this is not the only option. In other embodiments, the groove structure T may not penetrate the first transition material layer Lc. The specific design can be determined according to the requirements and is not specifically limited here.
[0077] Here, the material of the second transition material layer Ld can include low dielectric constant materials, such as silicon oxide, but is not limited to them. It can also be a high dielectric constant material different from the first transition material layer Lc. Specifically, it can be selected according to the actual situation, and no specific limitation is made here.
[0078] In this embodiment, after the hot annealing process, the first transition material layer Lc will form the first transition layer La, and the second transition material layer Ld will form the second transition layer Lb.
[0079] In this embodiment, the formation location of the transition layer 11, which includes the first transition layer La and the second transition layer Lb, can also include various cases: like Figure 7 As shown, the transition layer 11, comprising the first transition layer La and the second transition layer Lb, is disposed between the two electrode layers (the first electrode layer E1 and the second electrode layer E2) and the dielectric layer L1, but is not limited thereto. Figure 7 Based on the structure shown, the transition layer 11, which includes the first transition layer La and the second transition layer Lb, can also be configured to be located only between a single electrode layer (either the first electrode layer E1 or the second electrode layer E2) and the dielectric layer L1.
[0080] Similarly, in Figure 17as well as Figure 23 In the structure shown, the transition layer 11, which includes the first transition layer La and the second transition layer Lb, is disposed between the two electrode layers (the first electrode layer E1 and the second electrode layer E2) and the dielectric layer L1, but is not limited thereto. Figure 17 and Figure 23 Based on the structure shown, the transition layer 11, which includes the first transition layer La and the second transition layer Lb, can also be configured to be located only between a single electrode layer (either the first electrode layer E1 or the second electrode layer E2) and the dielectric layer L1.
[0081] Additionally, in any of the above embodiments, such as Figure 16 as well as Figure 18 As shown, in a structure where the first transition layer La and the second transition layer Lb, comprising the transition layer 11, are disposed at a single location, it also cooperates with the arrangement that the transition layer 11 comprises a single-component material layer, for example, it can be configured such that: Figure 7 , Figures 15 to 18 as well as Figure 23 The structure shown or in Figure 7 , Figures 15 to 18 as well as Figure 23 Based on the structure obtained by setting position changes, there can be a single material layer between one of the first electrode layer E1 and the second electrode layer E2 and the dielectric layer L1, while a transition layer 11 including a first transition layer La and a second transition layer Lb is set between the other of the first electrode layer E1 and the dielectric layer L1, which has high flexibility.
[0082] Regardless of the configuration, in a capacitor structure where the transition layer 11 includes a first transition layer La and a second transition layer Lb, the performance of the final capacitor structure C is improved. For example, when the first transition layer La contains a high-dielectric-constant material and the second transition layer Lb contains a low-dielectric-constant material, it is beneficial to improve temperature stability, breakdown resistance, and balance the relationship between dielectric constant and loss. Furthermore, when the first transition layer La and the second transition layer Lb contain high-dielectric-constant materials of different types, the synergy and cooperation between the two materials also contribute to improving the performance of the capacitor structure C.
[0083] This disclosure also provides a semiconductor structure, as shown in the attached figure. Figure 4 To be continued Figure 7 , Figure 10 , Figure 12 , Figure 13 , Figure 15 To be continued Figure 18 , Figures 20 to 23 as well as Figures 25 to 27 As shown, the semiconductor structure includes: First electrode layer E1; A dielectric layer L1 is located on the first electrode layer E1 and covers at least a portion of the surface of the first electrode layer E1; The second electrode layer E2 covers the surface of the dielectric layer L1 and is located on the side of the dielectric layer L1 away from the first electrode; A transition layer 11 is located between at least one of the first electrode layer E1 and the second electrode layer E2 and the dielectric layer L1; wherein the material of the transition layer 11 includes at least a metal oxide semiconductor material that has undergone thermal annealing.
[0084] In some embodiments, the metal oxide semiconductor material includes at least one of In-Zn oxides, In-Ga-Zn oxides, In-Sn-Zn oxides, Zn-In-Sn oxides, Si-In-Zn oxides, Al-Zn oxides, Ga-Zn oxides, In-Ga oxides, Zn-Sn-Al oxides (e.g., XEZO), Sn-Zn oxides, In-Al-Zn oxides, Sn-Ga-Zn oxides, and Al-Ga-Zn oxides.
[0085] It is understood that the first electrode layer E1, the subsequently formed dielectric layer L1, the second electrode layer E2, and the transition layer 11 can together constitute the capacitor structure C. The embodiments of this disclosure can include capacitor structures C with various structures.
[0086] In some embodiments, as shown in the appendix Figure 4 To be continued Figure 7 As shown, the first electrode layer E1 extends along the first direction, the dielectric layer L1 covers the surface of the first electrode layer E1, and the second electrode layer E2 covers the surface of the dielectric layer L1. The first direction is parallel to either the first horizontal direction D1 or the vertical direction.
[0087] The capacitor in this embodiment is a metal-insulator-metal capacitor (MIM capacitor), which has high reliability and stability.
[0088] In other embodiments, such as Figure 10 Appendix Figure 12 Appendix Figure 13 and appendix Figure 15 To be continued Figure 18 As shown, the first electrode layer E1 is columnar, the dielectric layer L1 covers the top and side surfaces of the first electrode layer E1, and the second electrode layer E2 covers the surface of the dielectric layer L1.
[0089] In this embodiment, the capacitor structure C is a pillar capacitor (Pillar.CAP), in which the second electrode layer E2 and the dielectric layer L1 are wrapped in concentric circles on the pillar formed by the first electrode layer E1. Compared with MIM capacitors, this capacitor structure C is advantageous in obtaining a capacitor structure with a larger capacitance value by increasing the height of the first electrode layer E1 within a limited substrate area (not shown in the figure).
[0090] In some other embodiments, such as the appendix Figure 20 To be continued Figure 23 As shown, the first electrode layer E1 is cylindrical, the dielectric layer L1 covers the top surface, inner surface and outer surface of the first electrode layer E1, and the second electrode layer E2 covers the surface of the dielectric layer L1.
[0091] In this embodiment, the capacitor structure C is a cylindrical capacitor (Cylinder Cap). The second electrode layer E2 is attached to the inner and outer walls of the first electrode layer E1, and the dielectric layer L1 is sandwiched between the first electrode layer E1 and the second electrode layer E2, which effectively increases the surface area. This capacitor structure C is advantageous for forming a structure with a larger capacitance value.
[0092] In some other embodiments, such as Figures 25 to 27 As shown, the first electrode layer E1 extends along the first horizontal direction D1, and the capacitor structure C obtained in this embodiment is a horizontal capacitor structure. It should be noted that, although in the attached... Figures 25 to 27 The first electrode layer E1 shown is a cylindrical structure extending along the first horizontal direction D1 (corresponding to the formation of a horizontal cylindrical capacitor structure), but it is not limited to this. (See attached diagram.) Figures 25 to 27 The first electrode layer E1 shown can also be configured as a columnar structure extending along the first horizontal direction D1 (corresponding to the formation of a horizontal columnar capacitor structure). In actual operation, it can be flexibly configured according to the actual situation, and no specific limitation is made here. The capacitor structure C in this embodiment can be applied to a three-dimensional (3D) stacked semiconductor structure, which is beneficial to improving the integration density.
[0093] In some embodiments, the electrical conductivity of the transition layer 11 material is in the range of 10. 2 S / cm~10 5 Between S / cm (including endpoint values), for example, 5×10 2 S / cm, 8×10 2 S / cm, 1×10 3 S / cm, 5×10 3 S / cm, 8×10 3 S / cm, 1×10 4 S / cm, 5×10 4 S / cm, 8×10 4 S / cm, etc.
[0094] In this embodiment, the introduction of a transition layer 11 in the capacitor structure C helps prevent the materials contained in the electrode layers (first electrode layer E1 and / or second electrode layer) and the dielectric layer located on both sides of the transition layer 11 and adjacent to it from diffusing into each other, thus reducing interface defect states. Simultaneously, the transition layer 11 also functions as a buffer layer to absorb interface stress.
[0095] Furthermore, since the transition layer 11 is obtained by performing a thermal annealing process during its formation, the oxygen vacancy concentration in the transition layer 11 can be effectively adjusted by adjusting the thermal annealing conditions (such as temperature, time, and atmosphere). In other words, the oxygen vacancy in the transition layer 11 can change accordingly with the process conditions. Therefore, the oxygen vacancy in the dielectric layer L1 can be adjusted by reasonably setting the oxygen vacancy concentration in the transition layer 11. By adjusting the oxygen vacancy in the dielectric layer L1, the defects in the material can be improved and adjusted, which is beneficial to improving the electrical performance and reliability of the final semiconductor structure.
[0096] Furthermore, the high conductivity of the transition layer 11 facilitates the integration of the aforementioned functions with the functionality of the electrode material, achieving a high degree of synergy between interface optimization and electrode application. Moreover, compared to the situation without the transition layer 11, where direct contact between the dielectric layer L1 and the electrode layers (first electrode layer E1 and / or second electrode layer) leads to a chain reaction of structural performance degradation, including material diffusion, interface layer formation, decreased dielectric constant, decreased capacitance, redox reactions, and leakage, the transition layer 11 in this embodiment significantly reduces or even avoids these issues, improving the electrical performance, lifespan, stability, and durability of the capacitor structure C.
[0097] In some embodiments, such as Figure 4 , Figure 10 , Figure 15 , Figure 20 as well as Figure 25 As shown, the transition layer 11 includes a first sublayer 111, which is located between the first electrode layer E1 and the dielectric layer L1.
[0098] For information regarding the effects of the structure obtained in this embodiment, please refer to the preparation method. Figure 4 , Figure 10 , Figure 15 , Figure 20 as well as Figure 25 The transition layer 11 described herein includes the corresponding effect part when the first sub-layer 111 is used, which will not be elaborated here.
[0099] In other embodiments, such as Figure 5 , Figure 12 , Figure 21 as well as Figure 26 As shown, the transition layer 11 includes a second sub-layer 112, which is located between the second electrode layer E2 and the dielectric layer L1.
[0100] For information regarding the effects of the structure obtained in this embodiment, please refer to the preparation method. Figure 5 , Figure 12 , Figure 21 as well as Figure 26 The transition layer 11 described herein includes the corresponding effect of the second sub-layer 112, which will not be elaborated here.
[0101] In some other embodiments, such as Figure 6 , Figure 7 , Figure 13 , Figures 16 to 18 , Figure 22 , Figure 23 as well as Figure 27 As shown, the transition layer 11 contains the structure of the first sub-layer 111 and the second sub-layer 112. It can be further understood that the transition layer 11 is located not only between the first electrode layer E1 and the dielectric layer L1, but also between the second electrode layer E2 and the dielectric layer L1.
[0102] For information regarding the effects of the structure obtained in this embodiment, please refer to the preparation method. Figure 6 , Figure 7 , Figure 13 , Figures 16 to 18 , Figure 22 , Figure 23 as well as Figure 27 The corresponding effects of the transition layer 11 described herein, which simultaneously includes the first sub-layer 111 and the second sub-layer 112, will not be elaborated here.
[0103] In some embodiments, such as Figure 7 , Figures 15 to 18 as well as Figure 23 As shown, the transition layer 11 includes a first transition layer La and a second transition layer Lb, which are distributed at intervals along the first horizontal direction D1 and on the side of the transition layer 11 adjacent to the second electrode layer E2. The material of the first transition layer La includes a metal oxide semiconductor material that has undergone thermal annealing.
[0104] In some embodiments, the surface of the second transition layer Lb away from the second electrode layer E2 can be flush with the surface of the first transition layer La away from the second electrode layer E2. Thus, the second transition layer Lb has a larger proportion in the transition layer 11, which can enhance the effect of the second transition layer Lb.
[0105] However, this is not the only embodiment. In other embodiments, the thickness of the second transition layer Lb may be less than the thickness of the first transition layer La in the direction from the first electrode layer E1 to the second electrode layer E2. This is beneficial for a better interface between the first transition layer La and the electrode layers (first electrode layer E1 and / or second electrode layer E2) and the dielectric layer L1, reducing the occurrence of defects, adverse reactions, etc.
[0106] Here, the material of the second transition layer Lb can include low dielectric constant materials, such as silicon oxide, but is not limited to them. It can also be a high dielectric constant material different from the first transition layer La. Specifically, it can be selected according to the actual situation, and no specific limitation is made here.
[0107] In this embodiment, the formation location of the transition layer 11, which includes the first transition layer La and the second transition layer Lb, can also include various cases: like Figure 7 As shown, the transition layer 11, comprising the first transition layer La and the second transition layer Lb, is disposed between the two electrode layers (the first electrode layer E1 and the second electrode layer E2) and the dielectric layer L1, but is not limited thereto. Figure 7 Based on the structure shown, the transition layer 11, which includes the first transition layer La and the second transition layer Lb, can also be configured to be located only between a single electrode layer (either the first electrode layer E1 or the second electrode layer E2) and the dielectric layer L1.
[0108] Similarly, in Figure 17 and Figure 23 In the structure shown, the transition layer 11, which includes the first transition layer La and the second transition layer Lb, is disposed between the two electrode layers (the first electrode layer E1 and the second electrode layer E2) and the dielectric layer L1, but is not limited thereto. Figure 17 and Figure 23 Based on the structure shown, the transition layer 11, which includes the first transition layer La and the second transition layer Lb, can also be configured to be located only between a single electrode layer (either the first electrode layer E1 or the second electrode layer E2) and the dielectric layer L1.
[0109] Additionally, in any of the above embodiments, such as Figure 16 as well as Figure 18 As shown, in a structure where the first transition layer La and the second transition layer Lb, comprising the transition layer 11, are disposed at a single location, it also cooperates with the arrangement that the transition layer 11 comprises a single-component material layer, for example, it can be configured such that: Figure 7 , Figures 15 to 18 as well as Figure 23 The structure shown or in Figure 7 , Figures 15 to 18 as well as Figure 23Based on the structure obtained by setting position changes, there can be a single material layer between one of the first electrode layer E1 and the second electrode layer E2 and the dielectric layer L1, while a transition layer 11 including a first transition layer La and a second transition layer Lb is set between the other of the first electrode layer E1 and the dielectric layer L1, which has high flexibility.
[0110] Regardless of the configuration, in a capacitor structure where the transition layer 11 includes a first transition layer La and a second transition layer Lb, the performance of the final capacitor structure C is improved. For example, when the first transition layer La contains a high-dielectric-constant material and the second transition layer Lb contains a low-dielectric-constant material, it is beneficial to improve temperature stability, breakdown resistance, and balance the relationship between dielectric constant and loss. Furthermore, when the first transition layer La and the second transition layer Lb contain high-dielectric-constant materials of different types, the synergy and cooperation between the two materials also contribute to improving the performance of the capacitor structure C.
[0111] In some embodiments, such as Figures 28 to 33 As shown, the semiconductor structure also includes a transistor structure Ta. In the top view, the structure consisting of the first electrode layer E1, the dielectric layer L1, the second electrode layer E2, and the transition layer 11, i.e., the capacitor structure C, is arranged adjacent to at least a portion of the transistor structure Ta along the first horizontal direction D1 or the vertical direction D2. The transistor structure Ta includes one of the following: planar transistor T1, vertical transistor T2, buried transistor T3, or three-dimensional stacked transistor T4.
[0112] In some embodiments, such as Figures 28 to 31 As shown, the transistor structure Ta may further include a gate layer G, a first source / drain region D11 and a second source / drain region D12, and the capacitor structure C may be connected to the second source / drain region D12.
[0113] When a semiconductor structure Ta is included and connected to a capacitor structure, the semiconductor structure can be a dynamic random access memory (DRAM) structure. However, it is not limited to this; the semiconductor structure provided in this disclosure can also include a capacitor structure C but be other types of semiconductor devices, and no specific limitation is made here. Regardless of the structure, improved stability and durability can be obtained due to the introduction of the transition layer 11.
[0114] This disclosure also provides an electronic device, including a semiconductor structure formed by the preparation method of any of the above embodiments, or including a semiconductor structure as described in any of the above embodiments.
[0115] In some embodiments, the electronic device may include, but is not limited to, a storage device, a smartphone, a computer, a mobile phone, a tablet computer, an artificial intelligence device, a wearable device, or a power bank.
[0116] The technical features described in the embodiments provided in this disclosure can be arbitrarily combined without conflict.
[0117] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A method of fabricating a semiconductor structure, characterized by, The preparation method includes: Form the first electrode layer; A dielectric layer is formed, the dielectric layer covering at least a portion of the surface of the first electrode layer; A second electrode layer is formed, which covers the surface of the dielectric layer; The preparation method further includes: forming a transition layer before and / or after forming the dielectric layer, the transition layer being located between at least one of the first electrode layer and the second electrode layer and the dielectric layer; Forming the transition layer includes: A transition material layer is formed, wherein the material of the transition material layer includes a metal oxide semiconductor material; A thermal annealing process is performed on the transition material layer to form the transition layer, wherein the electrical conductivity of the material in the transition material layer increases after the thermal annealing process.
2. The production method according to claim 1, characterized by, After the aforementioned hot annealing process, the oxygen vacancy concentration of the transition material layer increases.
3. The method of claim 1, wherein, Forming the transition layer includes: A first transition material layer is formed, wherein the first transition material layer is located between at least one of the first electrode layer and the second electrode layer and the dielectric layer; The first transition material layer is etched to remove a portion of the first transition material layer to form a groove structure along a first horizontal direction and on the side of the first transition material layer adjacent to the second electrode layer. The groove structure is spaced apart from the remaining first transition material layer. A second transition material layer is formed, and the second transition material layer fills the groove structure; Perform a thermal annealing process to form the transition layer; The material of the first transition material layer includes a metal oxide semiconductor material, and the electrical conductivity of the material of the first transition material layer increases after the thermal annealing process.
4. The production method according to any one of claims 1 to 3, characterized by, The temperature range for performing the hot annealing process is between 350°C and 450°C. And / or, The time range for performing the hot annealing process is between 30 seconds and 3 minutes. And / or, The atmosphere for performing the thermal annealing process is at least one of nitrogen or hydrogen.
5. The production method according to claim 4, characterized by, The metal oxide semiconductor material includes at least one of In-Zn oxides, In-Ga-Zn oxides, In-Sn-Zn oxides, Zn-In-Sn oxides, Si-In-Zn oxides, Al-Zn oxides, Ga-Zn oxides, In-Ga oxides, Zn-Sn-Al oxides, Sn-Zn oxides, In-Al-Zn oxides, Sn-Ga-Zn oxides, and Al-Ga-Zn oxides.
6. A semiconductor structure, characterized by The semiconductor structure includes: First electrode layer; A dielectric layer is located on the first electrode layer and covers at least a portion of the surface of the first electrode layer; The second electrode layer covers the surface of the dielectric layer and is located on the side of the dielectric layer away from the first electrode; A transition layer is located between at least one of the first electrode layer and the second electrode layer and the dielectric layer; wherein the material of the transition layer includes at least a thermally annealed metal oxide semiconductor material; The metal oxide semiconductor material includes at least one of In-Zn oxides, In-Ga-Zn oxides, In-Sn-Zn oxides, Zn-In-Sn oxides, Si-In-Zn oxides, Al-Zn oxides, Ga-Zn oxides, In-Ga oxides, Zn-Sn-Al oxides, Sn-Zn oxides, In-Al-Zn oxides, Sn-Ga-Zn oxides, and Al-Ga-Zn oxides.
7. The semiconductor structure of claim 6, wherein, The electrical conductivity of the material of the transition layer ranges between 10 2 S / cm ~ 10 5 S / cm.
8. The semiconductor structure of claim 6, wherein, The transition layer includes a first transition layer and a second transition layer, which are located along a first horizontal direction and on the side of the transition layer adjacent to the second electrode layer, with the first transition layer and the second transition layer being spaced apart. The material of the first transition layer includes a metal oxide semiconductor material that has undergone thermal annealing.
9. The semiconductor structure of claim 6, wherein, The first electrode layer is columnar, the dielectric layer covers the top and side surfaces of the first electrode layer, and the second electrode layer covers the surface of the dielectric layer.
10. The semiconductor structure of claim 6, wherein, The first electrode layer is cylindrical, the dielectric layer covers the top surface, inner surface and outer surface of the first electrode layer, and the second electrode layer covers the surface of the dielectric layer.
11. The semiconductor structure of claim 6, wherein, The first electrode layer extends along a first direction, the dielectric layer covers the surface of the first electrode layer, and the second electrode layer covers the surface of the dielectric layer; Wherein, the first direction is parallel to either the first horizontal direction or the first vertical direction.
12. The semiconductor structure of any of claims 6-11, wherein, The semiconductor structure further includes a transistor structure, wherein, in a top view, the structure formed by the first electrode layer, the dielectric layer, the second electrode layer, and the transition layer is disposed adjacent to at least a portion of the transistor structure along a first horizontal direction or a vertical direction; The transistor structure includes one of a planar transistor, a vertical transistor, a buried transistor, or a three-dimensional stacked transistor.
13. An electronic device, comprising: The electronic device comprises a semiconductor structure formed by the preparation method as described in any one of claims 1-5, or the electronic device comprises a semiconductor structure as described in any one of claims 6-12.