Semiconductor structure and method of manufacturing the same, electronic device

Abstract

This disclosure relates to the semiconductor field, providing a semiconductor structure and its fabrication method, and an electronic device. The semiconductor structure includes: an active portion, comprising a first source / drain region, a channel region, and a second source / drain region arranged sequentially; a first isolation layer and a second isolation layer, wherein the first isolation layer is located on the surfaces of the first and second source / drain regions, and the second isolation layer is located on the surface of the first isolation layer; and a word line structure located on the channel region, comprising a first portion and a second portion, wherein the first portion is located on the side of the first isolation layer, and the second portion is located on the side of the second isolation layer, wherein a first dimension of the first portion is larger than a second dimension of the second portion, which can at least improve the gate-induced drain leakage problem.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and its fabrication method, and an electronic device. Background Technology

[0002] Throughout the development of DRAM, as technology has evolved and device size has continued to shrink, while this has led to increased storage density and enhanced performance, it has also made the problem of gate-induced drain leakage (GIDL) increasingly severe.

[0003] Initially, to reduce GIDL, researchers primarily focused on optimizing semiconductor materials. The main approaches were as follows: 1. Attempts have been made to weaken the GIDL effect by using different silicon-based materials and adjusting their doping concentration and impurity distribution. However, this approach has limitations, as overdoping can lead to other problems, such as affecting carrier mobility and causing a decline in overall device performance.

[0004] 2. Special treatments are applied to the gate oxide layer in an attempt to reduce the electric field coupling between the gate and drain, thereby suppressing GIDL. However, as device dimensions shrink, the quantum tunneling effect becomes significant, and even very thin and high-quality oxide layers are difficult to effectively block leakage current, thus this method has gradually reached its bottleneck.

[0005] 3. Changing the spacing or shape between the drain and gate in an attempt to reduce GIDL by adjusting the electric field distribution. However, these changes often negatively impact other device performance parameters; for example, changes in capacitance affect the ability to retain stored charge, leading to decreased data storage stability. Summary of the Invention

[0006] This disclosure provides a semiconductor structure and its fabrication method, as well as an electronic device, which at least helps to solve the problem of gate-induced drain leakage.

[0007] This disclosure provides a semiconductor structure, comprising: an active portion including a first source / drain region, a channel region, and a second source / drain region arranged sequentially along a first direction; a first isolation layer and a second isolation layer, the first isolation layer being located on the surfaces of the first and second source / drain regions, and the second isolation layer being located on the surface of the first isolation layer away from the active portion; and a word line structure located on the surface of the channel region, the word line structure including a first portion and a second portion, the first portion being located on the side of the first isolation layer along the first direction, the second portion being located on the side of the second isolation layer along the first direction, and a first dimension of the first portion along the first direction being larger than a second dimension of the second portion along the first direction.

[0008] Optionally, the word line structure surrounds the channel region.

[0009] Optionally, it further includes: a substrate, wherein the active portion is located on the substrate, and the arrangement direction of the first source / drain region, the channel region, and the second source / drain region is perpendicular to the surface of the substrate.

[0010] Optionally, the first source / drain region, the channel region, and the second source / drain region are arranged in a first horizontal direction; it also includes: a bit line structure, which is coupled to the first source / drain region and extends in a vertical direction.

[0011] Optionally, it further includes: a substrate, wherein the active portion is located on the surface of the substrate, and the word line structure is located on the surface of the active portion.

[0012] Optionally, the character line structure includes a first character line and a second character line, wherein the first character line is located on the side of the channel region away from the substrate, and the second character line is located on the side of the channel region close to the substrate; a first portion of the first character line is a first sub-part, a second portion of the first character line is a second sub-part, and the dimension of the first sub-part along the first direction is greater than the dimension of the second sub-part along the first direction; a first portion of the second character line is a third sub-part, a second portion of the second character line is a fourth sub-part, and the dimension of the third sub-part along the first direction is greater than the dimension of the fourth sub-part along the first direction.

[0013] Optionally, the ratio of the difference between the second dimension and the first dimension to the first dimension is 1:300 to 1:10.

[0014] Optionally, the first part has a protrusion relative to the second part, the protrusion being close to the drain area.

[0015] Optionally, the protrusion includes a first end near the leak area and a second end near the second portion, wherein the thickness of the first end is less than the thickness of the second end.

[0016] Optionally, the thickness of the first isolation layer is less than the thickness of the second isolation layer.

[0017] Optionally, the thickness of the first isolation layer is greater than the thickness of the first part.

[0018] A second aspect of this disclosure also provides a method for fabricating a semiconductor structure, comprising: providing an active portion, the active portion including a first source / drain region, a channel region, and a second source / drain region arranged sequentially; forming a first isolation layer and a second isolation layer, the first isolation layer being located on the surfaces of the first source / drain region and the second source / drain region, and the second isolation layer being located on the surface of the first isolation layer; forming a word line structure, the word line structure being located on the channel region, the word line structure including a first part and a second part, the first part being located on the side of the first isolation layer, the second part being located on the side of the second isolation layer, and a first dimension of the first part being larger than a second dimension of the second part.

[0019] Optionally, before forming the character line structure, the process includes: removing a portion of the width of the first isolation layer and the second isolation layer to form a first groove; continuing to remove the first isolation layer to form a second groove, wherein the first groove and the second groove penetrate each other; and forming the character line structure within the first groove and the second groove.

[0020] A third aspect of this disclosure provides an electronic device, including: a processor; and a memory electrically connected to the processor, the memory including the semiconductor structure provided above.

[0021] The technical solution provided in this disclosure has at least the following advantages: The semiconductor structure disclosed herein includes a word line structure comprising a first portion and a second portion. The first portion is located on the side of a first isolation layer, and the second portion is located on the side of a second isolation layer. The first dimension of the first portion is larger than the second dimension of the second portion. Thus, the portion near the edge of the first source / drain channel is relatively thicker or wider. The larger first portion can physically push the effective edge of the gate away from the region with the highest carrier concentration in the first source / drain region, or disperse the electric field lines originally concentrated at sharp corners through its geometry (such as a stepped shape), thereby weakening the vertical electric field on the drain surface, making the band bending gentler, reducing the probability of band-to-band tunneling, and decreasing the GIDL current. Secondly, the wider first portion is closer to the active portion. For the gate dielectric layer located between the active portion and the word line structure, it disperses the high-electric-field carriers to the wider first portion. This reduces the probability of high-energy carriers being injected into the gate oxide layer, improving the long-term reliability of the device; it also makes the electric field distribution along the entire channel edge more uniform, avoiding premature local breakdown or performance degradation. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a first semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of a second semiconductor structure provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of a third semiconductor structure provided in an embodiment of the present disclosure; Figure 4 This is a schematic diagram of a word line structure in a semiconductor structure provided in an embodiment of the present disclosure; Figure 5 This is a schematic diagram of a fourth semiconductor structure provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of a fifth semiconductor structure provided in an embodiment of the present disclosure; Figure 7 A schematic diagram of a sixth semiconductor structure provided in an embodiment of this disclosure; Figure 8 A schematic diagram of a semiconductor structure corresponding to an active portion in a method for fabricating a semiconductor structure according to another embodiment of this disclosure; Figure 9 This is a schematic diagram of the semiconductor structure corresponding to the formation of the first trench in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure; Figure 10 This is a schematic diagram of the semiconductor structure corresponding to the formation of the second trench in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure; Figure 11 This is a schematic diagram of the semiconductor structure corresponding to the formation of the second groove in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure; Figure 12 This is a schematic diagram of a semiconductor structure corresponding to the gate dielectric layer in a method for fabricating a semiconductor structure according to another embodiment of the present disclosure; Figure 13 This is a schematic diagram of a semiconductor structure corresponding to a word line structure in a method for fabricating a semiconductor structure according to another embodiment of this disclosure.

[0024] Explanation of reference numerals in the attached figures: 10. Substrate; 100. Active portion; 101. First isolation layer; 102. Second isolation layer; 104. Gate dielectric layer; 105. Word line structure; 1051. Second part; 1052. First part; 106. Capacitor structure; 107. Bit line structure; 108. First groove; 109. Second groove; 111. First source / drain region; 112. Channel region; 113. Second source / drain region; 114. First word line; 1141. Second sub-part; 1142. First sub-part; 115. Second word line; 1151. Fourth sub-part; 1152. Third sub-part; 121. Protrusion; 122. Body portion; 131. First end; 132. Second end. Detailed Implementation

[0025] As can be seen from the background technology, the gate-induced drain leakage problem in current semiconductor structures is quite serious.

[0026] This disclosure provides a semiconductor structure in which the morphology of the word line structure is improved to form a first part and a second part, and the first dimension of the first part closer to the active part is larger than the second dimension of the second part farther from the active part. In this way, the vertical electric field of the drain surface can be changed, the band bending is made gentler, the probability of band tunneling is reduced, and the GIDL current is reduced.

[0027] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to embodiments of this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0028] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0029] In the description of the embodiments of this disclosure, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this disclosure and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of the embodiments of this disclosure; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0030] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0031] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this disclosure.

[0032] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0033] Gate-induced drain leakage mainly occurs in the off state (V G =0 or negative pressure, V D When the gate is at a high level, the energy band in the drain region bends under the influence of the gate electric field, causing electrons to tunnel from the valence band to the conduction band (band-to-band tunneling, BTBT), resulting in leakage current. The key to improving gate-induced drain leakage lies in the vertical electric field on the surface of the drain depletion region, avoiding excessively high electric field peaks in the overlapping area of ​​the gate and drain junction.

[0034] Therefore, according to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure to improve gate-induced drain leakage. The semiconductor structure includes: an active portion, comprising a first source / drain region, a channel region, and a second source / drain region arranged sequentially along a first direction. The semiconductor structure includes: a first isolation layer and a second isolation layer, the first isolation layer being located on the surfaces of the first and second source / drain regions, and the second isolation layer being located on the surface of the first isolation layer away from the active portion. The semiconductor structure includes: a word line structure, the word line structure being located on the side of the channel region away from the substrate, the word line structure including a first portion and a second portion, the first portion being located on the side of the first isolation layer along the first direction, and the second portion being located on the side of the second isolation layer along the first direction, the first dimension of the first portion along the first direction being larger than the second dimension of the second portion along the first direction.

[0035] The semiconductor structure provided in this disclosure includes a word line structure comprising a first part and a second part. The first part is located on the side of a first isolation layer, and the second part is located on the side of a second isolation layer. The first dimension of the first part is larger than the second dimension of the second part. Thus, the portion near the edge of the first source / drain channel is relatively thicker or wider. The larger first part can physically push the effective edge of the gate away from the region with the highest carrier concentration in the first source / drain region, or disperse the electric field lines originally concentrated at sharp corners through its geometry (such as a stepped shape), thereby weakening the vertical electric field on the drain surface, making the band bending gentler, reducing the probability of band-to-band tunneling, and decreasing the GIDL current. Secondly, the wider first part is closer to the active part. For the gate dielectric layer located between the active part and the word line structure, it disperses the high-electric-field carriers to the wider first part. This reduces the probability of high-energy carriers being injected into the gate oxide layer, improving the long-term reliability of the device; it also makes the electric field distribution along the entire channel edge more uniform, avoiding premature local breakdown or performance degradation.

[0036] The semiconductor structure provided in the above embodiments will be further described below with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic diagram of a first semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of a second semiconductor structure provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of a third semiconductor structure provided in an embodiment of the present disclosure. Figures 1-3 The vertical direction is the Z direction, the first horizontal direction is the X direction, and the second horizontal direction is the Y direction.

[0038] in, Figure 1 The semiconductor structure shown is a 3D stacked array transistor, with the active part extending along the first horizontal direction X, the word line structure extending along the second horizontal direction Y, and the bit line structure extending along the vertical direction Z. Figure 2 It is a planar transistor structure, with the active part and the substrate formed from the same original substrate. Figure 3 The structure is a vertical transistor, with the active portion extending in the vertical direction Z, the bit line structure extending in the second horizontal direction Y, and the word line structure extending in the first horizontal direction X. The semiconductor structure provided in the above embodiment will be described in detail below with reference to the specific accompanying drawings.

[0039] refer to Figure 1 The semiconductor structure includes an active portion 100, which includes a first source / drain region 111, a channel region 112, and a second source / drain region 113 arranged sequentially along a first direction.

[0040] The active region 100 is the area on the silicon wafer where active devices are fabricated. Different doping types in the active region 100 can form n-type or p-type active regions. The active region 100 is divided into a source region and a drain region (with the same doping type). Before interconnection, the two active regions are indistinguishable. After the circuit is connected, the source region or drain region is defined according to the direction of the current.

[0041] The active part 100 is made of undoped or doped semiconductor materials, two-dimensional semiconductor materials, amorphous metal-oxide-semiconductor materials, polycrystalline metal-oxide-semiconductor materials, or combinations thereof. Undoped or doped semiconductor materials include single-crystal Si, polycrystalline Si, SiGe, or SiC. Two-dimensional semiconductor materials include transition metal dichalcogenides (TMDs) (such as CuS2, CuSe2, WSe2, MoS2, MoSe2, WS2, etc.) and hexagonal boron nitride (h... Metal-oxide semiconductor materials may include In3O4, graphene, carbon nanotubes (CNTs), or combinations thereof. Zn-based oxides (IZO), Zn Sn-based oxides (ZTO), In Ga-based oxides (IGO), Y At least one of Zn-based oxide (YZO) or indium gallium zinc oxide (IGZO).

[0042] In some embodiments, reference Figure 1 The first source / drain region 111, the channel region 112, and the second source / drain region 113 are arranged in the first horizontal direction X.

[0043] In some embodiments, the first source / drain region 111, the channel region 112, and the second source / drain region 113 are all doped with the same type, i.e., the transistor is a junction-less transistor. Here, "junction-less" means without a PN junction, that is, the transistor composed of the active part 100 does not have a PN junction. The advantages of this include: on the one hand, there is no need to perform additional doping on the first source / drain region 111 and the second source / drain region 113, thereby avoiding the problem of difficult control of the doping process of the first source / drain region 111 and the second source / drain region 113. Especially as the transistor size is further reduced, if the first source / drain region 111 and the second source / drain region 113 are additionally doped, the doping concentration will be even more difficult to control. On the other hand, since the device is a junction-less transistor, it is beneficial to avoid the phenomenon of using an ultra-steep source / drain concentration gradient doping process to create an ultra-steep PN junction in the nanoscale range. Therefore, it can avoid problems such as threshold voltage drift and leakage current increase caused by doping abrupt changes. It is also beneficial to suppress short-channel effects and can still work in the range of a few nanometers. Therefore, it helps to further improve the integration density and electrical performance of the semiconductor structure. It is understandable that the additional doping here refers to the doping performed so that the dopant ion types of the first source / drain region 111 and the second source / drain region 113 are different from the dopant ion types of the channel region 112.

[0044] In some embodiments, the doping type of the first source-drain region 111 and the second source-drain region 113 is different from the doping type of the channel region 112, i.e., the transistor is a junction transistor. Junction transistors can have higher current drive capability, higher input impedance, and a higher rate of change of drain current with gate voltage, thereby having controllable gate-source bias, and the drain current can be controlled by changing the gate voltage. Junction transistors have high input impedance, low noise figure, and maintain a linear relationship within a certain range, thereby improving signal accuracy.

[0045] In some embodiments, the first source-drain region 111 is either a source region or a drain region, and the second source-drain region 113 is either a source region or a drain region. For example, the first source-drain region 111 is a drain region, and the second source-drain region 113 is a source region.

[0046] Continue to refer to Figure 1 The semiconductor structure includes a first isolation layer 101 and a second isolation layer 102. The first isolation layer 101 is located on the surfaces of the first source / drain region 111 and the second source / drain region 113, and the second isolation layer 102 is located on the surface of the first isolation layer 101 away from the active portion 100.

[0047] The semiconductor structure may include at least two first isolation layers 101, and the two first isolation layers 101 may be located on opposite sides of the active portion 100, with the first isolation layers 101 mainly located on the surfaces of the first source / drain region and the second source / drain region. In some embodiments, the first isolation layer 101 may surround the active portion 100.

[0048] The semiconductor structure may include at least two second isolation layers 102, and the two second isolation layers 102 may be located on opposite sides of the first isolation layer 101. The second isolation layers 102 are located on the first source / drain region 111 and the second source / drain region 113, and are located on a portion of the channel region. In some embodiments, the second isolation layer 102 may surround the active portion 100.

[0049] In some embodiments, the material of the first isolation layer 101 may be silicon oxide.

[0050] In some embodiments, the material of the second isolation layer 102 may be silicon nitride.

[0051] In some embodiments, the thickness of the first insulating layer 101 is less than the thickness of the second insulating layer 102. Thus, the first insulating layer 101 can serve as a dielectric layer to prevent leakage current, further mitigating the GIDL problem.

[0052] In some embodiments, the thickness of the first isolation layer 101 is greater than the thickness of the first portion 1052. In this way, by setting the thickness of the first portion 1052 to be thinner, fewer corresponding areas of word line structures are established, and the drain voltage is also smaller, which can reduce the drive current.

[0053] Continue to refer to Figure 1 The semiconductor structure includes a word line structure 105, which is located on the side of the channel region away from the substrate. The word line structure 105 includes a first part 1052 and a second part 1051. The first part 1052 is located on the side of the first isolation layer 101 along a first direction, and the second part 1051 is located on the side of the second isolation layer 102 along the first direction. The first dimension of the first part 1052 along the first direction is larger than the second dimension of the second part 1051 along the first direction.

[0054] The word line structure 105 is used to select a specific row of memory cells and control the turn-on / turn-off of transistors. The working principle is as follows: when a voltage is applied to the word line structure 105, the gates of all transistors in that row are activated (such as MOSFETs being turned on), connecting the bit line to the memory cell.

[0055] In some embodiments, the word line structure 105 surrounds the channel region. The word line structure 105 serves as the gate of the semiconductor structure. The word line surrounds the active portion 100 to form a gate-all-around (GAA) transistor structure, which can largely solve problems such as leakage current, capacitance effect, and short-channel effect caused by the reduction of gate pitch size, thereby improving the integration density of the semiconductor structure.

[0056] In some embodiments, the word line structure 105 is made of any one of tungsten, tantalum, molybdenum, titanium nitride, or tantalum nitride, forming a metal gate line. In other embodiments, the word line structure 105 is made of doped polysilicon. Since the band gap of polysilicon is similar to that of the channel material, and the work function of polysilicon can be changed by controlling the doping concentration, it is beneficial to reduce the threshold voltage between the gate and the channel region 112. The doping element type of the doped polysilicon may be the same as or different from the doping element type of the channel region 112.

[0057] Continue to refer to Figure 1 A gate dielectric layer 104 is provided between the word line structure 105 and the active part 100. The gate dielectric layer 104 can be made of silicon oxide, silicon carbide, silicon nitride or other materials with high dielectric constant, to suppress short-channel effects, thereby suppressing tunneling leakage current and other issues.

[0058] In some embodiments, the first part 1052 and the second part 1051 may be made of the same material, and the first part 1052 and the second part 1051 may be integrally formed continuous conductive materials. For example, the first part 1052 and the second part 1051 may include the same metallic material, such as tungsten, titanium, titanium nitride, etc.

[0059] In some embodiments, a work function adjustment layer is included between the first part 1052 and the second part 1051, and the work function adjustment layer continuously covers the surface of the first part 1052 and the inner surface of the second part 1051. The control voltage of the gate and the current conduction capability of the channel region are adjusted based on the work function adjustment layer to reduce the GIDL current.

[0060] In some embodiments, the ratio of the difference between the second dimension and the first dimension to the first dimension is 1:300 to 1:10. The ratio of the difference between the second dimension and the first dimension to the first dimension can be a range of any two values ​​from 1:300, 1:250, 1:200, 1:150, 1:100, 1:80, 1:60, 1:40, 1:20, or 1:10, or any value.

[0061] Figure 4 This is a schematic diagram of a word line structure in a semiconductor structure provided in an embodiment of the present disclosure.

[0062] In some embodiments, reference Figure 4 The first portion 1052 has a protrusion 121 compared to the second portion 1051, and the remaining portion 1052 can be a body portion 122. The protrusion 121 is close to the drain region. Thus, the relatively thin protrusion 121, located near the drain region, buffers the electric field impact of the drain high voltage on the gate edge, while the body portion 122 controls the channel inversion layer, ensuring the device's drive current. The potential on the protrusion 121 forms a local high potential barrier on the silicon surface below it. This barrier prevents further intrusion of the drain depletion layer into the channel below the body portion 122. Depletion layer expansion is suppressed, and the tunneling region is limited to a very small area below the protrusion 121. The electric field within this area is dispersed due to the geometry of the protrusion 121 to avoid GIDL current.

[0063] In some embodiments, reference Figure 4 The protrusion 121 includes a first end 131 near the drain region and a second end 132 near the second portion 1051, with the thickness of the first end 131 being smaller than the thickness of the second end 132. Thus, the smaller thickness of the first end 131 near the drain region, i.e., the smaller thickness of the portion of the word line structure 105 near the edge of the drain region, results in weaker capacitive coupling and a smoother bandgap transition, reducing the tunneling probability and decreasing the GIDL current. Furthermore, the smaller thickness of the first end 131 compared to the second end 132 allows the gate voltage to increase continuously and smoothly across the bandgap of the underlying silicon surface, rather than through a step-like transition. This smooth bandgap requires electrons to cross a wider effective barrier to tunnel from the valence band to the conduction band, thereby reducing the tunneling probability.

[0064] In some embodiments, the system further includes a bit line structure 107, which is coupled to the first source / drain region 111 and extends along the vertical direction Z.

[0065] Bit line structure 107 is the data transmission path between the memory cell and the external circuit, responsible for reading stored information or writing new data.

[0066] In some embodiments, the bit line structure 107 is a metallic bit line, and the material of the bit line structure 107 can be metals such as tungsten, copper, molybdenum, and silver. Metals have low resistance, which is beneficial for improving the conductivity between the bit line structure 107 and the active region. In other embodiments, the bit line structure 107 can be a semiconductor bit line, and the material of the semiconductor bit line can be silicon, germanium, germanium-silicon, silicon carbide, or polycrystalline silicon. Furthermore, the semiconductor bit line is doped with the same type of dopant element as the active region 100. The dopant element can act as a charge carrier, which can improve the migration and diffusion of charge carriers between the bit line structure 107 and the active region 100, thus improving the conductivity between the bit line structure 107 and the active region 100.

[0067] In some embodiments, the system further includes a capacitor structure 106, which is coupled to the second source / drain region 113.

[0068] The capacitor structure 106 further includes a first electrode, a dielectric layer, a second electrode, and a third electrode, which are stacked sequentially. The first electrode serves as the lower electrode of the capacitor structure 106, and the second and third electrodes together serve as the upper electrode of the capacitor structure 106. The second and third electrodes can be common electrodes of multiple capacitor structures 106. The capacitor structure 106 can be used as a storage element for storing data.

[0069] In some embodiments, the first electrode may be made of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten. The dielectric layer may be made of silicon oxide, silicon nitride, or one or more high-dielectric-constant materials, including hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, titanium oxide, tantalum oxide, niobium oxide, or strontium titanate. The second electrode may be made of titanium, titanium nitride, ruthenium, cobalt, nickel, or tungsten. The third electrode may be made of doped polycrystalline silicon or undoped polycrystalline silicon (i.e., intrinsic polycrystalline silicon).

[0070] refer to Figure 2 It also includes: a substrate 10, an active part 100 located on the surface of the substrate 10, and a word line structure 105 located on the surface of the active part 100.

[0071] refer to Figure 3 It also includes: a substrate 10, an active portion 100 located on the substrate 10, and the arrangement direction of the first source / drain region 111, the channel region 112, and the second source / drain region 113 being perpendicular to the surface of the substrate, i.e., the vertical direction Z. The bit line structure 107 extends along the second horizontal direction Y, and the word line structure 105 extends along the first horizontal direction X.

[0072] Figure 5 This is a schematic diagram of a fourth semiconductor structure provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of a fifth semiconductor structure provided in an embodiment of the present disclosure.

[0073] In some embodiments, reference Figure 5 The character line structure 105 includes a first character line 114 and a second character line 115. The first character line 114 is located on the side of the channel area 112 away from the substrate, and the second character line 115 is located on the side of the channel area 112 close to the substrate. The first part of the first character line 114 is a first sub-part 1142, and the second part of the first character line is a second sub-part 1141. The dimension of the first sub-part 1142 along the first direction is greater than the dimension of the second sub-part 1141 along the first direction. The first part of the second character line is a third sub-part 1152, and the second part of the second character line is a fourth sub-part 1151. The dimension of the third sub-part 1152 along the first direction is greater than the dimension of the fourth sub-part 1151 along the first direction.

[0074] In some embodiments, reference Figure 6 The word line structure is a single word line, located on either side of the active part, forming a single grid structure.

[0075] It should be noted that, Figure 5 and Figure 6 The corresponding structure is exemplified by a 3D stacked array transistor, meaning that the word line structure in a 3D stacked array transistor can be as follows: Figure 1 The ring gate structure shown can also be as follows: Figure 5 The double-gate structure shown can also be as follows: Figure 6 The single-gate structure is shown; for the vertical transistor structure, the word line structure can be as follows: Figure 3 The ring gate structure shown can also be a double gate structure, or even a single gate structure. This disclosure does not provide specific examples of each; those skilled in the art can refer to relevant examples. Figure 5 and Figure 6 The content.

[0076] The substrate 10 can be made of a semiconductor material, which may include any one of silicon, germanium, silicon carbide, or silicon germanide. The substrate 10 contains dopant elements, which may be N-type or P-type dopant elements. N-type dopant elements may be group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), while P-type dopant elements may be group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0077] In some embodiments, the material of the substrate 10 is the same as the material of the active portion 100.

[0078] It should be noted that, Figure 1 , Figure 2 as well as Figure 3 In the semiconductor structure, the positional relationship or extension direction of the active portion 100, word line structure 105, bit line structure 107, and substrate 10 may change, but the correspondence between the word line structure 105 and the active portion 100, and the correspondence between the bit line structure 107 and the active portion 100, remains unchanged. Therefore, Figure 1 , Figure 2 as well as Figure 3 The features of the same reference numerals in the accompanying drawings are identical, the difference being that... Figure 2 The word line structure 105 is not a ring grid structure. The word line structure 105 is located on the three surfaces of the active part 100, presenting a semi-circular structure or located on part of the surface of the active part 100.

[0079] Figure 7 This is a schematic diagram of a sixth semiconductor structure provided in an embodiment of the present disclosure.

[0080] refer to Figure 7 The first part 1052 has a protrusion towards the drain area and a protrusion towards the source area compared to the second part 1051. That is, the first part 1052 protrudes towards the first source-drain area and also protrudes towards the second source-drain area.

[0081] It should be noted that the embodiments disclosed herein do not separately illustrate the semiconductor structure in which the first part 1052 has a protrusion toward the source region compared to the second part 1051. Those skilled in the art can determine the semiconductor structure based on this. Figure 1 In the semiconductor structure, the first source / drain region can be defined as the source region.

[0082] Figures 1-7 The semiconductor structure provided by any one of the following includes a word line structure 105 comprising a first part 1052 and a second part 1051. The first part 1052 is located on the side of the first isolation layer 101, and the second part 1051 is located on the side of the second isolation layer 102. The first dimension of the first part 1052 is larger than the second dimension of the second part 1051. Thus, the portion near the edge of the first source-drain channel is relatively thicker or wider. The larger first part 1052 may physically push the effective edge of the gate away from the region with the highest carrier concentration in the first source-drain region, or disperse the electric field lines originally concentrated at the sharp corners through its geometry (such as step shape), thereby weakening the vertical electric field on the drain surface, making the band bending gentler, reducing the probability of band-to-band tunneling, and reducing the GIDL current. Secondly, the wider first portion 1052 is closer to the active portion 100. For the gate dielectric layer located between the active portion 100 and the word line structure 105, the high electric field carriers are dispersed to the wider first portion 1052. This reduces the probability of high-energy carriers being injected into the gate oxide layer, improving the long-term reliability of the device. It also makes the electric field distribution at the edge of the entire channel more uniform, avoiding premature local breakdown or performance degradation.

[0083] Accordingly, based on some embodiments of this disclosure, another aspect of this disclosure also provides a method for preparing a semiconductor structure, used to prepare the semiconductor structure provided in the above embodiments. The same or corresponding technical features as those in the above embodiments will not be described in detail here. Figure 1 The semiconductor structure shown is an example.

[0084] Figures 8-13 This is a schematic diagram of the semiconductor structure corresponding to each step in a method for preparing a semiconductor structure according to another embodiment of this disclosure.

[0085] refer to Figure 8 The preparation method includes providing an active part 100.

[0086] Continue to refer to Figure 8The preparation method includes forming a first isolation layer 101 and a second isolation layer 102, wherein the first isolation layer 101 is located on the surface of the active part 100 and the second isolation layer 102 is located on the surface of the first isolation layer 101.

[0087] refer to Figure 9 The preparation method includes removing a portion of the width of the first isolation layer 101 to form a first trench.

[0088] In some embodiments, the size of the removed first isolation layer 101 is a third size D1, which is smaller than the size D2 of the unetched first isolation layer 101. The size D2 of the unetched first isolation layer 101 can also be regarded as the length of the active portion 100.

[0089] refer to Figure 10 The preparation method includes removing a portion of the width of the second isolation layer 102 to form a second groove, wherein the first groove and the second groove together serve as a first groove 108.

[0090] refer to Figure 11 The preparation method includes: further removing the first isolation layer 101 to form a second groove 109, wherein the first groove 108 and the second groove 109 penetrate each other. The width of the second groove 109 along the first horizontal direction is D3.

[0091] refer to Figure 12 The preparation method includes: forming a gate dielectric layer 104, the gate dielectric layer 104 being located in the first groove 108 and the second groove 109, and the gate dielectric layer 104 surrounding the active portion 100.

[0092] refer to Figure 13 as well as Figure 1 The fabrication method includes forming a word line structure 105, which is located on a channel region 112. The word line structure 105 includes a first part 1052 and a second part 1051. The first part 1052 is located on the side of a first isolation layer 101, and the second part 1051 is located on the side of a second isolation layer 102. The first dimension of the first part 1052 is larger than the second dimension of the second part 1051. The active part 100 includes a first source / drain region 111, a channel region 112, and a second source / drain region 113 arranged sequentially.

[0093] Specifically: Reference Figure 13 The preparation method includes forming a character line structure 105 in the first groove 108 and the second groove 109.

[0094] refer to Figure 1 The preparation method further includes: forming a bit line structure 107, the bit line structure 107 being located on one side of the active portion 100, and the bit line structure 107 being coupled to the first source / drain region 111.

[0095] Continue to refer to Figure 1 The preparation method further includes: forming a capacitor structure 106, the capacitor structure 106 being located on the other side of the active part 100, and the capacitor structure 106 being coupled to the second source / drain region 113.

[0096] In the semiconductor structure fabrication method provided in this disclosure, the physical shape of the word line structure 105 is changed, and the passivation of the gate edge is cleverly achieved without adding an additional mask (usually achieved through etching or back-drilling processes). This reduces the electrostatic influence of the word line on the drain when the device is turned off, and reduces the degree of band bending on the drain surface, thereby effectively suppressing the gate-induced drain leakage current while maintaining good control over the channel.

[0097] Accordingly, according to some embodiments of the present disclosure, another aspect of the present disclosure also provides an electronic device, including a processor; and a memory electrically connected to the processor, the memory including a semiconductor structure as described in any one of the above embodiments or a semiconductor structure prepared by the method for preparing the semiconductor structure as described in any one of the above embodiments.

[0098] The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0099] Memory can be used to store computer programs and / or modules. The processor implements various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory. Memory can mainly include a program storage area and a data storage area. The program storage area can store the operating system, at least one application program required for a function, etc.; the data storage area can store data created based on the use of the terminal device, etc. Furthermore, storage devices can include high-speed random access memory, and can also include non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital cards (SD cards), flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0100] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: An active section, the active section comprising a first source / drain region, a channel region, and a second source / drain region arranged sequentially along a first direction; A first isolation layer and a second isolation layer, wherein the first isolation layer is located on the surfaces of the first source / drain region and the second source / drain region, and the second isolation layer is located on the surface of the first isolation layer away from the active portion; A character line structure is located on the surface of the channel region. The character line structure includes a first part and a second part. The first part is located on the side of the first isolation layer along the first direction, and the second part is located on the side of the second isolation layer along the first direction. The first dimension of the first part along the first direction is greater than the second dimension of the second part along the first direction. The first part has a protrusion compared to the second part, and the protrusion is close to the drain area; the protrusion includes a first end close to the drain area and a second end close to the second part, and the thickness of the first end is less than the thickness of the second end.

2. The semiconductor structure of claim 1, wherein, The word line structure surrounds the channel area.

3. The semiconductor structure according to claim 2, characterized in that, Also includes: The active portion is located on the substrate, and the arrangement direction of the first source / drain region, the channel region, and the second source / drain region is perpendicular to the surface of the substrate.

4. The semiconductor structure of claim 2, wherein, The first source / drain region, the channel region, and the second source / drain region are arranged in a first horizontal direction; it also includes a bitline structure, which is coupled to the first source / drain region and extends in a vertical direction.

5. The semiconductor structure of claim 1, wherein, Also includes: The substrate, the active portion is located on the surface of the substrate, and the word line structure is located on the surface of the active portion.

6. The semiconductor structure according to claim 5, characterized in that, The character line structure includes a first character line and a second character line. The first character line is located on the side of the channel region away from the substrate, and the second character line is located on the side of the channel region closer to the substrate. The first part of the first character line is a first sub-part, and the second part of the first character line is a second sub-part. The dimension of the first sub-part along the first direction is greater than the dimension of the second sub-part along the first direction. The first part of the second character line is a third sub-part, and the second part of the second character line is a fourth sub-part. The dimension of the third sub-part along the first direction is greater than the dimension of the fourth sub-part along the first direction.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The ratio of the difference between the second dimension and the first dimension to the first dimension is 1:300 to 1:

10.

8. The semiconductor structure of claim 1, wherein, The thickness of the first isolation layer is less than the thickness of the second isolation layer.

9. The semiconductor structure of claim 1 or 8, wherein, The thickness of the first isolation layer is greater than the thickness of the first part.

10. A method of fabricating a semiconductor structure, characterized by, include: An active part is provided, the active part including a first source-drain region, a channel region and a second source-drain region arranged in sequence; A first isolation layer and a second isolation layer are formed, wherein the first isolation layer is located on the surfaces of the first source / drain region and the second source / drain region, and the second isolation layer is located on the surface of the first isolation layer; A portion of the width of the first isolation layer and the second isolation layer is removed to form a first groove; the first isolation layer is then removed to form a second groove, and the first groove and the second groove penetrate each other. A character line structure is formed in the first groove and the second groove. The character line structure is located on the channel area. The character line structure includes a first part and a second part. The first part is located on the side of the first isolation layer, and the second part is located on the side of the second isolation layer. The first dimension of the first part is larger than the second dimension of the second part.

11. An electronic device, comprising: include: processor; as well as A memory electrically connected to the processor, the memory comprising the semiconductor structure according to any one of claims 1 to 9.

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